Unified Coverage Report :: Group Instance : salt_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3077

1

T2

1

T3

4

T7

1

auto[1]

296

1

T123

7

T124

7

T125

10

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T12	1		T16	1		T23	2
auto[134217728:268435455]	116	1			T13	1		T15	1		T120	1
auto[268435456:402653183]	93	1			T23	5		T123	2		T21	1
auto[402653184:536870911]	106	1			T34	2		T137	1		T140	1
auto[536870912:671088639]	101	1			T12	1		T23	1		T126	1
auto[671088640:805306367]	110	1			T12	1		T13	1		T15	1
auto[805306368:939524095]	121	1			T13	1		T49	1		T23	2
auto[939524096:1073741823]	106	1			T12	1		T123	1		T124	1
auto[1073741824:1207959551]	105	1			T13	1		T140	1		T125	2
auto[1207959552:1342177279]	98	1			T7	1		T33	1		T23	1
auto[1342177280:1476395007]	82	1			T15	1		T127	1		T54	1
auto[1476395008:1610612735]	96	1			T15	1		T34	1		T23	3
auto[1610612736:1744830463]	100	1			T3	1		T16	1		T184	1
auto[1744830464:1879048191]	95	1			T23	2		T140	1		T125	1
auto[1879048192:2013265919]	98	1			T16	1		T23	1		T122	1
auto[2013265920:2147483647]	109	1			T13	1		T34	3		T59	2
auto[2147483648:2281701375]	132	1			T3	1		T15	2		T23	2
auto[2281701376:2415919103]	95	1			T33	1		T23	1		T137	1
auto[2415919104:2550136831]	108	1			T23	1		T4	1		T48	1
auto[2550136832:2684354559]	103	1			T3	1		T12	1		T16	1
auto[2684354560:2818572287]	113	1			T12	2		T15	1		T23	2
auto[2818572288:2952790015]	105	1			T35	1		T137	1		T57	1
auto[2952790016:3087007743]	123	1			T12	1		T16	1		T33	1
auto[3087007744:3221225471]	107	1			T15	1		T51	1		T123	1
auto[3221225472:3355443199]	111	1			T12	1		T37	1		T120	1
auto[3355443200:3489660927]	106	1			T12	1		T16	1		T23	3
auto[3489660928:3623878655]	125	1			T2	1		T12	1		T37	2
auto[3623878656:3758096383]	95	1			T12	1		T37	1		T49	2
auto[3758096384:3892314111]	96	1			T3	1		T23	1		T124	1
auto[3892314112:4026531839]	101	1			T26	1		T59	1		T230	2
auto[4026531840:4160749567]	95	1			T12	2		T49	1		T140	1
auto[4160749568:4294967295]	116	1			T12	1		T16	1		T23	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	102	1			T12	1		T16	1		T23	2
auto[0:134217727]	auto[1]	4	1			T251	1		T290	1		T381	1
auto[134217728:268435455]	auto[0]	106	1			T13	1		T15	1		T120	1
auto[134217728:268435455]	auto[1]	10	1			T78	1		T275	1		T379	1
auto[268435456:402653183]	auto[0]	82	1			T23	5		T21	1		T126	1
auto[268435456:402653183]	auto[1]	11	1			T123	2		T124	1		T76	2
auto[402653184:536870911]	auto[0]	96	1			T34	2		T137	1		T140	1
auto[402653184:536870911]	auto[1]	10	1			T124	1		T129	1		T366	1
auto[536870912:671088639]	auto[0]	92	1			T12	1		T23	1		T127	1
auto[536870912:671088639]	auto[1]	9	1			T126	1		T230	1		T217	1
auto[671088640:805306367]	auto[0]	96	1			T12	1		T13	1		T15	1
auto[671088640:805306367]	auto[1]	14	1			T76	1		T78	1		T277	1
auto[805306368:939524095]	auto[0]	114	1			T13	1		T49	1		T23	2
auto[805306368:939524095]	auto[1]	7	1			T217	1		T366	1		T364	1
auto[939524096:1073741823]	auto[0]	95	1			T12	1		T236	1		T17	1
auto[939524096:1073741823]	auto[1]	11	1			T123	1		T124	1		T76	1
auto[1073741824:1207959551]	auto[0]	96	1			T13	1		T140	1		T59	1
auto[1073741824:1207959551]	auto[1]	9	1			T125	2		T126	1		T127	1
auto[1207959552:1342177279]	auto[0]	95	1			T7	1		T33	1		T23	1
auto[1207959552:1342177279]	auto[1]	3	1			T307	1		T382	1		T386	1
auto[1342177280:1476395007]	auto[0]	76	1			T15	1		T127	1		T54	1
auto[1342177280:1476395007]	auto[1]	6	1			T275	1		T307	1		T386	1
auto[1476395008:1610612735]	auto[0]	89	1			T15	1		T34	1		T23	3
auto[1476395008:1610612735]	auto[1]	7	1			T124	2		T125	1		T277	1
auto[1610612736:1744830463]	auto[0]	91	1			T3	1		T16	1		T184	1
auto[1610612736:1744830463]	auto[1]	9	1			T230	1		T78	1		T368	1
auto[1744830464:1879048191]	auto[0]	86	1			T23	2		T140	1		T142	1
auto[1744830464:1879048191]	auto[1]	9	1			T125	1		T127	1		T78	1
auto[1879048192:2013265919]	auto[0]	90	1			T16	1		T23	1		T122	1
auto[1879048192:2013265919]	auto[1]	8	1			T125	1		T275	1		T366	1
auto[2013265920:2147483647]	auto[0]	101	1			T13	1		T34	3		T59	2
auto[2013265920:2147483647]	auto[1]	8	1			T142	1		T143	1		T230	1
auto[2147483648:2281701375]	auto[0]	123	1			T3	1		T15	2		T23	2
auto[2147483648:2281701375]	auto[1]	9	1			T125	1		T364	1		T386	2
auto[2281701376:2415919103]	auto[0]	83	1			T33	1		T23	1		T137	1
auto[2281701376:2415919103]	auto[1]	12	1			T124	1		T76	2		T78	1
auto[2415919104:2550136831]	auto[0]	95	1			T23	1		T4	1		T48	1
auto[2415919104:2550136831]	auto[1]	13	1			T126	1		T76	2		T275	1
auto[2550136832:2684354559]	auto[0]	96	1			T3	1		T12	1		T16	1
auto[2550136832:2684354559]	auto[1]	7	1			T125	1		T364	1		T291	1
auto[2684354560:2818572287]	auto[0]	107	1			T12	2		T15	1		T23	2
auto[2684354560:2818572287]	auto[1]	6	1			T125	1		T78	1		T275	1
auto[2818572288:2952790015]	auto[0]	95	1			T35	1		T137	1		T57	1
auto[2818572288:2952790015]	auto[1]	10	1			T76	1		T217	1		T364	1
auto[2952790016:3087007743]	auto[0]	105	1			T12	1		T16	1		T33	1
auto[2952790016:3087007743]	auto[1]	18	1			T123	1		T125	1		T127	1
auto[3087007744:3221225471]	auto[0]	96	1			T15	1		T51	1		T21	1
auto[3087007744:3221225471]	auto[1]	11	1			T123	1		T76	1		T364	1
auto[3221225472:3355443199]	auto[0]	99	1			T12	1		T37	1		T120	1
auto[3221225472:3355443199]	auto[1]	12	1			T123	1		T127	1		T366	1
auto[3355443200:3489660927]	auto[0]	100	1			T12	1		T16	1		T23	3
auto[3355443200:3489660927]	auto[1]	6	1			T366	1		T379	1		T320	1
auto[3489660928:3623878655]	auto[0]	117	1			T2	1		T12	1		T37	2
auto[3489660928:3623878655]	auto[1]	8	1			T123	1		T230	1		T217	1
auto[3623878656:3758096383]	auto[0]	82	1			T12	1		T37	1		T49	2
auto[3623878656:3758096383]	auto[1]	13	1			T124	1		T126	1		T76	2
auto[3758096384:3892314111]	auto[0]	88	1			T3	1		T23	1		T124	1
auto[3758096384:3892314111]	auto[1]	8	1			T143	1		T364	2		T277	1
auto[3892314112:4026531839]	auto[0]	90	1			T26	1		T59	1		T230	1
auto[3892314112:4026531839]	auto[1]	11	1			T230	1		T129	1		T366	1
auto[4026531840:4160749567]	auto[0]	88	1			T12	2		T49	1		T140	1
auto[4026531840:4160749567]	auto[1]	7	1			T142	1		T127	1		T76	2
auto[4160749568:4294967295]	auto[0]	106	1			T12	1		T16	1		T23	1
auto[4160749568:4294967295]	auto[1]	10	1			T125	1		T142	1		T76	1