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Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 127 1 T12 1 T137 1 T57 1
auto[134217728:268435455] 108 1 T13 1 T34 1 T37 1
auto[268435456:402653183] 109 1 T16 1 T23 1 T142 1
auto[402653184:536870911] 106 1 T13 1 T16 1 T23 1
auto[536870912:671088639] 106 1 T49 1 T23 4 T122 1
auto[671088640:805306367] 99 1 T3 1 T33 1 T23 1
auto[805306368:939524095] 100 1 T34 1 T21 1 T59 1
auto[939524096:1073741823] 110 1 T57 1 T59 1 T236 1
auto[1073741824:1207959551] 109 1 T3 1 T12 1 T23 2
auto[1207959552:1342177279] 102 1 T3 1 T13 2 T23 1
auto[1342177280:1476395007] 102 1 T7 1 T12 1 T13 1
auto[1476395008:1610612735] 125 1 T15 1 T16 1 T34 2
auto[1610612736:1744830463] 131 1 T23 1 T140 1 T57 1
auto[1744830464:1879048191] 113 1 T3 1 T23 2 T48 1
auto[1879048192:2013265919] 99 1 T12 1 T23 1 T48 1
auto[2013265920:2147483647] 85 1 T16 1 T49 1 T120 1
auto[2147483648:2281701375] 121 1 T23 1 T4 1 T122 1
auto[2281701376:2415919103] 105 1 T12 1 T23 4 T137 1
auto[2415919104:2550136831] 123 1 T12 1 T13 1 T15 3
auto[2550136832:2684354559] 89 1 T12 2 T33 1 T49 1
auto[2684354560:2818572287] 100 1 T13 1 T23 1 T35 1
auto[2818572288:2952790015] 90 1 T15 1 T23 1 T122 1
auto[2952790016:3087007743] 125 1 T12 1 T34 1 T184 1
auto[3087007744:3221225471] 116 1 T2 1 T26 1 T23 2
auto[3221225472:3355443199] 89 1 T12 2 T16 1 T23 1
auto[3355443200:3489660927] 112 1 T12 2 T137 1 T51 1
auto[3489660928:3623878655] 119 1 T13 1 T15 1 T23 2
auto[3623878656:3758096383] 106 1 T34 1 T137 1 T57 1
auto[3758096384:3892314111] 118 1 T12 1 T16 1 T37 1
auto[3892314112:4026531839] 117 1 T15 2 T34 1 T23 1
auto[4026531840:4160749567] 118 1 T12 1 T13 1 T37 1
auto[4160749568:4294967295] 106 1 T16 1 T26 1 T23 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 57 1 T12 1 T59 1 T5 1
auto[0:134217727] auto[1] 70 1 T137 1 T57 1 T76 1
auto[134217728:268435455] auto[0] 49 1 T13 1 T37 1 T126 1
auto[134217728:268435455] auto[1] 59 1 T34 1 T143 1 T244 1
auto[268435456:402653183] auto[0] 57 1 T142 1 T17 1 T18 1
auto[268435456:402653183] auto[1] 52 1 T16 1 T23 1 T127 1
auto[402653184:536870911] auto[0] 57 1 T16 1 T23 1 T21 1
auto[402653184:536870911] auto[1] 49 1 T13 1 T51 1 T192 1
auto[536870912:671088639] auto[0] 47 1 T23 3 T122 1 T218 1
auto[536870912:671088639] auto[1] 59 1 T49 1 T23 1 T77 2
auto[671088640:805306367] auto[0] 47 1 T3 1 T33 1 T122 1
auto[671088640:805306367] auto[1] 52 1 T23 1 T35 1 T4 2
auto[805306368:939524095] auto[0] 47 1 T34 1 T127 1 T226 1
auto[805306368:939524095] auto[1] 53 1 T21 1 T59 1 T58 1
auto[939524096:1073741823] auto[0] 44 1 T236 1 T54 1 T275 1
auto[939524096:1073741823] auto[1] 66 1 T57 1 T59 1 T54 1
auto[1073741824:1207959551] auto[0] 37 1 T23 2 T54 1 T85 1
auto[1073741824:1207959551] auto[1] 72 1 T3 1 T12 1 T137 1
auto[1207959552:1342177279] auto[0] 54 1 T3 1 T13 2 T21 1
auto[1207959552:1342177279] auto[1] 48 1 T23 1 T126 1 T230 1
auto[1342177280:1476395007] auto[0] 55 1 T12 1 T13 1 T49 1
auto[1342177280:1476395007] auto[1] 47 1 T7 1 T137 1 T140 1
auto[1476395008:1610612735] auto[0] 67 1 T15 1 T16 1 T34 2
auto[1476395008:1610612735] auto[1] 58 1 T23 2 T122 1 T54 3
auto[1610612736:1744830463] auto[0] 60 1 T23 1 T122 1 T190 1
auto[1610612736:1744830463] auto[1] 71 1 T140 1 T57 1 T143 1
auto[1744830464:1879048191] auto[0] 55 1 T3 1 T23 1 T54 1
auto[1744830464:1879048191] auto[1] 58 1 T23 1 T48 1 T237 1
auto[1879048192:2013265919] auto[0] 48 1 T12 1 T23 1 T48 1
auto[1879048192:2013265919] auto[1] 51 1 T192 1 T54 1 T73 1
auto[2013265920:2147483647] auto[0] 39 1 T16 1 T49 1 T120 1
auto[2013265920:2147483647] auto[1] 46 1 T183 1 T174 1 T270 1
auto[2147483648:2281701375] auto[0] 66 1 T23 1 T122 1 T124 1
auto[2147483648:2281701375] auto[1] 55 1 T4 1 T24 1 T352 1
auto[2281701376:2415919103] auto[0] 51 1 T12 1 T23 1 T142 1
auto[2281701376:2415919103] auto[1] 54 1 T23 3 T137 1 T59 1
auto[2415919104:2550136831] auto[0] 60 1 T13 1 T15 1 T23 2
auto[2415919104:2550136831] auto[1] 63 1 T12 1 T15 2 T33 1
auto[2550136832:2684354559] auto[0] 39 1 T12 1 T33 1 T49 1
auto[2550136832:2684354559] auto[1] 50 1 T12 1 T23 3 T38 1
auto[2684354560:2818572287] auto[0] 52 1 T35 1 T21 1 T59 1
auto[2684354560:2818572287] auto[1] 48 1 T13 1 T23 1 T125 1
auto[2818572288:2952790015] auto[0] 42 1 T23 1 T122 1 T218 1
auto[2818572288:2952790015] auto[1] 48 1 T15 1 T54 1 T183 1
auto[2952790016:3087007743] auto[0] 60 1 T34 1 T184 1 T21 1
auto[2952790016:3087007743] auto[1] 65 1 T12 1 T182 1 T54 1
auto[3087007744:3221225471] auto[0] 52 1 T26 1 T184 1 T53 1
auto[3087007744:3221225471] auto[1] 64 1 T2 1 T23 2 T140 1
auto[3221225472:3355443199] auto[0] 51 1 T12 1 T16 1 T23 1
auto[3221225472:3355443199] auto[1] 38 1 T12 1 T124 1 T226 1
auto[3355443200:3489660927] auto[0] 56 1 T51 1 T126 1 T182 1
auto[3355443200:3489660927] auto[1] 56 1 T12 2 T137 1 T126 1
auto[3489660928:3623878655] auto[0] 57 1 T23 1 T122 2 T54 1
auto[3489660928:3623878655] auto[1] 62 1 T13 1 T15 1 T23 1
auto[3623878656:3758096383] auto[0] 51 1 T57 1 T21 1 T55 1
auto[3623878656:3758096383] auto[1] 55 1 T34 1 T137 1 T120 1
auto[3758096384:3892314111] auto[0] 59 1 T12 1 T16 1 T37 1
auto[3758096384:3892314111] auto[1] 59 1 T23 1 T124 1 T59 1
auto[3892314112:4026531839] auto[0] 62 1 T34 1 T23 1 T22 1
auto[3892314112:4026531839] auto[1] 55 1 T15 2 T59 1 T73 1
auto[4026531840:4160749567] auto[0] 57 1 T13 1 T23 1 T17 1
auto[4026531840:4160749567] auto[1] 61 1 T12 1 T37 1 T35 1
auto[4160749568:4294967295] auto[0] 50 1 T26 1 T35 1 T51 1
auto[4160749568:4294967295] auto[1] 56 1 T16 1 T23 1 T125 1

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