Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4772

1

T3

6

T7

2

T12

26

auto[1]

2198

1

T2

2

T3

2

T12

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	234	1			T15	2		T49	4		T23	2
auto[134217728:268435455]	240	1			T12	2		T140	2		T57	2
auto[268435456:402653183]	236	1			T7	2		T15	2		T23	2
auto[402653184:536870911]	210	1			T126	2		T54	2		T306	2
auto[536870912:671088639]	206	1			T13	2		T16	2		T23	2
auto[671088640:805306367]	230	1			T2	2		T12	2		T15	2
auto[805306368:939524095]	226	1			T3	2		T35	2		T123	2
auto[939524096:1073741823]	254	1			T12	2		T34	2		T23	2
auto[1073741824:1207959551]	204	1			T13	2		T37	2		T23	2
auto[1207959552:1342177279]	216	1			T15	2		T23	4		T57	2
auto[1342177280:1476395007]	210	1			T15	2		T16	2		T34	4
auto[1476395008:1610612735]	242	1			T12	2		T37	2		T23	2
auto[1610612736:1744830463]	210	1			T12	4		T23	2		T120	2
auto[1744830464:1879048191]	234	1			T12	2		T13	4		T15	2
auto[1879048192:2013265919]	218	1			T15	2		T34	4		T23	4
auto[2013265920:2147483647]	214	1			T48	2		T182	2		T76	2
auto[2147483648:2281701375]	208	1			T23	2		T218	2		T126	2
auto[2281701376:2415919103]	188	1			T12	2		T34	2		T26	2
auto[2415919104:2550136831]	198	1			T3	2		T26	2		T23	4
auto[2550136832:2684354559]	184	1			T13	2		T37	2		T137	2
auto[2684354560:2818572287]	194	1			T12	2		T16	2		T49	2
auto[2818572288:2952790015]	220	1			T13	6		T15	2		T23	4
auto[2952790016:3087007743]	230	1			T23	4		T35	2		T21	2
auto[3087007744:3221225471]	228	1			T3	2		T16	2		T49	2
auto[3221225472:3355443199]	226	1			T33	2		T23	6		T35	4
auto[3355443200:3489660927]	222	1			T12	2		T33	2		T23	2
auto[3489660928:3623878655]	182	1			T12	4		T16	2		T137	2
auto[3623878656:3758096383]	202	1			T12	2		T13	2		T23	6
auto[3758096384:3892314111]	222	1			T16	2		T33	2		T23	6
auto[3892314112:4026531839]	228	1			T12	4		T49	2		T23	2
auto[4026531840:4160749567]	238	1			T23	2		T137	2		T51	2
auto[4160749568:4294967295]	216	1			T3	2		T23	2		T57	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	158	1			T15	2		T49	2		T23	2
auto[0:134217727]	auto[1]	76	1			T49	2		T120	2		T51	2
auto[134217728:268435455]	auto[0]	154	1			T140	2		T122	2		T59	2
auto[134217728:268435455]	auto[1]	86	1			T12	2		T57	2		T54	2
auto[268435456:402653183]	auto[0]	178	1			T7	2		T15	2		T23	2
auto[268435456:402653183]	auto[1]	58	1			T21	2		T128	2		T283	2
auto[402653184:536870911]	auto[0]	144	1			T126	2		T5	2		T128	2
auto[402653184:536870911]	auto[1]	66	1			T54	2		T306	2		T86	2
auto[536870912:671088639]	auto[0]	140	1			T4	2		T142	2		T53	2
auto[536870912:671088639]	auto[1]	66	1			T13	2		T16	2		T23	2
auto[671088640:805306367]	auto[0]	132	1			T12	2		T15	2		T34	2
auto[671088640:805306367]	auto[1]	98	1			T2	2		T16	2		T57	2
auto[805306368:939524095]	auto[0]	148	1			T35	2		T59	2		T236	2
auto[805306368:939524095]	auto[1]	78	1			T3	2		T123	2		T124	2
auto[939524096:1073741823]	auto[0]	178	1			T34	2		T23	2		T35	2
auto[939524096:1073741823]	auto[1]	76	1			T12	2		T122	2		T192	2
auto[1073741824:1207959551]	auto[0]	124	1			T37	2		T23	2		T127	2
auto[1073741824:1207959551]	auto[1]	80	1			T13	2		T192	2		T59	2
auto[1207959552:1342177279]	auto[0]	150	1			T15	2		T23	4		T57	2
auto[1207959552:1342177279]	auto[1]	66	1			T47	2		T129	2		T39	2
auto[1342177280:1476395007]	auto[0]	144	1			T15	2		T16	2		T34	2
auto[1342177280:1476395007]	auto[1]	66	1			T34	2		T126	2		T54	2
auto[1476395008:1610612735]	auto[0]	166	1			T12	2		T23	2		T122	2
auto[1476395008:1610612735]	auto[1]	76	1			T37	2		T47	2		T116	2
auto[1610612736:1744830463]	auto[0]	162	1			T12	4		T23	2		T51	2
auto[1610612736:1744830463]	auto[1]	48	1			T120	2		T54	2		T46	2
auto[1744830464:1879048191]	auto[0]	172	1			T12	2		T13	4		T15	2
auto[1744830464:1879048191]	auto[1]	62	1			T236	2		T56	2		T283	2
auto[1879048192:2013265919]	auto[0]	158	1			T15	2		T34	2		T23	4
auto[1879048192:2013265919]	auto[1]	60	1			T34	2		T226	2		T78	2
auto[2013265920:2147483647]	auto[0]	160	1			T48	2		T182	2		T76	2
auto[2013265920:2147483647]	auto[1]	54	1			T237	2		T39	2		T221	2
auto[2147483648:2281701375]	auto[0]	154	1			T23	2		T218	2		T126	2
auto[2147483648:2281701375]	auto[1]	54	1			T53	2		T58	2		T226	2
auto[2281701376:2415919103]	auto[0]	132	1			T12	2		T34	2		T23	4
auto[2281701376:2415919103]	auto[1]	56	1			T26	2		T140	2		T120	2
auto[2415919104:2550136831]	auto[0]	132	1			T3	2		T23	2		T57	2
auto[2415919104:2550136831]	auto[1]	66	1			T26	2		T23	2		T125	2
auto[2550136832:2684354559]	auto[0]	130	1			T13	2		T37	2		T137	2
auto[2550136832:2684354559]	auto[1]	54	1			T124	2		T127	2		T237	2
auto[2684354560:2818572287]	auto[0]	136	1			T12	2		T23	6		T4	2
auto[2684354560:2818572287]	auto[1]	58	1			T16	2		T49	2		T58	2
auto[2818572288:2952790015]	auto[0]	148	1			T15	2		T23	4		T140	2
auto[2818572288:2952790015]	auto[1]	72	1			T13	6		T22	2		T76	2
auto[2952790016:3087007743]	auto[0]	164	1			T23	4		T35	2		T21	2
auto[2952790016:3087007743]	auto[1]	66	1			T273	2		T197	2		T231	2
auto[3087007744:3221225471]	auto[0]	146	1			T3	2		T16	2		T49	2
auto[3087007744:3221225471]	auto[1]	82	1			T192	2		T142	2		T77	2
auto[3221225472:3355443199]	auto[0]	144	1			T23	4		T35	4		T140	2
auto[3221225472:3355443199]	auto[1]	82	1			T33	2		T23	2		T230	2
auto[3355443200:3489660927]	auto[0]	154	1			T12	2		T33	2		T23	2
auto[3355443200:3489660927]	auto[1]	68	1			T5	2		T383	2		T197	2
auto[3489660928:3623878655]	auto[0]	134	1			T12	4		T16	2		T137	2
auto[3489660928:3623878655]	auto[1]	48	1			T124	2		T59	2		T5	2
auto[3623878656:3758096383]	auto[0]	130	1			T12	2		T23	2		T122	2
auto[3623878656:3758096383]	auto[1]	72	1			T13	2		T23	4		T85	2
auto[3758096384:3892314111]	auto[0]	152	1			T33	2		T23	4		T35	2
auto[3758096384:3892314111]	auto[1]	70	1			T16	2		T23	2		T57	2
auto[3892314112:4026531839]	auto[0]	150	1			T12	4		T49	2		T23	2
auto[3892314112:4026531839]	auto[1]	78	1			T4	2		T125	2		T59	2
auto[4026531840:4160749567]	auto[0]	150	1			T137	2		T182	2		T54	2
auto[4026531840:4160749567]	auto[1]	88	1			T23	2		T51	2		T226	2
auto[4160749568:4294967295]	auto[0]	148	1			T3	2		T23	2		T218	2
auto[4160749568:4294967295]	auto[1]	68	1			T57	2		T38	2		T192	2