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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4738 1 T3 6 T7 2 T12 26
auto[1] 2232 1 T2 2 T3 2 T12 4



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 186 1 T35 2 T38 2 T126 2
auto[134217728:268435455] 178 1 T33 2 T34 2 T137 2
auto[268435456:402653183] 238 1 T3 2 T12 2 T13 2
auto[402653184:536870911] 194 1 T23 4 T137 2 T120 2
auto[536870912:671088639] 180 1 T3 2 T12 4 T15 2
auto[671088640:805306367] 206 1 T13 2 T37 2 T137 2
auto[805306368:939524095] 188 1 T23 2 T48 2 T122 2
auto[939524096:1073741823] 230 1 T15 2 T16 2 T34 2
auto[1073741824:1207959551] 242 1 T15 2 T49 2 T23 2
auto[1207959552:1342177279] 218 1 T12 2 T13 2 T34 2
auto[1342177280:1476395007] 212 1 T12 2 T13 2 T15 2
auto[1476395008:1610612735] 226 1 T16 2 T23 2 T140 2
auto[1610612736:1744830463] 218 1 T12 2 T37 2 T57 2
auto[1744830464:1879048191] 240 1 T34 2 T54 2 T24 2
auto[1879048192:2013265919] 224 1 T15 2 T49 2 T23 4
auto[2013265920:2147483647] 206 1 T34 2 T23 4 T35 2
auto[2147483648:2281701375] 202 1 T12 2 T49 2 T23 4
auto[2281701376:2415919103] 250 1 T15 2 T23 6 T195 2
auto[2415919104:2550136831] 228 1 T49 2 T23 4 T137 2
auto[2550136832:2684354559] 202 1 T23 6 T140 2 T4 2
auto[2684354560:2818572287] 214 1 T12 2 T33 2 T49 2
auto[2818572288:2952790015] 250 1 T7 2 T13 2 T33 2
auto[2952790016:3087007743] 218 1 T12 2 T13 2 T37 2
auto[3087007744:3221225471] 232 1 T15 2 T34 2 T26 2
auto[3221225472:3355443199] 208 1 T12 2 T23 4 T4 2
auto[3355443200:3489660927] 186 1 T16 2 T23 4 T35 2
auto[3489660928:3623878655] 242 1 T12 2 T13 2 T16 2
auto[3623878656:3758096383] 248 1 T2 2 T12 4 T13 2
auto[3758096384:3892314111] 214 1 T3 2 T13 2 T16 2
auto[3892314112:4026531839] 230 1 T3 2 T12 2 T26 2
auto[4026531840:4160749567] 252 1 T16 2 T34 2 T23 4
auto[4160749568:4294967295] 208 1 T12 2 T16 2 T23 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 116 1 T35 2 T126 2 T190 2
auto[0:134217727] auto[1] 70 1 T38 2 T190 2 T54 2
auto[134217728:268435455] auto[0] 114 1 T137 2 T54 2 T85 2
auto[134217728:268435455] auto[1] 64 1 T33 2 T34 2 T236 2
auto[268435456:402653183] auto[0] 170 1 T12 2 T13 2 T140 2
auto[268435456:402653183] auto[1] 68 1 T3 2 T71 2 T46 2
auto[402653184:536870911] auto[0] 126 1 T23 4 T137 2 T122 2
auto[402653184:536870911] auto[1] 68 1 T120 2 T122 2 T51 2
auto[536870912:671088639] auto[0] 118 1 T3 2 T12 4 T184 2
auto[536870912:671088639] auto[1] 62 1 T15 2 T21 4 T5 2
auto[671088640:805306367] auto[0] 146 1 T13 2 T37 2 T137 2
auto[671088640:805306367] auto[1] 60 1 T183 2 T188 2 T174 2
auto[805306368:939524095] auto[0] 126 1 T48 2 T122 2 T184 2
auto[805306368:939524095] auto[1] 62 1 T23 2 T124 2 T142 2
auto[939524096:1073741823] auto[0] 152 1 T16 2 T34 2 T37 2
auto[939524096:1073741823] auto[1] 78 1 T15 2 T4 2 T143 2
auto[1073741824:1207959551] auto[0] 188 1 T23 2 T236 2 T127 2
auto[1073741824:1207959551] auto[1] 54 1 T15 2 T49 2 T21 2
auto[1207959552:1342177279] auto[0] 142 1 T12 2 T13 2 T34 2
auto[1207959552:1342177279] auto[1] 76 1 T143 4 T53 2 T128 2
auto[1342177280:1476395007] auto[0] 152 1 T13 2 T126 2 T127 2
auto[1342177280:1476395007] auto[1] 60 1 T12 2 T15 2 T57 2
auto[1476395008:1610612735] auto[0] 154 1 T16 2 T140 2 T195 2
auto[1476395008:1610612735] auto[1] 72 1 T23 2 T57 2 T184 2
auto[1610612736:1744830463] auto[0] 148 1 T37 2 T142 2 T76 2
auto[1610612736:1744830463] auto[1] 70 1 T12 2 T57 2 T120 2
auto[1744830464:1879048191] auto[0] 174 1 T34 2 T24 2 T47 2
auto[1744830464:1879048191] auto[1] 66 1 T54 2 T56 4 T183 2
auto[1879048192:2013265919] auto[0] 166 1 T15 2 T49 2 T23 4
auto[1879048192:2013265919] auto[1] 58 1 T21 2 T124 2 T218 2
auto[2013265920:2147483647] auto[0] 140 1 T23 2 T35 2 T54 2
auto[2013265920:2147483647] auto[1] 66 1 T34 2 T23 2 T184 4
auto[2147483648:2281701375] auto[0] 126 1 T12 2 T23 2 T122 2
auto[2147483648:2281701375] auto[1] 76 1 T49 2 T23 2 T54 2
auto[2281701376:2415919103] auto[0] 184 1 T15 2 T23 4 T195 2
auto[2281701376:2415919103] auto[1] 66 1 T23 2 T58 2 T183 4
auto[2415919104:2550136831] auto[0] 164 1 T49 2 T23 4 T17 2
auto[2415919104:2550136831] auto[1] 64 1 T137 2 T59 2 T283 2
auto[2550136832:2684354559] auto[0] 126 1 T23 4 T140 2 T4 2
auto[2550136832:2684354559] auto[1] 76 1 T23 2 T244 2 T54 2
auto[2684354560:2818572287] auto[0] 146 1 T12 2 T33 2 T49 2
auto[2684354560:2818572287] auto[1] 68 1 T58 2 T55 2 T78 2
auto[2818572288:2952790015] auto[0] 184 1 T7 2 T13 2 T33 2
auto[2818572288:2952790015] auto[1] 66 1 T120 2 T59 2 T17 2
auto[2952790016:3087007743] auto[0] 150 1 T12 2 T13 2 T37 2
auto[2952790016:3087007743] auto[1] 68 1 T124 2 T17 2 T54 2
auto[3087007744:3221225471] auto[0] 146 1 T23 2 T35 2 T59 2
auto[3087007744:3221225471] auto[1] 86 1 T15 2 T34 2 T26 2
auto[3221225472:3355443199] auto[0] 132 1 T12 2 T23 4 T218 2
auto[3221225472:3355443199] auto[1] 76 1 T4 2 T5 2 T174 2
auto[3355443200:3489660927] auto[0] 114 1 T16 2 T35 2 T48 2
auto[3355443200:3489660927] auto[1] 72 1 T23 4 T57 4 T51 2
auto[3489660928:3623878655] auto[0] 156 1 T12 2 T16 2 T23 2
auto[3489660928:3623878655] auto[1] 86 1 T13 2 T236 2 T143 2
auto[3623878656:3758096383] auto[0] 160 1 T12 4 T13 2 T15 2
auto[3623878656:3758096383] auto[1] 88 1 T2 2 T23 4 T123 2
auto[3758096384:3892314111] auto[0] 146 1 T3 2 T16 2 T23 2
auto[3758096384:3892314111] auto[1] 68 1 T13 2 T57 2 T218 2
auto[3892314112:4026531839] auto[0] 148 1 T3 2 T12 2 T23 2
auto[3892314112:4026531839] auto[1] 82 1 T26 2 T38 2 T17 2
auto[4026531840:4160749567] auto[0] 180 1 T16 2 T34 2 T23 4
auto[4026531840:4160749567] auto[1] 72 1 T59 2 T142 2 T46 2
auto[4160749568:4294967295] auto[0] 144 1 T12 2 T23 2 T137 2
auto[4160749568:4294967295] auto[1] 64 1 T16 2 T21 2 T53 2

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