Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.04 98.07 98.33 100.00 99.02 98.41 91.17


Total test records in report: 1086
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T1004 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1746808667 Jul 06 04:45:47 PM PDT 24 Jul 06 04:45:48 PM PDT 24 35920853 ps
T1005 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1412126098 Jul 06 04:45:32 PM PDT 24 Jul 06 04:45:34 PM PDT 24 161127187 ps
T1006 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2443560946 Jul 06 04:45:33 PM PDT 24 Jul 06 04:45:35 PM PDT 24 154844839 ps
T1007 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1910444034 Jul 06 04:45:36 PM PDT 24 Jul 06 04:45:39 PM PDT 24 143885269 ps
T1008 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.509560602 Jul 06 04:45:42 PM PDT 24 Jul 06 04:45:44 PM PDT 24 196160570 ps
T1009 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.516159722 Jul 06 04:45:49 PM PDT 24 Jul 06 04:45:50 PM PDT 24 34550348 ps
T1010 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.801220672 Jul 06 04:45:48 PM PDT 24 Jul 06 04:45:49 PM PDT 24 9784343 ps
T1011 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2847329448 Jul 06 04:45:00 PM PDT 24 Jul 06 04:45:02 PM PDT 24 32751103 ps
T1012 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1495720690 Jul 06 04:45:16 PM PDT 24 Jul 06 04:45:27 PM PDT 24 4759807602 ps
T1013 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.708113919 Jul 06 04:45:17 PM PDT 24 Jul 06 04:45:19 PM PDT 24 173083448 ps
T1014 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.687551646 Jul 06 04:45:33 PM PDT 24 Jul 06 04:45:34 PM PDT 24 56861679 ps
T1015 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.4045185219 Jul 06 04:44:59 PM PDT 24 Jul 06 04:45:01 PM PDT 24 102543113 ps
T1016 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1541568225 Jul 06 04:45:37 PM PDT 24 Jul 06 04:45:39 PM PDT 24 10537286 ps
T1017 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2520499565 Jul 06 04:45:34 PM PDT 24 Jul 06 04:45:48 PM PDT 24 4179555111 ps
T1018 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3741690664 Jul 06 04:45:17 PM PDT 24 Jul 06 04:45:32 PM PDT 24 866993801 ps
T1019 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1080179161 Jul 06 04:44:58 PM PDT 24 Jul 06 04:44:59 PM PDT 24 11774800 ps
T1020 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.319756134 Jul 06 04:45:11 PM PDT 24 Jul 06 04:45:14 PM PDT 24 98036757 ps
T1021 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2282315832 Jul 06 04:45:48 PM PDT 24 Jul 06 04:45:49 PM PDT 24 31853304 ps
T1022 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1536404372 Jul 06 04:45:21 PM PDT 24 Jul 06 04:45:23 PM PDT 24 74588244 ps
T1023 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2649909315 Jul 06 04:45:49 PM PDT 24 Jul 06 04:45:50 PM PDT 24 18179740 ps
T150 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2122212669 Jul 06 04:45:20 PM PDT 24 Jul 06 04:45:24 PM PDT 24 99650526 ps
T1024 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1145330216 Jul 06 04:45:47 PM PDT 24 Jul 06 04:45:48 PM PDT 24 13122213 ps
T1025 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1114547506 Jul 06 04:45:43 PM PDT 24 Jul 06 04:45:47 PM PDT 24 88837530 ps
T1026 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3619455750 Jul 06 04:45:40 PM PDT 24 Jul 06 04:45:41 PM PDT 24 9197819 ps
T152 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1109343414 Jul 06 04:45:30 PM PDT 24 Jul 06 04:45:35 PM PDT 24 180597056 ps
T1027 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3254714976 Jul 06 04:45:21 PM PDT 24 Jul 06 04:45:23 PM PDT 24 23512466 ps
T1028 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1655270067 Jul 06 04:45:24 PM PDT 24 Jul 06 04:45:25 PM PDT 24 37687073 ps
T1029 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3607542227 Jul 06 04:45:28 PM PDT 24 Jul 06 04:45:32 PM PDT 24 135226728 ps
T1030 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.4095374296 Jul 06 04:45:42 PM PDT 24 Jul 06 04:45:43 PM PDT 24 55695293 ps
T1031 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1649484698 Jul 06 04:45:23 PM PDT 24 Jul 06 04:45:25 PM PDT 24 205087937 ps
T1032 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.259699021 Jul 06 04:45:23 PM PDT 24 Jul 06 04:45:24 PM PDT 24 23253032 ps
T1033 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.349088278 Jul 06 04:45:25 PM PDT 24 Jul 06 04:45:27 PM PDT 24 197332376 ps
T1034 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2188069538 Jul 06 04:45:39 PM PDT 24 Jul 06 04:45:41 PM PDT 24 34395178 ps
T1035 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.332641539 Jul 06 04:45:38 PM PDT 24 Jul 06 04:45:40 PM PDT 24 11438744 ps
T1036 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.648679912 Jul 06 04:45:15 PM PDT 24 Jul 06 04:45:19 PM PDT 24 119556957 ps
T1037 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.815568259 Jul 06 04:45:29 PM PDT 24 Jul 06 04:45:30 PM PDT 24 39043973 ps
T1038 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3819396255 Jul 06 04:44:52 PM PDT 24 Jul 06 04:44:57 PM PDT 24 85715164 ps
T1039 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.600429931 Jul 06 04:45:20 PM PDT 24 Jul 06 04:45:21 PM PDT 24 8139577 ps
T1040 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2082329416 Jul 06 04:45:07 PM PDT 24 Jul 06 04:45:11 PM PDT 24 353327878 ps
T1041 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3245886127 Jul 06 04:45:15 PM PDT 24 Jul 06 04:45:18 PM PDT 24 106782333 ps
T151 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1074071344 Jul 06 04:45:42 PM PDT 24 Jul 06 04:45:53 PM PDT 24 1197635461 ps
T1042 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3733161662 Jul 06 04:45:00 PM PDT 24 Jul 06 04:45:06 PM PDT 24 2448812490 ps
T1043 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2907985373 Jul 06 04:45:00 PM PDT 24 Jul 06 04:45:02 PM PDT 24 171241551 ps
T1044 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3258304840 Jul 06 04:45:16 PM PDT 24 Jul 06 04:45:18 PM PDT 24 46815996 ps
T1045 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.575407378 Jul 06 04:45:23 PM PDT 24 Jul 06 04:45:25 PM PDT 24 437526444 ps
T1046 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1145455371 Jul 06 04:45:37 PM PDT 24 Jul 06 04:45:39 PM PDT 24 80764429 ps
T1047 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2599855953 Jul 06 04:44:58 PM PDT 24 Jul 06 04:45:01 PM PDT 24 245779726 ps
T1048 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.218144982 Jul 06 04:45:34 PM PDT 24 Jul 06 04:45:36 PM PDT 24 26474545 ps
T1049 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2367933926 Jul 06 04:44:52 PM PDT 24 Jul 06 04:44:53 PM PDT 24 111103736 ps
T1050 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3447318880 Jul 06 04:45:37 PM PDT 24 Jul 06 04:45:40 PM PDT 24 35816571 ps
T1051 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2935987662 Jul 06 04:45:34 PM PDT 24 Jul 06 04:45:39 PM PDT 24 319960945 ps
T1052 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3668263417 Jul 06 04:45:10 PM PDT 24 Jul 06 04:45:12 PM PDT 24 55459324 ps
T1053 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.453972080 Jul 06 04:45:18 PM PDT 24 Jul 06 04:45:21 PM PDT 24 268430946 ps
T1054 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.288732111 Jul 06 04:44:51 PM PDT 24 Jul 06 04:44:56 PM PDT 24 56430390 ps
T1055 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.441527992 Jul 06 04:45:05 PM PDT 24 Jul 06 04:45:08 PM PDT 24 57763238 ps
T1056 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.57129626 Jul 06 04:45:49 PM PDT 24 Jul 06 04:45:50 PM PDT 24 19705111 ps
T1057 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3661816347 Jul 06 04:45:41 PM PDT 24 Jul 06 04:45:42 PM PDT 24 37723166 ps
T1058 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2757711283 Jul 06 04:45:16 PM PDT 24 Jul 06 04:45:18 PM PDT 24 81295092 ps
T1059 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1896601231 Jul 06 04:45:38 PM PDT 24 Jul 06 04:45:44 PM PDT 24 442386479 ps
T1060 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.231372955 Jul 06 04:45:35 PM PDT 24 Jul 06 04:45:37 PM PDT 24 179719707 ps
T1061 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3812197809 Jul 06 04:45:07 PM PDT 24 Jul 06 04:45:09 PM PDT 24 24953261 ps
T1062 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1697156370 Jul 06 04:45:16 PM PDT 24 Jul 06 04:45:23 PM PDT 24 650212988 ps
T1063 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.172794248 Jul 06 04:45:07 PM PDT 24 Jul 06 04:45:10 PM PDT 24 171722314 ps
T1064 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2665307703 Jul 06 04:45:05 PM PDT 24 Jul 06 04:45:06 PM PDT 24 716732042 ps
T1065 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1837603079 Jul 06 04:45:47 PM PDT 24 Jul 06 04:45:48 PM PDT 24 37969476 ps
T1066 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3142796644 Jul 06 04:44:53 PM PDT 24 Jul 06 04:45:05 PM PDT 24 906178101 ps
T1067 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1475877378 Jul 06 04:45:35 PM PDT 24 Jul 06 04:45:37 PM PDT 24 68655507 ps
T1068 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3009673819 Jul 06 04:45:36 PM PDT 24 Jul 06 04:45:42 PM PDT 24 117179201 ps
T1069 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.389711061 Jul 06 04:45:33 PM PDT 24 Jul 06 04:45:35 PM PDT 24 100656365 ps
T1070 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.946118704 Jul 06 04:44:52 PM PDT 24 Jul 06 04:44:54 PM PDT 24 27169598 ps
T1071 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1104110504 Jul 06 04:45:23 PM PDT 24 Jul 06 04:45:24 PM PDT 24 28110315 ps
T1072 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2842502696 Jul 06 04:44:52 PM PDT 24 Jul 06 04:44:55 PM PDT 24 553310498 ps
T1073 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2919658781 Jul 06 04:45:00 PM PDT 24 Jul 06 04:45:15 PM PDT 24 257504511 ps
T1074 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2293161986 Jul 06 04:45:15 PM PDT 24 Jul 06 04:45:18 PM PDT 24 191092458 ps
T1075 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3870923604 Jul 06 04:45:16 PM PDT 24 Jul 06 04:45:19 PM PDT 24 63523627 ps
T1076 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3794477654 Jul 06 04:45:07 PM PDT 24 Jul 06 04:45:14 PM PDT 24 133102565 ps
T1077 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2797808790 Jul 06 04:45:28 PM PDT 24 Jul 06 04:45:30 PM PDT 24 77483166 ps
T1078 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2225905643 Jul 06 04:45:12 PM PDT 24 Jul 06 04:45:14 PM PDT 24 27177398 ps
T1079 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2102981804 Jul 06 04:45:42 PM PDT 24 Jul 06 04:45:43 PM PDT 24 11695542 ps
T1080 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1878026241 Jul 06 04:44:53 PM PDT 24 Jul 06 04:45:07 PM PDT 24 440848351 ps
T1081 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2903850891 Jul 06 04:45:41 PM PDT 24 Jul 06 04:45:44 PM PDT 24 58395842 ps
T1082 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4053428666 Jul 06 04:45:35 PM PDT 24 Jul 06 04:45:37 PM PDT 24 100056721 ps
T1083 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.191534365 Jul 06 04:45:17 PM PDT 24 Jul 06 04:45:21 PM PDT 24 224971332 ps
T1084 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3073091533 Jul 06 04:45:41 PM PDT 24 Jul 06 04:45:43 PM PDT 24 120926516 ps
T1085 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3404137621 Jul 06 04:45:51 PM PDT 24 Jul 06 04:45:52 PM PDT 24 15872544 ps
T1086 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4235405196 Jul 06 04:45:22 PM PDT 24 Jul 06 04:45:24 PM PDT 24 15353243 ps

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.500827856
Short name T12
Test name
Test status
Simulation time 1110433541 ps
CPU time 11.65 seconds
Started Jul 06 04:47:57 PM PDT 24
Finished Jul 06 04:48:09 PM PDT 24
Peak memory 222472 kb
Host smart-6abb169a-81a5-45f3-b5c2-772ec645a7d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500827856 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.500827856
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.837595954
Short name T23
Test name
Test status
Simulation time 2126626293 ps
CPU time 53.49 seconds
Started Jul 06 04:48:49 PM PDT 24
Finished Jul 06 04:49:44 PM PDT 24
Peak memory 222448 kb
Host smart-c7e44e48-1751-40c0-bd54-a59838c8e4c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837595954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.837595954
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2463308457
Short name T5
Test name
Test status
Simulation time 1940079938 ps
CPU time 30.67 seconds
Started Jul 06 04:47:18 PM PDT 24
Finished Jul 06 04:47:49 PM PDT 24
Peak memory 222536 kb
Host smart-b442a202-11fc-4b13-8e3f-e39afb2b6f6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463308457 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2463308457
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.4262112585
Short name T42
Test name
Test status
Simulation time 632663020 ps
CPU time 10.36 seconds
Started Jul 06 04:46:47 PM PDT 24
Finished Jul 06 04:46:58 PM PDT 24
Peak memory 237932 kb
Host smart-f53088b9-3747-466b-862d-6c20e762ddf7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262112585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.4262112585
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3608585657
Short name T54
Test name
Test status
Simulation time 2062519992 ps
CPU time 31.07 seconds
Started Jul 06 04:47:43 PM PDT 24
Finished Jul 06 04:48:14 PM PDT 24
Peak memory 215112 kb
Host smart-3dec9781-b4cc-45d4-8ccc-c5fe51d08412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608585657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3608585657
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3360058990
Short name T183
Test name
Test status
Simulation time 4500051244 ps
CPU time 49.96 seconds
Started Jul 06 04:48:50 PM PDT 24
Finished Jul 06 04:49:41 PM PDT 24
Peak memory 222452 kb
Host smart-c3c9e42d-1bf2-4660-926d-93b7da29aec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360058990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3360058990
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3005386876
Short name T7
Test name
Test status
Simulation time 305195949 ps
CPU time 2.15 seconds
Started Jul 06 04:46:43 PM PDT 24
Finished Jul 06 04:46:45 PM PDT 24
Peak memory 209192 kb
Host smart-227c9556-8aa1-4b49-b91c-4d7393642caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005386876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3005386876
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2424600203
Short name T127
Test name
Test status
Simulation time 3836705239 ps
CPU time 26.4 seconds
Started Jul 06 04:48:05 PM PDT 24
Finished Jul 06 04:48:33 PM PDT 24
Peak memory 214964 kb
Host smart-e3adbd12-7b29-4258-9eb6-f97c6078aa90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2424600203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2424600203
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3344939096
Short name T16
Test name
Test status
Simulation time 78038167 ps
CPU time 4.07 seconds
Started Jul 06 04:46:50 PM PDT 24
Finished Jul 06 04:46:54 PM PDT 24
Peak memory 214356 kb
Host smart-bcc01b23-e422-46ef-8ec8-873d3d20a8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344939096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3344939096
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.572025625
Short name T107
Test name
Test status
Simulation time 592231706 ps
CPU time 8.35 seconds
Started Jul 06 04:45:06 PM PDT 24
Finished Jul 06 04:45:14 PM PDT 24
Peak memory 220028 kb
Host smart-d3765873-4243-4196-9d39-57619861e0d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572025625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.572025625
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1036860380
Short name T364
Test name
Test status
Simulation time 167240120 ps
CPU time 9.13 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:48:58 PM PDT 24
Peak memory 214192 kb
Host smart-71fd8cec-67bc-406e-8b5d-d481d0d041c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1036860380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1036860380
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1993589863
Short name T174
Test name
Test status
Simulation time 3696973588 ps
CPU time 36.74 seconds
Started Jul 06 04:47:53 PM PDT 24
Finished Jul 06 04:48:31 PM PDT 24
Peak memory 222436 kb
Host smart-7c13ef56-7895-4a59-b041-f72ae2ac7331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993589863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1993589863
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1749622325
Short name T1
Test name
Test status
Simulation time 132702892 ps
CPU time 3.49 seconds
Started Jul 06 04:46:36 PM PDT 24
Finished Jul 06 04:46:40 PM PDT 24
Peak memory 210200 kb
Host smart-0c7d1c85-eada-4398-9d43-143fbcc5d435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749622325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1749622325
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1806433537
Short name T239
Test name
Test status
Simulation time 895246788 ps
CPU time 41.51 seconds
Started Jul 06 04:48:59 PM PDT 24
Finished Jul 06 04:49:42 PM PDT 24
Peak memory 214228 kb
Host smart-60958793-7c63-49e3-bd23-2aca4428f730
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1806433537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1806433537
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.4234498762
Short name T21
Test name
Test status
Simulation time 448517575 ps
CPU time 5.13 seconds
Started Jul 06 04:47:51 PM PDT 24
Finished Jul 06 04:47:57 PM PDT 24
Peak memory 214224 kb
Host smart-ca65bcc1-6b88-4968-ba89-c5403df0738b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234498762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4234498762
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.258904537
Short name T947
Test name
Test status
Simulation time 220188027 ps
CPU time 3.06 seconds
Started Jul 06 04:45:27 PM PDT 24
Finished Jul 06 04:45:31 PM PDT 24
Peak memory 213920 kb
Host smart-b18466fe-cf31-46cb-9f18-a5981c54a98b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258904537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.258904537
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1768534377
Short name T196
Test name
Test status
Simulation time 1774466675 ps
CPU time 48.56 seconds
Started Jul 06 04:47:11 PM PDT 24
Finished Jul 06 04:48:00 PM PDT 24
Peak memory 222404 kb
Host smart-3ec61554-4557-444b-975f-1763b57b83d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768534377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1768534377
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.3837655078
Short name T15
Test name
Test status
Simulation time 1782785022 ps
CPU time 25.48 seconds
Started Jul 06 04:47:15 PM PDT 24
Finished Jul 06 04:47:41 PM PDT 24
Peak memory 222540 kb
Host smart-801a72a4-6d31-40a8-856c-fc79b0b93ac0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837655078 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.3837655078
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3650249570
Short name T78
Test name
Test status
Simulation time 164333453 ps
CPU time 7.9 seconds
Started Jul 06 04:46:49 PM PDT 24
Finished Jul 06 04:46:58 PM PDT 24
Peak memory 215120 kb
Host smart-26289e35-5575-451b-8e01-99d266e53415
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3650249570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3650249570
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.353216724
Short name T275
Test name
Test status
Simulation time 12201714928 ps
CPU time 75.6 seconds
Started Jul 06 04:46:50 PM PDT 24
Finished Jul 06 04:48:06 PM PDT 24
Peak memory 216804 kb
Host smart-b76a27dd-5772-4a90-b9bc-1c7c87972552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=353216724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.353216724
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2164882294
Short name T64
Test name
Test status
Simulation time 1458982896 ps
CPU time 35.53 seconds
Started Jul 06 04:48:49 PM PDT 24
Finished Jul 06 04:49:25 PM PDT 24
Peak memory 215760 kb
Host smart-4e2b49d7-6b68-40bb-8666-81f989d12f2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164882294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2164882294
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3241681304
Short name T305
Test name
Test status
Simulation time 120053896 ps
CPU time 6.28 seconds
Started Jul 06 04:46:35 PM PDT 24
Finished Jul 06 04:46:41 PM PDT 24
Peak memory 214224 kb
Host smart-3d3147f4-4545-4667-b739-ccb8588e5d93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241681304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3241681304
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2069000116
Short name T37
Test name
Test status
Simulation time 312893734 ps
CPU time 4.57 seconds
Started Jul 06 04:47:20 PM PDT 24
Finished Jul 06 04:47:25 PM PDT 24
Peak memory 214336 kb
Host smart-cd5cfbf3-3c05-40f3-8cb2-29567be0ca06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069000116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2069000116
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.79235821
Short name T19
Test name
Test status
Simulation time 124416706 ps
CPU time 4.66 seconds
Started Jul 06 04:47:21 PM PDT 24
Finished Jul 06 04:47:26 PM PDT 24
Peak memory 209224 kb
Host smart-7bd87e1b-a3d4-4e27-8829-ffd9bd2ad8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79235821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.79235821
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3552178109
Short name T166
Test name
Test status
Simulation time 134504861 ps
CPU time 3.42 seconds
Started Jul 06 04:46:52 PM PDT 24
Finished Jul 06 04:46:56 PM PDT 24
Peak memory 222536 kb
Host smart-a437b7b7-4eea-4998-83a2-83b38e196f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552178109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3552178109
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3779725501
Short name T60
Test name
Test status
Simulation time 1480572820 ps
CPU time 40.14 seconds
Started Jul 06 04:48:49 PM PDT 24
Finished Jul 06 04:49:30 PM PDT 24
Peak memory 222452 kb
Host smart-a10a919f-aedf-40b0-99fb-bc1c35b421af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779725501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3779725501
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2074124588
Short name T17
Test name
Test status
Simulation time 383838709 ps
CPU time 2.9 seconds
Started Jul 06 04:48:24 PM PDT 24
Finished Jul 06 04:48:27 PM PDT 24
Peak memory 221852 kb
Host smart-b7a9314f-2e35-43a9-bfdb-ac1158faea69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074124588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2074124588
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1959361979
Short name T50
Test name
Test status
Simulation time 2976978743 ps
CPU time 29.51 seconds
Started Jul 06 04:46:51 PM PDT 24
Finished Jul 06 04:47:21 PM PDT 24
Peak memory 220380 kb
Host smart-4703e41a-8a04-4d60-a85e-566887b33609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959361979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1959361979
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1120507551
Short name T90
Test name
Test status
Simulation time 232280438 ps
CPU time 8.16 seconds
Started Jul 06 04:48:02 PM PDT 24
Finished Jul 06 04:48:11 PM PDT 24
Peak memory 220784 kb
Host smart-e46becf5-05af-41de-9092-d4ad005e3af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120507551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1120507551
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3030383320
Short name T737
Test name
Test status
Simulation time 280030203 ps
CPU time 4.33 seconds
Started Jul 06 04:47:01 PM PDT 24
Finished Jul 06 04:47:05 PM PDT 24
Peak memory 214180 kb
Host smart-1f2681a0-e71f-4e2e-877b-4344fe93b1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030383320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3030383320
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2156457038
Short name T320
Test name
Test status
Simulation time 60547828 ps
CPU time 4.6 seconds
Started Jul 06 04:47:47 PM PDT 24
Finished Jul 06 04:47:52 PM PDT 24
Peak memory 215556 kb
Host smart-d1045fa0-e2b3-412d-851b-7ed14e71625e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2156457038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2156457038
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3662466199
Short name T386
Test name
Test status
Simulation time 4252605175 ps
CPU time 37.06 seconds
Started Jul 06 04:47:33 PM PDT 24
Finished Jul 06 04:48:10 PM PDT 24
Peak memory 214376 kb
Host smart-403c471b-4581-47ec-b056-5746c4225e2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3662466199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3662466199
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1109343414
Short name T152
Test name
Test status
Simulation time 180597056 ps
CPU time 5.03 seconds
Started Jul 06 04:45:30 PM PDT 24
Finished Jul 06 04:45:35 PM PDT 24
Peak memory 213612 kb
Host smart-f9f0fb70-879b-49e8-a253-bf7ab1fe2f3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109343414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1109343414
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3826362549
Short name T20
Test name
Test status
Simulation time 1778885604 ps
CPU time 10.96 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:48:05 PM PDT 24
Peak memory 209860 kb
Host smart-a8dc8243-4d02-4d53-bcbd-f62308bd950d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826362549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3826362549
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3445246478
Short name T393
Test name
Test status
Simulation time 36213376 ps
CPU time 0.9 seconds
Started Jul 06 04:46:39 PM PDT 24
Finished Jul 06 04:46:40 PM PDT 24
Peak memory 205824 kb
Host smart-e895215f-8870-41eb-bb60-bd7bd5c32f20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445246478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3445246478
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2284049368
Short name T226
Test name
Test status
Simulation time 708385956 ps
CPU time 5.16 seconds
Started Jul 06 04:48:34 PM PDT 24
Finished Jul 06 04:48:39 PM PDT 24
Peak memory 214148 kb
Host smart-4ddbfe1d-05ed-4ebd-9590-56d9c52be108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284049368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2284049368
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.4005162020
Short name T146
Test name
Test status
Simulation time 467810732 ps
CPU time 6.69 seconds
Started Jul 06 04:45:11 PM PDT 24
Finished Jul 06 04:45:18 PM PDT 24
Peak memory 213600 kb
Host smart-efc3094c-9dec-4f40-b66e-020ad38b3a4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005162020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.4005162020
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2728580277
Short name T154
Test name
Test status
Simulation time 454006373 ps
CPU time 6.9 seconds
Started Jul 06 04:45:24 PM PDT 24
Finished Jul 06 04:45:31 PM PDT 24
Peak memory 213508 kb
Host smart-af78a90b-2dd4-480f-9dce-540c67e16c51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728580277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2728580277
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2480180084
Short name T178
Test name
Test status
Simulation time 5207799005 ps
CPU time 64.79 seconds
Started Jul 06 04:47:21 PM PDT 24
Finished Jul 06 04:48:27 PM PDT 24
Peak memory 222352 kb
Host smart-5ce7b2d6-45fd-4f68-a8f4-2d4ad42fe621
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480180084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2480180084
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3209252856
Short name T376
Test name
Test status
Simulation time 1289512800 ps
CPU time 12.44 seconds
Started Jul 06 04:47:19 PM PDT 24
Finished Jul 06 04:47:32 PM PDT 24
Peak memory 222468 kb
Host smart-2ebf28ca-8c9d-4e85-babf-f1638deff024
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3209252856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3209252856
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.671939498
Short name T76
Test name
Test status
Simulation time 599868298 ps
CPU time 9.51 seconds
Started Jul 06 04:48:39 PM PDT 24
Finished Jul 06 04:48:49 PM PDT 24
Peak memory 214208 kb
Host smart-94b044d7-d863-4e3f-8334-affb4a2c4c51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671939498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.671939498
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3949143788
Short name T103
Test name
Test status
Simulation time 1282613769 ps
CPU time 21.17 seconds
Started Jul 06 04:46:48 PM PDT 24
Finished Jul 06 04:47:10 PM PDT 24
Peak memory 222472 kb
Host smart-ec736d53-e036-42f0-89cb-6a5ffc3f2bb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949143788 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3949143788
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.790782426
Short name T91
Test name
Test status
Simulation time 1018832830 ps
CPU time 24.72 seconds
Started Jul 06 04:48:49 PM PDT 24
Finished Jul 06 04:49:15 PM PDT 24
Peak memory 222448 kb
Host smart-fd804545-586a-4d3e-9ae0-03b8119e5f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790782426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.790782426
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1934982023
Short name T243
Test name
Test status
Simulation time 3518193948 ps
CPU time 46.91 seconds
Started Jul 06 04:47:27 PM PDT 24
Finished Jul 06 04:48:14 PM PDT 24
Peak memory 222380 kb
Host smart-a7349525-21a5-44ff-b8c0-7c2ac5fa89b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1934982023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1934982023
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.165607208
Short name T41
Test name
Test status
Simulation time 157751858 ps
CPU time 3.55 seconds
Started Jul 06 04:47:05 PM PDT 24
Finished Jul 06 04:47:09 PM PDT 24
Peak memory 209964 kb
Host smart-7faa0b3c-e199-4775-b7f0-9b627275508e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165607208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.165607208
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2730009640
Short name T175
Test name
Test status
Simulation time 1124399203 ps
CPU time 39.35 seconds
Started Jul 06 04:46:36 PM PDT 24
Finished Jul 06 04:47:16 PM PDT 24
Peak memory 217152 kb
Host smart-956592ba-befc-4d86-bfac-94270a686430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730009640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2730009640
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1979314908
Short name T49
Test name
Test status
Simulation time 810503421 ps
CPU time 3.48 seconds
Started Jul 06 04:47:08 PM PDT 24
Finished Jul 06 04:47:12 PM PDT 24
Peak memory 214272 kb
Host smart-3d9fc5fc-44b5-4105-b2f0-319029fef9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979314908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1979314908
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2535754051
Short name T99
Test name
Test status
Simulation time 16853987730 ps
CPU time 99.45 seconds
Started Jul 06 04:47:46 PM PDT 24
Finished Jul 06 04:49:26 PM PDT 24
Peak memory 222460 kb
Host smart-343a828c-7cec-438c-a52d-3ac3d0119685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535754051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2535754051
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1559095391
Short name T387
Test name
Test status
Simulation time 389644968 ps
CPU time 10.02 seconds
Started Jul 06 04:47:59 PM PDT 24
Finished Jul 06 04:48:10 PM PDT 24
Peak memory 215104 kb
Host smart-2db0ffc4-ffa0-4973-b467-31b2d8e0fa8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559095391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1559095391
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2144634564
Short name T110
Test name
Test status
Simulation time 68325744 ps
CPU time 2.21 seconds
Started Jul 06 04:45:23 PM PDT 24
Finished Jul 06 04:45:26 PM PDT 24
Peak memory 218676 kb
Host smart-0db122b7-4ce7-4e73-8b53-003728afa6eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144634564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2144634564
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2171033762
Short name T161
Test name
Test status
Simulation time 405615041 ps
CPU time 5.82 seconds
Started Jul 06 04:45:12 PM PDT 24
Finished Jul 06 04:45:18 PM PDT 24
Peak memory 213580 kb
Host smart-894e9ed8-1203-4504-8156-1082e0ef4f5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171033762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2171033762
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1319809464
Short name T61
Test name
Test status
Simulation time 426503275 ps
CPU time 3.86 seconds
Started Jul 06 04:48:26 PM PDT 24
Finished Jul 06 04:48:31 PM PDT 24
Peak memory 218680 kb
Host smart-87119f2a-b339-478a-abdf-71f450db0579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319809464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1319809464
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.4159568527
Short name T104
Test name
Test status
Simulation time 135017125 ps
CPU time 2.31 seconds
Started Jul 06 04:47:40 PM PDT 24
Finished Jul 06 04:47:43 PM PDT 24
Peak memory 222472 kb
Host smart-a43edbad-83e4-4df4-8a76-41eec73a2e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159568527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.4159568527
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3101452046
Short name T579
Test name
Test status
Simulation time 79688501 ps
CPU time 2.46 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:47:56 PM PDT 24
Peak memory 214160 kb
Host smart-5b36256e-17ed-4111-a720-aa9e0975ad6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101452046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3101452046
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3906705434
Short name T790
Test name
Test status
Simulation time 51704518 ps
CPU time 3.59 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:46:59 PM PDT 24
Peak memory 214180 kb
Host smart-0569c51a-f890-469f-80c9-45a20467505d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906705434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3906705434
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1074071344
Short name T151
Test name
Test status
Simulation time 1197635461 ps
CPU time 10.75 seconds
Started Jul 06 04:45:42 PM PDT 24
Finished Jul 06 04:45:53 PM PDT 24
Peak memory 215916 kb
Host smart-dd200355-bdac-4bd6-a594-6458ae984e5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074071344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1074071344
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3315595887
Short name T169
Test name
Test status
Simulation time 87782594 ps
CPU time 4.92 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:48:54 PM PDT 24
Peak memory 218068 kb
Host smart-edd26e15-a3c9-4297-a78e-51e466b25462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315595887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3315595887
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2070820525
Short name T117
Test name
Test status
Simulation time 2229316625 ps
CPU time 23.97 seconds
Started Jul 06 04:47:35 PM PDT 24
Finished Jul 06 04:47:59 PM PDT 24
Peak memory 221972 kb
Host smart-2f03f305-413a-4e5d-a734-5c859ca057df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070820525 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2070820525
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.273465396
Short name T381
Test name
Test status
Simulation time 583288757 ps
CPU time 30.16 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:48:24 PM PDT 24
Peak memory 214292 kb
Host smart-55488560-5cb0-4ff1-9829-926d888d1ec5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=273465396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.273465396
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.536568181
Short name T123
Test name
Test status
Simulation time 1205641231 ps
CPU time 16.43 seconds
Started Jul 06 04:46:50 PM PDT 24
Finished Jul 06 04:47:07 PM PDT 24
Peak memory 214304 kb
Host smart-86f09cfd-0ce8-41e0-8357-45b2bc2edb71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=536568181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.536568181
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.103503727
Short name T350
Test name
Test status
Simulation time 40422241 ps
CPU time 2.99 seconds
Started Jul 06 04:48:15 PM PDT 24
Finished Jul 06 04:48:19 PM PDT 24
Peak memory 221492 kb
Host smart-ce7d90e3-7720-4d70-afaa-474acc9c1cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103503727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.103503727
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2083448986
Short name T235
Test name
Test status
Simulation time 39101841 ps
CPU time 1.96 seconds
Started Jul 06 04:48:33 PM PDT 24
Finished Jul 06 04:48:35 PM PDT 24
Peak memory 215112 kb
Host smart-f820111c-972b-4348-a48a-1c8dce3a0f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083448986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2083448986
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2989701169
Short name T32
Test name
Test status
Simulation time 86836206 ps
CPU time 3.87 seconds
Started Jul 06 04:47:19 PM PDT 24
Finished Jul 06 04:47:23 PM PDT 24
Peak memory 222704 kb
Host smart-08a9889d-12e8-4d5e-a4ba-afe06ed5964a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989701169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2989701169
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1215096649
Short name T128
Test name
Test status
Simulation time 114105521 ps
CPU time 4.38 seconds
Started Jul 06 04:48:49 PM PDT 24
Finished Jul 06 04:48:54 PM PDT 24
Peak memory 218316 kb
Host smart-3311f6dd-3b2f-4a3d-81ce-16aaa0d1b367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215096649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1215096649
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3374009311
Short name T297
Test name
Test status
Simulation time 59275921 ps
CPU time 2.75 seconds
Started Jul 06 04:46:38 PM PDT 24
Finished Jul 06 04:46:41 PM PDT 24
Peak memory 214472 kb
Host smart-ff201870-ffa3-49e8-b198-2ca1d6ebbd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374009311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3374009311
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2059553422
Short name T252
Test name
Test status
Simulation time 359244839 ps
CPU time 7.6 seconds
Started Jul 06 04:47:09 PM PDT 24
Finished Jul 06 04:47:17 PM PDT 24
Peak memory 208576 kb
Host smart-ed48bbef-a6bd-4edf-b20e-1429c69385ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059553422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2059553422
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3584427837
Short name T336
Test name
Test status
Simulation time 8242289048 ps
CPU time 56.28 seconds
Started Jul 06 04:47:10 PM PDT 24
Finished Jul 06 04:48:06 PM PDT 24
Peak memory 214240 kb
Host smart-a08a2e4c-b53c-432e-a5a8-3c9a933a33fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584427837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3584427837
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2683749703
Short name T125
Test name
Test status
Simulation time 3604988156 ps
CPU time 81.04 seconds
Started Jul 06 04:47:11 PM PDT 24
Finished Jul 06 04:48:33 PM PDT 24
Peak memory 222556 kb
Host smart-7a3589c9-19d5-4854-bc99-6de9565c2e87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2683749703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2683749703
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2104770292
Short name T176
Test name
Test status
Simulation time 2121653247 ps
CPU time 48.58 seconds
Started Jul 06 04:47:22 PM PDT 24
Finished Jul 06 04:48:11 PM PDT 24
Peak memory 222332 kb
Host smart-2828aa60-e7c0-4ecd-bbd7-ed0999eb773a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104770292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2104770292
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3394725876
Short name T368
Test name
Test status
Simulation time 173530247 ps
CPU time 3.25 seconds
Started Jul 06 04:47:28 PM PDT 24
Finished Jul 06 04:47:31 PM PDT 24
Peak memory 222380 kb
Host smart-c6504396-4497-45b2-83af-01a982a9ac58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3394725876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3394725876
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2187442569
Short name T205
Test name
Test status
Simulation time 1610047068 ps
CPU time 33.52 seconds
Started Jul 06 04:47:34 PM PDT 24
Finished Jul 06 04:48:07 PM PDT 24
Peak memory 222300 kb
Host smart-adbb4eb1-951e-40a2-8734-924ea6a6095d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187442569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2187442569
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2948849777
Short name T36
Test name
Test status
Simulation time 34649510 ps
CPU time 1.4 seconds
Started Jul 06 04:47:51 PM PDT 24
Finished Jul 06 04:47:53 PM PDT 24
Peak memory 209548 kb
Host smart-352e0399-6055-4931-87b4-5a9faf5ef3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948849777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2948849777
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3067656736
Short name T177
Test name
Test status
Simulation time 1512199283 ps
CPU time 35.09 seconds
Started Jul 06 04:48:07 PM PDT 24
Finished Jul 06 04:48:42 PM PDT 24
Peak memory 216184 kb
Host smart-0cb5c50b-c27a-4e1b-973b-77b1a787d7be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067656736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3067656736
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.1715742794
Short name T59
Test name
Test status
Simulation time 452093740 ps
CPU time 18.5 seconds
Started Jul 06 04:46:58 PM PDT 24
Finished Jul 06 04:47:17 PM PDT 24
Peak memory 222296 kb
Host smart-4d89d7e9-1d7f-46f2-9a1e-fcae709a9341
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715742794 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.1715742794
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3437150535
Short name T87
Test name
Test status
Simulation time 1746913046 ps
CPU time 34.93 seconds
Started Jul 06 04:47:56 PM PDT 24
Finished Jul 06 04:48:31 PM PDT 24
Peak memory 214208 kb
Host smart-4e6cc44e-3c4c-47b2-bad6-30e5e3edbb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437150535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3437150535
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3031900608
Short name T290
Test name
Test status
Simulation time 47843805 ps
CPU time 3.42 seconds
Started Jul 06 04:46:53 PM PDT 24
Finished Jul 06 04:46:59 PM PDT 24
Peak memory 214200 kb
Host smart-d610771a-2d3f-4ff4-8335-a8ca90c3a538
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3031900608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3031900608
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3441111643
Short name T155
Test name
Test status
Simulation time 102029832 ps
CPU time 5.25 seconds
Started Jul 06 04:45:34 PM PDT 24
Finished Jul 06 04:45:40 PM PDT 24
Peak memory 213544 kb
Host smart-0f8d941f-c76b-431f-9782-f4e9f3f7084f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441111643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3441111643
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.4110135901
Short name T168
Test name
Test status
Simulation time 436766392 ps
CPU time 4.2 seconds
Started Jul 06 04:47:26 PM PDT 24
Finished Jul 06 04:47:30 PM PDT 24
Peak memory 217568 kb
Host smart-86047083-5f05-4c40-b5fc-e6b1043b88d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110135901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.4110135901
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2931424644
Short name T167
Test name
Test status
Simulation time 108342926 ps
CPU time 5.27 seconds
Started Jul 06 04:48:46 PM PDT 24
Finished Jul 06 04:48:51 PM PDT 24
Peak memory 218200 kb
Host smart-f4ba725e-625c-42b6-ad18-e8a3a74a393f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931424644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2931424644
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1980982884
Short name T172
Test name
Test status
Simulation time 971601375 ps
CPU time 5.8 seconds
Started Jul 06 04:44:51 PM PDT 24
Finished Jul 06 04:44:57 PM PDT 24
Peak memory 205468 kb
Host smart-7e3d44cb-7f5d-4d57-a431-1635faee9356
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980982884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
980982884
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1205096787
Short name T74
Test name
Test status
Simulation time 711574298 ps
CPU time 3.2 seconds
Started Jul 06 04:46:41 PM PDT 24
Finished Jul 06 04:46:45 PM PDT 24
Peak memory 206716 kb
Host smart-847c196a-85f0-4758-960d-b517cbf9969d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205096787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1205096787
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.33875346
Short name T248
Test name
Test status
Simulation time 1205780444 ps
CPU time 30.97 seconds
Started Jul 06 04:46:37 PM PDT 24
Finished Jul 06 04:47:08 PM PDT 24
Peak memory 207956 kb
Host smart-580cc47c-1d56-4243-8c3b-d28e5bef201b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33875346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.33875346
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2200148275
Short name T324
Test name
Test status
Simulation time 2367141707 ps
CPU time 31.62 seconds
Started Jul 06 04:46:35 PM PDT 24
Finished Jul 06 04:47:07 PM PDT 24
Peak memory 216688 kb
Host smart-76cebcbc-f513-4e2d-a218-b5a97f798270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200148275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2200148275
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.550676916
Short name T67
Test name
Test status
Simulation time 1344422748 ps
CPU time 14.53 seconds
Started Jul 06 04:46:36 PM PDT 24
Finished Jul 06 04:46:51 PM PDT 24
Peak memory 222428 kb
Host smart-dea6151d-7c6e-4cab-a5ac-3c9cee167083
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550676916 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.550676916
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3911692060
Short name T329
Test name
Test status
Simulation time 28798458 ps
CPU time 1.94 seconds
Started Jul 06 04:47:04 PM PDT 24
Finished Jul 06 04:47:07 PM PDT 24
Peak memory 214216 kb
Host smart-27a27557-8060-4acf-90cf-60fee263adfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911692060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3911692060
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.329100309
Short name T58
Test name
Test status
Simulation time 279912682 ps
CPU time 3.87 seconds
Started Jul 06 04:47:04 PM PDT 24
Finished Jul 06 04:47:09 PM PDT 24
Peak memory 221396 kb
Host smart-76653be1-69ee-4c0d-9de3-af486f51acd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329100309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.329100309
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1171438828
Short name T287
Test name
Test status
Simulation time 1872497710 ps
CPU time 18.87 seconds
Started Jul 06 04:47:12 PM PDT 24
Finished Jul 06 04:47:31 PM PDT 24
Peak memory 220920 kb
Host smart-05aa2aa9-fb58-4f64-9a57-5c1242a7780c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171438828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1171438828
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3791806919
Short name T854
Test name
Test status
Simulation time 333129830 ps
CPU time 12.13 seconds
Started Jul 06 04:47:36 PM PDT 24
Finished Jul 06 04:47:49 PM PDT 24
Peak memory 209404 kb
Host smart-23babe16-4e1d-43af-8624-b0f3129a2318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791806919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3791806919
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2700006618
Short name T230
Test name
Test status
Simulation time 435575228 ps
CPU time 3.95 seconds
Started Jul 06 04:47:50 PM PDT 24
Finished Jul 06 04:47:55 PM PDT 24
Peak memory 214308 kb
Host smart-fcaa5066-65a0-4a77-a41d-ed2346b384e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2700006618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2700006618
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.629485536
Short name T331
Test name
Test status
Simulation time 35774191 ps
CPU time 1.9 seconds
Started Jul 06 04:46:41 PM PDT 24
Finished Jul 06 04:46:44 PM PDT 24
Peak memory 214240 kb
Host smart-c7d07ee3-bd49-4aea-937b-633a9e9d2993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629485536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.629485536
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.454315007
Short name T215
Test name
Test status
Simulation time 892455235 ps
CPU time 15.5 seconds
Started Jul 06 04:48:06 PM PDT 24
Finished Jul 06 04:48:22 PM PDT 24
Peak memory 222452 kb
Host smart-2bde42e3-a765-458f-8409-dae78f5bbf63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454315007 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.454315007
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1161454385
Short name T313
Test name
Test status
Simulation time 229498812 ps
CPU time 5.94 seconds
Started Jul 06 04:48:20 PM PDT 24
Finished Jul 06 04:48:27 PM PDT 24
Peak memory 222364 kb
Host smart-d3fcf20f-3643-4acc-9fbf-426584f6f8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161454385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1161454385
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2580329288
Short name T82
Test name
Test status
Simulation time 297008054 ps
CPU time 4.2 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:48:53 PM PDT 24
Peak memory 218428 kb
Host smart-379b7d9f-9824-44b3-97b6-fea7d38271a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580329288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2580329288
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3618256345
Short name T319
Test name
Test status
Simulation time 141280429 ps
CPU time 9.6 seconds
Started Jul 06 04:48:46 PM PDT 24
Finished Jul 06 04:48:56 PM PDT 24
Peak memory 222408 kb
Host smart-11fb1baa-bad5-447f-a028-e238f735b718
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618256345 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3618256345
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3142796644
Short name T1066
Test name
Test status
Simulation time 906178101 ps
CPU time 12.33 seconds
Started Jul 06 04:44:53 PM PDT 24
Finished Jul 06 04:45:05 PM PDT 24
Peak memory 205460 kb
Host smart-2b47dcd2-cb54-4d08-9da3-e7483f9a1558
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142796644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
142796644
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2835021365
Short name T982
Test name
Test status
Simulation time 19514548 ps
CPU time 1.1 seconds
Started Jul 06 04:44:53 PM PDT 24
Finished Jul 06 04:44:54 PM PDT 24
Peak memory 205400 kb
Host smart-c09d8d87-7ab7-4dc6-8e35-741b5ba3aa0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835021365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
835021365
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2863464949
Short name T1000
Test name
Test status
Simulation time 81370676 ps
CPU time 1.45 seconds
Started Jul 06 04:44:51 PM PDT 24
Finished Jul 06 04:44:53 PM PDT 24
Peak memory 213764 kb
Host smart-ce141c0c-febb-4a81-8061-44c224c4a08f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863464949 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2863464949
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.946118704
Short name T1070
Test name
Test status
Simulation time 27169598 ps
CPU time 1.45 seconds
Started Jul 06 04:44:52 PM PDT 24
Finished Jul 06 04:44:54 PM PDT 24
Peak memory 205396 kb
Host smart-342fb4d4-f5ff-40f3-ae04-091e2fa8ca12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946118704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.946118704
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2367933926
Short name T1049
Test name
Test status
Simulation time 111103736 ps
CPU time 0.81 seconds
Started Jul 06 04:44:52 PM PDT 24
Finished Jul 06 04:44:53 PM PDT 24
Peak memory 205168 kb
Host smart-0e7d3bfb-7ca6-4bfd-bef9-ea31dd158648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367933926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2367933926
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3833284074
Short name T932
Test name
Test status
Simulation time 100519054 ps
CPU time 1.5 seconds
Started Jul 06 04:44:52 PM PDT 24
Finished Jul 06 04:44:54 PM PDT 24
Peak memory 205472 kb
Host smart-ef303a9b-4018-4084-9ee6-bc4aa2fc78c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833284074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3833284074
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1543647701
Short name T951
Test name
Test status
Simulation time 77057124 ps
CPU time 1.82 seconds
Started Jul 06 04:44:52 PM PDT 24
Finished Jul 06 04:44:54 PM PDT 24
Peak memory 213776 kb
Host smart-161f9d49-bb84-4980-b2c3-f2a03e51fc57
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543647701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1543647701
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1878026241
Short name T1080
Test name
Test status
Simulation time 440848351 ps
CPU time 14.41 seconds
Started Jul 06 04:44:53 PM PDT 24
Finished Jul 06 04:45:07 PM PDT 24
Peak memory 214208 kb
Host smart-29f5c0af-ba4b-4bc9-baac-76644552a989
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878026241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1878026241
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1014498214
Short name T969
Test name
Test status
Simulation time 143690907 ps
CPU time 2.15 seconds
Started Jul 06 04:44:57 PM PDT 24
Finished Jul 06 04:45:00 PM PDT 24
Peak memory 215100 kb
Host smart-e7674b45-fc6a-43fb-ade9-e3da70a79a15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014498214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1014498214
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2937590613
Short name T160
Test name
Test status
Simulation time 72507623 ps
CPU time 2.57 seconds
Started Jul 06 04:44:52 PM PDT 24
Finished Jul 06 04:44:55 PM PDT 24
Peak memory 213648 kb
Host smart-c9317639-d3de-4775-aab4-ff80fa5a06d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937590613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2937590613
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3733161662
Short name T1042
Test name
Test status
Simulation time 2448812490 ps
CPU time 6.02 seconds
Started Jul 06 04:45:00 PM PDT 24
Finished Jul 06 04:45:06 PM PDT 24
Peak memory 205472 kb
Host smart-4cfcdc09-2220-498a-b2fc-9b3904fe9de2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733161662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
733161662
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2919658781
Short name T1073
Test name
Test status
Simulation time 257504511 ps
CPU time 14.66 seconds
Started Jul 06 04:45:00 PM PDT 24
Finished Jul 06 04:45:15 PM PDT 24
Peak memory 205436 kb
Host smart-7860a058-d78c-4e0a-a4a6-456302b41db4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919658781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
919658781
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.903509978
Short name T943
Test name
Test status
Simulation time 36055153 ps
CPU time 1.16 seconds
Started Jul 06 04:44:53 PM PDT 24
Finished Jul 06 04:44:54 PM PDT 24
Peak memory 205388 kb
Host smart-9ad37b66-aec1-4a37-aa28-7a73644ee318
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903509978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.903509978
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3137895293
Short name T981
Test name
Test status
Simulation time 149109294 ps
CPU time 2.26 seconds
Started Jul 06 04:45:00 PM PDT 24
Finished Jul 06 04:45:03 PM PDT 24
Peak memory 213660 kb
Host smart-0752efc0-6232-43fa-b64c-867ccf623812
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137895293 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3137895293
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2847329448
Short name T1011
Test name
Test status
Simulation time 32751103 ps
CPU time 1.12 seconds
Started Jul 06 04:45:00 PM PDT 24
Finished Jul 06 04:45:02 PM PDT 24
Peak memory 205316 kb
Host smart-b89c0f7a-c97c-4fdc-b1b1-be7f931243b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847329448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2847329448
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3186122724
Short name T987
Test name
Test status
Simulation time 58547174 ps
CPU time 0.75 seconds
Started Jul 06 04:44:54 PM PDT 24
Finished Jul 06 04:44:55 PM PDT 24
Peak memory 205208 kb
Host smart-02734ca0-c674-4e79-b2ff-2af74fa1c98a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186122724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3186122724
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3496674209
Short name T135
Test name
Test status
Simulation time 90671927 ps
CPU time 3.76 seconds
Started Jul 06 04:45:00 PM PDT 24
Finished Jul 06 04:45:04 PM PDT 24
Peak memory 205344 kb
Host smart-08747219-33d0-410c-8081-adc9b6a99818
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496674209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3496674209
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2842502696
Short name T1072
Test name
Test status
Simulation time 553310498 ps
CPU time 2.84 seconds
Started Jul 06 04:44:52 PM PDT 24
Finished Jul 06 04:44:55 PM PDT 24
Peak memory 213800 kb
Host smart-a6243953-0907-4632-b815-b56a6f4961e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842502696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2842502696
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3819396255
Short name T1038
Test name
Test status
Simulation time 85715164 ps
CPU time 3.75 seconds
Started Jul 06 04:44:52 PM PDT 24
Finished Jul 06 04:44:57 PM PDT 24
Peak memory 213812 kb
Host smart-3f155b74-ba17-4aa3-8a6f-ebb0a6cea932
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819396255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3819396255
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.288732111
Short name T1054
Test name
Test status
Simulation time 56430390 ps
CPU time 3.96 seconds
Started Jul 06 04:44:51 PM PDT 24
Finished Jul 06 04:44:56 PM PDT 24
Peak memory 216812 kb
Host smart-168a8fc0-7cb9-41bf-a020-9207350ebc71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288732111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.288732111
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2205416651
Short name T158
Test name
Test status
Simulation time 162197496 ps
CPU time 3.88 seconds
Started Jul 06 04:44:52 PM PDT 24
Finished Jul 06 04:44:57 PM PDT 24
Peak memory 213620 kb
Host smart-27f6e9e3-f951-4cfb-adc3-2acecfb43688
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205416651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2205416651
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1536404372
Short name T1022
Test name
Test status
Simulation time 74588244 ps
CPU time 1.28 seconds
Started Jul 06 04:45:21 PM PDT 24
Finished Jul 06 04:45:23 PM PDT 24
Peak memory 213624 kb
Host smart-7cc34b5f-01c7-4927-b570-38d57590d2f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536404372 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1536404372
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4235405196
Short name T1086
Test name
Test status
Simulation time 15353243 ps
CPU time 1.08 seconds
Started Jul 06 04:45:22 PM PDT 24
Finished Jul 06 04:45:24 PM PDT 24
Peak memory 205408 kb
Host smart-862a6981-0533-44df-8f7c-d372ffcd842a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235405196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.4235405196
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1655270067
Short name T1028
Test name
Test status
Simulation time 37687073 ps
CPU time 0.84 seconds
Started Jul 06 04:45:24 PM PDT 24
Finished Jul 06 04:45:25 PM PDT 24
Peak memory 205276 kb
Host smart-f3b608fe-2bb3-44a0-baba-f9b4bec0e922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655270067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1655270067
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2020832074
Short name T130
Test name
Test status
Simulation time 456810145 ps
CPU time 3.31 seconds
Started Jul 06 04:45:23 PM PDT 24
Finished Jul 06 04:45:27 PM PDT 24
Peak memory 213584 kb
Host smart-ce093802-5eff-4a8a-912a-193ae28c275c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020832074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2020832074
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.575407378
Short name T1045
Test name
Test status
Simulation time 437526444 ps
CPU time 2.34 seconds
Started Jul 06 04:45:23 PM PDT 24
Finished Jul 06 04:45:25 PM PDT 24
Peak memory 213764 kb
Host smart-4aa4ff82-d89f-4102-a1a3-3c4934836047
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575407378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.575407378
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1631517113
Short name T113
Test name
Test status
Simulation time 625590086 ps
CPU time 8.66 seconds
Started Jul 06 04:45:22 PM PDT 24
Finished Jul 06 04:45:31 PM PDT 24
Peak memory 213920 kb
Host smart-5ac68f8b-23cc-47b4-a86b-51dba6ca8cfd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631517113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1631517113
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2935987662
Short name T1051
Test name
Test status
Simulation time 319960945 ps
CPU time 4.63 seconds
Started Jul 06 04:45:34 PM PDT 24
Finished Jul 06 04:45:39 PM PDT 24
Peak memory 213556 kb
Host smart-6639a98f-5cd9-4bf8-9fe9-f9646b0f92cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935987662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2935987662
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.469443122
Short name T163
Test name
Test status
Simulation time 60532693 ps
CPU time 2.66 seconds
Started Jul 06 04:45:24 PM PDT 24
Finished Jul 06 04:45:27 PM PDT 24
Peak memory 213608 kb
Host smart-3f615b83-f4b8-46c1-ae3f-09637e1feea7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469443122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.469443122
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.687551646
Short name T1014
Test name
Test status
Simulation time 56861679 ps
CPU time 1.54 seconds
Started Jul 06 04:45:33 PM PDT 24
Finished Jul 06 04:45:34 PM PDT 24
Peak memory 213656 kb
Host smart-667e80bc-76dc-48ce-a8cd-909abfd23e6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687551646 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.687551646
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.741606564
Short name T948
Test name
Test status
Simulation time 27229676 ps
CPU time 1.05 seconds
Started Jul 06 04:45:23 PM PDT 24
Finished Jul 06 04:45:24 PM PDT 24
Peak memory 205404 kb
Host smart-456f35a7-bc74-47e5-880c-49d1797f4eb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741606564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.741606564
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1837633209
Short name T923
Test name
Test status
Simulation time 12579263 ps
CPU time 0.89 seconds
Started Jul 06 04:45:22 PM PDT 24
Finished Jul 06 04:45:23 PM PDT 24
Peak memory 205220 kb
Host smart-bcf34a92-4111-45ab-8877-93559fdf573a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837633209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1837633209
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.389711061
Short name T1069
Test name
Test status
Simulation time 100656365 ps
CPU time 1.68 seconds
Started Jul 06 04:45:33 PM PDT 24
Finished Jul 06 04:45:35 PM PDT 24
Peak memory 205324 kb
Host smart-50bf0e68-4bea-4c76-ae0d-7eadbab8136d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389711061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.389711061
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2443560946
Short name T1006
Test name
Test status
Simulation time 154844839 ps
CPU time 1.5 seconds
Started Jul 06 04:45:33 PM PDT 24
Finished Jul 06 04:45:35 PM PDT 24
Peak memory 213808 kb
Host smart-0233ced6-bf9b-4867-ae03-4d1e855560b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443560946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2443560946
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.389950738
Short name T996
Test name
Test status
Simulation time 294141605 ps
CPU time 3.86 seconds
Started Jul 06 04:45:23 PM PDT 24
Finished Jul 06 04:45:28 PM PDT 24
Peak memory 213932 kb
Host smart-3de9c67c-8888-4b62-8ddb-e9e69d3615e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389950738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.389950738
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3254714976
Short name T1027
Test name
Test status
Simulation time 23512466 ps
CPU time 1.58 seconds
Started Jul 06 04:45:21 PM PDT 24
Finished Jul 06 04:45:23 PM PDT 24
Peak memory 213552 kb
Host smart-b5056345-daaf-4652-b139-067632c0e71e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254714976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3254714976
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.841318163
Short name T358
Test name
Test status
Simulation time 399597198 ps
CPU time 5.22 seconds
Started Jul 06 04:45:23 PM PDT 24
Finished Jul 06 04:45:28 PM PDT 24
Peak memory 213528 kb
Host smart-001df89d-bbc0-413f-a09d-1b1c384bff53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841318163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.841318163
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2317697998
Short name T365
Test name
Test status
Simulation time 31045484 ps
CPU time 1.2 seconds
Started Jul 06 04:45:29 PM PDT 24
Finished Jul 06 04:45:30 PM PDT 24
Peak memory 205324 kb
Host smart-b7bcd326-8534-4ee8-a006-8971c27abd08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317697998 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2317697998
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.815568259
Short name T1037
Test name
Test status
Simulation time 39043973 ps
CPU time 0.94 seconds
Started Jul 06 04:45:29 PM PDT 24
Finished Jul 06 04:45:30 PM PDT 24
Peak memory 205340 kb
Host smart-eda193d7-f13e-4325-888e-2302a729783b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815568259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.815568259
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1024794511
Short name T959
Test name
Test status
Simulation time 15092935 ps
CPU time 0.9 seconds
Started Jul 06 04:45:34 PM PDT 24
Finished Jul 06 04:45:36 PM PDT 24
Peak memory 205232 kb
Host smart-eeeda2db-d402-4a84-8758-0bb5a65931be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024794511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1024794511
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1687672726
Short name T995
Test name
Test status
Simulation time 333828376 ps
CPU time 2.42 seconds
Started Jul 06 04:45:28 PM PDT 24
Finished Jul 06 04:45:31 PM PDT 24
Peak memory 205432 kb
Host smart-74228d66-7d98-4137-9ab1-e1b9d8a714d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687672726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1687672726
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2520499565
Short name T1017
Test name
Test status
Simulation time 4179555111 ps
CPU time 13.94 seconds
Started Jul 06 04:45:34 PM PDT 24
Finished Jul 06 04:45:48 PM PDT 24
Peak memory 221012 kb
Host smart-226cfd76-08ea-4ad4-8b21-d28e86141517
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520499565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2520499565
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.572771655
Short name T970
Test name
Test status
Simulation time 52121646 ps
CPU time 1.69 seconds
Started Jul 06 04:45:34 PM PDT 24
Finished Jul 06 04:45:37 PM PDT 24
Peak memory 213560 kb
Host smart-091f101e-ff87-4a87-b0c4-dec16c7d8fa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572771655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.572771655
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2797808790
Short name T1077
Test name
Test status
Simulation time 77483166 ps
CPU time 1.45 seconds
Started Jul 06 04:45:28 PM PDT 24
Finished Jul 06 04:45:30 PM PDT 24
Peak memory 213692 kb
Host smart-c0a84a8b-3168-4733-959f-991943449e81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797808790 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2797808790
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.229100875
Short name T985
Test name
Test status
Simulation time 11715484 ps
CPU time 1.06 seconds
Started Jul 06 04:45:29 PM PDT 24
Finished Jul 06 04:45:31 PM PDT 24
Peak memory 205340 kb
Host smart-9cd5df83-087b-4f77-abba-e62d7f2696cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229100875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.229100875
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.624404678
Short name T934
Test name
Test status
Simulation time 12247485 ps
CPU time 0.81 seconds
Started Jul 06 04:45:29 PM PDT 24
Finished Jul 06 04:45:30 PM PDT 24
Peak memory 205200 kb
Host smart-c6efcd29-c092-4896-9dee-0ff185ff4a61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624404678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.624404678
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.191764558
Short name T955
Test name
Test status
Simulation time 371738885 ps
CPU time 2.58 seconds
Started Jul 06 04:45:29 PM PDT 24
Finished Jul 06 04:45:31 PM PDT 24
Peak memory 205444 kb
Host smart-a69bdd18-ca00-4955-9ded-32296063a6e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191764558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.191764558
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4074606645
Short name T115
Test name
Test status
Simulation time 558115184 ps
CPU time 3.67 seconds
Started Jul 06 04:45:28 PM PDT 24
Finished Jul 06 04:45:32 PM PDT 24
Peak memory 219856 kb
Host smart-f2ee968c-2e21-44e9-9314-281e106363ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074606645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.4074606645
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3607542227
Short name T1029
Test name
Test status
Simulation time 135226728 ps
CPU time 3.31 seconds
Started Jul 06 04:45:28 PM PDT 24
Finished Jul 06 04:45:32 PM PDT 24
Peak memory 213624 kb
Host smart-af01810b-79fe-489d-a4ab-2d4958d3fe24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607542227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3607542227
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3257290251
Short name T144
Test name
Test status
Simulation time 1029668332 ps
CPU time 10.62 seconds
Started Jul 06 04:45:29 PM PDT 24
Finished Jul 06 04:45:40 PM PDT 24
Peak memory 213604 kb
Host smart-5d37e64e-5681-4640-a05b-3e032e1e94f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257290251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3257290251
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1433744607
Short name T961
Test name
Test status
Simulation time 120042091 ps
CPU time 1.51 seconds
Started Jul 06 04:45:36 PM PDT 24
Finished Jul 06 04:45:38 PM PDT 24
Peak memory 213648 kb
Host smart-a3a47301-a216-4edf-8139-f4939d0310cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433744607 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1433744607
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.427978051
Short name T134
Test name
Test status
Simulation time 22152906 ps
CPU time 1.24 seconds
Started Jul 06 04:45:27 PM PDT 24
Finished Jul 06 04:45:29 PM PDT 24
Peak memory 205428 kb
Host smart-9fb497f8-5db4-400b-8d54-172a702f7874
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427978051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.427978051
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2461890450
Short name T940
Test name
Test status
Simulation time 39465453 ps
CPU time 0.7 seconds
Started Jul 06 04:45:28 PM PDT 24
Finished Jul 06 04:45:29 PM PDT 24
Peak memory 205180 kb
Host smart-7d6c6126-06a0-401f-acd3-a71170b458cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461890450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2461890450
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1475877378
Short name T1067
Test name
Test status
Simulation time 68655507 ps
CPU time 1.6 seconds
Started Jul 06 04:45:35 PM PDT 24
Finished Jul 06 04:45:37 PM PDT 24
Peak memory 205508 kb
Host smart-e1b6205e-c28d-4195-a682-3aa8f78ffc2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475877378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1475877378
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1412126098
Short name T1005
Test name
Test status
Simulation time 161127187 ps
CPU time 1.55 seconds
Started Jul 06 04:45:32 PM PDT 24
Finished Jul 06 04:45:34 PM PDT 24
Peak memory 213812 kb
Host smart-cc76e7d0-8842-4459-ade9-1693a12d0f1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412126098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1412126098
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2805404331
Short name T958
Test name
Test status
Simulation time 156573294 ps
CPU time 6.98 seconds
Started Jul 06 04:45:31 PM PDT 24
Finished Jul 06 04:45:38 PM PDT 24
Peak memory 220164 kb
Host smart-45934430-125f-4b5d-8d67-0696c92c2f4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805404331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2805404331
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1376065490
Short name T984
Test name
Test status
Simulation time 42026777 ps
CPU time 2.61 seconds
Started Jul 06 04:45:29 PM PDT 24
Finished Jul 06 04:45:32 PM PDT 24
Peak memory 213580 kb
Host smart-d1af5f5d-32a7-45a2-97df-07d6ffa0323d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376065490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1376065490
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1910444034
Short name T1007
Test name
Test status
Simulation time 143885269 ps
CPU time 2.33 seconds
Started Jul 06 04:45:36 PM PDT 24
Finished Jul 06 04:45:39 PM PDT 24
Peak memory 213684 kb
Host smart-6adf0bb2-885c-419c-adc8-6da81eff063f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910444034 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1910444034
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1307517703
Short name T363
Test name
Test status
Simulation time 15611729 ps
CPU time 1.18 seconds
Started Jul 06 04:45:35 PM PDT 24
Finished Jul 06 04:45:37 PM PDT 24
Peak memory 205336 kb
Host smart-cbcdd813-f3df-4fdf-b9c0-f12887dff910
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307517703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1307517703
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.975750014
Short name T929
Test name
Test status
Simulation time 11465878 ps
CPU time 0.74 seconds
Started Jul 06 04:45:38 PM PDT 24
Finished Jul 06 04:45:39 PM PDT 24
Peak memory 205196 kb
Host smart-45f726a0-7d86-4c0d-b35b-a439dfc6763e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975750014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.975750014
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.500399426
Short name T937
Test name
Test status
Simulation time 314505502 ps
CPU time 2.83 seconds
Started Jul 06 04:45:35 PM PDT 24
Finished Jul 06 04:45:38 PM PDT 24
Peak memory 205392 kb
Host smart-68c94126-9d87-4151-a85a-30812032fe68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500399426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.500399426
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3913245183
Short name T997
Test name
Test status
Simulation time 227867078 ps
CPU time 3.08 seconds
Started Jul 06 04:45:34 PM PDT 24
Finished Jul 06 04:45:38 PM PDT 24
Peak memory 213820 kb
Host smart-80f6df98-4782-4930-abc5-1410405e7642
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913245183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3913245183
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3009673819
Short name T1068
Test name
Test status
Simulation time 117179201 ps
CPU time 4.86 seconds
Started Jul 06 04:45:36 PM PDT 24
Finished Jul 06 04:45:42 PM PDT 24
Peak memory 213948 kb
Host smart-0702fc27-e3df-4f1f-85f7-30a29ed5d12b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009673819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3009673819
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.231372955
Short name T1060
Test name
Test status
Simulation time 179719707 ps
CPU time 1.41 seconds
Started Jul 06 04:45:35 PM PDT 24
Finished Jul 06 04:45:37 PM PDT 24
Peak memory 213616 kb
Host smart-e55a5468-e56f-4dba-8545-f4f81a44517d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231372955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.231372955
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.507668574
Short name T998
Test name
Test status
Simulation time 100981380 ps
CPU time 2.49 seconds
Started Jul 06 04:45:34 PM PDT 24
Finished Jul 06 04:45:37 PM PDT 24
Peak memory 213532 kb
Host smart-59fccdc0-22ba-4ae0-a493-a48e0e06f171
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507668574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.507668574
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2375406262
Short name T1002
Test name
Test status
Simulation time 31900367 ps
CPU time 1.52 seconds
Started Jul 06 04:45:35 PM PDT 24
Finished Jul 06 04:45:37 PM PDT 24
Peak memory 205388 kb
Host smart-6aac0811-5b8c-4b99-b3ba-da3c702d43c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375406262 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2375406262
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.669132569
Short name T925
Test name
Test status
Simulation time 31945653 ps
CPU time 0.93 seconds
Started Jul 06 04:45:34 PM PDT 24
Finished Jul 06 04:45:36 PM PDT 24
Peak memory 205260 kb
Host smart-a6467f25-dfef-4d63-8697-307f8cfd8401
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669132569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.669132569
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1541568225
Short name T1016
Test name
Test status
Simulation time 10537286 ps
CPU time 0.8 seconds
Started Jul 06 04:45:37 PM PDT 24
Finished Jul 06 04:45:39 PM PDT 24
Peak memory 205180 kb
Host smart-fb60b017-bcce-4292-854b-d7e4fe891eef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541568225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1541568225
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1908413155
Short name T993
Test name
Test status
Simulation time 22591268 ps
CPU time 1.47 seconds
Started Jul 06 04:45:34 PM PDT 24
Finished Jul 06 04:45:36 PM PDT 24
Peak memory 205396 kb
Host smart-4618345a-e397-4956-a2c9-095710cbd237
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908413155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1908413155
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.4031893313
Short name T976
Test name
Test status
Simulation time 91724778 ps
CPU time 2.72 seconds
Started Jul 06 04:45:36 PM PDT 24
Finished Jul 06 04:45:39 PM PDT 24
Peak memory 213800 kb
Host smart-9b525fba-82fc-4f1d-8a28-f59f9d8a66d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031893313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.4031893313
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2610005960
Short name T992
Test name
Test status
Simulation time 778989479 ps
CPU time 6.79 seconds
Started Jul 06 04:45:34 PM PDT 24
Finished Jul 06 04:45:41 PM PDT 24
Peak memory 213960 kb
Host smart-47c3f0bd-21f5-4209-92c4-3c3524ece38d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610005960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2610005960
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1145455371
Short name T1046
Test name
Test status
Simulation time 80764429 ps
CPU time 1.97 seconds
Started Jul 06 04:45:37 PM PDT 24
Finished Jul 06 04:45:39 PM PDT 24
Peak memory 213804 kb
Host smart-07451129-3056-4f61-8027-bf25f9410b2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145455371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1145455371
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.545958756
Short name T145
Test name
Test status
Simulation time 171611088 ps
CPU time 2.71 seconds
Started Jul 06 04:45:34 PM PDT 24
Finished Jul 06 04:45:38 PM PDT 24
Peak memory 213576 kb
Host smart-d7390181-6dc6-4b13-821e-4e2b6a7aaaae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545958756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.545958756
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3447318880
Short name T1050
Test name
Test status
Simulation time 35816571 ps
CPU time 1.82 seconds
Started Jul 06 04:45:37 PM PDT 24
Finished Jul 06 04:45:40 PM PDT 24
Peak memory 213680 kb
Host smart-36a6d801-a260-4eb9-bdfe-990548e20063
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447318880 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3447318880
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3788657313
Short name T956
Test name
Test status
Simulation time 34074231 ps
CPU time 1.13 seconds
Started Jul 06 04:45:37 PM PDT 24
Finished Jul 06 04:45:38 PM PDT 24
Peak memory 205416 kb
Host smart-d377e15b-efd0-4d02-8da4-22f935963b62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788657313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3788657313
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.332641539
Short name T1035
Test name
Test status
Simulation time 11438744 ps
CPU time 0.75 seconds
Started Jul 06 04:45:38 PM PDT 24
Finished Jul 06 04:45:40 PM PDT 24
Peak memory 205224 kb
Host smart-a435ca55-9e43-4055-843b-26290f8914c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332641539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.332641539
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4053428666
Short name T1082
Test name
Test status
Simulation time 100056721 ps
CPU time 1.77 seconds
Started Jul 06 04:45:35 PM PDT 24
Finished Jul 06 04:45:37 PM PDT 24
Peak memory 205332 kb
Host smart-f269c599-bfa9-4eca-826e-d65577e04533
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053428666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.4053428666
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.925077649
Short name T111
Test name
Test status
Simulation time 606317545 ps
CPU time 5.34 seconds
Started Jul 06 04:45:35 PM PDT 24
Finished Jul 06 04:45:41 PM PDT 24
Peak memory 213936 kb
Host smart-65ece8f3-3856-42a0-976a-c0ae00d24148
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925077649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.925077649
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1896601231
Short name T1059
Test name
Test status
Simulation time 442386479 ps
CPU time 5.7 seconds
Started Jul 06 04:45:38 PM PDT 24
Finished Jul 06 04:45:44 PM PDT 24
Peak memory 213944 kb
Host smart-ccb96c2d-3f6b-4d96-be56-00690c8f42b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896601231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1896601231
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.953889658
Short name T920
Test name
Test status
Simulation time 797786357 ps
CPU time 2.99 seconds
Started Jul 06 04:45:34 PM PDT 24
Finished Jul 06 04:45:37 PM PDT 24
Peak memory 213552 kb
Host smart-c9331867-6a6c-45a1-a635-8153e0c1801b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953889658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.953889658
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1030647343
Short name T941
Test name
Test status
Simulation time 18963066 ps
CPU time 1.24 seconds
Started Jul 06 04:45:39 PM PDT 24
Finished Jul 06 04:45:41 PM PDT 24
Peak memory 213676 kb
Host smart-21a78784-9504-4db0-b781-fea1c415432f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030647343 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1030647343
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.77157679
Short name T133
Test name
Test status
Simulation time 69288791 ps
CPU time 0.95 seconds
Started Jul 06 04:45:41 PM PDT 24
Finished Jul 06 04:45:43 PM PDT 24
Peak memory 205264 kb
Host smart-78487eca-de11-4a53-95bb-62502a25dd0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77157679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.77157679
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3181099894
Short name T971
Test name
Test status
Simulation time 94072531 ps
CPU time 0.82 seconds
Started Jul 06 04:45:43 PM PDT 24
Finished Jul 06 04:45:44 PM PDT 24
Peak memory 205192 kb
Host smart-d1c14d6f-32c4-4e40-a0d1-5affe0e43516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181099894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3181099894
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.4073325537
Short name T1003
Test name
Test status
Simulation time 242278432 ps
CPU time 1.77 seconds
Started Jul 06 04:45:40 PM PDT 24
Finished Jul 06 04:45:43 PM PDT 24
Peak memory 205344 kb
Host smart-cabbd5f9-726f-4ba7-b74b-de4a96056417
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073325537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.4073325537
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2173446686
Short name T965
Test name
Test status
Simulation time 204749085 ps
CPU time 3.08 seconds
Started Jul 06 04:45:40 PM PDT 24
Finished Jul 06 04:45:43 PM PDT 24
Peak memory 214052 kb
Host smart-eafb044c-d2a7-4709-a3d8-befa1f679ab6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173446686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2173446686
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1875539810
Short name T991
Test name
Test status
Simulation time 1812891565 ps
CPU time 8.69 seconds
Started Jul 06 04:45:40 PM PDT 24
Finished Jul 06 04:45:49 PM PDT 24
Peak memory 213984 kb
Host smart-94fda984-309f-4ec3-827c-d9eae10f8113
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875539810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1875539810
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1855023158
Short name T974
Test name
Test status
Simulation time 54418843 ps
CPU time 2.21 seconds
Started Jul 06 04:45:41 PM PDT 24
Finished Jul 06 04:45:44 PM PDT 24
Peak memory 213520 kb
Host smart-ed3765d6-647a-464a-854f-9dfff3c1504b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855023158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1855023158
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2286013669
Short name T162
Test name
Test status
Simulation time 205389127 ps
CPU time 4.41 seconds
Started Jul 06 04:45:51 PM PDT 24
Finished Jul 06 04:45:56 PM PDT 24
Peak memory 213528 kb
Host smart-aecfc4ca-c908-4414-9d92-adc95cf1ce3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286013669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2286013669
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2903850891
Short name T1081
Test name
Test status
Simulation time 58395842 ps
CPU time 2.16 seconds
Started Jul 06 04:45:41 PM PDT 24
Finished Jul 06 04:45:44 PM PDT 24
Peak memory 213760 kb
Host smart-ed502645-04da-4f32-85ee-a8f87568c841
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903850891 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2903850891
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.4095374296
Short name T1030
Test name
Test status
Simulation time 55695293 ps
CPU time 1.08 seconds
Started Jul 06 04:45:42 PM PDT 24
Finished Jul 06 04:45:43 PM PDT 24
Peak memory 205468 kb
Host smart-0a462ff2-9aad-4e00-a80b-1e14a4f263c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095374296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.4095374296
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2188069538
Short name T1034
Test name
Test status
Simulation time 34395178 ps
CPU time 0.85 seconds
Started Jul 06 04:45:39 PM PDT 24
Finished Jul 06 04:45:41 PM PDT 24
Peak memory 205184 kb
Host smart-4e80d0f6-698b-41a2-8d8d-7b1c5721c4f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188069538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2188069538
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.509560602
Short name T1008
Test name
Test status
Simulation time 196160570 ps
CPU time 1.77 seconds
Started Jul 06 04:45:42 PM PDT 24
Finished Jul 06 04:45:44 PM PDT 24
Peak memory 205344 kb
Host smart-cf5dd44d-5cd7-4997-a96a-4124ea07a68d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509560602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.509560602
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3073091533
Short name T1084
Test name
Test status
Simulation time 120926516 ps
CPU time 1.42 seconds
Started Jul 06 04:45:41 PM PDT 24
Finished Jul 06 04:45:43 PM PDT 24
Peak memory 213720 kb
Host smart-c51529fb-18af-40f8-9b97-7486b6e10a84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073091533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3073091533
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1114547506
Short name T1025
Test name
Test status
Simulation time 88837530 ps
CPU time 4.1 seconds
Started Jul 06 04:45:43 PM PDT 24
Finished Jul 06 04:45:47 PM PDT 24
Peak memory 219824 kb
Host smart-f2a0ba5c-78c8-4beb-ac34-031d7a9cf026
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114547506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1114547506
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.4041032052
Short name T980
Test name
Test status
Simulation time 57434291 ps
CPU time 2.18 seconds
Started Jul 06 04:45:40 PM PDT 24
Finished Jul 06 04:45:43 PM PDT 24
Peak memory 213592 kb
Host smart-c3a2ec8c-daf0-421c-9f6a-ff6b5035da08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041032052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.4041032052
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1464563301
Short name T132
Test name
Test status
Simulation time 1023202212 ps
CPU time 5.75 seconds
Started Jul 06 04:45:01 PM PDT 24
Finished Jul 06 04:45:07 PM PDT 24
Peak memory 205364 kb
Host smart-dea37283-c746-465b-8630-81736d7bfb90
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464563301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
464563301
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1322623877
Short name T935
Test name
Test status
Simulation time 747035560 ps
CPU time 12.58 seconds
Started Jul 06 04:45:00 PM PDT 24
Finished Jul 06 04:45:13 PM PDT 24
Peak memory 205480 kb
Host smart-fa29872d-677b-4cec-b229-488c2740000b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322623877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
322623877
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.4045185219
Short name T1015
Test name
Test status
Simulation time 102543113 ps
CPU time 1.03 seconds
Started Jul 06 04:44:59 PM PDT 24
Finished Jul 06 04:45:01 PM PDT 24
Peak memory 205340 kb
Host smart-773a977c-042e-4ec7-a2e1-ab747f69d08b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045185219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.4
045185219
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.521219449
Short name T181
Test name
Test status
Simulation time 382654873 ps
CPU time 1.59 seconds
Started Jul 06 04:45:06 PM PDT 24
Finished Jul 06 04:45:08 PM PDT 24
Peak memory 213608 kb
Host smart-1aa032ae-10d6-4dcc-99cb-1fba858fc8c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521219449 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.521219449
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1631017019
Short name T946
Test name
Test status
Simulation time 24372418 ps
CPU time 1.28 seconds
Started Jul 06 04:44:59 PM PDT 24
Finished Jul 06 04:45:01 PM PDT 24
Peak memory 205412 kb
Host smart-7ab38e25-35f2-40a0-8ad8-08622efb91c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631017019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1631017019
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1080179161
Short name T1019
Test name
Test status
Simulation time 11774800 ps
CPU time 0.74 seconds
Started Jul 06 04:44:58 PM PDT 24
Finished Jul 06 04:44:59 PM PDT 24
Peak memory 205112 kb
Host smart-116e9222-d772-4d7f-b427-278031a5ba01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080179161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1080179161
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2599855953
Short name T1047
Test name
Test status
Simulation time 245779726 ps
CPU time 2.2 seconds
Started Jul 06 04:44:58 PM PDT 24
Finished Jul 06 04:45:01 PM PDT 24
Peak memory 205416 kb
Host smart-bd2b331d-8a33-495a-9808-f5b3b7e87cff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599855953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2599855953
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3438537301
Short name T954
Test name
Test status
Simulation time 179652840 ps
CPU time 2.19 seconds
Started Jul 06 04:45:02 PM PDT 24
Finished Jul 06 04:45:04 PM PDT 24
Peak memory 213896 kb
Host smart-3fcdf2da-57b2-4ba5-9a8f-d8c9a040d460
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438537301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3438537301
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.4195233552
Short name T109
Test name
Test status
Simulation time 960084509 ps
CPU time 9.1 seconds
Started Jul 06 04:45:00 PM PDT 24
Finished Jul 06 04:45:10 PM PDT 24
Peak memory 220028 kb
Host smart-32dfadaf-430b-45c2-9e72-9cc6fd2e2041
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195233552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.4195233552
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3010690234
Short name T173
Test name
Test status
Simulation time 124339011 ps
CPU time 4.48 seconds
Started Jul 06 04:45:01 PM PDT 24
Finished Jul 06 04:45:06 PM PDT 24
Peak memory 213604 kb
Host smart-dcac8404-9300-43e2-92dc-b48e5e0b83a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010690234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3010690234
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2907985373
Short name T1043
Test name
Test status
Simulation time 171241551 ps
CPU time 2.48 seconds
Started Jul 06 04:45:00 PM PDT 24
Finished Jul 06 04:45:02 PM PDT 24
Peak memory 213712 kb
Host smart-fa300959-f578-4c6d-af2c-ec244d4b8629
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907985373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2907985373
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3661816347
Short name T1057
Test name
Test status
Simulation time 37723166 ps
CPU time 0.87 seconds
Started Jul 06 04:45:41 PM PDT 24
Finished Jul 06 04:45:42 PM PDT 24
Peak memory 205216 kb
Host smart-c689a5f5-322e-4fdd-b927-f285b93a86fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661816347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3661816347
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2102981804
Short name T1079
Test name
Test status
Simulation time 11695542 ps
CPU time 0.75 seconds
Started Jul 06 04:45:42 PM PDT 24
Finished Jul 06 04:45:43 PM PDT 24
Peak memory 205148 kb
Host smart-ac6e0c8d-c16b-4d09-a64c-5ab31a8a97bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102981804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2102981804
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3619455750
Short name T1026
Test name
Test status
Simulation time 9197819 ps
CPU time 0.81 seconds
Started Jul 06 04:45:40 PM PDT 24
Finished Jul 06 04:45:41 PM PDT 24
Peak memory 205136 kb
Host smart-e124cf59-ee1f-473a-8e4f-3a66f1e1b26d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619455750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3619455750
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1614334125
Short name T967
Test name
Test status
Simulation time 53155860 ps
CPU time 0.82 seconds
Started Jul 06 04:45:41 PM PDT 24
Finished Jul 06 04:45:42 PM PDT 24
Peak memory 205204 kb
Host smart-8f762660-8c76-487b-8505-c425bb374d83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614334125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1614334125
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1294082714
Short name T964
Test name
Test status
Simulation time 142094711 ps
CPU time 0.76 seconds
Started Jul 06 04:45:49 PM PDT 24
Finished Jul 06 04:45:50 PM PDT 24
Peak memory 205192 kb
Host smart-0ce73a4b-9dbf-43b3-bfe9-bdc29f5bc920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294082714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1294082714
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1651331333
Short name T975
Test name
Test status
Simulation time 15275301 ps
CPU time 0.7 seconds
Started Jul 06 04:45:48 PM PDT 24
Finished Jul 06 04:45:49 PM PDT 24
Peak memory 205212 kb
Host smart-fa8b8569-45a7-4c29-b13a-bcdfa1c117c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651331333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1651331333
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.223530618
Short name T927
Test name
Test status
Simulation time 23973238 ps
CPU time 0.77 seconds
Started Jul 06 04:45:50 PM PDT 24
Finished Jul 06 04:45:51 PM PDT 24
Peak memory 205164 kb
Host smart-0835a5b1-adbf-4344-b282-03752eec4acb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223530618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.223530618
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.25492197
Short name T968
Test name
Test status
Simulation time 38430372 ps
CPU time 0.84 seconds
Started Jul 06 04:46:52 PM PDT 24
Finished Jul 06 04:46:53 PM PDT 24
Peak memory 205196 kb
Host smart-2c185308-bd38-415d-8c17-385eb6750dad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25492197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.25492197
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1837603079
Short name T1065
Test name
Test status
Simulation time 37969476 ps
CPU time 0.84 seconds
Started Jul 06 04:45:47 PM PDT 24
Finished Jul 06 04:45:48 PM PDT 24
Peak memory 205148 kb
Host smart-61281337-5166-49c4-9b5d-a7614bb96d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837603079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1837603079
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1290047460
Short name T990
Test name
Test status
Simulation time 121485497 ps
CPU time 0.85 seconds
Started Jul 06 04:45:46 PM PDT 24
Finished Jul 06 04:45:47 PM PDT 24
Peak memory 205192 kb
Host smart-0d08a7a3-1de2-4cf9-8fd0-9c0ad0206048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290047460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1290047460
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1563548637
Short name T983
Test name
Test status
Simulation time 128290381 ps
CPU time 7.61 seconds
Started Jul 06 04:45:04 PM PDT 24
Finished Jul 06 04:45:12 PM PDT 24
Peak memory 213608 kb
Host smart-e57c88a1-691c-4e2f-a9d6-a39a655f51b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563548637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
563548637
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3794477654
Short name T1076
Test name
Test status
Simulation time 133102565 ps
CPU time 6.17 seconds
Started Jul 06 04:45:07 PM PDT 24
Finished Jul 06 04:45:14 PM PDT 24
Peak memory 205420 kb
Host smart-8fd96827-8a4d-4c98-a8b4-96d109438ec8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794477654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
794477654
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3812197809
Short name T1061
Test name
Test status
Simulation time 24953261 ps
CPU time 1.01 seconds
Started Jul 06 04:45:07 PM PDT 24
Finished Jul 06 04:45:09 PM PDT 24
Peak memory 205420 kb
Host smart-e3f77ec9-6e58-483a-8a36-7b3d70612bf7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812197809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
812197809
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2665307703
Short name T1064
Test name
Test status
Simulation time 716732042 ps
CPU time 1.43 seconds
Started Jul 06 04:45:05 PM PDT 24
Finished Jul 06 04:45:06 PM PDT 24
Peak memory 213644 kb
Host smart-d4666d3b-87f7-490a-beea-308653d93076
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665307703 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2665307703
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3706003041
Short name T131
Test name
Test status
Simulation time 58170296 ps
CPU time 1.09 seconds
Started Jul 06 04:45:05 PM PDT 24
Finished Jul 06 04:45:07 PM PDT 24
Peak memory 205304 kb
Host smart-df9d6edb-d295-4262-b169-b797d7adf5bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706003041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3706003041
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1454875835
Short name T944
Test name
Test status
Simulation time 32979340 ps
CPU time 0.73 seconds
Started Jul 06 04:45:05 PM PDT 24
Finished Jul 06 04:45:06 PM PDT 24
Peak memory 205220 kb
Host smart-e622a6c0-fcb5-46e8-87c3-ab7f92dc9442
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454875835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1454875835
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2082329416
Short name T1040
Test name
Test status
Simulation time 353327878 ps
CPU time 2.87 seconds
Started Jul 06 04:45:07 PM PDT 24
Finished Jul 06 04:45:11 PM PDT 24
Peak memory 205396 kb
Host smart-32ec788a-df2c-484a-881c-690b859f8946
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082329416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2082329416
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.319756134
Short name T1020
Test name
Test status
Simulation time 98036757 ps
CPU time 2.38 seconds
Started Jul 06 04:45:11 PM PDT 24
Finished Jul 06 04:45:14 PM PDT 24
Peak memory 213888 kb
Host smart-24d86579-f7f4-491f-8abd-d9f72b215370
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319756134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.319756134
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.172794248
Short name T1063
Test name
Test status
Simulation time 171722314 ps
CPU time 3.32 seconds
Started Jul 06 04:45:07 PM PDT 24
Finished Jul 06 04:45:10 PM PDT 24
Peak memory 213604 kb
Host smart-1ef01d12-07d0-411e-bb5a-864a06426526
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172794248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.172794248
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.516159722
Short name T1009
Test name
Test status
Simulation time 34550348 ps
CPU time 0.75 seconds
Started Jul 06 04:45:49 PM PDT 24
Finished Jul 06 04:45:50 PM PDT 24
Peak memory 205192 kb
Host smart-f9a9023e-bd00-4ef7-881d-55b7a26b057c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516159722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.516159722
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2443115554
Short name T936
Test name
Test status
Simulation time 13094282 ps
CPU time 0.72 seconds
Started Jul 06 04:45:47 PM PDT 24
Finished Jul 06 04:45:48 PM PDT 24
Peak memory 205192 kb
Host smart-5a6552c1-4b08-4137-8a6f-cd61579394e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443115554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2443115554
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1746808667
Short name T1004
Test name
Test status
Simulation time 35920853 ps
CPU time 0.73 seconds
Started Jul 06 04:45:47 PM PDT 24
Finished Jul 06 04:45:48 PM PDT 24
Peak memory 205080 kb
Host smart-35a59f82-00ef-4834-a8fa-f3d15bb8eab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746808667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1746808667
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3680414338
Short name T960
Test name
Test status
Simulation time 165190164 ps
CPU time 0.74 seconds
Started Jul 06 04:45:46 PM PDT 24
Finished Jul 06 04:45:47 PM PDT 24
Peak memory 205104 kb
Host smart-1a511eeb-bbc9-4365-a034-f2596327bd86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680414338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3680414338
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3404137621
Short name T1085
Test name
Test status
Simulation time 15872544 ps
CPU time 0.83 seconds
Started Jul 06 04:45:51 PM PDT 24
Finished Jul 06 04:45:52 PM PDT 24
Peak memory 205168 kb
Host smart-68e36232-2274-48f7-97be-653ff27c59ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404137621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3404137621
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.4066301597
Short name T950
Test name
Test status
Simulation time 9228617 ps
CPU time 0.79 seconds
Started Jul 06 04:45:46 PM PDT 24
Finished Jul 06 04:45:47 PM PDT 24
Peak memory 205192 kb
Host smart-8538fbfe-820e-49f0-a505-71dcb6c707f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066301597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.4066301597
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.94802815
Short name T926
Test name
Test status
Simulation time 14921832 ps
CPU time 0.95 seconds
Started Jul 06 04:45:51 PM PDT 24
Finished Jul 06 04:45:52 PM PDT 24
Peak memory 204564 kb
Host smart-31a1282e-189a-465c-8863-dc6e5395f269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94802815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.94802815
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1049500114
Short name T973
Test name
Test status
Simulation time 18334469 ps
CPU time 0.94 seconds
Started Jul 06 04:45:46 PM PDT 24
Finished Jul 06 04:45:47 PM PDT 24
Peak memory 205268 kb
Host smart-a35ed0a7-862e-4f14-a52c-c8bbc392257f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049500114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1049500114
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.4283991900
Short name T957
Test name
Test status
Simulation time 36520357 ps
CPU time 0.73 seconds
Started Jul 06 04:45:48 PM PDT 24
Finished Jul 06 04:45:49 PM PDT 24
Peak memory 205124 kb
Host smart-34992b2d-6e13-419b-872f-7315e9dc5047
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283991900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.4283991900
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.359008295
Short name T952
Test name
Test status
Simulation time 40344895 ps
CPU time 0.73 seconds
Started Jul 06 04:45:47 PM PDT 24
Finished Jul 06 04:45:48 PM PDT 24
Peak memory 205184 kb
Host smart-0e1d0174-592d-44a4-b277-8832a2d32a2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359008295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.359008295
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.629619307
Short name T136
Test name
Test status
Simulation time 1386405564 ps
CPU time 7.87 seconds
Started Jul 06 04:45:12 PM PDT 24
Finished Jul 06 04:45:20 PM PDT 24
Peak memory 205340 kb
Host smart-884a225e-1288-4a19-a884-5c0ea9d835d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629619307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.629619307
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2451495593
Short name T988
Test name
Test status
Simulation time 993871462 ps
CPU time 12.04 seconds
Started Jul 06 04:45:14 PM PDT 24
Finished Jul 06 04:45:27 PM PDT 24
Peak memory 205320 kb
Host smart-f70674c8-2f28-4a44-b536-febaf61b3b9a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451495593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
451495593
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3535705450
Short name T931
Test name
Test status
Simulation time 164636124 ps
CPU time 1.13 seconds
Started Jul 06 04:45:23 PM PDT 24
Finished Jul 06 04:45:24 PM PDT 24
Peak memory 205336 kb
Host smart-e1857372-36b5-422b-a9df-76afca602920
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535705450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
535705450
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.259699021
Short name T1032
Test name
Test status
Simulation time 23253032 ps
CPU time 1.27 seconds
Started Jul 06 04:45:23 PM PDT 24
Finished Jul 06 04:45:24 PM PDT 24
Peak memory 205400 kb
Host smart-897f4d22-99c7-4fd0-8fdd-b27788b3fb80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259699021 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.259699021
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1104110504
Short name T1071
Test name
Test status
Simulation time 28110315 ps
CPU time 1.24 seconds
Started Jul 06 04:45:23 PM PDT 24
Finished Jul 06 04:45:24 PM PDT 24
Peak memory 205352 kb
Host smart-9c8e78ae-4efe-433f-9002-4dcf36d39dcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104110504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1104110504
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.4046850850
Short name T922
Test name
Test status
Simulation time 100175036 ps
CPU time 0.74 seconds
Started Jul 06 04:45:11 PM PDT 24
Finished Jul 06 04:45:12 PM PDT 24
Peak memory 205216 kb
Host smart-052701fd-277e-4ab4-8a90-1435447336ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046850850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.4046850850
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4109379086
Short name T966
Test name
Test status
Simulation time 261381075 ps
CPU time 1.58 seconds
Started Jul 06 04:45:11 PM PDT 24
Finished Jul 06 04:45:12 PM PDT 24
Peak memory 205484 kb
Host smart-7c647f9e-c1ba-4b70-ae0a-6926202fc96d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109379086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.4109379086
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3285734578
Short name T108
Test name
Test status
Simulation time 111679998 ps
CPU time 3.69 seconds
Started Jul 06 04:45:05 PM PDT 24
Finished Jul 06 04:45:09 PM PDT 24
Peak memory 213824 kb
Host smart-a7fc4ffc-1f09-4034-87e7-940ab63e75f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285734578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3285734578
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1579492402
Short name T994
Test name
Test status
Simulation time 1388648151 ps
CPU time 13.02 seconds
Started Jul 06 04:45:06 PM PDT 24
Finished Jul 06 04:45:19 PM PDT 24
Peak memory 213844 kb
Host smart-12592a70-b267-4107-8e46-d6095376ec5c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579492402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1579492402
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.441527992
Short name T1055
Test name
Test status
Simulation time 57763238 ps
CPU time 2.15 seconds
Started Jul 06 04:45:05 PM PDT 24
Finished Jul 06 04:45:08 PM PDT 24
Peak memory 213592 kb
Host smart-fda9820d-af26-4efa-9585-0c3c81d25cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441527992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.441527992
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3092089683
Short name T159
Test name
Test status
Simulation time 1539259144 ps
CPU time 8.67 seconds
Started Jul 06 04:45:07 PM PDT 24
Finished Jul 06 04:45:15 PM PDT 24
Peak memory 205400 kb
Host smart-30efb1af-835e-48f7-b3f9-b07eea9f38c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092089683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3092089683
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2603865578
Short name T949
Test name
Test status
Simulation time 56253408 ps
CPU time 0.86 seconds
Started Jul 06 04:45:45 PM PDT 24
Finished Jul 06 04:45:47 PM PDT 24
Peak memory 205112 kb
Host smart-92ba86c3-233f-45e8-99de-e624d767a5d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603865578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2603865578
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1145330216
Short name T1024
Test name
Test status
Simulation time 13122213 ps
CPU time 0.88 seconds
Started Jul 06 04:45:47 PM PDT 24
Finished Jul 06 04:45:48 PM PDT 24
Peak memory 205292 kb
Host smart-38ecfcd5-412a-40fb-ac54-53bdec50e115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145330216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1145330216
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.57129626
Short name T1056
Test name
Test status
Simulation time 19705111 ps
CPU time 0.96 seconds
Started Jul 06 04:45:49 PM PDT 24
Finished Jul 06 04:45:50 PM PDT 24
Peak memory 205260 kb
Host smart-22647bd0-91f5-4d22-9e63-e19a1cf81d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57129626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.57129626
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.387887086
Short name T924
Test name
Test status
Simulation time 12960123 ps
CPU time 0.95 seconds
Started Jul 06 04:45:50 PM PDT 24
Finished Jul 06 04:45:51 PM PDT 24
Peak memory 205192 kb
Host smart-997a9b1b-9289-411d-8a03-74d6e8f48500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387887086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.387887086
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1836043763
Short name T928
Test name
Test status
Simulation time 38596368 ps
CPU time 0.86 seconds
Started Jul 06 04:45:51 PM PDT 24
Finished Jul 06 04:45:53 PM PDT 24
Peak memory 205196 kb
Host smart-43922545-b898-48e5-a362-d08a1d2b8125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836043763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1836043763
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3331991558
Short name T921
Test name
Test status
Simulation time 38707887 ps
CPU time 0.84 seconds
Started Jul 06 04:45:45 PM PDT 24
Finished Jul 06 04:45:47 PM PDT 24
Peak memory 205112 kb
Host smart-e0b75d8d-76ac-4db2-9e06-59e10c3540f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331991558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3331991558
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2649909315
Short name T1023
Test name
Test status
Simulation time 18179740 ps
CPU time 0.86 seconds
Started Jul 06 04:45:49 PM PDT 24
Finished Jul 06 04:45:50 PM PDT 24
Peak memory 205224 kb
Host smart-d6568604-395b-46d4-aec8-741d124b12ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649909315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2649909315
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3073318060
Short name T989
Test name
Test status
Simulation time 31800485 ps
CPU time 0.78 seconds
Started Jul 06 04:45:51 PM PDT 24
Finished Jul 06 04:45:52 PM PDT 24
Peak memory 204272 kb
Host smart-2bca0ae8-ee41-454a-9f8e-75db232600f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073318060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3073318060
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.801220672
Short name T1010
Test name
Test status
Simulation time 9784343 ps
CPU time 0.82 seconds
Started Jul 06 04:45:48 PM PDT 24
Finished Jul 06 04:45:49 PM PDT 24
Peak memory 205168 kb
Host smart-06d8fce9-e67a-44d0-8e8d-21a24bbe18a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801220672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.801220672
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2282315832
Short name T1021
Test name
Test status
Simulation time 31853304 ps
CPU time 0.73 seconds
Started Jul 06 04:45:48 PM PDT 24
Finished Jul 06 04:45:49 PM PDT 24
Peak memory 205200 kb
Host smart-44625794-aace-4a60-a48f-8e516b7518aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282315832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2282315832
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2225905643
Short name T1078
Test name
Test status
Simulation time 27177398 ps
CPU time 1.67 seconds
Started Jul 06 04:45:12 PM PDT 24
Finished Jul 06 04:45:14 PM PDT 24
Peak memory 217696 kb
Host smart-cae0c2ab-5483-4781-b596-8100cfe359a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225905643 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2225905643
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1153210623
Short name T938
Test name
Test status
Simulation time 26509922 ps
CPU time 1.47 seconds
Started Jul 06 04:45:14 PM PDT 24
Finished Jul 06 04:45:16 PM PDT 24
Peak memory 205408 kb
Host smart-dd0425e1-4072-448f-ae1a-d84601fbd51c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153210623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1153210623
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3559787430
Short name T945
Test name
Test status
Simulation time 8664216 ps
CPU time 0.7 seconds
Started Jul 06 04:45:13 PM PDT 24
Finished Jul 06 04:45:14 PM PDT 24
Peak memory 205216 kb
Host smart-821446f9-6745-4a6f-82d7-920b15dcedc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559787430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3559787430
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3358026560
Short name T939
Test name
Test status
Simulation time 104607541 ps
CPU time 3.7 seconds
Started Jul 06 04:45:14 PM PDT 24
Finished Jul 06 04:45:18 PM PDT 24
Peak memory 205396 kb
Host smart-71223141-057d-4e3c-a591-bdbcdb4c614e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358026560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3358026560
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3668263417
Short name T1052
Test name
Test status
Simulation time 55459324 ps
CPU time 1.62 seconds
Started Jul 06 04:45:10 PM PDT 24
Finished Jul 06 04:45:12 PM PDT 24
Peak memory 213900 kb
Host smart-9f69e2be-a852-48c5-b104-a9528b02c588
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668263417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3668263417
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.367403321
Short name T1001
Test name
Test status
Simulation time 443193699 ps
CPU time 5.56 seconds
Started Jul 06 04:45:11 PM PDT 24
Finished Jul 06 04:45:17 PM PDT 24
Peak memory 219828 kb
Host smart-6d76eeed-4732-4434-91b1-819713e292ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367403321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.367403321
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2437079330
Short name T962
Test name
Test status
Simulation time 680953982 ps
CPU time 3.8 seconds
Started Jul 06 04:45:11 PM PDT 24
Finished Jul 06 04:45:15 PM PDT 24
Peak memory 213612 kb
Host smart-8aeab3cf-d145-4c21-8a7b-bba4a1a24c70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437079330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2437079330
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3245886127
Short name T1041
Test name
Test status
Simulation time 106782333 ps
CPU time 1.96 seconds
Started Jul 06 04:45:15 PM PDT 24
Finished Jul 06 04:45:18 PM PDT 24
Peak memory 213704 kb
Host smart-7f0816e8-b342-4efd-9507-30092ed5dfea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245886127 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3245886127
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.894675834
Short name T953
Test name
Test status
Simulation time 28773407 ps
CPU time 1.16 seconds
Started Jul 06 04:45:18 PM PDT 24
Finished Jul 06 04:45:19 PM PDT 24
Peak memory 205328 kb
Host smart-6aefaa98-69fe-4e41-bf24-b2138246f430
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894675834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.894675834
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.4239832112
Short name T972
Test name
Test status
Simulation time 13539317 ps
CPU time 0.7 seconds
Started Jul 06 04:45:15 PM PDT 24
Finished Jul 06 04:45:16 PM PDT 24
Peak memory 205156 kb
Host smart-f1c15756-f027-47da-9c5d-b398b06d99ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239832112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.4239832112
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2757711283
Short name T1058
Test name
Test status
Simulation time 81295092 ps
CPU time 1.35 seconds
Started Jul 06 04:45:16 PM PDT 24
Finished Jul 06 04:45:18 PM PDT 24
Peak memory 205404 kb
Host smart-9ec51942-dcd7-4a5f-b00d-677dc48bbc5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757711283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2757711283
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3870923604
Short name T1075
Test name
Test status
Simulation time 63523627 ps
CPU time 2.08 seconds
Started Jul 06 04:45:16 PM PDT 24
Finished Jul 06 04:45:19 PM PDT 24
Peak memory 205296 kb
Host smart-820e30e9-81cf-4cc5-86a0-a8fe7f43323a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870923604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3870923604
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3741690664
Short name T1018
Test name
Test status
Simulation time 866993801 ps
CPU time 14.32 seconds
Started Jul 06 04:45:17 PM PDT 24
Finished Jul 06 04:45:32 PM PDT 24
Peak memory 214292 kb
Host smart-99eb400e-e71e-47ee-aa0c-f8706ca4e84e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741690664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3741690664
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.648679912
Short name T1036
Test name
Test status
Simulation time 119556957 ps
CPU time 2.86 seconds
Started Jul 06 04:45:15 PM PDT 24
Finished Jul 06 04:45:19 PM PDT 24
Peak memory 213576 kb
Host smart-260431ad-3bb7-408a-ae39-24f108458319
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648679912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.648679912
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.306180026
Short name T942
Test name
Test status
Simulation time 50618557 ps
CPU time 2.44 seconds
Started Jul 06 04:45:20 PM PDT 24
Finished Jul 06 04:45:22 PM PDT 24
Peak memory 214052 kb
Host smart-c7690507-796d-4355-bdac-943309258d2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306180026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
306180026
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3258304840
Short name T1044
Test name
Test status
Simulation time 46815996 ps
CPU time 2.1 seconds
Started Jul 06 04:45:16 PM PDT 24
Finished Jul 06 04:45:18 PM PDT 24
Peak memory 213656 kb
Host smart-fb5ddb02-e5ec-4c1f-b22f-bd4acfa7ceed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258304840 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3258304840
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.526073335
Short name T986
Test name
Test status
Simulation time 100965173 ps
CPU time 1.19 seconds
Started Jul 06 04:45:24 PM PDT 24
Finished Jul 06 04:45:25 PM PDT 24
Peak memory 205260 kb
Host smart-60563f99-340c-4c1c-bd23-e75a14c5b81d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526073335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.526073335
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.470575470
Short name T963
Test name
Test status
Simulation time 42280829 ps
CPU time 0.8 seconds
Started Jul 06 04:45:16 PM PDT 24
Finished Jul 06 04:45:18 PM PDT 24
Peak memory 205108 kb
Host smart-cba912ed-d574-4b00-98d8-b70fa55e5849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470575470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.470575470
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.277215094
Short name T977
Test name
Test status
Simulation time 67387357 ps
CPU time 1.45 seconds
Started Jul 06 04:45:16 PM PDT 24
Finished Jul 06 04:45:18 PM PDT 24
Peak memory 205360 kb
Host smart-e0933da1-dc53-4820-9a89-7f6645780969
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277215094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.277215094
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.191534365
Short name T1083
Test name
Test status
Simulation time 224971332 ps
CPU time 3.95 seconds
Started Jul 06 04:45:17 PM PDT 24
Finished Jul 06 04:45:21 PM PDT 24
Peak memory 213892 kb
Host smart-1b24a3b4-1647-4f3c-92d4-0d8c9e4f7dbb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191534365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.191534365
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1697156370
Short name T1062
Test name
Test status
Simulation time 650212988 ps
CPU time 6.79 seconds
Started Jul 06 04:45:16 PM PDT 24
Finished Jul 06 04:45:23 PM PDT 24
Peak memory 213932 kb
Host smart-2185327d-de61-47d7-b560-da1823a5d7f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697156370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1697156370
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1649484698
Short name T1031
Test name
Test status
Simulation time 205087937 ps
CPU time 1.48 seconds
Started Jul 06 04:45:23 PM PDT 24
Finished Jul 06 04:45:25 PM PDT 24
Peak memory 213556 kb
Host smart-1d5c5c9b-0e90-4017-9f57-715bf073eb93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649484698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1649484698
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2122212669
Short name T150
Test name
Test status
Simulation time 99650526 ps
CPU time 4.27 seconds
Started Jul 06 04:45:20 PM PDT 24
Finished Jul 06 04:45:24 PM PDT 24
Peak memory 205808 kb
Host smart-db928a26-5273-49c7-afe7-3e996deb75b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122212669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2122212669
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.708113919
Short name T1013
Test name
Test status
Simulation time 173083448 ps
CPU time 1.79 seconds
Started Jul 06 04:45:17 PM PDT 24
Finished Jul 06 04:45:19 PM PDT 24
Peak memory 213628 kb
Host smart-68ee6229-391a-4333-b0b9-1861725b8d12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708113919 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.708113919
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.746421364
Short name T933
Test name
Test status
Simulation time 77730430 ps
CPU time 1.27 seconds
Started Jul 06 04:45:17 PM PDT 24
Finished Jul 06 04:45:18 PM PDT 24
Peak memory 205404 kb
Host smart-34f7f624-54ad-4a54-b425-934d76e19c4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746421364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.746421364
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.600429931
Short name T1039
Test name
Test status
Simulation time 8139577 ps
CPU time 0.78 seconds
Started Jul 06 04:45:20 PM PDT 24
Finished Jul 06 04:45:21 PM PDT 24
Peak memory 205080 kb
Host smart-80e9d6bb-69c3-46c6-9194-7ad75aec8768
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600429931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.600429931
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3572697303
Short name T999
Test name
Test status
Simulation time 138665647 ps
CPU time 2.23 seconds
Started Jul 06 04:45:23 PM PDT 24
Finished Jul 06 04:45:26 PM PDT 24
Peak memory 205392 kb
Host smart-23150e00-db4e-4cca-a8da-75bea743a398
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572697303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3572697303
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2293161986
Short name T1074
Test name
Test status
Simulation time 191092458 ps
CPU time 2.88 seconds
Started Jul 06 04:45:15 PM PDT 24
Finished Jul 06 04:45:18 PM PDT 24
Peak memory 213912 kb
Host smart-5febb091-4d53-45d4-b0f4-d42ea0b1bbbc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293161986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2293161986
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1339437005
Short name T112
Test name
Test status
Simulation time 173151182 ps
CPU time 7.12 seconds
Started Jul 06 04:45:18 PM PDT 24
Finished Jul 06 04:45:25 PM PDT 24
Peak memory 213856 kb
Host smart-6517fed7-24e3-48bd-8c43-4661489c9769
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339437005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1339437005
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.453972080
Short name T1053
Test name
Test status
Simulation time 268430946 ps
CPU time 3.53 seconds
Started Jul 06 04:45:18 PM PDT 24
Finished Jul 06 04:45:21 PM PDT 24
Peak memory 213608 kb
Host smart-ec75a742-ca80-4f70-9387-d1b0d46d5003
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453972080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.453972080
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4106996190
Short name T149
Test name
Test status
Simulation time 100564971 ps
CPU time 4.3 seconds
Started Jul 06 04:45:23 PM PDT 24
Finished Jul 06 04:45:28 PM PDT 24
Peak memory 205276 kb
Host smart-24bef960-be29-4de4-a703-f81ed47cbe10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106996190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.4106996190
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.218144982
Short name T1048
Test name
Test status
Simulation time 26474545 ps
CPU time 1.54 seconds
Started Jul 06 04:45:34 PM PDT 24
Finished Jul 06 04:45:36 PM PDT 24
Peak memory 213632 kb
Host smart-12c9d7b1-1581-40a7-b6da-b0a6a12fc69b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218144982 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.218144982
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1986554857
Short name T930
Test name
Test status
Simulation time 19723205 ps
CPU time 1.22 seconds
Started Jul 06 04:45:23 PM PDT 24
Finished Jul 06 04:45:24 PM PDT 24
Peak memory 205488 kb
Host smart-6817630d-218f-42c2-b9ab-b72e52c79371
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986554857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1986554857
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3945287508
Short name T978
Test name
Test status
Simulation time 152829969 ps
CPU time 0.91 seconds
Started Jul 06 04:45:17 PM PDT 24
Finished Jul 06 04:45:18 PM PDT 24
Peak memory 205140 kb
Host smart-b45e3e46-901e-458f-ae76-3ebe8e7f31ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945287508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3945287508
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.349088278
Short name T1033
Test name
Test status
Simulation time 197332376 ps
CPU time 2.37 seconds
Started Jul 06 04:45:25 PM PDT 24
Finished Jul 06 04:45:27 PM PDT 24
Peak memory 205420 kb
Host smart-89b77ea1-1731-4a96-a107-f003a1735c04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349088278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.349088278
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.333313944
Short name T114
Test name
Test status
Simulation time 156219839 ps
CPU time 2.47 seconds
Started Jul 06 04:45:19 PM PDT 24
Finished Jul 06 04:45:21 PM PDT 24
Peak memory 213832 kb
Host smart-7cc60dc6-c2f9-4f0c-9871-060e63ed2fe1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333313944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.333313944
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1495720690
Short name T1012
Test name
Test status
Simulation time 4759807602 ps
CPU time 10.23 seconds
Started Jul 06 04:45:16 PM PDT 24
Finished Jul 06 04:45:27 PM PDT 24
Peak memory 213892 kb
Host smart-77f70ced-06f3-4223-bc73-324acc9fc8c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495720690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1495720690
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2559253188
Short name T979
Test name
Test status
Simulation time 148632220 ps
CPU time 3.2 seconds
Started Jul 06 04:45:15 PM PDT 24
Finished Jul 06 04:45:19 PM PDT 24
Peak memory 215848 kb
Host smart-9c428437-4604-4be6-8f68-444682872760
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559253188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2559253188
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3525901939
Short name T148
Test name
Test status
Simulation time 70934880 ps
CPU time 3.33 seconds
Started Jul 06 04:45:17 PM PDT 24
Finished Jul 06 04:45:21 PM PDT 24
Peak memory 213596 kb
Host smart-30903f89-2aff-42ec-b04e-11709bfb68b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525901939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3525901939
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2944795426
Short name T748
Test name
Test status
Simulation time 58431792 ps
CPU time 0.77 seconds
Started Jul 06 04:46:41 PM PDT 24
Finished Jul 06 04:46:42 PM PDT 24
Peak memory 205828 kb
Host smart-17eb675b-08d2-4cab-9dee-4e34f9171026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944795426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2944795426
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1346749484
Short name T307
Test name
Test status
Simulation time 1002562653 ps
CPU time 26.53 seconds
Started Jul 06 04:46:38 PM PDT 24
Finished Jul 06 04:47:04 PM PDT 24
Peak memory 215284 kb
Host smart-0ea7798d-3ab3-4f76-b88a-a0a9e8eb39a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1346749484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1346749484
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3165122219
Short name T28
Test name
Test status
Simulation time 46057390 ps
CPU time 2.69 seconds
Started Jul 06 04:46:34 PM PDT 24
Finished Jul 06 04:46:37 PM PDT 24
Peak memory 206740 kb
Host smart-a0313a2e-beee-403b-9210-7d7d7416c93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165122219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3165122219
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3392782469
Short name T621
Test name
Test status
Simulation time 188227493 ps
CPU time 2.54 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:46:59 PM PDT 24
Peak memory 210132 kb
Host smart-4c2bf0b9-601a-43da-9676-064e7c6d499b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392782469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3392782469
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.4166286230
Short name T22
Test name
Test status
Simulation time 218541392 ps
CPU time 4.91 seconds
Started Jul 06 04:46:48 PM PDT 24
Finished Jul 06 04:46:54 PM PDT 24
Peak memory 208736 kb
Host smart-6d8843d9-616d-45e3-a9a4-645dcbb623af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166286230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.4166286230
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.4144957258
Short name T682
Test name
Test status
Simulation time 222734348 ps
CPU time 2.02 seconds
Started Jul 06 04:46:37 PM PDT 24
Finished Jul 06 04:46:39 PM PDT 24
Peak memory 219724 kb
Host smart-c299f34a-1411-40c2-9f29-9ddb0d6ea519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144957258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.4144957258
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3708148212
Short name T855
Test name
Test status
Simulation time 120683734 ps
CPU time 2.95 seconds
Started Jul 06 04:46:40 PM PDT 24
Finished Jul 06 04:46:43 PM PDT 24
Peak memory 218104 kb
Host smart-25dcb2a2-3547-4c78-b51e-3dd3b3f7bf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708148212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3708148212
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1749478599
Short name T9
Test name
Test status
Simulation time 2525355796 ps
CPU time 12.97 seconds
Started Jul 06 04:46:36 PM PDT 24
Finished Jul 06 04:46:49 PM PDT 24
Peak memory 230816 kb
Host smart-1ac3a919-3323-4281-8e11-f7907dad52bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749478599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1749478599
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3475268967
Short name T812
Test name
Test status
Simulation time 32171638 ps
CPU time 2.3 seconds
Started Jul 06 04:46:38 PM PDT 24
Finished Jul 06 04:46:40 PM PDT 24
Peak memory 206664 kb
Host smart-effb472e-a561-4580-b385-4bf76293b7ac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475268967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3475268967
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.155913503
Short name T457
Test name
Test status
Simulation time 204882197 ps
CPU time 3.46 seconds
Started Jul 06 04:46:49 PM PDT 24
Finished Jul 06 04:46:53 PM PDT 24
Peak memory 206852 kb
Host smart-2d5ec5b5-be7b-42e6-aec0-2e520964721c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155913503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.155913503
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2250330159
Short name T511
Test name
Test status
Simulation time 386274084 ps
CPU time 3.18 seconds
Started Jul 06 04:46:39 PM PDT 24
Finished Jul 06 04:46:42 PM PDT 24
Peak memory 208616 kb
Host smart-dd3317d2-92b9-4165-adb2-15e340e695be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250330159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2250330159
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2834224119
Short name T534
Test name
Test status
Simulation time 56379036 ps
CPU time 2.79 seconds
Started Jul 06 04:46:37 PM PDT 24
Finished Jul 06 04:46:40 PM PDT 24
Peak memory 208232 kb
Host smart-5ae2309a-d25d-4648-bed3-77e8c62db7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834224119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2834224119
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.531635877
Short name T904
Test name
Test status
Simulation time 58284642 ps
CPU time 3.29 seconds
Started Jul 06 04:46:35 PM PDT 24
Finished Jul 06 04:46:39 PM PDT 24
Peak memory 208016 kb
Host smart-22a34a3a-895b-464d-aa5a-56181d14bc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531635877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.531635877
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1671200173
Short name T646
Test name
Test status
Simulation time 490078174 ps
CPU time 1.71 seconds
Started Jul 06 04:46:40 PM PDT 24
Finished Jul 06 04:46:42 PM PDT 24
Peak memory 210036 kb
Host smart-64a1f261-60b7-4dad-828a-0431eb6fdcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671200173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1671200173
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.273002267
Short name T203
Test name
Test status
Simulation time 250983957 ps
CPU time 5.43 seconds
Started Jul 06 04:46:38 PM PDT 24
Finished Jul 06 04:46:44 PM PDT 24
Peak memory 209480 kb
Host smart-0048fce4-a1fa-4df7-8fb2-ae55f21304aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273002267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.273002267
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3009493302
Short name T678
Test name
Test status
Simulation time 118971894 ps
CPU time 2.68 seconds
Started Jul 06 04:46:39 PM PDT 24
Finished Jul 06 04:46:42 PM PDT 24
Peak memory 218316 kb
Host smart-c8d970c9-d3f3-40a7-b769-a2e0e6268a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009493302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3009493302
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2756138194
Short name T712
Test name
Test status
Simulation time 671045449 ps
CPU time 5.44 seconds
Started Jul 06 04:46:36 PM PDT 24
Finished Jul 06 04:46:42 PM PDT 24
Peak memory 208480 kb
Host smart-66295c9d-eb0e-4ec7-9934-214a7398797c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756138194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2756138194
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1658039909
Short name T300
Test name
Test status
Simulation time 116907479 ps
CPU time 4.09 seconds
Started Jul 06 04:46:35 PM PDT 24
Finished Jul 06 04:46:40 PM PDT 24
Peak memory 220304 kb
Host smart-cf183efe-cd24-49ea-9d25-426050333b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658039909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1658039909
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1151403690
Short name T644
Test name
Test status
Simulation time 282902135 ps
CPU time 3.31 seconds
Started Jul 06 04:46:41 PM PDT 24
Finished Jul 06 04:46:44 PM PDT 24
Peak memory 214280 kb
Host smart-03b9aaeb-16ad-46f2-a942-3cba673216ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151403690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1151403690
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3233686837
Short name T477
Test name
Test status
Simulation time 799986665 ps
CPU time 6.08 seconds
Started Jul 06 04:46:37 PM PDT 24
Finished Jul 06 04:46:44 PM PDT 24
Peak memory 209752 kb
Host smart-93934bbb-51eb-42ea-85cb-ed9f7329b60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233686837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3233686837
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1803132806
Short name T8
Test name
Test status
Simulation time 768483902 ps
CPU time 12.74 seconds
Started Jul 06 04:46:48 PM PDT 24
Finished Jul 06 04:47:02 PM PDT 24
Peak memory 237980 kb
Host smart-94e4e302-897f-4347-9941-ac781d204b2f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803132806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1803132806
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3767294107
Short name T255
Test name
Test status
Simulation time 85745109 ps
CPU time 3.27 seconds
Started Jul 06 04:46:48 PM PDT 24
Finished Jul 06 04:46:52 PM PDT 24
Peak memory 206836 kb
Host smart-095dd014-54e8-42e0-92d6-9769cfbbad1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767294107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3767294107
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.8937408
Short name T507
Test name
Test status
Simulation time 454208949 ps
CPU time 3.94 seconds
Started Jul 06 04:46:39 PM PDT 24
Finished Jul 06 04:46:43 PM PDT 24
Peak memory 208268 kb
Host smart-35405adc-e00a-4a78-93a8-933889481195
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8937408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.8937408
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3156896786
Short name T717
Test name
Test status
Simulation time 362196369 ps
CPU time 3.99 seconds
Started Jul 06 04:46:35 PM PDT 24
Finished Jul 06 04:46:40 PM PDT 24
Peak memory 208348 kb
Host smart-3788b620-a041-4c75-8a21-13f55a931409
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156896786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3156896786
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.272172288
Short name T702
Test name
Test status
Simulation time 36501591 ps
CPU time 2.29 seconds
Started Jul 06 04:46:36 PM PDT 24
Finished Jul 06 04:46:38 PM PDT 24
Peak memory 206864 kb
Host smart-2b7cf8a9-3d87-4ee4-85a8-de87fe628086
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272172288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.272172288
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3192839168
Short name T497
Test name
Test status
Simulation time 188710713 ps
CPU time 2.75 seconds
Started Jul 06 04:46:41 PM PDT 24
Finished Jul 06 04:46:44 PM PDT 24
Peak memory 208772 kb
Host smart-87fda7eb-60e7-4981-bbd2-7b9325c3dfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192839168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3192839168
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3894803598
Short name T186
Test name
Test status
Simulation time 204085977 ps
CPU time 2.47 seconds
Started Jul 06 04:46:41 PM PDT 24
Finished Jul 06 04:46:43 PM PDT 24
Peak memory 208740 kb
Host smart-e56c72f2-1302-48e7-a00b-5a7eb6ded5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894803598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3894803598
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1996734437
Short name T574
Test name
Test status
Simulation time 6771638401 ps
CPU time 40.61 seconds
Started Jul 06 04:46:37 PM PDT 24
Finished Jul 06 04:47:18 PM PDT 24
Peak memory 207916 kb
Host smart-38ca83ad-a862-4002-9c41-7ee529403a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996734437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1996734437
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1998906517
Short name T858
Test name
Test status
Simulation time 64476615 ps
CPU time 0.79 seconds
Started Jul 06 04:47:04 PM PDT 24
Finished Jul 06 04:47:06 PM PDT 24
Peak memory 205792 kb
Host smart-ef2c5988-2eaa-4924-ad03-ba45e87aacc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998906517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1998906517
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2825058822
Short name T240
Test name
Test status
Simulation time 37798640 ps
CPU time 2.76 seconds
Started Jul 06 04:47:04 PM PDT 24
Finished Jul 06 04:47:07 PM PDT 24
Peak memory 215324 kb
Host smart-5ce16f8f-810b-42b1-9ff3-aae71a8628fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2825058822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2825058822
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.4051378934
Short name T106
Test name
Test status
Simulation time 78545921 ps
CPU time 1.36 seconds
Started Jul 06 04:47:03 PM PDT 24
Finished Jul 06 04:47:05 PM PDT 24
Peak memory 206680 kb
Host smart-5f227c4f-1562-483e-a7fb-b22b5f31310f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051378934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.4051378934
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2818760437
Short name T778
Test name
Test status
Simulation time 332688918 ps
CPU time 4.47 seconds
Started Jul 06 04:47:04 PM PDT 24
Finished Jul 06 04:47:09 PM PDT 24
Peak memory 214220 kb
Host smart-d91ca2b9-9e9c-448f-83a6-831f371fd4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818760437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2818760437
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.694670203
Short name T770
Test name
Test status
Simulation time 95921398 ps
CPU time 3.22 seconds
Started Jul 06 04:47:03 PM PDT 24
Finished Jul 06 04:47:07 PM PDT 24
Peak memory 218424 kb
Host smart-2d4912ae-4375-4ec3-91c5-b9764d33e39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694670203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.694670203
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2682708921
Short name T715
Test name
Test status
Simulation time 57132991 ps
CPU time 2.74 seconds
Started Jul 06 04:47:00 PM PDT 24
Finished Jul 06 04:47:03 PM PDT 24
Peak memory 207896 kb
Host smart-0ba7b261-62a1-41e3-b4f9-6ae54af50958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682708921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2682708921
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2835807715
Short name T814
Test name
Test status
Simulation time 751261166 ps
CPU time 5.73 seconds
Started Jul 06 04:47:05 PM PDT 24
Finished Jul 06 04:47:12 PM PDT 24
Peak memory 208636 kb
Host smart-06b1f5e3-a73f-41b3-8feb-12d9ad4b3ad0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835807715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2835807715
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.4116197500
Short name T566
Test name
Test status
Simulation time 61536385 ps
CPU time 3.28 seconds
Started Jul 06 04:47:02 PM PDT 24
Finished Jul 06 04:47:06 PM PDT 24
Peak memory 208820 kb
Host smart-eb3068a1-e592-449b-b216-8b4bb0c706c4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116197500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.4116197500
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1333678597
Short name T641
Test name
Test status
Simulation time 171466929 ps
CPU time 4.37 seconds
Started Jul 06 04:47:05 PM PDT 24
Finished Jul 06 04:47:09 PM PDT 24
Peak memory 210064 kb
Host smart-81ede21f-eed7-466d-bc3d-109f870bbdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333678597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1333678597
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.424530208
Short name T405
Test name
Test status
Simulation time 844980192 ps
CPU time 4.85 seconds
Started Jul 06 04:47:04 PM PDT 24
Finished Jul 06 04:47:09 PM PDT 24
Peak memory 207852 kb
Host smart-00f70c22-dfd7-4e61-9315-b1cc5912a48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424530208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.424530208
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1857711881
Short name T809
Test name
Test status
Simulation time 999050293 ps
CPU time 16.38 seconds
Started Jul 06 04:47:03 PM PDT 24
Finished Jul 06 04:47:20 PM PDT 24
Peak memory 216352 kb
Host smart-759865db-28d7-4e97-8c5d-e785a8502bcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857711881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1857711881
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.765679672
Short name T754
Test name
Test status
Simulation time 420271673 ps
CPU time 16.57 seconds
Started Jul 06 04:47:02 PM PDT 24
Finished Jul 06 04:47:19 PM PDT 24
Peak memory 222504 kb
Host smart-93a761cc-06f3-4c78-ab31-dd8be46052b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765679672 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.765679672
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3807616259
Short name T680
Test name
Test status
Simulation time 152672199 ps
CPU time 6.9 seconds
Started Jul 06 04:47:04 PM PDT 24
Finished Jul 06 04:47:11 PM PDT 24
Peak memory 214228 kb
Host smart-988f2cab-f573-4a16-bec9-7a5d0a417350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807616259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3807616259
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1509825796
Short name T105
Test name
Test status
Simulation time 26360920 ps
CPU time 0.77 seconds
Started Jul 06 04:47:06 PM PDT 24
Finished Jul 06 04:47:08 PM PDT 24
Peak memory 205860 kb
Host smart-bc07a98e-ce38-4ce3-9772-301a8e09608f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509825796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1509825796
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1728755243
Short name T382
Test name
Test status
Simulation time 69846194 ps
CPU time 3.33 seconds
Started Jul 06 04:47:11 PM PDT 24
Finished Jul 06 04:47:15 PM PDT 24
Peak memory 214328 kb
Host smart-84380f4c-30dc-4175-8b2d-9d08dabc7de4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1728755243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1728755243
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2411517123
Short name T570
Test name
Test status
Simulation time 1244544254 ps
CPU time 18.37 seconds
Started Jul 06 04:47:06 PM PDT 24
Finished Jul 06 04:47:25 PM PDT 24
Peak memory 214220 kb
Host smart-18f97b78-b881-411d-a597-14077bb688bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411517123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2411517123
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3425506556
Short name T590
Test name
Test status
Simulation time 84200016 ps
CPU time 3.68 seconds
Started Jul 06 04:47:06 PM PDT 24
Finished Jul 06 04:47:11 PM PDT 24
Peak memory 214304 kb
Host smart-592277a5-7e25-4c3b-92b7-594ad2da0827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425506556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3425506556
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2529147100
Short name T788
Test name
Test status
Simulation time 587557173 ps
CPU time 8.11 seconds
Started Jul 06 04:47:07 PM PDT 24
Finished Jul 06 04:47:16 PM PDT 24
Peak memory 220692 kb
Host smart-bc46ddc9-768c-43a7-8b23-b2e68980ec46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529147100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2529147100
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2765713868
Short name T206
Test name
Test status
Simulation time 45864744 ps
CPU time 2.59 seconds
Started Jul 06 04:47:06 PM PDT 24
Finished Jul 06 04:47:10 PM PDT 24
Peak memory 216248 kb
Host smart-cdad3f1c-cbf6-45cd-95d1-c4f67df347bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765713868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2765713868
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.4002729376
Short name T430
Test name
Test status
Simulation time 372682274 ps
CPU time 3.88 seconds
Started Jul 06 04:47:11 PM PDT 24
Finished Jul 06 04:47:16 PM PDT 24
Peak memory 207664 kb
Host smart-258d35a2-c355-44c4-8358-625bb49c4fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002729376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.4002729376
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3834906768
Short name T650
Test name
Test status
Simulation time 7453717849 ps
CPU time 48.33 seconds
Started Jul 06 04:47:15 PM PDT 24
Finished Jul 06 04:48:04 PM PDT 24
Peak memory 208220 kb
Host smart-ee1f0be6-b219-4e9a-856f-f3f86b5cf235
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834906768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3834906768
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3637104574
Short name T45
Test name
Test status
Simulation time 804286757 ps
CPU time 21.75 seconds
Started Jul 06 04:47:07 PM PDT 24
Finished Jul 06 04:47:29 PM PDT 24
Peak memory 207712 kb
Host smart-ad4925e9-17b5-490e-a333-05b82e6710c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637104574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3637104574
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.584505136
Short name T227
Test name
Test status
Simulation time 7172425456 ps
CPU time 46.74 seconds
Started Jul 06 04:47:06 PM PDT 24
Finished Jul 06 04:47:54 PM PDT 24
Peak memory 208712 kb
Host smart-61b26143-72f5-4b83-b410-a343d8f78a60
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584505136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.584505136
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2987132904
Short name T401
Test name
Test status
Simulation time 555397413 ps
CPU time 3.49 seconds
Started Jul 06 04:47:14 PM PDT 24
Finished Jul 06 04:47:18 PM PDT 24
Peak memory 209092 kb
Host smart-95470bbe-97ec-445c-892d-e6742de1a881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987132904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2987132904
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2276930716
Short name T185
Test name
Test status
Simulation time 202647253 ps
CPU time 5.38 seconds
Started Jul 06 04:47:15 PM PDT 24
Finished Jul 06 04:47:21 PM PDT 24
Peak memory 208392 kb
Host smart-c81bc4a3-aa29-4959-8167-8ee07aaa5bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276930716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2276930716
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3349618472
Short name T576
Test name
Test status
Simulation time 549707478 ps
CPU time 8.93 seconds
Started Jul 06 04:47:06 PM PDT 24
Finished Jul 06 04:47:16 PM PDT 24
Peak memory 214332 kb
Host smart-d0372fd8-8e57-4006-8f8a-2386a7608f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349618472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3349618472
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1988422558
Short name T153
Test name
Test status
Simulation time 458144014 ps
CPU time 8.93 seconds
Started Jul 06 04:47:09 PM PDT 24
Finished Jul 06 04:47:18 PM PDT 24
Peak memory 210928 kb
Host smart-13a4351e-32d3-4aa3-9769-94c7f050c81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988422558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1988422558
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3929450385
Short name T624
Test name
Test status
Simulation time 25088793 ps
CPU time 0.88 seconds
Started Jul 06 04:47:10 PM PDT 24
Finished Jul 06 04:47:11 PM PDT 24
Peak memory 205876 kb
Host smart-c801fb8c-1485-47be-8c3b-a02e233cfc1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929450385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3929450385
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.822612307
Short name T385
Test name
Test status
Simulation time 227356382 ps
CPU time 3.89 seconds
Started Jul 06 04:47:06 PM PDT 24
Finished Jul 06 04:47:11 PM PDT 24
Peak memory 215196 kb
Host smart-bf6cd110-f10c-4146-8a1f-231a02285575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=822612307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.822612307
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.4151480355
Short name T25
Test name
Test status
Simulation time 440978994 ps
CPU time 2.57 seconds
Started Jul 06 04:47:06 PM PDT 24
Finished Jul 06 04:47:10 PM PDT 24
Peak memory 210732 kb
Host smart-12840dd6-3407-4c28-ba88-165a5b87b0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151480355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.4151480355
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2916800382
Short name T69
Test name
Test status
Simulation time 152118244 ps
CPU time 3.23 seconds
Started Jul 06 04:47:06 PM PDT 24
Finished Jul 06 04:47:11 PM PDT 24
Peak memory 214228 kb
Host smart-ef9424fd-fd91-482d-8dac-26a6995b3cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916800382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2916800382
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3798656790
Short name T711
Test name
Test status
Simulation time 575965862 ps
CPU time 5.23 seconds
Started Jul 06 04:47:11 PM PDT 24
Finished Jul 06 04:47:16 PM PDT 24
Peak memory 220836 kb
Host smart-dbbf87a8-7bea-4fed-b9e2-ad3fe92c1507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798656790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3798656790
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3559185931
Short name T686
Test name
Test status
Simulation time 366421635 ps
CPU time 3.63 seconds
Started Jul 06 04:47:15 PM PDT 24
Finished Jul 06 04:47:19 PM PDT 24
Peak memory 218760 kb
Host smart-678cbd71-ee1d-42e7-9edf-362f08ae83b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559185931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3559185931
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3479185586
Short name T411
Test name
Test status
Simulation time 173075021 ps
CPU time 5.2 seconds
Started Jul 06 04:47:09 PM PDT 24
Finished Jul 06 04:47:14 PM PDT 24
Peak memory 218368 kb
Host smart-ff371aad-9ce9-4480-b54a-526fd627e124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479185586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3479185586
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2240158174
Short name T919
Test name
Test status
Simulation time 74406849 ps
CPU time 2.75 seconds
Started Jul 06 04:47:05 PM PDT 24
Finished Jul 06 04:47:09 PM PDT 24
Peak memory 206768 kb
Host smart-9031f280-1718-4b6f-81a8-1121efcaf49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240158174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2240158174
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.4192244096
Short name T806
Test name
Test status
Simulation time 55206977 ps
CPU time 2.92 seconds
Started Jul 06 04:47:08 PM PDT 24
Finished Jul 06 04:47:11 PM PDT 24
Peak memory 208844 kb
Host smart-6b722f12-1314-4fdf-bab2-e152360fc8cf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192244096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.4192244096
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.558598460
Short name T437
Test name
Test status
Simulation time 122440911 ps
CPU time 4.45 seconds
Started Jul 06 04:47:10 PM PDT 24
Finished Jul 06 04:47:15 PM PDT 24
Peak memory 206824 kb
Host smart-257ada83-da59-4ab7-a1ff-d0b5593f8c1a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558598460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.558598460
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2097181247
Short name T877
Test name
Test status
Simulation time 54157659 ps
CPU time 2.21 seconds
Started Jul 06 04:47:12 PM PDT 24
Finished Jul 06 04:47:14 PM PDT 24
Peak memory 208804 kb
Host smart-47bd4b83-efbc-44e2-8db2-e60deb9a3b0a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097181247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2097181247
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.150212234
Short name T489
Test name
Test status
Simulation time 378559027 ps
CPU time 3.71 seconds
Started Jul 06 04:47:06 PM PDT 24
Finished Jul 06 04:47:11 PM PDT 24
Peak memory 209228 kb
Host smart-d0224637-d07d-44c5-96da-eb85b0f6933f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150212234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.150212234
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2821900018
Short name T610
Test name
Test status
Simulation time 697092523 ps
CPU time 6.85 seconds
Started Jul 06 04:47:10 PM PDT 24
Finished Jul 06 04:47:18 PM PDT 24
Peak memory 206540 kb
Host smart-e23d55b4-17c0-4732-9d25-75ab388d2b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821900018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2821900018
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1550814992
Short name T863
Test name
Test status
Simulation time 121396213 ps
CPU time 4.26 seconds
Started Jul 06 04:47:08 PM PDT 24
Finished Jul 06 04:47:12 PM PDT 24
Peak memory 210000 kb
Host smart-71a86104-ded9-41ae-a388-6bf0408465fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550814992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1550814992
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.118471571
Short name T838
Test name
Test status
Simulation time 1639775163 ps
CPU time 4.51 seconds
Started Jul 06 04:47:05 PM PDT 24
Finished Jul 06 04:47:10 PM PDT 24
Peak memory 210744 kb
Host smart-c5792982-d3f5-40e8-922a-db7363786f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118471571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.118471571
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.460162727
Short name T398
Test name
Test status
Simulation time 17555025 ps
CPU time 0.98 seconds
Started Jul 06 04:47:14 PM PDT 24
Finished Jul 06 04:47:15 PM PDT 24
Peak memory 206100 kb
Host smart-59f51a7b-299d-41e7-9912-37ba1b066bed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460162727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.460162727
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2552725281
Short name T38
Test name
Test status
Simulation time 145593310 ps
CPU time 4.79 seconds
Started Jul 06 04:47:15 PM PDT 24
Finished Jul 06 04:47:20 PM PDT 24
Peak memory 210280 kb
Host smart-e9a85b37-894c-45ba-a2f6-97cf06b05432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552725281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2552725281
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.887110821
Short name T65
Test name
Test status
Simulation time 77245833 ps
CPU time 3.52 seconds
Started Jul 06 04:47:12 PM PDT 24
Finished Jul 06 04:47:16 PM PDT 24
Peak memory 209412 kb
Host smart-9339c7be-ebed-4f39-8338-0fc84cb6f10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887110821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.887110821
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1398097808
Short name T84
Test name
Test status
Simulation time 101916544 ps
CPU time 3.36 seconds
Started Jul 06 04:47:11 PM PDT 24
Finished Jul 06 04:47:15 PM PDT 24
Peak memory 222376 kb
Host smart-d66fdfce-4b32-4b7e-bce0-2a8c08f7ac7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398097808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1398097808
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2390386612
Short name T917
Test name
Test status
Simulation time 113337533 ps
CPU time 1.59 seconds
Started Jul 06 04:47:11 PM PDT 24
Finished Jul 06 04:47:13 PM PDT 24
Peak memory 214124 kb
Host smart-7948737b-cf85-48e1-add2-05b0f9a5c03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390386612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2390386612
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2132936050
Short name T509
Test name
Test status
Simulation time 94396591 ps
CPU time 3.16 seconds
Started Jul 06 04:47:15 PM PDT 24
Finished Jul 06 04:47:19 PM PDT 24
Peak memory 210228 kb
Host smart-f4953b96-2075-4c02-a7f0-f3671e51e0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132936050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2132936050
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.4038964336
Short name T190
Test name
Test status
Simulation time 359937774 ps
CPU time 9.68 seconds
Started Jul 06 04:47:06 PM PDT 24
Finished Jul 06 04:47:17 PM PDT 24
Peak memory 214216 kb
Host smart-6c845278-41e9-4021-a1e4-25ba3fbaa269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038964336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.4038964336
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.126520914
Short name T311
Test name
Test status
Simulation time 33808516 ps
CPU time 2.27 seconds
Started Jul 06 04:47:08 PM PDT 24
Finished Jul 06 04:47:11 PM PDT 24
Peak memory 206940 kb
Host smart-401738fe-5705-48f5-9740-b7ec6385a7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126520914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.126520914
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.236416860
Short name T535
Test name
Test status
Simulation time 1795595853 ps
CPU time 60.51 seconds
Started Jul 06 04:47:10 PM PDT 24
Finished Jul 06 04:48:11 PM PDT 24
Peak memory 208444 kb
Host smart-829c541e-1b07-4851-b97f-132c49009938
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236416860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.236416860
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3040520999
Short name T519
Test name
Test status
Simulation time 108889510 ps
CPU time 2.8 seconds
Started Jul 06 04:47:07 PM PDT 24
Finished Jul 06 04:47:10 PM PDT 24
Peak memory 206868 kb
Host smart-fbd56147-e713-451a-a7c8-53a3e557daab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040520999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3040520999
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1223152733
Short name T813
Test name
Test status
Simulation time 268596956 ps
CPU time 4.4 seconds
Started Jul 06 04:47:10 PM PDT 24
Finished Jul 06 04:47:15 PM PDT 24
Peak memory 206800 kb
Host smart-22c18c90-f4f9-44b0-98cd-f9c878b81f38
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223152733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1223152733
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2554636282
Short name T688
Test name
Test status
Simulation time 372890377 ps
CPU time 3.41 seconds
Started Jul 06 04:47:15 PM PDT 24
Finished Jul 06 04:47:19 PM PDT 24
Peak memory 209476 kb
Host smart-e765e754-a514-470c-9895-dcc068f7631f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554636282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2554636282
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3827522557
Short name T187
Test name
Test status
Simulation time 25155509 ps
CPU time 2 seconds
Started Jul 06 04:47:11 PM PDT 24
Finished Jul 06 04:47:13 PM PDT 24
Peak memory 208732 kb
Host smart-c0a13f53-959d-45ea-830c-ae94d9010126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827522557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3827522557
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2583551637
Short name T79
Test name
Test status
Simulation time 108284549 ps
CPU time 2.8 seconds
Started Jul 06 04:47:13 PM PDT 24
Finished Jul 06 04:47:16 PM PDT 24
Peak memory 207188 kb
Host smart-c385cee1-f6d0-4bda-ad64-ad38ae16e737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583551637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2583551637
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2891427314
Short name T747
Test name
Test status
Simulation time 1524636345 ps
CPU time 21.03 seconds
Started Jul 06 04:47:19 PM PDT 24
Finished Jul 06 04:47:40 PM PDT 24
Peak memory 218240 kb
Host smart-49419e34-2039-4da2-b6f3-a26c6dbceb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891427314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2891427314
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.715827177
Short name T695
Test name
Test status
Simulation time 75441001 ps
CPU time 2.07 seconds
Started Jul 06 04:47:15 PM PDT 24
Finished Jul 06 04:47:18 PM PDT 24
Peak memory 210148 kb
Host smart-3803cbbe-8778-49a8-9290-407d09a0caa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715827177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.715827177
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1919276107
Short name T913
Test name
Test status
Simulation time 15876699 ps
CPU time 0.93 seconds
Started Jul 06 04:47:12 PM PDT 24
Finished Jul 06 04:47:13 PM PDT 24
Peak memory 205952 kb
Host smart-1bec2508-c76c-4c4a-ac94-d8b37ae1480d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919276107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1919276107
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3128727937
Short name T821
Test name
Test status
Simulation time 31066853 ps
CPU time 2.14 seconds
Started Jul 06 04:47:11 PM PDT 24
Finished Jul 06 04:47:13 PM PDT 24
Peak memory 214212 kb
Host smart-5225a31d-013d-4a6f-885c-c6375aaeeae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128727937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3128727937
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1860998329
Short name T656
Test name
Test status
Simulation time 348956381 ps
CPU time 2.91 seconds
Started Jul 06 04:47:14 PM PDT 24
Finished Jul 06 04:47:17 PM PDT 24
Peak memory 214228 kb
Host smart-d295867f-1b47-415b-948e-f1571b65ca54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860998329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1860998329
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.513353943
Short name T729
Test name
Test status
Simulation time 97786788 ps
CPU time 4.14 seconds
Started Jul 06 04:47:17 PM PDT 24
Finished Jul 06 04:47:21 PM PDT 24
Peak memory 218884 kb
Host smart-5cb58fd8-920f-491c-88c0-0414b7e53754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513353943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.513353943
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3278204810
Short name T609
Test name
Test status
Simulation time 215348260 ps
CPU time 3.92 seconds
Started Jul 06 04:47:11 PM PDT 24
Finished Jul 06 04:47:15 PM PDT 24
Peak memory 220388 kb
Host smart-04f37915-900a-4920-bd7f-5aa8db4b86a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278204810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3278204810
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2590728911
Short name T521
Test name
Test status
Simulation time 101778643 ps
CPU time 3.95 seconds
Started Jul 06 04:47:14 PM PDT 24
Finished Jul 06 04:47:18 PM PDT 24
Peak memory 208196 kb
Host smart-73d343bd-4c02-4b7a-8ff0-2a5572fda252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590728911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2590728911
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.116610398
Short name T652
Test name
Test status
Simulation time 50532080 ps
CPU time 2.79 seconds
Started Jul 06 04:47:15 PM PDT 24
Finished Jul 06 04:47:18 PM PDT 24
Peak memory 206800 kb
Host smart-c1c965ca-068e-40f3-a546-4f2f900bb3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116610398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.116610398
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2567685743
Short name T868
Test name
Test status
Simulation time 68287276 ps
CPU time 3.33 seconds
Started Jul 06 04:47:12 PM PDT 24
Finished Jul 06 04:47:16 PM PDT 24
Peak memory 207876 kb
Host smart-7d004470-1926-4e54-9343-37b43c9bc776
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567685743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2567685743
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.536830442
Short name T474
Test name
Test status
Simulation time 648846268 ps
CPU time 2.88 seconds
Started Jul 06 04:47:13 PM PDT 24
Finished Jul 06 04:47:16 PM PDT 24
Peak memory 207208 kb
Host smart-57508bcf-caaf-4cef-9291-708229e1847a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536830442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.536830442
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3035391199
Short name T777
Test name
Test status
Simulation time 212137684 ps
CPU time 6.08 seconds
Started Jul 06 04:47:12 PM PDT 24
Finished Jul 06 04:47:18 PM PDT 24
Peak memory 207988 kb
Host smart-104c5759-e49d-442b-89fb-011e22542a74
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035391199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3035391199
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1149770862
Short name T888
Test name
Test status
Simulation time 821206692 ps
CPU time 6.03 seconds
Started Jul 06 04:47:10 PM PDT 24
Finished Jul 06 04:47:16 PM PDT 24
Peak memory 214248 kb
Host smart-fe7f936e-a33d-4198-a356-c8f79b07ee2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149770862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1149770862
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3001700933
Short name T456
Test name
Test status
Simulation time 30422064 ps
CPU time 2.16 seconds
Started Jul 06 04:47:12 PM PDT 24
Finished Jul 06 04:47:15 PM PDT 24
Peak memory 208356 kb
Host smart-8a175128-bc29-492b-9ae7-3d24dc2fcd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001700933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3001700933
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.19434606
Short name T586
Test name
Test status
Simulation time 1253692965 ps
CPU time 10.02 seconds
Started Jul 06 04:47:12 PM PDT 24
Finished Jul 06 04:47:22 PM PDT 24
Peak memory 221832 kb
Host smart-574055f9-5e5b-4e72-8ea0-54dfa8c9b86f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19434606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.19434606
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.322957361
Short name T118
Test name
Test status
Simulation time 645707154 ps
CPU time 10.71 seconds
Started Jul 06 04:47:15 PM PDT 24
Finished Jul 06 04:47:27 PM PDT 24
Peak memory 222616 kb
Host smart-7d0ab213-21f7-4565-b756-a1fb74cadc95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322957361 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.322957361
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2923184332
Short name T605
Test name
Test status
Simulation time 673695610 ps
CPU time 4.66 seconds
Started Jul 06 04:47:15 PM PDT 24
Finished Jul 06 04:47:21 PM PDT 24
Peak memory 214216 kb
Host smart-355e915a-edcd-4b45-8a5e-661d8054d99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923184332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2923184332
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.4229703502
Short name T826
Test name
Test status
Simulation time 104616188 ps
CPU time 1.94 seconds
Started Jul 06 04:47:12 PM PDT 24
Finished Jul 06 04:47:15 PM PDT 24
Peak memory 209896 kb
Host smart-5742e959-d84c-40c8-b2df-0289a7c33a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229703502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.4229703502
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.453668727
Short name T658
Test name
Test status
Simulation time 12027415 ps
CPU time 0.76 seconds
Started Jul 06 04:47:20 PM PDT 24
Finished Jul 06 04:47:21 PM PDT 24
Peak memory 205848 kb
Host smart-9535cfff-5ca4-4d3b-a807-27af3356690e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453668727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.453668727
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.626448340
Short name T216
Test name
Test status
Simulation time 106125104 ps
CPU time 3.62 seconds
Started Jul 06 04:47:15 PM PDT 24
Finished Jul 06 04:47:19 PM PDT 24
Peak memory 214708 kb
Host smart-57d02216-ca35-4483-828b-fc451c4664a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626448340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.626448340
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1880845463
Short name T620
Test name
Test status
Simulation time 214922092 ps
CPU time 3.09 seconds
Started Jul 06 04:47:16 PM PDT 24
Finished Jul 06 04:47:20 PM PDT 24
Peak memory 210208 kb
Host smart-f75138d5-e0bc-4437-bd94-513cee5d686d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880845463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1880845463
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3562039750
Short name T354
Test name
Test status
Simulation time 1014888270 ps
CPU time 10.75 seconds
Started Jul 06 04:47:12 PM PDT 24
Finished Jul 06 04:47:24 PM PDT 24
Peak memory 214152 kb
Host smart-acd2da67-8bcf-4b28-bca6-a46fe059eea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562039750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3562039750
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1954470074
Short name T348
Test name
Test status
Simulation time 244200742 ps
CPU time 5.52 seconds
Started Jul 06 04:47:13 PM PDT 24
Finished Jul 06 04:47:19 PM PDT 24
Peak memory 214992 kb
Host smart-49f76063-d4f7-45b8-9f32-845972654961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954470074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1954470074
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3048917052
Short name T897
Test name
Test status
Simulation time 430249939 ps
CPU time 2.94 seconds
Started Jul 06 04:47:12 PM PDT 24
Finished Jul 06 04:47:16 PM PDT 24
Peak memory 219832 kb
Host smart-99e94c27-ebcf-4488-92a9-329fccc92d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048917052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3048917052
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2334584045
Short name T182
Test name
Test status
Simulation time 122450543 ps
CPU time 6.3 seconds
Started Jul 06 04:47:16 PM PDT 24
Finished Jul 06 04:47:23 PM PDT 24
Peak memory 209812 kb
Host smart-3a8b3429-63cf-4cb4-a046-65c9069b4604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334584045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2334584045
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3844559861
Short name T292
Test name
Test status
Simulation time 69716550 ps
CPU time 3.13 seconds
Started Jul 06 04:47:17 PM PDT 24
Finished Jul 06 04:47:20 PM PDT 24
Peak memory 208484 kb
Host smart-66a0088e-3350-4d09-81c4-dd4f69a97d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844559861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3844559861
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1064225829
Short name T671
Test name
Test status
Simulation time 391717331 ps
CPU time 3.64 seconds
Started Jul 06 04:47:14 PM PDT 24
Finished Jul 06 04:47:18 PM PDT 24
Peak memory 208768 kb
Host smart-d1247196-c391-4005-9867-20e603aa8b03
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064225829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1064225829
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.685266828
Short name T505
Test name
Test status
Simulation time 39297470 ps
CPU time 1.75 seconds
Started Jul 06 04:47:13 PM PDT 24
Finished Jul 06 04:47:15 PM PDT 24
Peak memory 206784 kb
Host smart-5c494d32-bc08-4825-9340-e8f9596e828a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685266828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.685266828
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3931409488
Short name T553
Test name
Test status
Simulation time 67304928 ps
CPU time 3.27 seconds
Started Jul 06 04:47:12 PM PDT 24
Finished Jul 06 04:47:16 PM PDT 24
Peak memory 207816 kb
Host smart-c9dc4943-4995-4dbe-b2a7-650a78443d58
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931409488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3931409488
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3414052617
Short name T660
Test name
Test status
Simulation time 605014017 ps
CPU time 4.46 seconds
Started Jul 06 04:47:18 PM PDT 24
Finished Jul 06 04:47:23 PM PDT 24
Peak memory 209764 kb
Host smart-2b52c840-63fa-43e3-8519-d85a22d89145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414052617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3414052617
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1564290678
Short name T696
Test name
Test status
Simulation time 124925949 ps
CPU time 2.47 seconds
Started Jul 06 04:47:13 PM PDT 24
Finished Jul 06 04:47:16 PM PDT 24
Peak memory 206708 kb
Host smart-d21dd875-3500-4ee7-8a39-7a3ac5f1fed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564290678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1564290678
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2923293168
Short name T733
Test name
Test status
Simulation time 176721653 ps
CPU time 4.15 seconds
Started Jul 06 04:47:13 PM PDT 24
Finished Jul 06 04:47:17 PM PDT 24
Peak memory 207104 kb
Host smart-0217887f-915c-4dc7-8c06-9cb958b5eb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923293168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2923293168
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2490529906
Short name T52
Test name
Test status
Simulation time 77960121 ps
CPU time 1.74 seconds
Started Jul 06 04:47:17 PM PDT 24
Finished Jul 06 04:47:19 PM PDT 24
Peak memory 209932 kb
Host smart-d313d7c8-88c1-43e5-b22c-78eb7ca6bab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490529906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2490529906
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1442481481
Short name T807
Test name
Test status
Simulation time 27257738 ps
CPU time 0.8 seconds
Started Jul 06 04:47:19 PM PDT 24
Finished Jul 06 04:47:20 PM PDT 24
Peak memory 205880 kb
Host smart-7214008b-93b2-4d3b-952d-e620e9fcb753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442481481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1442481481
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3950539537
Short name T327
Test name
Test status
Simulation time 188620897 ps
CPU time 3.64 seconds
Started Jul 06 04:47:20 PM PDT 24
Finished Jul 06 04:47:24 PM PDT 24
Peak memory 215052 kb
Host smart-794129df-6fdc-43c0-96f1-9124b96993ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3950539537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3950539537
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3262830910
Short name T18
Test name
Test status
Simulation time 150503818 ps
CPU time 2.1 seconds
Started Jul 06 04:47:17 PM PDT 24
Finished Jul 06 04:47:20 PM PDT 24
Peak memory 218608 kb
Host smart-4735d726-53d9-4e4a-aae9-9aa67e4d1b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262830910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3262830910
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2761962480
Short name T293
Test name
Test status
Simulation time 26494470 ps
CPU time 2.08 seconds
Started Jul 06 04:47:19 PM PDT 24
Finished Jul 06 04:47:22 PM PDT 24
Peak memory 207676 kb
Host smart-f2eb8821-33f4-460b-94b8-04b389a016da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761962480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2761962480
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2140906669
Short name T100
Test name
Test status
Simulation time 265392637 ps
CPU time 1.76 seconds
Started Jul 06 04:47:17 PM PDT 24
Finished Jul 06 04:47:20 PM PDT 24
Peak memory 214124 kb
Host smart-01ac0990-60b4-4c20-81a7-785b63075594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140906669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2140906669
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.74713345
Short name T726
Test name
Test status
Simulation time 319431971 ps
CPU time 2.28 seconds
Started Jul 06 04:47:18 PM PDT 24
Finished Jul 06 04:47:20 PM PDT 24
Peak memory 214204 kb
Host smart-dac92a05-4c67-4376-b426-7a597ef3edbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74713345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.74713345
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2292777694
Short name T738
Test name
Test status
Simulation time 50587733 ps
CPU time 3.38 seconds
Started Jul 06 04:47:19 PM PDT 24
Finished Jul 06 04:47:23 PM PDT 24
Peak memory 207324 kb
Host smart-15288079-85d3-4086-abde-fc768fea1891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292777694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2292777694
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1688051352
Short name T874
Test name
Test status
Simulation time 210931625 ps
CPU time 3.16 seconds
Started Jul 06 04:47:21 PM PDT 24
Finished Jul 06 04:47:24 PM PDT 24
Peak memory 208388 kb
Host smart-7ec06841-3dc0-432e-bc59-f70bacfc2d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688051352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1688051352
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1101512856
Short name T694
Test name
Test status
Simulation time 41160375 ps
CPU time 1.79 seconds
Started Jul 06 04:47:21 PM PDT 24
Finished Jul 06 04:47:23 PM PDT 24
Peak memory 206916 kb
Host smart-17eccd14-7332-47d4-b05b-c96e70284b1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101512856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1101512856
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1115154272
Short name T502
Test name
Test status
Simulation time 2935892607 ps
CPU time 29.44 seconds
Started Jul 06 04:47:17 PM PDT 24
Finished Jul 06 04:47:47 PM PDT 24
Peak memory 208376 kb
Host smart-89dc5bd8-f88a-4785-a667-0a2f564df512
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115154272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1115154272
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2338017724
Short name T648
Test name
Test status
Simulation time 43923310 ps
CPU time 1.86 seconds
Started Jul 06 04:47:21 PM PDT 24
Finished Jul 06 04:47:23 PM PDT 24
Peak memory 206904 kb
Host smart-b4b3ff9b-4a2c-4719-984e-543899e3066f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338017724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2338017724
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2846535235
Short name T869
Test name
Test status
Simulation time 108663983 ps
CPU time 2.1 seconds
Started Jul 06 04:47:18 PM PDT 24
Finished Jul 06 04:47:20 PM PDT 24
Peak memory 215672 kb
Host smart-952a7ab4-fb0b-4af2-8989-231e22321f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846535235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2846535235
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2118039923
Short name T372
Test name
Test status
Simulation time 118476705 ps
CPU time 2.72 seconds
Started Jul 06 04:47:22 PM PDT 24
Finished Jul 06 04:47:25 PM PDT 24
Peak memory 206540 kb
Host smart-d4090223-bfa5-4cef-b94a-d99e16c2d6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118039923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2118039923
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3896154347
Short name T752
Test name
Test status
Simulation time 182422862 ps
CPU time 6.47 seconds
Started Jul 06 04:47:17 PM PDT 24
Finished Jul 06 04:47:23 PM PDT 24
Peak memory 222484 kb
Host smart-d051b0f3-1db5-4fce-8695-70517ef25373
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896154347 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3896154347
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.397890930
Short name T836
Test name
Test status
Simulation time 274646080 ps
CPU time 10.15 seconds
Started Jul 06 04:47:22 PM PDT 24
Finished Jul 06 04:47:32 PM PDT 24
Peak memory 218296 kb
Host smart-3826aefe-5aa1-4c3a-ba88-4c8acc47d95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397890930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.397890930
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.774682942
Short name T693
Test name
Test status
Simulation time 56831570 ps
CPU time 2.46 seconds
Started Jul 06 04:47:21 PM PDT 24
Finished Jul 06 04:47:24 PM PDT 24
Peak memory 210088 kb
Host smart-24137024-63d6-447d-a867-4269496ebbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774682942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.774682942
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.221208322
Short name T796
Test name
Test status
Simulation time 25613183 ps
CPU time 1.03 seconds
Started Jul 06 04:47:29 PM PDT 24
Finished Jul 06 04:47:31 PM PDT 24
Peak memory 206016 kb
Host smart-74a8a73b-5ecc-45c4-bd94-477c4f2dcc81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221208322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.221208322
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2592966904
Short name T472
Test name
Test status
Simulation time 394792726 ps
CPU time 6.2 seconds
Started Jul 06 04:47:26 PM PDT 24
Finished Jul 06 04:47:33 PM PDT 24
Peak memory 207848 kb
Host smart-43194fdb-3414-4050-991a-b5c6c691f610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592966904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2592966904
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.4237974360
Short name T220
Test name
Test status
Simulation time 1996826365 ps
CPU time 13.85 seconds
Started Jul 06 04:47:25 PM PDT 24
Finished Jul 06 04:47:39 PM PDT 24
Peak memory 214308 kb
Host smart-52929065-3eb9-4b03-92b6-b7ff7f6a91c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237974360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.4237974360
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3279835993
Short name T238
Test name
Test status
Simulation time 60369047 ps
CPU time 3.21 seconds
Started Jul 06 04:47:29 PM PDT 24
Finished Jul 06 04:47:33 PM PDT 24
Peak memory 222252 kb
Host smart-ca9aac9e-6275-444c-8e61-9b0c0d0734cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279835993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3279835993
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.975086556
Short name T602
Test name
Test status
Simulation time 183296250 ps
CPU time 2.5 seconds
Started Jul 06 04:47:26 PM PDT 24
Finished Jul 06 04:47:29 PM PDT 24
Peak memory 208344 kb
Host smart-d68af6d5-eb11-40c6-9aad-26f6f5816fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975086556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.975086556
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3999209627
Short name T232
Test name
Test status
Simulation time 381490338 ps
CPU time 4.73 seconds
Started Jul 06 04:47:19 PM PDT 24
Finished Jul 06 04:47:24 PM PDT 24
Peak memory 209716 kb
Host smart-2f65f277-903b-4090-b5c7-3a4e7d08e161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999209627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3999209627
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2222720593
Short name T727
Test name
Test status
Simulation time 650296876 ps
CPU time 4.34 seconds
Started Jul 06 04:47:19 PM PDT 24
Finished Jul 06 04:47:24 PM PDT 24
Peak memory 208788 kb
Host smart-89c358f9-3b60-4b98-a49d-6d16173dc7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222720593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2222720593
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.76235654
Short name T483
Test name
Test status
Simulation time 187199858 ps
CPU time 4.47 seconds
Started Jul 06 04:47:21 PM PDT 24
Finished Jul 06 04:47:26 PM PDT 24
Peak memory 208712 kb
Host smart-4fb36ac8-39d7-4470-b3c3-3976fee3d5b1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76235654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.76235654
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2699729943
Short name T862
Test name
Test status
Simulation time 3819302551 ps
CPU time 26.83 seconds
Started Jul 06 04:47:19 PM PDT 24
Finished Jul 06 04:47:46 PM PDT 24
Peak memory 208936 kb
Host smart-aba5fcf4-43d4-462b-b91a-edbba39d15d2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699729943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2699729943
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2515591572
Short name T552
Test name
Test status
Simulation time 142606934 ps
CPU time 2.81 seconds
Started Jul 06 04:47:21 PM PDT 24
Finished Jul 06 04:47:24 PM PDT 24
Peak memory 208792 kb
Host smart-ccee8dcf-715c-4f3b-8f1e-cfcf9a5540e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515591572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2515591572
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2936190358
Short name T907
Test name
Test status
Simulation time 302374765 ps
CPU time 3.79 seconds
Started Jul 06 04:47:29 PM PDT 24
Finished Jul 06 04:47:33 PM PDT 24
Peak memory 214288 kb
Host smart-2f5bf16f-5985-4df0-a302-b5164a712e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936190358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2936190358
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2872229245
Short name T627
Test name
Test status
Simulation time 360221655 ps
CPU time 3.56 seconds
Started Jul 06 04:47:21 PM PDT 24
Finished Jul 06 04:47:25 PM PDT 24
Peak memory 208328 kb
Host smart-8490a45e-791b-45e8-8d44-489dd62a1c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872229245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2872229245
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3892414061
Short name T70
Test name
Test status
Simulation time 2381599887 ps
CPU time 21.56 seconds
Started Jul 06 04:47:27 PM PDT 24
Finished Jul 06 04:47:48 PM PDT 24
Peak memory 219208 kb
Host smart-e861006f-c124-426e-b0af-bce09b7fd8f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892414061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3892414061
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.266510635
Short name T440
Test name
Test status
Simulation time 1597914752 ps
CPU time 6.69 seconds
Started Jul 06 04:47:25 PM PDT 24
Finished Jul 06 04:47:32 PM PDT 24
Peak memory 208624 kb
Host smart-9a2e6209-74e3-46b2-bd56-235841f9dc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266510635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.266510635
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1356680487
Short name T356
Test name
Test status
Simulation time 178967430 ps
CPU time 3.86 seconds
Started Jul 06 04:47:25 PM PDT 24
Finished Jul 06 04:47:30 PM PDT 24
Peak memory 210024 kb
Host smart-cde039ba-3160-42f3-8283-e2eeb8335265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356680487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1356680487
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2912485623
Short name T550
Test name
Test status
Simulation time 51770279 ps
CPU time 0.92 seconds
Started Jul 06 04:47:34 PM PDT 24
Finished Jul 06 04:47:36 PM PDT 24
Peak memory 205892 kb
Host smart-c154220c-ff8a-4081-9c6b-8a703d44d9e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912485623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2912485623
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1799585796
Short name T26
Test name
Test status
Simulation time 126568442 ps
CPU time 3.35 seconds
Started Jul 06 04:47:28 PM PDT 24
Finished Jul 06 04:47:32 PM PDT 24
Peak memory 209936 kb
Host smart-807ee0e6-985f-4b45-a143-ea6dc93507c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799585796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1799585796
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2777243025
Short name T234
Test name
Test status
Simulation time 1311553262 ps
CPU time 3.8 seconds
Started Jul 06 04:47:41 PM PDT 24
Finished Jul 06 04:47:46 PM PDT 24
Peak memory 210340 kb
Host smart-c17e72cd-dcd5-4cc9-ae6d-fab10e4dc630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777243025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2777243025
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2528291154
Short name T873
Test name
Test status
Simulation time 132439030 ps
CPU time 2.62 seconds
Started Jul 06 04:47:29 PM PDT 24
Finished Jul 06 04:47:32 PM PDT 24
Peak memory 207108 kb
Host smart-17a687ce-1b95-4f24-ae06-682d0cd4f56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528291154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2528291154
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1446482181
Short name T34
Test name
Test status
Simulation time 238024992 ps
CPU time 4.24 seconds
Started Jul 06 04:47:26 PM PDT 24
Finished Jul 06 04:47:30 PM PDT 24
Peak memory 214128 kb
Host smart-176e61e0-a926-4398-8ea6-79d0ad1643a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446482181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1446482181
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1457562840
Short name T373
Test name
Test status
Simulation time 103784148 ps
CPU time 5.19 seconds
Started Jul 06 04:47:25 PM PDT 24
Finished Jul 06 04:47:31 PM PDT 24
Peak memory 207772 kb
Host smart-333a52f2-9da6-472d-8be7-669430716e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457562840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1457562840
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2332482217
Short name T400
Test name
Test status
Simulation time 1024124083 ps
CPU time 5.56 seconds
Started Jul 06 04:47:27 PM PDT 24
Finished Jul 06 04:47:33 PM PDT 24
Peak memory 207320 kb
Host smart-493f3479-f1f9-4d8d-9a8b-0b1bd0bcc205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332482217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2332482217
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1411722947
Short name T604
Test name
Test status
Simulation time 291579156 ps
CPU time 3.49 seconds
Started Jul 06 04:47:27 PM PDT 24
Finished Jul 06 04:47:31 PM PDT 24
Peak memory 208692 kb
Host smart-5a77cb10-0095-4065-ba86-d73a455616f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411722947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1411722947
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1581308606
Short name T677
Test name
Test status
Simulation time 143406291 ps
CPU time 2.78 seconds
Started Jul 06 04:47:27 PM PDT 24
Finished Jul 06 04:47:30 PM PDT 24
Peak memory 208780 kb
Host smart-354bbd9c-d23a-4177-8895-b629bbd32e1c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581308606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1581308606
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1552613839
Short name T102
Test name
Test status
Simulation time 398796049 ps
CPU time 6.04 seconds
Started Jul 06 04:47:26 PM PDT 24
Finished Jul 06 04:47:32 PM PDT 24
Peak memory 207884 kb
Host smart-8e98a25b-4d8a-4e05-97fc-8ea8136fa94c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552613839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1552613839
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3373663364
Short name T453
Test name
Test status
Simulation time 2064141483 ps
CPU time 13.44 seconds
Started Jul 06 04:47:26 PM PDT 24
Finished Jul 06 04:47:39 PM PDT 24
Peak memory 208960 kb
Host smart-3048f255-f698-4963-b41c-93f4431ae91b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373663364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3373663364
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3817491241
Short name T435
Test name
Test status
Simulation time 1047002748 ps
CPU time 11.65 seconds
Started Jul 06 04:47:27 PM PDT 24
Finished Jul 06 04:47:38 PM PDT 24
Peak memory 209064 kb
Host smart-3907c197-ab4c-49a4-ae69-2373a6e53292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817491241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3817491241
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2034405480
Short name T773
Test name
Test status
Simulation time 125338271 ps
CPU time 2.69 seconds
Started Jul 06 04:47:30 PM PDT 24
Finished Jul 06 04:47:32 PM PDT 24
Peak memory 206736 kb
Host smart-3024accf-e8cd-479d-b9d9-3a5dc97ceeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034405480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2034405480
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2519295151
Short name T370
Test name
Test status
Simulation time 225775866 ps
CPU time 6.81 seconds
Started Jul 06 04:47:25 PM PDT 24
Finished Jul 06 04:47:32 PM PDT 24
Peak memory 208624 kb
Host smart-778f6d4d-11ca-4fbe-b6ec-7972aa8081ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519295151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2519295151
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2404374431
Short name T683
Test name
Test status
Simulation time 403246615 ps
CPU time 7.56 seconds
Started Jul 06 04:47:25 PM PDT 24
Finished Jul 06 04:47:33 PM PDT 24
Peak memory 210844 kb
Host smart-beb51b1e-ecb2-40f2-a5aa-0559de2d0fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404374431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2404374431
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1802498577
Short name T799
Test name
Test status
Simulation time 31850404 ps
CPU time 1.09 seconds
Started Jul 06 04:47:37 PM PDT 24
Finished Jul 06 04:47:38 PM PDT 24
Peak memory 206024 kb
Host smart-592b1e7f-fdc5-42eb-a6a6-0dcbd58b2113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802498577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1802498577
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2078419976
Short name T577
Test name
Test status
Simulation time 41021389 ps
CPU time 1.91 seconds
Started Jul 06 04:47:37 PM PDT 24
Finished Jul 06 04:47:39 PM PDT 24
Peak memory 214328 kb
Host smart-b80892d5-2938-47c6-90a3-5f27c040e6dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2078419976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2078419976
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2738126260
Short name T31
Test name
Test status
Simulation time 48302761 ps
CPU time 2.4 seconds
Started Jul 06 04:47:38 PM PDT 24
Finished Jul 06 04:47:41 PM PDT 24
Peak memory 208108 kb
Host smart-8686c9ae-8275-4537-930b-6ee70e7fa723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738126260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2738126260
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2004888698
Short name T724
Test name
Test status
Simulation time 83785372 ps
CPU time 1.46 seconds
Started Jul 06 04:47:35 PM PDT 24
Finished Jul 06 04:47:37 PM PDT 24
Peak memory 207408 kb
Host smart-20db2f77-60bc-4c67-a446-4b85ad7ab573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004888698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2004888698
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1912348292
Short name T95
Test name
Test status
Simulation time 84655516 ps
CPU time 4.12 seconds
Started Jul 06 04:47:33 PM PDT 24
Finished Jul 06 04:47:37 PM PDT 24
Peak memory 209232 kb
Host smart-da59d30e-b183-4c0f-a702-84b339f9db49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912348292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1912348292
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1654177019
Short name T261
Test name
Test status
Simulation time 1448118357 ps
CPU time 5.16 seconds
Started Jul 06 04:47:40 PM PDT 24
Finished Jul 06 04:47:46 PM PDT 24
Peak memory 214960 kb
Host smart-0ab01083-8a98-4e6f-af7b-ae6cf3f6acb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654177019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1654177019
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.485832383
Short name T575
Test name
Test status
Simulation time 2223527528 ps
CPU time 4.99 seconds
Started Jul 06 04:47:38 PM PDT 24
Finished Jul 06 04:47:44 PM PDT 24
Peak memory 210196 kb
Host smart-82fba1fa-a36f-4076-a2df-47567c8ba495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485832383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.485832383
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.858000650
Short name T120
Test name
Test status
Simulation time 148478229 ps
CPU time 6.2 seconds
Started Jul 06 04:47:33 PM PDT 24
Finished Jul 06 04:47:40 PM PDT 24
Peak memory 219732 kb
Host smart-a38e345f-9579-4a6d-a9ea-dbb368aa443f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858000650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.858000650
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3925292066
Short name T591
Test name
Test status
Simulation time 64333230 ps
CPU time 3.56 seconds
Started Jul 06 04:47:34 PM PDT 24
Finished Jul 06 04:47:38 PM PDT 24
Peak memory 208664 kb
Host smart-89e6c054-5c58-4b88-aa5f-1de05b8dec75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925292066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3925292066
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1446339353
Short name T666
Test name
Test status
Simulation time 326255250 ps
CPU time 3.98 seconds
Started Jul 06 04:47:32 PM PDT 24
Finished Jul 06 04:47:36 PM PDT 24
Peak memory 208680 kb
Host smart-2ea11b7d-4430-4ae6-b315-c6b78291247b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446339353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1446339353
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1513053996
Short name T903
Test name
Test status
Simulation time 84793140 ps
CPU time 2.4 seconds
Started Jul 06 04:47:40 PM PDT 24
Finished Jul 06 04:47:43 PM PDT 24
Peak memory 206916 kb
Host smart-eab18420-b3b7-4334-82f0-55a316a69353
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513053996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1513053996
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3073799526
Short name T459
Test name
Test status
Simulation time 617318938 ps
CPU time 4.84 seconds
Started Jul 06 04:47:35 PM PDT 24
Finished Jul 06 04:47:40 PM PDT 24
Peak memory 208564 kb
Host smart-c3369777-e5a8-4c7b-a654-2f3202f803a9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073799526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3073799526
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2417530093
Short name T506
Test name
Test status
Simulation time 139572402 ps
CPU time 4.09 seconds
Started Jul 06 04:47:37 PM PDT 24
Finished Jul 06 04:47:42 PM PDT 24
Peak memory 209708 kb
Host smart-edad0611-0801-46ca-ba73-6ebbe75ccce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417530093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2417530093
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.375257733
Short name T403
Test name
Test status
Simulation time 3635494845 ps
CPU time 19.31 seconds
Started Jul 06 04:47:38 PM PDT 24
Finished Jul 06 04:47:58 PM PDT 24
Peak memory 207948 kb
Host smart-780b46d1-9260-47a7-8eb1-203d3c8015f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375257733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.375257733
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3482399389
Short name T629
Test name
Test status
Simulation time 295223235 ps
CPU time 16.9 seconds
Started Jul 06 04:47:35 PM PDT 24
Finished Jul 06 04:47:53 PM PDT 24
Peak memory 221672 kb
Host smart-7794e4ea-67df-4037-a43c-200e17c9529d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482399389 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3482399389
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2483957247
Short name T692
Test name
Test status
Simulation time 376349924 ps
CPU time 5.63 seconds
Started Jul 06 04:47:35 PM PDT 24
Finished Jul 06 04:47:41 PM PDT 24
Peak memory 218020 kb
Host smart-77e5f46e-3a32-4d34-aa91-22194dda9b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483957247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2483957247
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2750046437
Short name T359
Test name
Test status
Simulation time 312881170 ps
CPU time 5.21 seconds
Started Jul 06 04:47:38 PM PDT 24
Finished Jul 06 04:47:44 PM PDT 24
Peak memory 210640 kb
Host smart-46bd7e1e-5e76-49ac-ad74-2047e1869e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750046437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2750046437
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2192335793
Short name T558
Test name
Test status
Simulation time 16815945 ps
CPU time 0.91 seconds
Started Jul 06 04:46:53 PM PDT 24
Finished Jul 06 04:46:55 PM PDT 24
Peak memory 205968 kb
Host smart-1c7067c3-adf6-4496-a1fc-46412f70edc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192335793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2192335793
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.331128739
Short name T217
Test name
Test status
Simulation time 422934235 ps
CPU time 11.98 seconds
Started Jul 06 04:46:52 PM PDT 24
Finished Jul 06 04:47:05 PM PDT 24
Peak memory 214196 kb
Host smart-7484b6ce-f4cf-4d62-96ce-dc0071debb9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=331128739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.331128739
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3931694032
Short name T68
Test name
Test status
Simulation time 57211527 ps
CPU time 2.63 seconds
Started Jul 06 04:46:42 PM PDT 24
Finished Jul 06 04:46:45 PM PDT 24
Peak memory 209328 kb
Host smart-5af0d53a-e3d9-4a07-aaf5-6bbb2683cfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931694032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3931694032
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2852743042
Short name T93
Test name
Test status
Simulation time 209666262 ps
CPU time 4.8 seconds
Started Jul 06 04:46:42 PM PDT 24
Finished Jul 06 04:46:47 PM PDT 24
Peak memory 221876 kb
Host smart-f9b48a8c-c919-4363-9ec0-c93b15fe3dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852743042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2852743042
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.543091093
Short name T914
Test name
Test status
Simulation time 564103027 ps
CPU time 5.81 seconds
Started Jul 06 04:46:44 PM PDT 24
Finished Jul 06 04:46:50 PM PDT 24
Peak memory 214124 kb
Host smart-974f6a13-a121-4984-8738-ec452cced16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543091093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.543091093
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1406024568
Short name T201
Test name
Test status
Simulation time 175576505 ps
CPU time 3.71 seconds
Started Jul 06 04:46:43 PM PDT 24
Finished Jul 06 04:46:47 PM PDT 24
Peak memory 214212 kb
Host smart-690d548a-c00a-47af-adfc-88a1fd2daef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406024568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1406024568
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.554686471
Short name T137
Test name
Test status
Simulation time 464512276 ps
CPU time 5.65 seconds
Started Jul 06 04:46:46 PM PDT 24
Finished Jul 06 04:46:52 PM PDT 24
Peak memory 206996 kb
Host smart-43b27987-2bc0-46f0-b31b-0a641554bbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554686471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.554686471
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.19848047
Short name T43
Test name
Test status
Simulation time 1674678975 ps
CPU time 9.37 seconds
Started Jul 06 04:46:42 PM PDT 24
Finished Jul 06 04:46:51 PM PDT 24
Peak memory 233804 kb
Host smart-273dd7bf-ec27-4d8c-bc57-216aa09ccb02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19848047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.19848047
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2798586862
Short name T263
Test name
Test status
Simulation time 92607413 ps
CPU time 3.95 seconds
Started Jul 06 04:46:41 PM PDT 24
Finished Jul 06 04:46:45 PM PDT 24
Peak memory 208724 kb
Host smart-24606e77-f493-4a78-9ded-0c9c6567a131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798586862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2798586862
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1747661318
Short name T285
Test name
Test status
Simulation time 79249534 ps
CPU time 1.91 seconds
Started Jul 06 04:46:38 PM PDT 24
Finished Jul 06 04:46:40 PM PDT 24
Peak memory 206768 kb
Host smart-22d9754d-e11b-4444-bbcc-70f20a8998eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747661318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1747661318
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1823824810
Short name T417
Test name
Test status
Simulation time 700192709 ps
CPU time 2.9 seconds
Started Jul 06 04:46:35 PM PDT 24
Finished Jul 06 04:46:39 PM PDT 24
Peak memory 206728 kb
Host smart-7f69b320-918b-4218-ab25-b76c95d25641
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823824810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1823824810
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1589134918
Short name T308
Test name
Test status
Simulation time 299468282 ps
CPU time 3.49 seconds
Started Jul 06 04:46:36 PM PDT 24
Finished Jul 06 04:46:40 PM PDT 24
Peak memory 206908 kb
Host smart-6edbff93-60b9-4d46-953c-f0bca45c7f7a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589134918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1589134918
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1261804756
Short name T460
Test name
Test status
Simulation time 638601713 ps
CPU time 4.83 seconds
Started Jul 06 04:46:42 PM PDT 24
Finished Jul 06 04:46:47 PM PDT 24
Peak memory 208680 kb
Host smart-9f5df0b3-49bb-495d-970f-4fc04492122c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261804756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1261804756
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1138054655
Short name T848
Test name
Test status
Simulation time 196426303 ps
CPU time 2.54 seconds
Started Jul 06 04:46:41 PM PDT 24
Finished Jul 06 04:46:44 PM PDT 24
Peak memory 206720 kb
Host smart-9b25ad9d-75cf-4197-9eaf-3bc128f0ff52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138054655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1138054655
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2389367777
Short name T197
Test name
Test status
Simulation time 343484582 ps
CPU time 8.18 seconds
Started Jul 06 04:46:45 PM PDT 24
Finished Jul 06 04:46:53 PM PDT 24
Peak memory 219972 kb
Host smart-2f36cc91-5157-472f-9f6d-1fbb8b9b85f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389367777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2389367777
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3172091870
Short name T690
Test name
Test status
Simulation time 322862566 ps
CPU time 8.2 seconds
Started Jul 06 04:46:46 PM PDT 24
Finished Jul 06 04:46:55 PM PDT 24
Peak memory 208792 kb
Host smart-ac56c103-3aa2-4b08-8f7d-ded65b835689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172091870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3172091870
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3431800017
Short name T892
Test name
Test status
Simulation time 70409107 ps
CPU time 1.99 seconds
Started Jul 06 04:46:41 PM PDT 24
Finished Jul 06 04:46:44 PM PDT 24
Peak memory 209972 kb
Host smart-88e6b136-1943-4ea8-b688-b8f498e77085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431800017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3431800017
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.513019539
Short name T665
Test name
Test status
Simulation time 19681097 ps
CPU time 1.07 seconds
Started Jul 06 04:47:34 PM PDT 24
Finished Jul 06 04:47:35 PM PDT 24
Peak memory 205988 kb
Host smart-c15634c3-ae7d-437c-9caf-8e9e08c9be02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513019539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.513019539
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1364764862
Short name T561
Test name
Test status
Simulation time 79314822 ps
CPU time 2.91 seconds
Started Jul 06 04:47:37 PM PDT 24
Finished Jul 06 04:47:41 PM PDT 24
Peak memory 214216 kb
Host smart-7787fbf2-cc50-4691-a8c5-34040afc2d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364764862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1364764862
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2917949835
Short name T675
Test name
Test status
Simulation time 866312125 ps
CPU time 6.38 seconds
Started Jul 06 04:47:34 PM PDT 24
Finished Jul 06 04:47:41 PM PDT 24
Peak memory 218308 kb
Host smart-f6086114-4a13-4d11-9a96-d7b84f844af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917949835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2917949835
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2482114396
Short name T638
Test name
Test status
Simulation time 94224307 ps
CPU time 4.41 seconds
Started Jul 06 04:47:37 PM PDT 24
Finished Jul 06 04:47:42 PM PDT 24
Peak memory 207040 kb
Host smart-f5f47565-5c7b-436a-b655-306cdb1195e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482114396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2482114396
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.645369671
Short name T878
Test name
Test status
Simulation time 118699693 ps
CPU time 2.54 seconds
Started Jul 06 04:47:36 PM PDT 24
Finished Jul 06 04:47:39 PM PDT 24
Peak memory 222212 kb
Host smart-01a54059-b646-4abe-9503-31d6bf489661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645369671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.645369671
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1888497275
Short name T57
Test name
Test status
Simulation time 40515167 ps
CPU time 3.02 seconds
Started Jul 06 04:47:39 PM PDT 24
Finished Jul 06 04:47:43 PM PDT 24
Peak memory 214204 kb
Host smart-233677b1-2d37-4371-aab6-39d4491663e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888497275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1888497275
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.850975991
Short name T71
Test name
Test status
Simulation time 518420247 ps
CPU time 4.67 seconds
Started Jul 06 04:47:35 PM PDT 24
Finished Jul 06 04:47:40 PM PDT 24
Peak memory 208000 kb
Host smart-cca53064-133a-49a5-9884-babd83724ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850975991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.850975991
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1747521692
Short name T193
Test name
Test status
Simulation time 180925294 ps
CPU time 2.57 seconds
Started Jul 06 04:47:38 PM PDT 24
Finished Jul 06 04:47:42 PM PDT 24
Peak memory 206856 kb
Host smart-42253246-4c92-4156-93ce-af738f2a76c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747521692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1747521692
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.4070766360
Short name T612
Test name
Test status
Simulation time 3746349612 ps
CPU time 58.97 seconds
Started Jul 06 04:47:34 PM PDT 24
Finished Jul 06 04:48:34 PM PDT 24
Peak memory 208308 kb
Host smart-0ce98038-56f9-4f67-a911-93b5ef05123f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070766360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.4070766360
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2704862883
Short name T768
Test name
Test status
Simulation time 60139753 ps
CPU time 2.37 seconds
Started Jul 06 04:47:35 PM PDT 24
Finished Jul 06 04:47:37 PM PDT 24
Peak memory 206132 kb
Host smart-1ad16ba7-97fe-4e31-b4c6-07a518544d96
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704862883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2704862883
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.50303359
Short name T555
Test name
Test status
Simulation time 86363486 ps
CPU time 3.87 seconds
Started Jul 06 04:47:35 PM PDT 24
Finished Jul 06 04:47:39 PM PDT 24
Peak memory 208676 kb
Host smart-139cbf73-2381-4614-be78-66fa31a13222
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50303359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.50303359
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1528530420
Short name T672
Test name
Test status
Simulation time 508896564 ps
CPU time 5.78 seconds
Started Jul 06 04:47:34 PM PDT 24
Finished Jul 06 04:47:40 PM PDT 24
Peak memory 208316 kb
Host smart-2d85db76-0676-4ace-bea9-c5eb4228ee69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528530420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1528530420
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1078847325
Short name T282
Test name
Test status
Simulation time 10856290587 ps
CPU time 73.49 seconds
Started Jul 06 04:47:33 PM PDT 24
Finished Jul 06 04:48:47 PM PDT 24
Peak memory 222540 kb
Host smart-ff990b89-5d0d-4145-8050-bdaccb5e34fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078847325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1078847325
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1926325682
Short name T371
Test name
Test status
Simulation time 128073779 ps
CPU time 4.41 seconds
Started Jul 06 04:47:33 PM PDT 24
Finished Jul 06 04:47:38 PM PDT 24
Peak memory 209480 kb
Host smart-d84dae24-d80b-4bc0-b73b-95edd56f98b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926325682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1926325682
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.4116217139
Short name T157
Test name
Test status
Simulation time 92732057 ps
CPU time 3.47 seconds
Started Jul 06 04:47:36 PM PDT 24
Finished Jul 06 04:47:40 PM PDT 24
Peak memory 210056 kb
Host smart-b06f98cf-8dbb-4d7e-8ee9-4c384ced17bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116217139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.4116217139
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3448304528
Short name T475
Test name
Test status
Simulation time 40664803 ps
CPU time 0.86 seconds
Started Jul 06 04:47:33 PM PDT 24
Finished Jul 06 04:47:34 PM PDT 24
Peak memory 205912 kb
Host smart-f7bb7e57-891d-4438-b656-a8f6815fa62e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448304528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3448304528
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.356433861
Short name T228
Test name
Test status
Simulation time 90350310 ps
CPU time 3.07 seconds
Started Jul 06 04:47:33 PM PDT 24
Finished Jul 06 04:47:36 PM PDT 24
Peak memory 215336 kb
Host smart-d40b8676-fcb6-4689-acd1-144d16f09770
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=356433861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.356433861
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2041467083
Short name T860
Test name
Test status
Simulation time 358821700 ps
CPU time 2.84 seconds
Started Jul 06 04:47:31 PM PDT 24
Finished Jul 06 04:47:34 PM PDT 24
Peak memory 209440 kb
Host smart-94001863-9e65-40de-820b-4f4adc95aa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041467083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2041467083
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.4091107087
Short name T55
Test name
Test status
Simulation time 97588304 ps
CPU time 1.67 seconds
Started Jul 06 04:47:37 PM PDT 24
Finished Jul 06 04:47:39 PM PDT 24
Peak memory 209420 kb
Host smart-468a5eea-ae59-4152-b296-ffe165afecf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091107087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.4091107087
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3412349908
Short name T351
Test name
Test status
Simulation time 794193761 ps
CPU time 6.47 seconds
Started Jul 06 04:47:36 PM PDT 24
Finished Jul 06 04:47:42 PM PDT 24
Peak memory 214124 kb
Host smart-79819511-492f-4739-a80f-6729573fff4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412349908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3412349908
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.544909934
Short name T213
Test name
Test status
Simulation time 85389619 ps
CPU time 4.04 seconds
Started Jul 06 04:47:35 PM PDT 24
Finished Jul 06 04:47:40 PM PDT 24
Peak memory 209584 kb
Host smart-76b92274-f4da-48e4-9cfd-553ae3c66409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544909934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.544909934
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3823652430
Short name T451
Test name
Test status
Simulation time 1341582113 ps
CPU time 5.76 seconds
Started Jul 06 04:47:39 PM PDT 24
Finished Jul 06 04:47:46 PM PDT 24
Peak memory 206872 kb
Host smart-25ffa479-fe92-4875-9864-75c108a18466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823652430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3823652430
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1457504181
Short name T427
Test name
Test status
Simulation time 268676305 ps
CPU time 3.69 seconds
Started Jul 06 04:47:35 PM PDT 24
Finished Jul 06 04:47:39 PM PDT 24
Peak memory 206736 kb
Host smart-561b0913-4492-4094-9c1c-ddef3b82b780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457504181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1457504181
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1174313340
Short name T704
Test name
Test status
Simulation time 182452993 ps
CPU time 2.72 seconds
Started Jul 06 04:47:37 PM PDT 24
Finished Jul 06 04:47:40 PM PDT 24
Peak memory 207008 kb
Host smart-60d1ba61-ee24-4ac1-9f76-e572772f2323
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174313340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1174313340
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2752955835
Short name T889
Test name
Test status
Simulation time 54558173 ps
CPU time 2.61 seconds
Started Jul 06 04:47:38 PM PDT 24
Finished Jul 06 04:47:42 PM PDT 24
Peak memory 207792 kb
Host smart-c294135c-03c1-4a97-90eb-fd52059c6d43
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752955835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2752955835
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2571049420
Short name T640
Test name
Test status
Simulation time 138285614 ps
CPU time 4.12 seconds
Started Jul 06 04:47:35 PM PDT 24
Finished Jul 06 04:47:39 PM PDT 24
Peak memory 208792 kb
Host smart-5fad26ab-f916-4416-8523-3be0c0b3dce5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571049420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2571049420
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3448194854
Short name T600
Test name
Test status
Simulation time 466591436 ps
CPU time 2.84 seconds
Started Jul 06 04:47:35 PM PDT 24
Finished Jul 06 04:47:38 PM PDT 24
Peak memory 215756 kb
Host smart-0a652a6b-1564-4119-8e9c-aefd3bcc3d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448194854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3448194854
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2634476315
Short name T406
Test name
Test status
Simulation time 69573142 ps
CPU time 2.07 seconds
Started Jul 06 04:47:35 PM PDT 24
Finished Jul 06 04:47:38 PM PDT 24
Peak memory 208432 kb
Host smart-e1968300-53d0-4999-8002-4ab32cc8d6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634476315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2634476315
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.4138308901
Short name T850
Test name
Test status
Simulation time 205861167 ps
CPU time 5.59 seconds
Started Jul 06 04:47:36 PM PDT 24
Finished Jul 06 04:47:42 PM PDT 24
Peak memory 215420 kb
Host smart-62d80a91-68e3-4e5c-ae83-24bcadcf24c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138308901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.4138308901
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.4267426930
Short name T171
Test name
Test status
Simulation time 202331313 ps
CPU time 8.04 seconds
Started Jul 06 04:47:39 PM PDT 24
Finished Jul 06 04:47:48 PM PDT 24
Peak memory 218912 kb
Host smart-fd4097e0-35f7-4c6e-8e0c-819ecf575169
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267426930 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.4267426930
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1248554807
Short name T77
Test name
Test status
Simulation time 295174220 ps
CPU time 4.51 seconds
Started Jul 06 04:47:38 PM PDT 24
Finished Jul 06 04:47:43 PM PDT 24
Peak memory 218096 kb
Host smart-42783390-7054-48d5-97ac-061f3fbcebeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248554807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1248554807
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2841159437
Short name T691
Test name
Test status
Simulation time 286523792 ps
CPU time 6.08 seconds
Started Jul 06 04:47:34 PM PDT 24
Finished Jul 06 04:47:40 PM PDT 24
Peak memory 210368 kb
Host smart-1f0af58e-ae84-4944-8cac-d40fcf2c8c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841159437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2841159437
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3092258893
Short name T466
Test name
Test status
Simulation time 40565191 ps
CPU time 0.74 seconds
Started Jul 06 04:47:42 PM PDT 24
Finished Jul 06 04:47:43 PM PDT 24
Peak memory 205892 kb
Host smart-b79fb43f-6336-42b2-b2b4-3a97c9c699b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092258893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3092258893
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.4124609598
Short name T379
Test name
Test status
Simulation time 93391810 ps
CPU time 3.96 seconds
Started Jul 06 04:47:48 PM PDT 24
Finished Jul 06 04:47:52 PM PDT 24
Peak memory 215428 kb
Host smart-9e8dba71-d8ef-4b00-9083-3c1c71205596
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4124609598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.4124609598
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3351576024
Short name T831
Test name
Test status
Simulation time 4317834232 ps
CPU time 10.37 seconds
Started Jul 06 04:47:42 PM PDT 24
Finished Jul 06 04:47:53 PM PDT 24
Peak memory 217036 kb
Host smart-eb0453d3-7ba5-4c6a-a93d-40015490a8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351576024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3351576024
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2662746950
Short name T231
Test name
Test status
Simulation time 86505686 ps
CPU time 2.42 seconds
Started Jul 06 04:47:39 PM PDT 24
Finished Jul 06 04:47:42 PM PDT 24
Peak memory 208092 kb
Host smart-743ceb4c-51ff-4273-ae17-9f9085af3aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662746950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2662746950
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3277099673
Short name T837
Test name
Test status
Simulation time 55564559 ps
CPU time 2.18 seconds
Started Jul 06 04:47:42 PM PDT 24
Finished Jul 06 04:47:45 PM PDT 24
Peak memory 214232 kb
Host smart-3916cdfd-fcde-4cc1-aa4c-8c02254a87b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277099673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3277099673
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2705454660
Short name T825
Test name
Test status
Simulation time 203140461 ps
CPU time 4.82 seconds
Started Jul 06 04:47:45 PM PDT 24
Finished Jul 06 04:47:51 PM PDT 24
Peak memory 214012 kb
Host smart-172e483f-d00f-4c9d-a9b9-b83433da4fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705454660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2705454660
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3638584772
Short name T746
Test name
Test status
Simulation time 49430601 ps
CPU time 3.28 seconds
Started Jul 06 04:47:44 PM PDT 24
Finished Jul 06 04:47:48 PM PDT 24
Peak memory 220100 kb
Host smart-bd9a4cfc-ba92-493e-bb04-34ce21d0a5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638584772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3638584772
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3195756928
Short name T705
Test name
Test status
Simulation time 1517833133 ps
CPU time 14.46 seconds
Started Jul 06 04:47:46 PM PDT 24
Finished Jul 06 04:48:01 PM PDT 24
Peak memory 208292 kb
Host smart-c2802503-4ed1-4261-9175-131c9c8b31b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195756928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3195756928
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.979938973
Short name T399
Test name
Test status
Simulation time 66922614 ps
CPU time 2.42 seconds
Started Jul 06 04:47:39 PM PDT 24
Finished Jul 06 04:47:42 PM PDT 24
Peak memory 208528 kb
Host smart-edf8d352-d07d-4c5e-bd80-3835394c7884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979938973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.979938973
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1741985124
Short name T339
Test name
Test status
Simulation time 5173473468 ps
CPU time 22.55 seconds
Started Jul 06 04:47:38 PM PDT 24
Finished Jul 06 04:48:02 PM PDT 24
Peak memory 208468 kb
Host smart-f1906015-a434-4eab-aaea-7513c34961f1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741985124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1741985124
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2959159252
Short name T338
Test name
Test status
Simulation time 153122490 ps
CPU time 2.45 seconds
Started Jul 06 04:47:41 PM PDT 24
Finished Jul 06 04:47:44 PM PDT 24
Peak memory 206916 kb
Host smart-eff99e26-c5f7-4c12-8501-8a68a675eba5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959159252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2959159252
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.914752407
Short name T765
Test name
Test status
Simulation time 368522947 ps
CPU time 13.15 seconds
Started Jul 06 04:47:42 PM PDT 24
Finished Jul 06 04:47:56 PM PDT 24
Peak memory 208688 kb
Host smart-f04cae97-6c0d-4fb8-8dfa-d208a0b0ffe2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914752407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.914752407
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1091169791
Short name T811
Test name
Test status
Simulation time 522568370 ps
CPU time 4.49 seconds
Started Jul 06 04:47:40 PM PDT 24
Finished Jul 06 04:47:45 PM PDT 24
Peak memory 209984 kb
Host smart-7383bb2a-ed50-4409-97ea-fab1ee351ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091169791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1091169791
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2427676162
Short name T594
Test name
Test status
Simulation time 404367061 ps
CPU time 3.29 seconds
Started Jul 06 04:47:38 PM PDT 24
Finished Jul 06 04:47:42 PM PDT 24
Peak memory 208492 kb
Host smart-960d3999-eef5-4428-8417-ea943f6a1f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427676162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2427676162
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1265312040
Short name T204
Test name
Test status
Simulation time 79136530 ps
CPU time 4.53 seconds
Started Jul 06 04:47:37 PM PDT 24
Finished Jul 06 04:47:43 PM PDT 24
Peak memory 222348 kb
Host smart-e735e496-034b-4929-9af3-81f2e3a2396e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265312040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1265312040
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2049308050
Short name T769
Test name
Test status
Simulation time 302692343 ps
CPU time 6.25 seconds
Started Jul 06 04:47:48 PM PDT 24
Finished Jul 06 04:47:54 PM PDT 24
Peak memory 222512 kb
Host smart-0e7f754f-1aa0-4dce-b737-5a6188e859b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049308050 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2049308050
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1767711068
Short name T734
Test name
Test status
Simulation time 51485464 ps
CPU time 2.93 seconds
Started Jul 06 04:47:46 PM PDT 24
Finished Jul 06 04:47:49 PM PDT 24
Peak memory 214180 kb
Host smart-46761a43-87c8-467e-bd1f-908918199e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767711068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1767711068
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2977529345
Short name T467
Test name
Test status
Simulation time 237204122 ps
CPU time 8.31 seconds
Started Jul 06 04:47:38 PM PDT 24
Finished Jul 06 04:47:47 PM PDT 24
Peak memory 210416 kb
Host smart-c6350d74-1a43-4b06-967b-ddd2ef38362e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977529345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2977529345
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3467408183
Short name T685
Test name
Test status
Simulation time 13099150 ps
CPU time 0.87 seconds
Started Jul 06 04:47:40 PM PDT 24
Finished Jul 06 04:47:42 PM PDT 24
Peak memory 205892 kb
Host smart-8a550f17-40dd-4cdb-9f06-9e03a7e7ae1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467408183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3467408183
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.170286916
Short name T278
Test name
Test status
Simulation time 109733870 ps
CPU time 2.32 seconds
Started Jul 06 04:47:37 PM PDT 24
Finished Jul 06 04:47:40 PM PDT 24
Peak memory 214288 kb
Host smart-e207b05a-61fa-43c3-9f19-ca1b7ace59a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=170286916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.170286916
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1242402643
Short name T909
Test name
Test status
Simulation time 537914396 ps
CPU time 2.54 seconds
Started Jul 06 04:47:39 PM PDT 24
Finished Jul 06 04:47:42 PM PDT 24
Peak memory 214544 kb
Host smart-8aebcc68-41c7-407f-ad76-12e689595da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242402643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1242402643
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2443574587
Short name T719
Test name
Test status
Simulation time 193439583 ps
CPU time 2.61 seconds
Started Jul 06 04:47:45 PM PDT 24
Finished Jul 06 04:47:49 PM PDT 24
Peak memory 208312 kb
Host smart-df1b0a0a-de4a-4796-aa5f-7a12511fcc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443574587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2443574587
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1631986147
Short name T262
Test name
Test status
Simulation time 1246452328 ps
CPU time 4.25 seconds
Started Jul 06 04:47:40 PM PDT 24
Finished Jul 06 04:47:45 PM PDT 24
Peak memory 214212 kb
Host smart-8dc7be9f-e73f-4c4f-9a7f-7b7f4cd7cdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631986147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1631986147
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.4144922684
Short name T202
Test name
Test status
Simulation time 1508264836 ps
CPU time 19.18 seconds
Started Jul 06 04:47:41 PM PDT 24
Finished Jul 06 04:48:01 PM PDT 24
Peak memory 220268 kb
Host smart-818db437-171b-4182-a29d-3ba0f65527e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144922684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4144922684
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2628989695
Short name T317
Test name
Test status
Simulation time 87099862 ps
CPU time 4.43 seconds
Started Jul 06 04:47:39 PM PDT 24
Finished Jul 06 04:47:44 PM PDT 24
Peak memory 210100 kb
Host smart-e6cc3682-977b-4cf0-940d-ea0c5b0a8c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628989695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2628989695
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.29509685
Short name T233
Test name
Test status
Simulation time 845595890 ps
CPU time 2.78 seconds
Started Jul 06 04:47:37 PM PDT 24
Finished Jul 06 04:47:41 PM PDT 24
Peak memory 206776 kb
Host smart-14a4fd99-ab51-46bb-8489-12c15d1537c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29509685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.29509685
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2771643469
Short name T866
Test name
Test status
Simulation time 7452238931 ps
CPU time 54.4 seconds
Started Jul 06 04:47:47 PM PDT 24
Finished Jul 06 04:48:42 PM PDT 24
Peak memory 208456 kb
Host smart-0d0232cb-26a5-42b6-9f33-f7878a809292
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771643469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2771643469
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.191483416
Short name T649
Test name
Test status
Simulation time 1571704427 ps
CPU time 4.62 seconds
Started Jul 06 04:47:48 PM PDT 24
Finished Jul 06 04:47:53 PM PDT 24
Peak memory 208292 kb
Host smart-c0b75d0b-270d-41e5-8281-412e2d521522
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191483416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.191483416
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2586795808
Short name T520
Test name
Test status
Simulation time 246562239 ps
CPU time 2.95 seconds
Started Jul 06 04:47:46 PM PDT 24
Finished Jul 06 04:47:49 PM PDT 24
Peak memory 208468 kb
Host smart-45eda353-357d-46f2-9606-0bc094c15546
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586795808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2586795808
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.333927966
Short name T242
Test name
Test status
Simulation time 66882436 ps
CPU time 2.39 seconds
Started Jul 06 04:47:41 PM PDT 24
Finished Jul 06 04:47:44 PM PDT 24
Peak memory 208416 kb
Host smart-d7dc72e7-0027-45bf-8075-a2d422bb0e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333927966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.333927966
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3893345647
Short name T523
Test name
Test status
Simulation time 150770003 ps
CPU time 4.42 seconds
Started Jul 06 04:47:37 PM PDT 24
Finished Jul 06 04:47:43 PM PDT 24
Peak memory 208228 kb
Host smart-a16cc0ef-d9f9-4e8a-b2a3-bc7f7656f95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893345647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3893345647
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1413415414
Short name T11
Test name
Test status
Simulation time 489640713 ps
CPU time 4.88 seconds
Started Jul 06 04:47:49 PM PDT 24
Finished Jul 06 04:47:54 PM PDT 24
Peak memory 206708 kb
Host smart-6e96dc21-fb1f-40f0-830e-42db203829a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413415414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1413415414
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1011446808
Short name T249
Test name
Test status
Simulation time 468549023 ps
CPU time 7.22 seconds
Started Jul 06 04:47:41 PM PDT 24
Finished Jul 06 04:47:48 PM PDT 24
Peak memory 209760 kb
Host smart-d209b5d9-426c-4991-91cf-472ffb231090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011446808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1011446808
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1420252041
Short name T593
Test name
Test status
Simulation time 118261779 ps
CPU time 1.67 seconds
Started Jul 06 04:47:41 PM PDT 24
Finished Jul 06 04:47:44 PM PDT 24
Peak memory 209764 kb
Host smart-7cd0461b-86bd-4ae8-b7ec-2accb57eef45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420252041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1420252041
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.4051430643
Short name T595
Test name
Test status
Simulation time 16413657 ps
CPU time 0.77 seconds
Started Jul 06 04:47:47 PM PDT 24
Finished Jul 06 04:47:48 PM PDT 24
Peak memory 205972 kb
Host smart-36d41350-7ba1-4afa-9318-1194b415bb75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051430643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.4051430643
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.40572577
Short name T857
Test name
Test status
Simulation time 34029055 ps
CPU time 2.57 seconds
Started Jul 06 04:47:40 PM PDT 24
Finished Jul 06 04:47:43 PM PDT 24
Peak memory 214244 kb
Host smart-ff553f32-84cb-4611-8854-77fd73a67160
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=40572577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.40572577
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3435298337
Short name T762
Test name
Test status
Simulation time 252627406 ps
CPU time 3.15 seconds
Started Jul 06 04:47:42 PM PDT 24
Finished Jul 06 04:47:46 PM PDT 24
Peak memory 210228 kb
Host smart-8ea830e4-8cc0-4b4e-955c-42f8a9ee9c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435298337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3435298337
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1390467076
Short name T742
Test name
Test status
Simulation time 451280371 ps
CPU time 5.74 seconds
Started Jul 06 04:47:48 PM PDT 24
Finished Jul 06 04:47:54 PM PDT 24
Peak memory 207908 kb
Host smart-636472af-9c1f-42f2-93c3-22c021478f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390467076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1390467076
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1799469321
Short name T551
Test name
Test status
Simulation time 112743090 ps
CPU time 4.81 seconds
Started Jul 06 04:47:40 PM PDT 24
Finished Jul 06 04:47:46 PM PDT 24
Peak memory 209448 kb
Host smart-95fc00e8-0ec0-477a-b05c-1360a7572900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799469321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1799469321
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.423057999
Short name T296
Test name
Test status
Simulation time 226334643 ps
CPU time 3.2 seconds
Started Jul 06 04:47:38 PM PDT 24
Finished Jul 06 04:47:42 PM PDT 24
Peak memory 214264 kb
Host smart-4c854725-dfb9-467b-9180-66b06a56359e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423057999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.423057999
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3832552915
Short name T753
Test name
Test status
Simulation time 123565385 ps
CPU time 5.23 seconds
Started Jul 06 04:47:45 PM PDT 24
Finished Jul 06 04:47:51 PM PDT 24
Peak memory 209356 kb
Host smart-3247ffab-2c40-49bf-b3c3-2a699a881ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832552915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3832552915
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.786799533
Short name T541
Test name
Test status
Simulation time 170977302 ps
CPU time 4.42 seconds
Started Jul 06 04:47:39 PM PDT 24
Finished Jul 06 04:47:44 PM PDT 24
Peak memory 207276 kb
Host smart-417ed3f8-898f-482c-9988-d9bc902e9514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786799533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.786799533
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3025413424
Short name T325
Test name
Test status
Simulation time 133566306 ps
CPU time 3.36 seconds
Started Jul 06 04:47:39 PM PDT 24
Finished Jul 06 04:47:44 PM PDT 24
Peak memory 207380 kb
Host smart-7b900f02-ac95-490c-9cd9-288c56d6a58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025413424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3025413424
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1743077710
Short name T81
Test name
Test status
Simulation time 108225565 ps
CPU time 2.91 seconds
Started Jul 06 04:47:40 PM PDT 24
Finished Jul 06 04:47:44 PM PDT 24
Peak memory 206860 kb
Host smart-79dddcdc-e0e4-4139-8aad-ead74c540ea2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743077710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1743077710
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4035312423
Short name T517
Test name
Test status
Simulation time 150311335 ps
CPU time 4.58 seconds
Started Jul 06 04:47:48 PM PDT 24
Finished Jul 06 04:47:52 PM PDT 24
Peak memory 207664 kb
Host smart-2dd9d052-db0a-49a4-ba9a-0200786632fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035312423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4035312423
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.4173671279
Short name T559
Test name
Test status
Simulation time 136461981 ps
CPU time 2.38 seconds
Started Jul 06 04:47:38 PM PDT 24
Finished Jul 06 04:47:41 PM PDT 24
Peak memory 206856 kb
Host smart-4c309245-bab1-46dc-b9ca-d305674a00e6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173671279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.4173671279
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2768666315
Short name T546
Test name
Test status
Simulation time 78997872 ps
CPU time 1.63 seconds
Started Jul 06 04:47:45 PM PDT 24
Finished Jul 06 04:47:47 PM PDT 24
Peak memory 209228 kb
Host smart-adedb529-5883-41bc-9884-0b1e1f0a0d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768666315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2768666315
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2163692308
Short name T687
Test name
Test status
Simulation time 340558541 ps
CPU time 6.16 seconds
Started Jul 06 04:47:49 PM PDT 24
Finished Jul 06 04:47:55 PM PDT 24
Peak memory 208476 kb
Host smart-d5b6231f-9ff5-4619-bf88-4d3851bb88f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163692308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2163692308
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2800731401
Short name T563
Test name
Test status
Simulation time 215760782 ps
CPU time 6.06 seconds
Started Jul 06 04:47:45 PM PDT 24
Finished Jul 06 04:47:52 PM PDT 24
Peak memory 208108 kb
Host smart-2ed4fd8a-4ba9-4b29-b0c9-77a2b68d4ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800731401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2800731401
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.295605637
Short name T564
Test name
Test status
Simulation time 24812591 ps
CPU time 0.9 seconds
Started Jul 06 04:47:45 PM PDT 24
Finished Jul 06 04:47:47 PM PDT 24
Peak memory 205900 kb
Host smart-c8a9b149-d8cf-4d96-b11a-7c0dcf5bdc2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295605637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.295605637
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2577537883
Short name T211
Test name
Test status
Simulation time 128473746 ps
CPU time 2.64 seconds
Started Jul 06 04:47:49 PM PDT 24
Finished Jul 06 04:47:53 PM PDT 24
Peak memory 209496 kb
Host smart-eec5a8a5-9cc4-4ead-9f42-2f0625cd6d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577537883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2577537883
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.497710804
Short name T750
Test name
Test status
Simulation time 64171053 ps
CPU time 2.7 seconds
Started Jul 06 04:47:50 PM PDT 24
Finished Jul 06 04:47:53 PM PDT 24
Peak memory 214172 kb
Host smart-bd96e9f1-7ca2-464d-8de0-3774f1d5b389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497710804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.497710804
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.4009683893
Short name T89
Test name
Test status
Simulation time 616762288 ps
CPU time 4.59 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:47:58 PM PDT 24
Peak memory 209412 kb
Host smart-8fca7727-3023-4347-a167-36dc7c8a4168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009683893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.4009683893
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2435230870
Short name T455
Test name
Test status
Simulation time 451199548 ps
CPU time 3.56 seconds
Started Jul 06 04:47:45 PM PDT 24
Finished Jul 06 04:47:49 PM PDT 24
Peak memory 222236 kb
Host smart-bd6540cb-db0b-484b-8522-6e897304212e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435230870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2435230870
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.143638569
Short name T611
Test name
Test status
Simulation time 724877204 ps
CPU time 2.04 seconds
Started Jul 06 04:47:48 PM PDT 24
Finished Jul 06 04:47:51 PM PDT 24
Peak memory 220028 kb
Host smart-f2bf21da-5a0e-433a-b688-aacdc470fa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143638569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.143638569
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2361505951
Short name T122
Test name
Test status
Simulation time 1260031283 ps
CPU time 6.47 seconds
Started Jul 06 04:47:45 PM PDT 24
Finished Jul 06 04:47:52 PM PDT 24
Peak memory 219324 kb
Host smart-ccb50059-cac5-466f-b111-4d91036ad404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361505951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2361505951
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3455367849
Short name T503
Test name
Test status
Simulation time 77444872 ps
CPU time 2.38 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:47:56 PM PDT 24
Peak memory 206736 kb
Host smart-d2155555-27aa-4aeb-b4d5-cd3d19e23d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455367849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3455367849
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.834987182
Short name T491
Test name
Test status
Simulation time 3489069085 ps
CPU time 21.95 seconds
Started Jul 06 04:47:50 PM PDT 24
Finished Jul 06 04:48:13 PM PDT 24
Peak memory 208892 kb
Host smart-479db0ca-a884-49c1-b36e-71ead1050bea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834987182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.834987182
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1102322749
Short name T409
Test name
Test status
Simulation time 37281914 ps
CPU time 1.76 seconds
Started Jul 06 04:47:47 PM PDT 24
Finished Jul 06 04:47:49 PM PDT 24
Peak memory 206708 kb
Host smart-dd0ade1a-f03a-4229-9792-63b8f6ffb6b4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102322749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1102322749
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.4075096613
Short name T315
Test name
Test status
Simulation time 1594610611 ps
CPU time 6.24 seconds
Started Jul 06 04:48:06 PM PDT 24
Finished Jul 06 04:48:13 PM PDT 24
Peak memory 208788 kb
Host smart-907298ed-d7f1-49cf-861e-2c853c84a111
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075096613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.4075096613
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.394581136
Short name T708
Test name
Test status
Simulation time 962314353 ps
CPU time 5.92 seconds
Started Jul 06 04:47:50 PM PDT 24
Finished Jul 06 04:47:56 PM PDT 24
Peak memory 209068 kb
Host smart-95aee544-e25d-438b-b374-c1c93686fb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394581136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.394581136
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2473422439
Short name T394
Test name
Test status
Simulation time 1192552769 ps
CPU time 10.2 seconds
Started Jul 06 04:47:51 PM PDT 24
Finished Jul 06 04:48:02 PM PDT 24
Peak memory 208296 kb
Host smart-e1d8caa6-ac91-4b17-bd7f-00ad48da21f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473422439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2473422439
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1377373266
Short name T312
Test name
Test status
Simulation time 1131050725 ps
CPU time 42.26 seconds
Started Jul 06 04:47:45 PM PDT 24
Finished Jul 06 04:48:28 PM PDT 24
Peak memory 222484 kb
Host smart-305e7439-1a17-42f8-9b9a-010dad0cf6ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377373266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1377373266
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.494590770
Short name T13
Test name
Test status
Simulation time 329285998 ps
CPU time 14.14 seconds
Started Jul 06 04:47:46 PM PDT 24
Finished Jul 06 04:48:01 PM PDT 24
Peak memory 222524 kb
Host smart-d72b7670-f072-4b12-8fc5-a18897656fe3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494590770 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.494590770
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1712132697
Short name T426
Test name
Test status
Simulation time 670120273 ps
CPU time 9.84 seconds
Started Jul 06 04:47:49 PM PDT 24
Finished Jul 06 04:47:59 PM PDT 24
Peak memory 214168 kb
Host smart-1ce0f7cd-bda5-4c56-902e-ad5e72697daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712132697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1712132697
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2186590459
Short name T585
Test name
Test status
Simulation time 55407477 ps
CPU time 2.42 seconds
Started Jul 06 04:47:48 PM PDT 24
Finished Jul 06 04:47:51 PM PDT 24
Peak memory 209928 kb
Host smart-94dbd16e-3ef8-4e97-890b-56c37ed7f273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186590459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2186590459
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2255091813
Short name T730
Test name
Test status
Simulation time 49047000 ps
CPU time 0.89 seconds
Started Jul 06 04:47:51 PM PDT 24
Finished Jul 06 04:47:53 PM PDT 24
Peak memory 205904 kb
Host smart-bdb5255b-6b0d-4e99-abca-a2fd911a2973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255091813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2255091813
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2120848318
Short name T581
Test name
Test status
Simulation time 48646230 ps
CPU time 2.39 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:47:56 PM PDT 24
Peak memory 216708 kb
Host smart-33433552-a0aa-4d73-bbf5-a1cedc98c9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120848318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2120848318
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.603129239
Short name T617
Test name
Test status
Simulation time 252249223 ps
CPU time 2.76 seconds
Started Jul 06 04:47:48 PM PDT 24
Finished Jul 06 04:47:52 PM PDT 24
Peak memory 207588 kb
Host smart-e66d67cc-9a9d-4935-95e9-ee5cc90989b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603129239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.603129239
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2983922112
Short name T674
Test name
Test status
Simulation time 190139687 ps
CPU time 2.89 seconds
Started Jul 06 04:47:53 PM PDT 24
Finished Jul 06 04:47:58 PM PDT 24
Peak memory 214224 kb
Host smart-28dc004a-db4c-4233-af13-b2811859db5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983922112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2983922112
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.812355616
Short name T384
Test name
Test status
Simulation time 76050364 ps
CPU time 2.91 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:47:57 PM PDT 24
Peak memory 218248 kb
Host smart-bd89cee9-a273-4262-90e4-f2c189c70325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812355616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.812355616
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.4122690668
Short name T270
Test name
Test status
Simulation time 533293438 ps
CPU time 6.07 seconds
Started Jul 06 04:47:53 PM PDT 24
Finished Jul 06 04:48:00 PM PDT 24
Peak memory 214224 kb
Host smart-428f808d-4c8e-4167-9fd2-17f0f0726d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122690668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.4122690668
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3060318731
Short name T288
Test name
Test status
Simulation time 569892983 ps
CPU time 8.38 seconds
Started Jul 06 04:47:46 PM PDT 24
Finished Jul 06 04:47:55 PM PDT 24
Peak memory 208640 kb
Host smart-cf096444-7a8d-4331-8608-819f1b4d9605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060318731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3060318731
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2986840267
Short name T545
Test name
Test status
Simulation time 67639633 ps
CPU time 3.17 seconds
Started Jul 06 04:47:50 PM PDT 24
Finished Jul 06 04:47:54 PM PDT 24
Peak memory 208096 kb
Host smart-1a3e746c-1d18-4543-831c-8ba967f73c35
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986840267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2986840267
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2065898899
Short name T75
Test name
Test status
Simulation time 52034577 ps
CPU time 2.87 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:47:57 PM PDT 24
Peak memory 208576 kb
Host smart-cbddc766-d346-4c9f-8a3b-d9c94ba63ae4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065898899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2065898899
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1282003430
Short name T539
Test name
Test status
Simulation time 508013953 ps
CPU time 3.37 seconds
Started Jul 06 04:47:49 PM PDT 24
Finished Jul 06 04:47:53 PM PDT 24
Peak memory 206828 kb
Host smart-433901fb-41f5-4514-9d98-b5d66922e85f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282003430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1282003430
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3936636725
Short name T340
Test name
Test status
Simulation time 295494911 ps
CPU time 3.58 seconds
Started Jul 06 04:47:49 PM PDT 24
Finished Jul 06 04:47:53 PM PDT 24
Peak memory 208604 kb
Host smart-061618b3-a034-4fab-bfaf-11e0d37babef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936636725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3936636725
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3640511255
Short name T573
Test name
Test status
Simulation time 4277270302 ps
CPU time 18.11 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:48:12 PM PDT 24
Peak memory 208340 kb
Host smart-8ea9fa61-5739-49ef-9b62-c368b0b305c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640511255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3640511255
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2728784657
Short name T755
Test name
Test status
Simulation time 1182926898 ps
CPU time 36.12 seconds
Started Jul 06 04:47:49 PM PDT 24
Finished Jul 06 04:48:26 PM PDT 24
Peak memory 216540 kb
Host smart-bdc98f0f-d4ef-4914-817c-dfe2667d94ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728784657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2728784657
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3279714775
Short name T247
Test name
Test status
Simulation time 1874690908 ps
CPU time 21.04 seconds
Started Jul 06 04:47:48 PM PDT 24
Finished Jul 06 04:48:10 PM PDT 24
Peak memory 222524 kb
Host smart-9788a908-c645-4133-befd-f0d67b3285dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279714775 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3279714775
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3490905515
Short name T219
Test name
Test status
Simulation time 116955256 ps
CPU time 2.46 seconds
Started Jul 06 04:47:49 PM PDT 24
Finished Jul 06 04:47:52 PM PDT 24
Peak memory 209764 kb
Host smart-ce93cdb4-6ea0-4aec-a107-d47664c66fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490905515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3490905515
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2222506800
Short name T360
Test name
Test status
Simulation time 179931429 ps
CPU time 2.43 seconds
Started Jul 06 04:47:49 PM PDT 24
Finished Jul 06 04:47:52 PM PDT 24
Peak memory 210184 kb
Host smart-c903a5be-28ed-4cbb-80c7-a7bf4c436152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222506800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2222506800
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3487297275
Short name T96
Test name
Test status
Simulation time 9708211 ps
CPU time 0.68 seconds
Started Jul 06 04:47:51 PM PDT 24
Finished Jul 06 04:47:52 PM PDT 24
Peak memory 205912 kb
Host smart-3b9a4acd-a391-4723-b1f7-f13b401863f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487297275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3487297275
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1567595525
Short name T388
Test name
Test status
Simulation time 3421796044 ps
CPU time 47.12 seconds
Started Jul 06 04:47:50 PM PDT 24
Finished Jul 06 04:48:37 PM PDT 24
Peak memory 215816 kb
Host smart-3a801a88-e3b5-4e31-9810-b51efb41dea9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1567595525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1567595525
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.566151173
Short name T165
Test name
Test status
Simulation time 36630495 ps
CPU time 3.34 seconds
Started Jul 06 04:47:49 PM PDT 24
Finished Jul 06 04:47:53 PM PDT 24
Peak memory 218280 kb
Host smart-b7831467-6144-4ce6-b679-83e31a878761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566151173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.566151173
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1412095535
Short name T596
Test name
Test status
Simulation time 205401546 ps
CPU time 7.47 seconds
Started Jul 06 04:47:47 PM PDT 24
Finished Jul 06 04:47:55 PM PDT 24
Peak memory 218288 kb
Host smart-5e8ab75a-c6d7-4ec6-ba21-5ecdc51c24d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412095535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1412095535
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3010199053
Short name T86
Test name
Test status
Simulation time 317347348 ps
CPU time 4.2 seconds
Started Jul 06 04:47:44 PM PDT 24
Finished Jul 06 04:47:49 PM PDT 24
Peak memory 214228 kb
Host smart-d0101d45-6dd2-4b88-a3b1-53a10e77d4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010199053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3010199053
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2289080377
Short name T332
Test name
Test status
Simulation time 94228695 ps
CPU time 4 seconds
Started Jul 06 04:47:48 PM PDT 24
Finished Jul 06 04:47:52 PM PDT 24
Peak memory 214132 kb
Host smart-df157611-94fd-4cec-b2c7-420d3ef36036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289080377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2289080377
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.691524203
Short name T654
Test name
Test status
Simulation time 1507439857 ps
CPU time 5.33 seconds
Started Jul 06 04:47:51 PM PDT 24
Finished Jul 06 04:47:58 PM PDT 24
Peak memory 209660 kb
Host smart-600b95c5-af52-40e5-9611-59288d2913de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691524203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.691524203
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3439237503
Short name T792
Test name
Test status
Simulation time 115125006 ps
CPU time 4.55 seconds
Started Jul 06 04:47:46 PM PDT 24
Finished Jul 06 04:47:51 PM PDT 24
Peak memory 209984 kb
Host smart-6fe97dae-ac35-4966-b41a-2d22f78c6d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439237503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3439237503
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3383323795
Short name T835
Test name
Test status
Simulation time 227529410 ps
CPU time 3.43 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:47:58 PM PDT 24
Peak memory 208068 kb
Host smart-cd0442ec-5a5e-4b1b-93b5-21f3cee512f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383323795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3383323795
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3251657222
Short name T121
Test name
Test status
Simulation time 51636205 ps
CPU time 2.78 seconds
Started Jul 06 04:47:48 PM PDT 24
Finished Jul 06 04:47:52 PM PDT 24
Peak memory 208304 kb
Host smart-be7c5465-cab0-4e9a-a17c-94b710b4d161
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251657222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3251657222
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.19976318
Short name T905
Test name
Test status
Simulation time 63645712 ps
CPU time 2.31 seconds
Started Jul 06 04:47:51 PM PDT 24
Finished Jul 06 04:47:55 PM PDT 24
Peak memory 206776 kb
Host smart-453aff8b-c1a9-421e-8139-acf87abe4a5e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19976318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.19976318
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.4136778194
Short name T759
Test name
Test status
Simulation time 320189195 ps
CPU time 3.26 seconds
Started Jul 06 04:47:49 PM PDT 24
Finished Jul 06 04:47:53 PM PDT 24
Peak memory 208756 kb
Host smart-abb60db0-d5b8-4904-a480-ac05420b06a6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136778194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4136778194
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3235151434
Short name T766
Test name
Test status
Simulation time 75780579 ps
CPU time 2.94 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:47:57 PM PDT 24
Peak memory 218364 kb
Host smart-9d9d4793-d040-49bf-abbb-83377516aa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235151434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3235151434
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2259874694
Short name T728
Test name
Test status
Simulation time 210546704 ps
CPU time 3.67 seconds
Started Jul 06 04:47:47 PM PDT 24
Finished Jul 06 04:47:51 PM PDT 24
Peak memory 206688 kb
Host smart-2e0e6c30-9039-4ddd-bc90-6905a9d7f385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259874694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2259874694
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.675012297
Short name T631
Test name
Test status
Simulation time 511909480 ps
CPU time 6.04 seconds
Started Jul 06 04:48:05 PM PDT 24
Finished Jul 06 04:48:12 PM PDT 24
Peak memory 215876 kb
Host smart-de9206ad-94a7-469b-97d5-2a85676b8c56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675012297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.675012297
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.386459216
Short name T51
Test name
Test status
Simulation time 662591984 ps
CPU time 17.88 seconds
Started Jul 06 04:48:07 PM PDT 24
Finished Jul 06 04:48:25 PM PDT 24
Peak memory 220864 kb
Host smart-3d5c8179-0ca9-47d6-8638-429e802da85f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386459216 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.386459216
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3667935818
Short name T140
Test name
Test status
Simulation time 135028413 ps
CPU time 3.35 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:47:58 PM PDT 24
Peak memory 207296 kb
Host smart-8f682b2a-76cc-477f-af51-5b537a2fd200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667935818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3667935818
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3073643150
Short name T362
Test name
Test status
Simulation time 1702358377 ps
CPU time 12.26 seconds
Started Jul 06 04:47:51 PM PDT 24
Finished Jul 06 04:48:04 PM PDT 24
Peak memory 210508 kb
Host smart-2e89c651-87e1-4175-9376-c29eeed8ec75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073643150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3073643150
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1873078770
Short name T402
Test name
Test status
Simulation time 20722736 ps
CPU time 0.76 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:47:55 PM PDT 24
Peak memory 205892 kb
Host smart-2da87f8f-4b57-4632-96e4-3d063c435857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873078770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1873078770
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.143526163
Short name T129
Test name
Test status
Simulation time 239802795 ps
CPU time 4.57 seconds
Started Jul 06 04:48:07 PM PDT 24
Finished Jul 06 04:48:12 PM PDT 24
Peak memory 214196 kb
Host smart-a6dacda8-c1c7-4a7f-ba05-33d8a7d22dc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=143526163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.143526163
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3626853947
Short name T653
Test name
Test status
Simulation time 150536389 ps
CPU time 5.94 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:47:59 PM PDT 24
Peak memory 220220 kb
Host smart-fbf54713-b9c0-4e39-bd17-c0803cba3eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626853947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3626853947
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.413089351
Short name T810
Test name
Test status
Simulation time 189945044 ps
CPU time 2.09 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:47:55 PM PDT 24
Peak memory 207384 kb
Host smart-aae69758-9f16-4850-9508-f223dc4dd215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413089351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.413089351
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.350996278
Short name T257
Test name
Test status
Simulation time 84026803 ps
CPU time 1.59 seconds
Started Jul 06 04:47:53 PM PDT 24
Finished Jul 06 04:47:56 PM PDT 24
Peak memory 214232 kb
Host smart-9f0915d0-8401-4c9c-8faa-7f0daa86c795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350996278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.350996278
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.4264404810
Short name T223
Test name
Test status
Simulation time 28035594 ps
CPU time 1.74 seconds
Started Jul 06 04:47:54 PM PDT 24
Finished Jul 06 04:47:57 PM PDT 24
Peak memory 214272 kb
Host smart-a293edcd-9054-4664-be50-645f70aa81f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264404810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.4264404810
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3310065881
Short name T499
Test name
Test status
Simulation time 424899107 ps
CPU time 4.49 seconds
Started Jul 06 04:47:53 PM PDT 24
Finished Jul 06 04:47:59 PM PDT 24
Peak memory 222396 kb
Host smart-b98614cd-e119-48c9-8fd0-b1e856260b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310065881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3310065881
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1701876762
Short name T723
Test name
Test status
Simulation time 1412525766 ps
CPU time 11.3 seconds
Started Jul 06 04:47:53 PM PDT 24
Finished Jul 06 04:48:06 PM PDT 24
Peak memory 214420 kb
Host smart-d80ffa8b-f886-479c-a944-d8d6c12d4beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701876762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1701876762
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1322797287
Short name T289
Test name
Test status
Simulation time 1482609528 ps
CPU time 9.74 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:48:03 PM PDT 24
Peak memory 207848 kb
Host smart-2c8fe847-6512-41f0-b40f-1db9042fdeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322797287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1322797287
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1795756160
Short name T865
Test name
Test status
Simulation time 1092102594 ps
CPU time 25.66 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:48:19 PM PDT 24
Peak memory 208292 kb
Host smart-ad732f76-adb5-429d-bb24-06bdd051a273
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795756160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1795756160
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1100219997
Short name T284
Test name
Test status
Simulation time 825017269 ps
CPU time 10.23 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:48:03 PM PDT 24
Peak memory 209120 kb
Host smart-654bebab-a98f-4324-9391-d678bf3fc172
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100219997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1100219997
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1388824029
Short name T547
Test name
Test status
Simulation time 921428665 ps
CPU time 9.11 seconds
Started Jul 06 04:47:51 PM PDT 24
Finished Jul 06 04:48:01 PM PDT 24
Peak memory 208848 kb
Host smart-742b1794-7334-425e-97f2-3de08095c82a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388824029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1388824029
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2218090794
Short name T597
Test name
Test status
Simulation time 250283154 ps
CPU time 2.05 seconds
Started Jul 06 04:47:55 PM PDT 24
Finished Jul 06 04:47:58 PM PDT 24
Peak memory 214228 kb
Host smart-737adce3-0178-46c8-be21-0357055f9e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218090794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2218090794
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.4046363824
Short name T867
Test name
Test status
Simulation time 58394158 ps
CPU time 2.81 seconds
Started Jul 06 04:47:50 PM PDT 24
Finished Jul 06 04:47:54 PM PDT 24
Peak memory 208484 kb
Host smart-6899c991-eabb-4560-b9c4-11a7b19a1338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046363824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.4046363824
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1257457650
Short name T254
Test name
Test status
Simulation time 275384846 ps
CPU time 7.7 seconds
Started Jul 06 04:48:00 PM PDT 24
Finished Jul 06 04:48:09 PM PDT 24
Peak memory 218196 kb
Host smart-355291e6-2c02-4128-8d42-d02ae3b8e742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257457650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1257457650
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3750506185
Short name T749
Test name
Test status
Simulation time 443611592 ps
CPU time 3.87 seconds
Started Jul 06 04:47:53 PM PDT 24
Finished Jul 06 04:47:59 PM PDT 24
Peak memory 210300 kb
Host smart-01024e51-401d-4c13-b718-6388dcc2145a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750506185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3750506185
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1095138427
Short name T833
Test name
Test status
Simulation time 13963263 ps
CPU time 0.78 seconds
Started Jul 06 04:47:53 PM PDT 24
Finished Jul 06 04:47:56 PM PDT 24
Peak memory 205984 kb
Host smart-f3507976-74d2-4ea4-9dad-102c93a726d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095138427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1095138427
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.163807800
Short name T432
Test name
Test status
Simulation time 39651527 ps
CPU time 1.92 seconds
Started Jul 06 04:47:59 PM PDT 24
Finished Jul 06 04:48:02 PM PDT 24
Peak memory 218248 kb
Host smart-9afe9f02-69ad-4db9-bbe4-222b9f8dcee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163807800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.163807800
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.874990182
Short name T689
Test name
Test status
Simulation time 314143475 ps
CPU time 3.27 seconds
Started Jul 06 04:47:53 PM PDT 24
Finished Jul 06 04:47:58 PM PDT 24
Peak memory 208596 kb
Host smart-fcaafd8c-fe43-4089-b758-0bb7a34afac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874990182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.874990182
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.217125026
Short name T35
Test name
Test status
Simulation time 190045943 ps
CPU time 5.24 seconds
Started Jul 06 04:48:04 PM PDT 24
Finished Jul 06 04:48:10 PM PDT 24
Peak memory 214224 kb
Host smart-0e7bd5d9-2ca4-4dd0-b33c-f89767c9892a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217125026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.217125026
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.4178398053
Short name T322
Test name
Test status
Simulation time 373294603 ps
CPU time 5.51 seconds
Started Jul 06 04:47:51 PM PDT 24
Finished Jul 06 04:47:58 PM PDT 24
Peak memory 218860 kb
Host smart-7db25b7a-c4cb-4376-913b-fff3a432dcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178398053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.4178398053
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1856557731
Short name T192
Test name
Test status
Simulation time 54549133 ps
CPU time 3.3 seconds
Started Jul 06 04:47:50 PM PDT 24
Finished Jul 06 04:47:54 PM PDT 24
Peak memory 214168 kb
Host smart-069b317b-51d7-4239-aca5-8fef200d79b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856557731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1856557731
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3906717097
Short name T478
Test name
Test status
Simulation time 30460919 ps
CPU time 2.2 seconds
Started Jul 06 04:48:06 PM PDT 24
Finished Jul 06 04:48:09 PM PDT 24
Peak memory 206728 kb
Host smart-4107f71b-54b3-4209-993e-488860c8d3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906717097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3906717097
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2762855321
Short name T508
Test name
Test status
Simulation time 71541234 ps
CPU time 1.79 seconds
Started Jul 06 04:47:54 PM PDT 24
Finished Jul 06 04:47:57 PM PDT 24
Peak memory 206728 kb
Host smart-79f274e6-00bc-4a10-91d5-5f6a003197d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762855321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2762855321
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1725054024
Short name T667
Test name
Test status
Simulation time 61471494 ps
CPU time 2.49 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:47:56 PM PDT 24
Peak memory 206832 kb
Host smart-472c1c62-996b-409a-bc49-7657e257cce7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725054024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1725054024
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3267171446
Short name T449
Test name
Test status
Simulation time 2241538521 ps
CPU time 22.68 seconds
Started Jul 06 04:48:07 PM PDT 24
Finished Jul 06 04:48:30 PM PDT 24
Peak memory 209120 kb
Host smart-f8975562-b59d-490c-b59c-26dd8f5599a4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267171446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3267171446
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.430097294
Short name T915
Test name
Test status
Simulation time 201442710 ps
CPU time 3.74 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:47:57 PM PDT 24
Peak memory 208560 kb
Host smart-618003b8-db1c-4b59-b48e-568c567f27fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430097294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.430097294
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.634407682
Short name T651
Test name
Test status
Simulation time 134494242 ps
CPU time 2.6 seconds
Started Jul 06 04:47:53 PM PDT 24
Finished Jul 06 04:47:58 PM PDT 24
Peak memory 206840 kb
Host smart-ca0cbb94-fa05-4883-b5eb-3a84cf29cd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634407682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.634407682
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.451459481
Short name T894
Test name
Test status
Simulation time 224224064 ps
CPU time 3.63 seconds
Started Jul 06 04:47:53 PM PDT 24
Finished Jul 06 04:47:58 PM PDT 24
Peak memory 207344 kb
Host smart-286c72b9-cf36-4190-8273-226a04911272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451459481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.451459481
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3657447604
Short name T818
Test name
Test status
Simulation time 33362632 ps
CPU time 2 seconds
Started Jul 06 04:47:53 PM PDT 24
Finished Jul 06 04:47:57 PM PDT 24
Peak memory 209956 kb
Host smart-bf2105fa-8eeb-48f5-bd65-37c579817709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657447604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3657447604
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.4139733468
Short name T462
Test name
Test status
Simulation time 16791568 ps
CPU time 0.82 seconds
Started Jul 06 04:46:47 PM PDT 24
Finished Jul 06 04:46:48 PM PDT 24
Peak memory 205800 kb
Host smart-fa359ce5-4464-4b6b-9402-45a5e4c9b73d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139733468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.4139733468
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.580621895
Short name T225
Test name
Test status
Simulation time 239267028 ps
CPU time 2.85 seconds
Started Jul 06 04:46:51 PM PDT 24
Finished Jul 06 04:46:55 PM PDT 24
Peak memory 214228 kb
Host smart-0d856297-b565-443c-8270-0741012d070c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580621895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.580621895
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2898208824
Short name T88
Test name
Test status
Simulation time 4202498008 ps
CPU time 13.49 seconds
Started Jul 06 04:46:46 PM PDT 24
Finished Jul 06 04:47:00 PM PDT 24
Peak memory 214356 kb
Host smart-7591e3dc-994a-46ba-b9d5-dc3a8bef9024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898208824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2898208824
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.462375155
Short name T46
Test name
Test status
Simulation time 872172030 ps
CPU time 3.97 seconds
Started Jul 06 04:46:49 PM PDT 24
Finished Jul 06 04:46:54 PM PDT 24
Peak memory 220324 kb
Host smart-927c040b-681c-4ac3-b0d3-160ba967f4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462375155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.462375155
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.328052535
Short name T884
Test name
Test status
Simulation time 2797814158 ps
CPU time 7.38 seconds
Started Jul 06 04:46:43 PM PDT 24
Finished Jul 06 04:46:51 PM PDT 24
Peak memory 218172 kb
Host smart-67a5d75b-811b-4ed1-8dc2-518911d709b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328052535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.328052535
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2393822694
Short name T269
Test name
Test status
Simulation time 68394440 ps
CPU time 3.31 seconds
Started Jul 06 04:46:43 PM PDT 24
Finished Jul 06 04:46:47 PM PDT 24
Peak memory 207936 kb
Host smart-d4d157bc-f3d7-42ca-9fbc-c313ec7dd928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393822694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2393822694
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2428479372
Short name T433
Test name
Test status
Simulation time 32252224 ps
CPU time 2.19 seconds
Started Jul 06 04:46:41 PM PDT 24
Finished Jul 06 04:46:44 PM PDT 24
Peak memory 206852 kb
Host smart-8ead6de8-b591-414a-a052-ce6c55c5c27d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428479372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2428479372
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3693140884
Short name T713
Test name
Test status
Simulation time 1263941649 ps
CPU time 31 seconds
Started Jul 06 04:46:42 PM PDT 24
Finished Jul 06 04:47:14 PM PDT 24
Peak memory 208060 kb
Host smart-81777589-a12a-4e8f-804e-262cefa799e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693140884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3693140884
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1931095804
Short name T414
Test name
Test status
Simulation time 25801974 ps
CPU time 2 seconds
Started Jul 06 04:46:40 PM PDT 24
Finished Jul 06 04:46:42 PM PDT 24
Peak memory 206872 kb
Host smart-994a7285-48b8-49e1-802b-3b3e18dda71a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931095804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1931095804
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2131613220
Short name T244
Test name
Test status
Simulation time 217028047 ps
CPU time 2.08 seconds
Started Jul 06 04:46:43 PM PDT 24
Finished Jul 06 04:46:46 PM PDT 24
Peak memory 215424 kb
Host smart-4372b4d6-370f-4060-84be-c6d96c2f1427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131613220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2131613220
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3168123631
Short name T471
Test name
Test status
Simulation time 1415865666 ps
CPU time 24.23 seconds
Started Jul 06 04:46:44 PM PDT 24
Finished Jul 06 04:47:08 PM PDT 24
Peak memory 208860 kb
Host smart-7621bd62-fa98-4903-b0d7-8639b001290a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168123631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3168123631
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.668563151
Short name T200
Test name
Test status
Simulation time 59334931376 ps
CPU time 607.44 seconds
Started Jul 06 04:46:53 PM PDT 24
Finished Jul 06 04:57:01 PM PDT 24
Peak memory 222420 kb
Host smart-34435635-e15f-4a69-b1cf-4bf12583eb83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668563151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.668563151
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3100029237
Short name T549
Test name
Test status
Simulation time 280754443 ps
CPU time 5.11 seconds
Started Jul 06 04:46:42 PM PDT 24
Finished Jul 06 04:46:48 PM PDT 24
Peak memory 214212 kb
Host smart-bad46524-6c63-4ea1-82d0-752a86aa5a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100029237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3100029237
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.4051700818
Short name T543
Test name
Test status
Simulation time 58545134 ps
CPU time 2.34 seconds
Started Jul 06 04:46:43 PM PDT 24
Finished Jul 06 04:46:46 PM PDT 24
Peak memory 209748 kb
Host smart-23562825-7791-4576-ac87-454c5049820b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051700818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.4051700818
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.50039329
Short name T657
Test name
Test status
Simulation time 58820973 ps
CPU time 0.81 seconds
Started Jul 06 04:48:06 PM PDT 24
Finished Jul 06 04:48:07 PM PDT 24
Peak memory 205900 kb
Host smart-448828ce-65eb-49a5-aa12-d40acb085cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50039329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.50039329
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3871068007
Short name T367
Test name
Test status
Simulation time 54221979 ps
CPU time 3.84 seconds
Started Jul 06 04:47:50 PM PDT 24
Finished Jul 06 04:47:54 PM PDT 24
Peak memory 214208 kb
Host smart-f2347cd2-38e5-41db-9135-7322a6519f08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871068007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3871068007
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1466787759
Short name T27
Test name
Test status
Simulation time 455792027 ps
CPU time 3.29 seconds
Started Jul 06 04:48:05 PM PDT 24
Finished Jul 06 04:48:10 PM PDT 24
Peak memory 220552 kb
Host smart-cc956833-9575-42b3-bbc4-671d55e1833a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466787759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1466787759
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.762051919
Short name T847
Test name
Test status
Simulation time 73567182 ps
CPU time 1.51 seconds
Started Jul 06 04:47:53 PM PDT 24
Finished Jul 06 04:47:56 PM PDT 24
Peak memory 207148 kb
Host smart-78d9b8ab-f3ce-4843-aa83-a63167a0481f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762051919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.762051919
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2136875257
Short name T353
Test name
Test status
Simulation time 575651755 ps
CPU time 3.33 seconds
Started Jul 06 04:47:54 PM PDT 24
Finished Jul 06 04:47:58 PM PDT 24
Peak memory 209236 kb
Host smart-37c0c1c3-744b-455f-9a1e-65a166129bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136875257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2136875257
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.375082247
Short name T222
Test name
Test status
Simulation time 254074110 ps
CPU time 2.59 seconds
Started Jul 06 04:47:50 PM PDT 24
Finished Jul 06 04:47:53 PM PDT 24
Peak memory 214168 kb
Host smart-4828aaa7-65d7-489a-8bf8-ac67058f3204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375082247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.375082247
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.4253886569
Short name T661
Test name
Test status
Simulation time 196118937 ps
CPU time 3.18 seconds
Started Jul 06 04:47:50 PM PDT 24
Finished Jul 06 04:47:53 PM PDT 24
Peak memory 209552 kb
Host smart-d3ecce12-9fbe-4a3f-916d-705710188cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253886569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.4253886569
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.295841434
Short name T374
Test name
Test status
Simulation time 97552708 ps
CPU time 5.36 seconds
Started Jul 06 04:47:54 PM PDT 24
Finished Jul 06 04:48:01 PM PDT 24
Peak memory 208192 kb
Host smart-91ce8d49-28b2-4d41-b294-8c25d16c4c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295841434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.295841434
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1350799317
Short name T918
Test name
Test status
Simulation time 93127782 ps
CPU time 3.74 seconds
Started Jul 06 04:48:05 PM PDT 24
Finished Jul 06 04:48:10 PM PDT 24
Peak memory 208548 kb
Host smart-ac66d9b7-3f55-4d04-9472-013e06c6f553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350799317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1350799317
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2488219716
Short name T645
Test name
Test status
Simulation time 605676533 ps
CPU time 7.21 seconds
Started Jul 06 04:48:05 PM PDT 24
Finished Jul 06 04:48:14 PM PDT 24
Peak memory 207032 kb
Host smart-8a416751-73e4-4514-b7b6-1baa6552ccb9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488219716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2488219716
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3289050782
Short name T669
Test name
Test status
Simulation time 2234562345 ps
CPU time 15.09 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:48:09 PM PDT 24
Peak memory 208916 kb
Host smart-4efd3933-24bd-4714-8485-077f2e12224f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289050782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3289050782
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1165980585
Short name T341
Test name
Test status
Simulation time 34841756 ps
CPU time 1.76 seconds
Started Jul 06 04:47:51 PM PDT 24
Finished Jul 06 04:47:54 PM PDT 24
Peak memory 206844 kb
Host smart-03d7fe12-3793-47e8-9e04-13ef4ecffe4e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165980585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1165980585
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1848529690
Short name T2
Test name
Test status
Simulation time 302998595 ps
CPU time 5.57 seconds
Started Jul 06 04:48:00 PM PDT 24
Finished Jul 06 04:48:06 PM PDT 24
Peak memory 209568 kb
Host smart-201db8de-c7c7-488c-8d1e-bbe29862f3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848529690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1848529690
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1024162640
Short name T396
Test name
Test status
Simulation time 5688380491 ps
CPU time 19.78 seconds
Started Jul 06 04:47:52 PM PDT 24
Finished Jul 06 04:48:13 PM PDT 24
Peak memory 208064 kb
Host smart-39bce18c-cb0a-42a2-8212-cced4c286009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024162640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1024162640
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1641398632
Short name T422
Test name
Test status
Simulation time 24115199 ps
CPU time 0.86 seconds
Started Jul 06 04:47:58 PM PDT 24
Finished Jul 06 04:48:00 PM PDT 24
Peak memory 205892 kb
Host smart-daedf0ba-89c9-4f84-acce-fafd00a2ceba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641398632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1641398632
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.4144737538
Short name T410
Test name
Test status
Simulation time 1058159274 ps
CPU time 9.11 seconds
Started Jul 06 04:47:57 PM PDT 24
Finished Jul 06 04:48:07 PM PDT 24
Peak memory 206860 kb
Host smart-dae41ec3-7b85-4f5f-b381-68192fb1073e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144737538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.4144737538
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.344246793
Short name T40
Test name
Test status
Simulation time 251912730 ps
CPU time 2.29 seconds
Started Jul 06 04:47:58 PM PDT 24
Finished Jul 06 04:48:01 PM PDT 24
Peak memory 210248 kb
Host smart-3d90f222-93a2-4951-ba73-63a0355bffde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344246793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.344246793
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3055539205
Short name T97
Test name
Test status
Simulation time 19178283 ps
CPU time 0.76 seconds
Started Jul 06 04:48:02 PM PDT 24
Finished Jul 06 04:48:03 PM PDT 24
Peak memory 205868 kb
Host smart-ece8bcc0-f0f0-4f8f-994c-74e27f8e51e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055539205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3055539205
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2419747355
Short name T530
Test name
Test status
Simulation time 126262115 ps
CPU time 4.33 seconds
Started Jul 06 04:48:09 PM PDT 24
Finished Jul 06 04:48:14 PM PDT 24
Peak memory 217664 kb
Host smart-7ee93180-fa25-440d-90a7-30d042920e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419747355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2419747355
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1174028375
Short name T419
Test name
Test status
Simulation time 36708506 ps
CPU time 2.62 seconds
Started Jul 06 04:48:04 PM PDT 24
Finished Jul 06 04:48:07 PM PDT 24
Peak memory 209696 kb
Host smart-575e045e-203f-4d62-9731-53a832fcfc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174028375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1174028375
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2608377016
Short name T518
Test name
Test status
Simulation time 349339127 ps
CPU time 3.62 seconds
Started Jul 06 04:48:02 PM PDT 24
Finished Jul 06 04:48:06 PM PDT 24
Peak memory 214132 kb
Host smart-d7fb878f-72ba-4079-9295-3fd93fb43531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608377016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2608377016
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1108634496
Short name T199
Test name
Test status
Simulation time 770127383 ps
CPU time 3.67 seconds
Started Jul 06 04:48:02 PM PDT 24
Finished Jul 06 04:48:06 PM PDT 24
Peak memory 219836 kb
Host smart-82b0ed37-0c82-4d11-ba82-13ea6eb2edc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108634496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1108634496
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1511640633
Short name T845
Test name
Test status
Simulation time 48293710 ps
CPU time 3.45 seconds
Started Jul 06 04:47:58 PM PDT 24
Finished Jul 06 04:48:02 PM PDT 24
Peak memory 210432 kb
Host smart-aa5e8b1c-39e7-47a5-ba53-729d5a238af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511640633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1511640633
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3120777439
Short name T480
Test name
Test status
Simulation time 108394904 ps
CPU time 4.39 seconds
Started Jul 06 04:47:59 PM PDT 24
Finished Jul 06 04:48:05 PM PDT 24
Peak memory 208568 kb
Host smart-e24b1934-5092-4494-b7d8-511e410c3a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120777439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3120777439
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2924270089
Short name T618
Test name
Test status
Simulation time 34020410 ps
CPU time 2.38 seconds
Started Jul 06 04:48:00 PM PDT 24
Finished Jul 06 04:48:03 PM PDT 24
Peak memory 207420 kb
Host smart-1cae94ad-edda-4e90-bd8b-22b9e0d24472
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924270089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2924270089
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1324590014
Short name T280
Test name
Test status
Simulation time 91306767 ps
CPU time 4.06 seconds
Started Jul 06 04:48:01 PM PDT 24
Finished Jul 06 04:48:05 PM PDT 24
Peak memory 208800 kb
Host smart-7f4e7237-4274-4352-bf76-b35cf613b3b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324590014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1324590014
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.4028779482
Short name T101
Test name
Test status
Simulation time 2092552356 ps
CPU time 7.33 seconds
Started Jul 06 04:47:57 PM PDT 24
Finished Jul 06 04:48:06 PM PDT 24
Peak memory 208780 kb
Host smart-e7687b64-6869-4997-88dd-d083d7a23e78
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028779482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.4028779482
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1102529725
Short name T429
Test name
Test status
Simulation time 62684409 ps
CPU time 2.53 seconds
Started Jul 06 04:48:00 PM PDT 24
Finished Jul 06 04:48:03 PM PDT 24
Peak memory 218140 kb
Host smart-88a95049-9d09-4cfa-99e6-ee8abcbca2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102529725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1102529725
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3875044506
Short name T533
Test name
Test status
Simulation time 628845341 ps
CPU time 4.34 seconds
Started Jul 06 04:47:58 PM PDT 24
Finished Jul 06 04:48:03 PM PDT 24
Peak memory 208512 kb
Host smart-fbc2570a-818a-4612-9508-0dcaabb4c51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875044506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3875044506
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3526943341
Short name T198
Test name
Test status
Simulation time 8647543159 ps
CPU time 265.83 seconds
Started Jul 06 04:47:57 PM PDT 24
Finished Jul 06 04:52:24 PM PDT 24
Peak memory 220352 kb
Host smart-85381479-0699-4414-b7d6-bd8da604883b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526943341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3526943341
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3992947602
Short name T328
Test name
Test status
Simulation time 666793242 ps
CPU time 18.5 seconds
Started Jul 06 04:48:01 PM PDT 24
Finished Jul 06 04:48:20 PM PDT 24
Peak memory 222452 kb
Host smart-bff43f6e-ab5f-47cd-a1d6-68b734acb026
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992947602 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3992947602
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3307704884
Short name T548
Test name
Test status
Simulation time 8393761131 ps
CPU time 54.55 seconds
Started Jul 06 04:47:57 PM PDT 24
Finished Jul 06 04:48:52 PM PDT 24
Peak memory 209748 kb
Host smart-2350004b-3314-4d23-86d3-d2693d4be992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307704884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3307704884
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.4249074462
Short name T512
Test name
Test status
Simulation time 148503160 ps
CPU time 3.13 seconds
Started Jul 06 04:47:59 PM PDT 24
Finished Jul 06 04:48:03 PM PDT 24
Peak memory 210336 kb
Host smart-d4ade02a-10b9-47d1-9b78-af6cb39bf0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249074462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.4249074462
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2426988973
Short name T898
Test name
Test status
Simulation time 42391188 ps
CPU time 0.75 seconds
Started Jul 06 04:48:04 PM PDT 24
Finished Jul 06 04:48:05 PM PDT 24
Peak memory 205868 kb
Host smart-a7862df9-4f88-4f4a-9e4c-c22b6f9c43e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426988973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2426988973
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3293443627
Short name T274
Test name
Test status
Simulation time 536262616 ps
CPU time 5.32 seconds
Started Jul 06 04:47:59 PM PDT 24
Finished Jul 06 04:48:05 PM PDT 24
Peak memory 221176 kb
Host smart-69f687dd-442c-4687-a4b7-92608523c27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293443627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3293443627
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3580786202
Short name T62
Test name
Test status
Simulation time 226828189 ps
CPU time 2.24 seconds
Started Jul 06 04:48:01 PM PDT 24
Finished Jul 06 04:48:04 PM PDT 24
Peak memory 207492 kb
Host smart-aa6cb31d-dc49-40cb-a903-d261b95005ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580786202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3580786202
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.666540365
Short name T94
Test name
Test status
Simulation time 646264967 ps
CPU time 6.27 seconds
Started Jul 06 04:47:57 PM PDT 24
Finished Jul 06 04:48:05 PM PDT 24
Peak memory 209268 kb
Host smart-39fa8704-0cf3-425f-99c6-59b62f21b1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666540365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.666540365
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1833908248
Short name T330
Test name
Test status
Simulation time 92803975 ps
CPU time 1.99 seconds
Started Jul 06 04:48:01 PM PDT 24
Finished Jul 06 04:48:03 PM PDT 24
Peak memory 214164 kb
Host smart-8cd42f5c-934f-4ec4-b331-ec1473abb5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833908248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1833908248
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_random.3919148072
Short name T820
Test name
Test status
Simulation time 879541910 ps
CPU time 6.45 seconds
Started Jul 06 04:48:02 PM PDT 24
Finished Jul 06 04:48:09 PM PDT 24
Peak memory 208064 kb
Host smart-06988857-b0db-4833-b5a5-96d2949b4926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919148072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3919148072
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1767527730
Short name T598
Test name
Test status
Simulation time 27041585 ps
CPU time 2.11 seconds
Started Jul 06 04:47:58 PM PDT 24
Finished Jul 06 04:48:01 PM PDT 24
Peak memory 208352 kb
Host smart-5ae967a4-cfd6-4cf7-bd97-85d8f3adf661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767527730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1767527730
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.183667543
Short name T309
Test name
Test status
Simulation time 102252049 ps
CPU time 3.3 seconds
Started Jul 06 04:48:03 PM PDT 24
Finished Jul 06 04:48:07 PM PDT 24
Peak memory 206812 kb
Host smart-5f025e9b-fe5a-4e09-91e0-4c73acf7e54b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183667543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.183667543
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.150772366
Short name T490
Test name
Test status
Simulation time 130272771 ps
CPU time 2.66 seconds
Started Jul 06 04:48:00 PM PDT 24
Finished Jul 06 04:48:03 PM PDT 24
Peak memory 206808 kb
Host smart-79b61a1d-cb6f-4213-bee0-bbd4024a4313
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150772366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.150772366
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3334710598
Short name T525
Test name
Test status
Simulation time 124543324 ps
CPU time 2.44 seconds
Started Jul 06 04:48:03 PM PDT 24
Finished Jul 06 04:48:06 PM PDT 24
Peak memory 207260 kb
Host smart-a565ef1f-af2e-4929-9b69-90f9dbda3e43
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334710598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3334710598
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3301986925
Short name T676
Test name
Test status
Simulation time 87852822 ps
CPU time 2.19 seconds
Started Jul 06 04:48:00 PM PDT 24
Finished Jul 06 04:48:03 PM PDT 24
Peak memory 209364 kb
Host smart-161642ef-4ebc-4db2-9a69-9fa1d0ee6e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301986925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3301986925
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3155245463
Short name T447
Test name
Test status
Simulation time 414063301 ps
CPU time 4.68 seconds
Started Jul 06 04:47:57 PM PDT 24
Finished Jul 06 04:48:02 PM PDT 24
Peak memory 206720 kb
Host smart-34d75d0b-6c33-499f-aa66-05ffb9a2ce0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155245463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3155245463
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1937370389
Short name T532
Test name
Test status
Simulation time 16818695 ps
CPU time 0.83 seconds
Started Jul 06 04:48:05 PM PDT 24
Finished Jul 06 04:48:07 PM PDT 24
Peak memory 205976 kb
Host smart-d9ded35d-3512-4abf-94c8-4b82257c5219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937370389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1937370389
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.313465906
Short name T390
Test name
Test status
Simulation time 230807378 ps
CPU time 4.09 seconds
Started Jul 06 04:48:08 PM PDT 24
Finished Jul 06 04:48:12 PM PDT 24
Peak memory 208136 kb
Host smart-6b6e4271-b841-48a2-bf55-61503e0d655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313465906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.313465906
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1987482892
Short name T584
Test name
Test status
Simulation time 82799844 ps
CPU time 2.08 seconds
Started Jul 06 04:48:03 PM PDT 24
Finished Jul 06 04:48:06 PM PDT 24
Peak memory 209780 kb
Host smart-27afc91b-140f-47e4-8247-c421b1cf6bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987482892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1987482892
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.578764143
Short name T802
Test name
Test status
Simulation time 36085315 ps
CPU time 0.79 seconds
Started Jul 06 04:48:03 PM PDT 24
Finished Jul 06 04:48:04 PM PDT 24
Peak memory 205888 kb
Host smart-ae20271e-36c8-40eb-afb8-23812e7739b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578764143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.578764143
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1239769757
Short name T703
Test name
Test status
Simulation time 198989540 ps
CPU time 4.05 seconds
Started Jul 06 04:48:04 PM PDT 24
Finished Jul 06 04:48:08 PM PDT 24
Peak memory 215236 kb
Host smart-3c16fe45-8ecc-4ded-acc2-fbce81b09577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1239769757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1239769757
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1971463333
Short name T891
Test name
Test status
Simulation time 153423264 ps
CPU time 2.44 seconds
Started Jul 06 04:48:04 PM PDT 24
Finished Jul 06 04:48:07 PM PDT 24
Peak memory 214532 kb
Host smart-8cc5aed2-be39-4a70-bfca-2132938af98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971463333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1971463333
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3718066039
Short name T662
Test name
Test status
Simulation time 79540686 ps
CPU time 2.87 seconds
Started Jul 06 04:48:07 PM PDT 24
Finished Jul 06 04:48:11 PM PDT 24
Peak memory 214208 kb
Host smart-a2ff21f7-2e35-4717-8946-339e5db95361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718066039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3718066039
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2365628134
Short name T272
Test name
Test status
Simulation time 400970466 ps
CPU time 5.41 seconds
Started Jul 06 04:48:04 PM PDT 24
Finished Jul 06 04:48:10 PM PDT 24
Peak memory 222332 kb
Host smart-21de9183-0a71-4c5a-aed8-f678a12ccfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365628134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2365628134
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2916989690
Short name T439
Test name
Test status
Simulation time 62677507 ps
CPU time 3.94 seconds
Started Jul 06 04:48:08 PM PDT 24
Finished Jul 06 04:48:13 PM PDT 24
Peak memory 209400 kb
Host smart-615c718f-c755-4dc6-bb41-32e06ed5420e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916989690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2916989690
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2041198737
Short name T716
Test name
Test status
Simulation time 63452964 ps
CPU time 2.54 seconds
Started Jul 06 04:48:05 PM PDT 24
Finished Jul 06 04:48:08 PM PDT 24
Peak memory 208544 kb
Host smart-c55e0079-1977-4a9a-951f-cd8af34a3f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041198737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2041198737
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1885369464
Short name T856
Test name
Test status
Simulation time 916144417 ps
CPU time 6.15 seconds
Started Jul 06 04:48:09 PM PDT 24
Finished Jul 06 04:48:15 PM PDT 24
Peak memory 208180 kb
Host smart-46891a8e-c1c7-4b78-a7fc-a33b0b9121a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885369464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1885369464
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2922274388
Short name T473
Test name
Test status
Simulation time 2911892464 ps
CPU time 31.62 seconds
Started Jul 06 04:48:06 PM PDT 24
Finished Jul 06 04:48:38 PM PDT 24
Peak memory 208424 kb
Host smart-fecdadf5-3533-40bb-9de9-53c0e66decf6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922274388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2922274388
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3713984802
Short name T655
Test name
Test status
Simulation time 2074364348 ps
CPU time 5.57 seconds
Started Jul 06 04:48:04 PM PDT 24
Finished Jul 06 04:48:10 PM PDT 24
Peak memory 208580 kb
Host smart-9b9046d3-db9b-4cb8-a0de-9fb8e9bc7efd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713984802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3713984802
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1654228080
Short name T191
Test name
Test status
Simulation time 103129576 ps
CPU time 3.33 seconds
Started Jul 06 04:48:03 PM PDT 24
Finished Jul 06 04:48:07 PM PDT 24
Peak memory 208008 kb
Host smart-18c3a88b-88a5-4b4c-aeb4-a3324cdded83
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654228080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1654228080
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1179503906
Short name T832
Test name
Test status
Simulation time 146552715 ps
CPU time 2.27 seconds
Started Jul 06 04:48:03 PM PDT 24
Finished Jul 06 04:48:06 PM PDT 24
Peak memory 214208 kb
Host smart-1cbecde3-ba1d-485a-83ee-cad4d4f9f6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179503906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1179503906
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.898649971
Short name T887
Test name
Test status
Simulation time 435848059 ps
CPU time 2.69 seconds
Started Jul 06 04:48:03 PM PDT 24
Finished Jul 06 04:48:07 PM PDT 24
Peak memory 206816 kb
Host smart-d985c091-025e-4e70-b73e-438461e02991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898649971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.898649971
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1278737626
Short name T774
Test name
Test status
Simulation time 221576192 ps
CPU time 9.13 seconds
Started Jul 06 04:48:04 PM PDT 24
Finished Jul 06 04:48:14 PM PDT 24
Peak memory 214364 kb
Host smart-d1614511-2187-41ae-adb9-0504f7dd0e07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278737626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1278737626
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.251251630
Short name T56
Test name
Test status
Simulation time 1974204645 ps
CPU time 23.63 seconds
Started Jul 06 04:48:19 PM PDT 24
Finished Jul 06 04:48:43 PM PDT 24
Peak memory 222520 kb
Host smart-bab21025-b719-4751-908b-bc2817ee83a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251251630 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.251251630
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1661855710
Short name T583
Test name
Test status
Simulation time 531696650 ps
CPU time 4.33 seconds
Started Jul 06 04:48:01 PM PDT 24
Finished Jul 06 04:48:06 PM PDT 24
Peak memory 207628 kb
Host smart-c6ded827-e957-451a-b59f-3581d0585f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661855710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1661855710
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.404544886
Short name T357
Test name
Test status
Simulation time 206130812 ps
CPU time 2.69 seconds
Started Jul 06 04:48:05 PM PDT 24
Finished Jul 06 04:48:08 PM PDT 24
Peak memory 210196 kb
Host smart-d29e1096-079f-4175-bc98-ead6a6482e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404544886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.404544886
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.4148133612
Short name T700
Test name
Test status
Simulation time 13161339 ps
CPU time 0.9 seconds
Started Jul 06 04:48:14 PM PDT 24
Finished Jul 06 04:48:15 PM PDT 24
Peak memory 205912 kb
Host smart-1759feb2-6e4a-4c56-a560-d5917f3f36da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148133612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.4148133612
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2863797693
Short name T380
Test name
Test status
Simulation time 955620285 ps
CPU time 50.03 seconds
Started Jul 06 04:48:03 PM PDT 24
Finished Jul 06 04:48:54 PM PDT 24
Peak memory 215052 kb
Host smart-4d7c733b-2979-4589-b46b-d144c9714fc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2863797693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2863797693
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1416839908
Short name T496
Test name
Test status
Simulation time 185461785 ps
CPU time 3.23 seconds
Started Jul 06 04:48:11 PM PDT 24
Finished Jul 06 04:48:14 PM PDT 24
Peak memory 217900 kb
Host smart-8b5a4d4c-fcc8-4c73-aa12-0e69984a756e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416839908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1416839908
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1018519793
Short name T492
Test name
Test status
Simulation time 21885980 ps
CPU time 1.8 seconds
Started Jul 06 04:48:13 PM PDT 24
Finished Jul 06 04:48:15 PM PDT 24
Peak memory 207192 kb
Host smart-883cfeab-7ae0-41ee-a180-04e8bf6113fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018519793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1018519793
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.786799861
Short name T260
Test name
Test status
Simulation time 365591246 ps
CPU time 3.05 seconds
Started Jul 06 04:48:19 PM PDT 24
Finished Jul 06 04:48:23 PM PDT 24
Peak memory 214220 kb
Host smart-9a2a4051-d71d-482e-89d4-ee0861c659d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786799861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.786799861
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.453360473
Short name T808
Test name
Test status
Simulation time 90137635 ps
CPU time 2.46 seconds
Started Jul 06 04:48:02 PM PDT 24
Finished Jul 06 04:48:05 PM PDT 24
Peak memory 220220 kb
Host smart-4bff8112-59d2-47b2-8912-5d2ca7b3224f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453360473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.453360473
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1178385347
Short name T470
Test name
Test status
Simulation time 39458271 ps
CPU time 3.09 seconds
Started Jul 06 04:48:08 PM PDT 24
Finished Jul 06 04:48:11 PM PDT 24
Peak memory 207336 kb
Host smart-ccb0d3fb-d3c5-46a9-9992-7daf5c308b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178385347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1178385347
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2236801386
Short name T791
Test name
Test status
Simulation time 169167924 ps
CPU time 3.81 seconds
Started Jul 06 04:48:15 PM PDT 24
Finished Jul 06 04:48:19 PM PDT 24
Peak memory 208412 kb
Host smart-90c383ad-4c6e-4613-9b97-bbd42f638f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236801386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2236801386
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2939021607
Short name T619
Test name
Test status
Simulation time 1849153785 ps
CPU time 39.64 seconds
Started Jul 06 04:48:08 PM PDT 24
Finished Jul 06 04:48:48 PM PDT 24
Peak memory 208348 kb
Host smart-3671aa2c-8517-4d48-af25-7084098baf2e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939021607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2939021607
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2644486431
Short name T864
Test name
Test status
Simulation time 196079801 ps
CPU time 4.85 seconds
Started Jul 06 04:48:06 PM PDT 24
Finished Jul 06 04:48:11 PM PDT 24
Peak memory 208072 kb
Host smart-c60c2139-94f4-466e-827e-9a9bb45df6d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644486431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2644486431
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2102512649
Short name T452
Test name
Test status
Simulation time 115386027 ps
CPU time 2.87 seconds
Started Jul 06 04:48:07 PM PDT 24
Finished Jul 06 04:48:10 PM PDT 24
Peak memory 208588 kb
Host smart-d915601a-3a45-4f81-b366-de45d6bcd942
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102512649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2102512649
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3259198970
Short name T732
Test name
Test status
Simulation time 2861109671 ps
CPU time 28.89 seconds
Started Jul 06 04:48:13 PM PDT 24
Finished Jul 06 04:48:42 PM PDT 24
Peak memory 209612 kb
Host smart-bb5b73a1-f79e-49de-8da5-62ffcf9d9734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259198970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3259198970
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.949373738
Short name T731
Test name
Test status
Simulation time 399701176 ps
CPU time 3.07 seconds
Started Jul 06 04:48:08 PM PDT 24
Finished Jul 06 04:48:11 PM PDT 24
Peak memory 208408 kb
Host smart-ad9579c7-8be7-43a2-836e-d012d3cb2fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949373738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.949373738
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1317127683
Short name T720
Test name
Test status
Simulation time 994112004 ps
CPU time 37.26 seconds
Started Jul 06 04:48:09 PM PDT 24
Finished Jul 06 04:48:47 PM PDT 24
Peak memory 221080 kb
Host smart-ca595391-2283-4825-9036-56410549c3ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317127683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1317127683
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3569368948
Short name T333
Test name
Test status
Simulation time 106518603 ps
CPU time 5 seconds
Started Jul 06 04:48:04 PM PDT 24
Finished Jul 06 04:48:10 PM PDT 24
Peak memory 218244 kb
Host smart-b98a51ef-362f-4109-99f1-c345c9a814e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569368948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3569368948
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1210176921
Short name T622
Test name
Test status
Simulation time 1650967612 ps
CPU time 3.67 seconds
Started Jul 06 04:48:19 PM PDT 24
Finished Jul 06 04:48:23 PM PDT 24
Peak memory 210372 kb
Host smart-4e64920d-e484-4a5f-a639-8d28bc7084d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210176921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1210176921
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.972077410
Short name T875
Test name
Test status
Simulation time 14548602 ps
CPU time 0.78 seconds
Started Jul 06 04:48:10 PM PDT 24
Finished Jul 06 04:48:11 PM PDT 24
Peak memory 205904 kb
Host smart-94ae1d63-22c7-4f6b-ad6f-e10a4372edfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972077410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.972077410
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3204688965
Short name T389
Test name
Test status
Simulation time 51150717 ps
CPU time 3.63 seconds
Started Jul 06 04:48:10 PM PDT 24
Finished Jul 06 04:48:14 PM PDT 24
Peak memory 214412 kb
Host smart-1ceb46e0-e39d-4011-b898-507dc7c7ab3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3204688965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3204688965
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3483375855
Short name T828
Test name
Test status
Simulation time 145739082 ps
CPU time 4.33 seconds
Started Jul 06 04:48:12 PM PDT 24
Finished Jul 06 04:48:17 PM PDT 24
Peak memory 214184 kb
Host smart-1a0f51da-6b6e-45cc-8cd5-f09cb1be304c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483375855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3483375855
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1836279774
Short name T48
Test name
Test status
Simulation time 1827988710 ps
CPU time 23.65 seconds
Started Jul 06 04:48:07 PM PDT 24
Finished Jul 06 04:48:31 PM PDT 24
Peak memory 209576 kb
Host smart-6b70f89e-7a36-4a6f-98fe-d3c5ebcc458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836279774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1836279774
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.839016520
Short name T772
Test name
Test status
Simulation time 357333188 ps
CPU time 2.49 seconds
Started Jul 06 04:48:35 PM PDT 24
Finished Jul 06 04:48:38 PM PDT 24
Peak memory 214296 kb
Host smart-167b8dda-76e4-47b8-a607-08e0f2928f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839016520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.839016520
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3158248434
Short name T299
Test name
Test status
Simulation time 453602382 ps
CPU time 5.14 seconds
Started Jul 06 04:48:12 PM PDT 24
Finished Jul 06 04:48:18 PM PDT 24
Peak memory 214608 kb
Host smart-9970d66c-3ed7-456a-85ec-f5f05118922a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158248434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3158248434
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3985630966
Short name T6
Test name
Test status
Simulation time 109297113 ps
CPU time 1.92 seconds
Started Jul 06 04:48:09 PM PDT 24
Finished Jul 06 04:48:11 PM PDT 24
Peak memory 208064 kb
Host smart-e13f6621-ecba-4f41-a6d5-acf4087fbf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985630966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3985630966
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.882840392
Short name T819
Test name
Test status
Simulation time 2432019490 ps
CPU time 75.82 seconds
Started Jul 06 04:48:28 PM PDT 24
Finished Jul 06 04:49:44 PM PDT 24
Peak memory 214348 kb
Host smart-fe6c2bd9-1e9b-497a-a4d0-98ab7c1e6f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882840392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.882840392
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1971011742
Short name T615
Test name
Test status
Simulation time 449535489 ps
CPU time 3.09 seconds
Started Jul 06 04:48:15 PM PDT 24
Finished Jul 06 04:48:18 PM PDT 24
Peak memory 208696 kb
Host smart-9e2368d3-2785-47f5-9d9b-8cfe94b39f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971011742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1971011742
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3063065907
Short name T849
Test name
Test status
Simulation time 2290260555 ps
CPU time 13.46 seconds
Started Jul 06 04:48:14 PM PDT 24
Finished Jul 06 04:48:28 PM PDT 24
Peak memory 207932 kb
Host smart-d1d0e079-e78b-49bf-a2db-62fd033edcd3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063065907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3063065907
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2837992784
Short name T407
Test name
Test status
Simulation time 246661937 ps
CPU time 3.11 seconds
Started Jul 06 04:48:08 PM PDT 24
Finished Jul 06 04:48:11 PM PDT 24
Peak memory 206700 kb
Host smart-68ec7775-dc21-4b17-8a35-14365e6643e5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837992784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2837992784
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1084528303
Short name T709
Test name
Test status
Simulation time 181963689 ps
CPU time 6.39 seconds
Started Jul 06 04:48:23 PM PDT 24
Finished Jul 06 04:48:30 PM PDT 24
Peak memory 208416 kb
Host smart-bc196b90-abe0-409a-8053-793d639e258e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084528303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1084528303
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.598658920
Short name T303
Test name
Test status
Simulation time 133770998 ps
CPU time 4.92 seconds
Started Jul 06 04:48:10 PM PDT 24
Finished Jul 06 04:48:15 PM PDT 24
Peak memory 218280 kb
Host smart-e0d3864a-0e75-4c34-9dbf-60045e431490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598658920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.598658920
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1822480707
Short name T560
Test name
Test status
Simulation time 340593878 ps
CPU time 2.92 seconds
Started Jul 06 04:48:29 PM PDT 24
Finished Jul 06 04:48:32 PM PDT 24
Peak memory 206564 kb
Host smart-84f64975-f795-4862-b6ae-b90b3e156c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822480707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1822480707
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3306893398
Short name T179
Test name
Test status
Simulation time 3025684535 ps
CPU time 65.54 seconds
Started Jul 06 04:48:12 PM PDT 24
Finished Jul 06 04:49:18 PM PDT 24
Peak memory 216672 kb
Host smart-686a4911-0e86-4616-85fb-889bffaafe05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306893398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3306893398
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2990648977
Short name T210
Test name
Test status
Simulation time 1296517549 ps
CPU time 21.1 seconds
Started Jul 06 04:48:19 PM PDT 24
Finished Jul 06 04:48:41 PM PDT 24
Peak memory 222516 kb
Host smart-a5bb6f73-40ec-4390-bc58-2f2ead2c944e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990648977 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2990648977
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2531638372
Short name T310
Test name
Test status
Simulation time 165724217 ps
CPU time 3.83 seconds
Started Jul 06 04:48:46 PM PDT 24
Finished Jul 06 04:48:50 PM PDT 24
Peak memory 207532 kb
Host smart-5aaaaf4d-9742-4121-bd27-dc863064104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531638372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2531638372
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2459042003
Short name T361
Test name
Test status
Simulation time 114110961 ps
CPU time 1.67 seconds
Started Jul 06 04:48:23 PM PDT 24
Finished Jul 06 04:48:25 PM PDT 24
Peak memory 210408 kb
Host smart-64a153c6-4c22-46ae-b8bb-807c0902fb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459042003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2459042003
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1720039493
Short name T395
Test name
Test status
Simulation time 27715767 ps
CPU time 0.7 seconds
Started Jul 06 04:48:15 PM PDT 24
Finished Jul 06 04:48:16 PM PDT 24
Peak memory 205896 kb
Host smart-b5ca55fc-4fbb-4404-b7f4-39b888c2c122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720039493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1720039493
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2199696174
Short name T142
Test name
Test status
Simulation time 646083170 ps
CPU time 3.85 seconds
Started Jul 06 04:48:17 PM PDT 24
Finished Jul 06 04:48:21 PM PDT 24
Peak memory 215324 kb
Host smart-ee52f5b4-842e-4d0f-af0c-113029bdcc07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2199696174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2199696174
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1232237099
Short name T30
Test name
Test status
Simulation time 69614060 ps
CPU time 2.35 seconds
Started Jul 06 04:48:17 PM PDT 24
Finished Jul 06 04:48:20 PM PDT 24
Peak memory 222736 kb
Host smart-06b8e151-5818-4226-9b72-5a3453312823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232237099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1232237099
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.253062016
Short name T522
Test name
Test status
Simulation time 335105996 ps
CPU time 7.17 seconds
Started Jul 06 04:48:16 PM PDT 24
Finished Jul 06 04:48:23 PM PDT 24
Peak memory 210148 kb
Host smart-f1b1ecbd-3954-4e72-a12c-cf89b97a7135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253062016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.253062016
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2805984488
Short name T355
Test name
Test status
Simulation time 313726227 ps
CPU time 5.14 seconds
Started Jul 06 04:48:18 PM PDT 24
Finished Jul 06 04:48:23 PM PDT 24
Peak memory 209400 kb
Host smart-4cbbc821-aa37-4acc-9a07-78015110f8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805984488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2805984488
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3639665115
Short name T823
Test name
Test status
Simulation time 32983313 ps
CPU time 2.6 seconds
Started Jul 06 04:48:27 PM PDT 24
Finished Jul 06 04:48:30 PM PDT 24
Peak memory 209688 kb
Host smart-12309b28-20fa-455c-a653-9ed965c933bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639665115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3639665115
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.71335997
Short name T267
Test name
Test status
Simulation time 178509503 ps
CPU time 4.08 seconds
Started Jul 06 04:48:15 PM PDT 24
Finished Jul 06 04:48:20 PM PDT 24
Peak memory 210412 kb
Host smart-12f0e7cc-dae5-4af2-a0a7-41057f4e7540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71335997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.71335997
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.442385436
Short name T436
Test name
Test status
Simulation time 1717197813 ps
CPU time 28.76 seconds
Started Jul 06 04:48:10 PM PDT 24
Finished Jul 06 04:48:39 PM PDT 24
Peak memory 208400 kb
Host smart-221cdfee-b26d-4190-895d-1335686936ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442385436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.442385436
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.254204273
Short name T616
Test name
Test status
Simulation time 67573990 ps
CPU time 3.29 seconds
Started Jul 06 04:48:10 PM PDT 24
Finished Jul 06 04:48:14 PM PDT 24
Peak memory 207324 kb
Host smart-da998bf7-f2a3-4c30-beb7-921f1ed649e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254204273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.254204273
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2869891342
Short name T780
Test name
Test status
Simulation time 75422167 ps
CPU time 1.87 seconds
Started Jul 06 04:48:17 PM PDT 24
Finished Jul 06 04:48:19 PM PDT 24
Peak memory 206780 kb
Host smart-93d39550-9547-40af-8636-4910f44739d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869891342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2869891342
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2522517824
Short name T528
Test name
Test status
Simulation time 154849316 ps
CPU time 3.97 seconds
Started Jul 06 04:48:08 PM PDT 24
Finished Jul 06 04:48:12 PM PDT 24
Peak memory 208120 kb
Host smart-2ec00199-0cce-4f7c-9c54-bcb1075bf289
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522517824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2522517824
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.813269135
Short name T565
Test name
Test status
Simulation time 372933831 ps
CPU time 5.3 seconds
Started Jul 06 04:48:20 PM PDT 24
Finished Jul 06 04:48:26 PM PDT 24
Peak memory 218368 kb
Host smart-eb0b52e8-b860-442e-b432-acbe476ce3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813269135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.813269135
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.806205063
Short name T450
Test name
Test status
Simulation time 225326495 ps
CPU time 2.64 seconds
Started Jul 06 04:48:11 PM PDT 24
Finished Jul 06 04:48:14 PM PDT 24
Peak memory 206000 kb
Host smart-54a3486b-785e-45f3-a41b-814e8a44a0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806205063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.806205063
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2147710532
Short name T843
Test name
Test status
Simulation time 259182087 ps
CPU time 5.29 seconds
Started Jul 06 04:48:15 PM PDT 24
Finished Jul 06 04:48:21 PM PDT 24
Peak memory 216616 kb
Host smart-47fc7ed3-6621-4971-9d45-429b9de4e922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147710532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2147710532
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3877031243
Short name T872
Test name
Test status
Simulation time 620777850 ps
CPU time 22.79 seconds
Started Jul 06 04:48:17 PM PDT 24
Finished Jul 06 04:48:40 PM PDT 24
Peak memory 222496 kb
Host smart-ab173670-c579-4643-8f10-d05b22c31f89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877031243 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3877031243
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2216661581
Short name T514
Test name
Test status
Simulation time 152041057 ps
CPU time 4.03 seconds
Started Jul 06 04:48:19 PM PDT 24
Finished Jul 06 04:48:24 PM PDT 24
Peak memory 207832 kb
Host smart-fdaef9e7-a166-4d42-b389-4c91eab36c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216661581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2216661581
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1959013405
Short name T562
Test name
Test status
Simulation time 441245679 ps
CPU time 4.2 seconds
Started Jul 06 04:48:20 PM PDT 24
Finished Jul 06 04:48:25 PM PDT 24
Peak memory 209724 kb
Host smart-49d32118-ff90-4fc7-a629-087de3293a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959013405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1959013405
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3559549810
Short name T408
Test name
Test status
Simulation time 45838486 ps
CPU time 0.79 seconds
Started Jul 06 04:48:17 PM PDT 24
Finished Jul 06 04:48:18 PM PDT 24
Peak memory 205900 kb
Host smart-98fcb5e7-99ad-4273-b8fa-981ca0aec976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559549810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3559549810
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2701211253
Short name T291
Test name
Test status
Simulation time 134228473 ps
CPU time 7.21 seconds
Started Jul 06 04:48:24 PM PDT 24
Finished Jul 06 04:48:31 PM PDT 24
Peak memory 214200 kb
Host smart-a8958614-c64d-47df-a29f-c75d9cc52581
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2701211253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2701211253
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2623108243
Short name T256
Test name
Test status
Simulation time 45159832 ps
CPU time 1.86 seconds
Started Jul 06 04:48:29 PM PDT 24
Finished Jul 06 04:48:31 PM PDT 24
Peak memory 208076 kb
Host smart-212f2187-bd31-4f1e-b268-db17d4766113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623108243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2623108243
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.749096553
Short name T295
Test name
Test status
Simulation time 642928505 ps
CPU time 2.48 seconds
Started Jul 06 04:48:20 PM PDT 24
Finished Jul 06 04:48:24 PM PDT 24
Peak memory 214228 kb
Host smart-d65cd553-940e-45af-bdb9-ef5a77e9b9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749096553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.749096553
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.438148772
Short name T301
Test name
Test status
Simulation time 156992729 ps
CPU time 4 seconds
Started Jul 06 04:48:15 PM PDT 24
Finished Jul 06 04:48:19 PM PDT 24
Peak memory 214280 kb
Host smart-07977adf-2cb9-4867-ad7f-7d90ce472b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438148772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.438148772
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1734943320
Short name T839
Test name
Test status
Simulation time 139632643 ps
CPU time 2.69 seconds
Started Jul 06 04:48:18 PM PDT 24
Finished Jul 06 04:48:21 PM PDT 24
Peak memory 214180 kb
Host smart-1f806f05-fa2c-429a-852f-278671683fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734943320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1734943320
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3250481474
Short name T633
Test name
Test status
Simulation time 8640019715 ps
CPU time 28.69 seconds
Started Jul 06 04:48:15 PM PDT 24
Finished Jul 06 04:48:44 PM PDT 24
Peak memory 208460 kb
Host smart-c889e55a-7259-4bb5-b513-be95d445e011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250481474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3250481474
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.576732731
Short name T344
Test name
Test status
Simulation time 5412850917 ps
CPU time 34.65 seconds
Started Jul 06 04:48:18 PM PDT 24
Finished Jul 06 04:48:53 PM PDT 24
Peak memory 208276 kb
Host smart-93442a3b-59cd-4d6e-853d-4d5f6b9c9d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576732731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.576732731
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3882483468
Short name T578
Test name
Test status
Simulation time 458625851 ps
CPU time 3.02 seconds
Started Jul 06 04:48:19 PM PDT 24
Finished Jul 06 04:48:23 PM PDT 24
Peak memory 208868 kb
Host smart-bbe14ce3-0f50-4837-808c-1216e90f5062
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882483468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3882483468
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1517022161
Short name T488
Test name
Test status
Simulation time 35832540 ps
CPU time 2.51 seconds
Started Jul 06 04:48:13 PM PDT 24
Finished Jul 06 04:48:16 PM PDT 24
Peak memory 206824 kb
Host smart-eb9a699e-f4c1-4fe5-bb12-3f16fae76c80
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517022161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1517022161
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.4207252052
Short name T861
Test name
Test status
Simulation time 222784920 ps
CPU time 7.79 seconds
Started Jul 06 04:48:17 PM PDT 24
Finished Jul 06 04:48:25 PM PDT 24
Peak memory 208064 kb
Host smart-6d371128-c51d-4ce7-8931-8279e23f27df
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207252052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.4207252052
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3758949452
Short name T783
Test name
Test status
Simulation time 205810921 ps
CPU time 2.97 seconds
Started Jul 06 04:48:18 PM PDT 24
Finished Jul 06 04:48:26 PM PDT 24
Peak memory 207740 kb
Host smart-0f7a22a7-4622-44b3-b080-b1685de637bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758949452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3758949452
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.292613379
Short name T495
Test name
Test status
Simulation time 226942784 ps
CPU time 3.54 seconds
Started Jul 06 04:48:28 PM PDT 24
Finished Jul 06 04:48:32 PM PDT 24
Peak memory 206684 kb
Host smart-0b9814d6-457a-421f-b65d-94d502255fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292613379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.292613379
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3615978155
Short name T208
Test name
Test status
Simulation time 15868186821 ps
CPU time 363.73 seconds
Started Jul 06 04:48:26 PM PDT 24
Finished Jul 06 04:54:31 PM PDT 24
Peak memory 216872 kb
Host smart-17f06eef-a446-4a1a-a00d-2a0cb0330dda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615978155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3615978155
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3450707912
Short name T464
Test name
Test status
Simulation time 57997453 ps
CPU time 3.51 seconds
Started Jul 06 04:48:21 PM PDT 24
Finished Jul 06 04:48:26 PM PDT 24
Peak memory 207236 kb
Host smart-242f60f9-a560-4aa4-a352-f8c708617a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450707912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3450707912
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.111460812
Short name T147
Test name
Test status
Simulation time 227612629 ps
CPU time 2.79 seconds
Started Jul 06 04:48:19 PM PDT 24
Finished Jul 06 04:48:23 PM PDT 24
Peak memory 210180 kb
Host smart-542242af-ae4a-422b-a590-bcb87304999f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111460812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.111460812
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.4024744967
Short name T98
Test name
Test status
Simulation time 33236349 ps
CPU time 0.71 seconds
Started Jul 06 04:48:22 PM PDT 24
Finished Jul 06 04:48:24 PM PDT 24
Peak memory 205900 kb
Host smart-b945d12b-5a25-4b54-89ca-b5e9743fc1a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024744967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.4024744967
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2825474355
Short name T143
Test name
Test status
Simulation time 218273746 ps
CPU time 6.58 seconds
Started Jul 06 04:48:30 PM PDT 24
Finished Jul 06 04:48:37 PM PDT 24
Peak memory 214440 kb
Host smart-7ea75a24-0fe2-4346-a9e7-ff95b896bb0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2825474355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2825474355
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3391599525
Short name T764
Test name
Test status
Simulation time 119455348 ps
CPU time 5.01 seconds
Started Jul 06 04:48:40 PM PDT 24
Finished Jul 06 04:48:46 PM PDT 24
Peak memory 222496 kb
Host smart-ae7867ff-b518-4971-a3f2-a82062357fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391599525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3391599525
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.215578495
Short name T334
Test name
Test status
Simulation time 189088472 ps
CPU time 2.89 seconds
Started Jul 06 04:48:22 PM PDT 24
Finished Jul 06 04:48:26 PM PDT 24
Peak memory 210004 kb
Host smart-089c023b-c055-41b0-97f5-978f17b2c150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215578495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.215578495
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2936167750
Short name T779
Test name
Test status
Simulation time 175786542 ps
CPU time 3.08 seconds
Started Jul 06 04:48:30 PM PDT 24
Finished Jul 06 04:48:34 PM PDT 24
Peak memory 221100 kb
Host smart-8e391c2d-5f9f-4453-85d9-3b765397f420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936167750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2936167750
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2641071494
Short name T258
Test name
Test status
Simulation time 32311911 ps
CPU time 2.27 seconds
Started Jul 06 04:48:19 PM PDT 24
Finished Jul 06 04:48:22 PM PDT 24
Peak memory 214248 kb
Host smart-142e7acb-f97d-4972-926d-089f118096e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641071494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2641071494
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1457101988
Short name T214
Test name
Test status
Simulation time 53560064 ps
CPU time 3.38 seconds
Started Jul 06 04:48:20 PM PDT 24
Finished Jul 06 04:48:24 PM PDT 24
Peak memory 220140 kb
Host smart-1ab7ae09-187b-4ca3-a33d-d5a70ab8c427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457101988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1457101988
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2667690719
Short name T424
Test name
Test status
Simulation time 237150346 ps
CPU time 3.39 seconds
Started Jul 06 04:48:39 PM PDT 24
Finished Jul 06 04:48:43 PM PDT 24
Peak memory 207404 kb
Host smart-03c29282-8d79-44e4-aae7-3830d2b6e4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667690719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2667690719
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.461562211
Short name T544
Test name
Test status
Simulation time 541264483 ps
CPU time 5.77 seconds
Started Jul 06 04:48:16 PM PDT 24
Finished Jul 06 04:48:22 PM PDT 24
Peak memory 207920 kb
Host smart-5ef71f1d-8ce3-4343-aa8a-13567c2aae87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461562211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.461562211
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3491065150
Short name T567
Test name
Test status
Simulation time 1429199557 ps
CPU time 18.21 seconds
Started Jul 06 04:48:20 PM PDT 24
Finished Jul 06 04:48:39 PM PDT 24
Peak memory 208292 kb
Host smart-42bf76b3-24b2-4c2d-b4a9-88a475faa18a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491065150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3491065150
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.4089381350
Short name T698
Test name
Test status
Simulation time 285215300 ps
CPU time 3.58 seconds
Started Jul 06 04:48:14 PM PDT 24
Finished Jul 06 04:48:18 PM PDT 24
Peak memory 208356 kb
Host smart-e1546dcf-7730-4b17-900a-87067e6f8fd2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089381350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.4089381350
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2926253997
Short name T800
Test name
Test status
Simulation time 97770855 ps
CPU time 2.82 seconds
Started Jul 06 04:48:20 PM PDT 24
Finished Jul 06 04:48:24 PM PDT 24
Peak memory 206736 kb
Host smart-be08bf69-886c-4072-b670-b6332b288463
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926253997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2926253997
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1892142276
Short name T481
Test name
Test status
Simulation time 487634137 ps
CPU time 3.42 seconds
Started Jul 06 04:48:20 PM PDT 24
Finished Jul 06 04:48:25 PM PDT 24
Peak memory 217992 kb
Host smart-c1c50ca9-d8f9-43b5-85d0-119fae7bcbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892142276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1892142276
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2853445228
Short name T793
Test name
Test status
Simulation time 262058457 ps
CPU time 2.96 seconds
Started Jul 06 04:48:45 PM PDT 24
Finished Jul 06 04:48:48 PM PDT 24
Peak memory 206784 kb
Host smart-a2148d4c-3308-4f8e-8b7a-0dfa546086ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853445228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2853445228
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.812752662
Short name T829
Test name
Test status
Simulation time 2788210685 ps
CPU time 53.19 seconds
Started Jul 06 04:48:20 PM PDT 24
Finished Jul 06 04:49:14 PM PDT 24
Peak memory 215408 kb
Host smart-768ac915-f2a7-4fac-859a-b3ba1838bfd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812752662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.812752662
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.4216777051
Short name T458
Test name
Test status
Simulation time 657542561 ps
CPU time 10.01 seconds
Started Jul 06 04:48:26 PM PDT 24
Finished Jul 06 04:48:37 PM PDT 24
Peak memory 219904 kb
Host smart-1c11b6e5-de9c-481c-8fc7-ac80c9d2a86e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216777051 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.4216777051
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3310165098
Short name T184
Test name
Test status
Simulation time 1312459056 ps
CPU time 11.92 seconds
Started Jul 06 04:48:49 PM PDT 24
Finished Jul 06 04:49:02 PM PDT 24
Peak memory 209240 kb
Host smart-4fa42b8d-6a0c-4ab1-b34c-473d12da6e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310165098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3310165098
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2839707304
Short name T608
Test name
Test status
Simulation time 100189891 ps
CPU time 2.55 seconds
Started Jul 06 04:48:22 PM PDT 24
Finished Jul 06 04:48:25 PM PDT 24
Peak memory 210644 kb
Host smart-650a6435-8863-46fd-9739-56e99c527891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839707304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2839707304
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3257997409
Short name T632
Test name
Test status
Simulation time 35665517 ps
CPU time 0.82 seconds
Started Jul 06 04:48:21 PM PDT 24
Finished Jul 06 04:48:23 PM PDT 24
Peak memory 205896 kb
Host smart-5d50d417-c7cc-4427-b121-632383141edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257997409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3257997409
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2929909387
Short name T377
Test name
Test status
Simulation time 105816956 ps
CPU time 5.62 seconds
Started Jul 06 04:48:26 PM PDT 24
Finished Jul 06 04:48:32 PM PDT 24
Peak memory 214232 kb
Host smart-aa569ac1-d429-4328-832c-0b3541175c0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2929909387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2929909387
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1338602319
Short name T902
Test name
Test status
Simulation time 263023968 ps
CPU time 2.87 seconds
Started Jul 06 04:48:25 PM PDT 24
Finished Jul 06 04:48:28 PM PDT 24
Peak memory 208876 kb
Host smart-e120c0b3-591f-4664-b1d6-83e5044bfbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338602319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1338602319
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3747134191
Short name T482
Test name
Test status
Simulation time 74111602 ps
CPU time 3.59 seconds
Started Jul 06 04:48:25 PM PDT 24
Finished Jul 06 04:48:29 PM PDT 24
Peak memory 208356 kb
Host smart-29b65ed4-cf1e-4e82-9e05-d0babb653a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747134191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3747134191
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.486743184
Short name T92
Test name
Test status
Simulation time 86318914 ps
CPU time 4.17 seconds
Started Jul 06 04:48:22 PM PDT 24
Finished Jul 06 04:48:27 PM PDT 24
Peak memory 214328 kb
Host smart-dbda1a75-2b45-4e1b-b179-0e6145aae0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486743184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.486743184
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3269309077
Short name T758
Test name
Test status
Simulation time 288225557 ps
CPU time 3.82 seconds
Started Jul 06 04:48:22 PM PDT 24
Finished Jul 06 04:48:27 PM PDT 24
Peak memory 214336 kb
Host smart-789303b2-b6a6-46c6-8cdc-e76a97a57c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269309077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3269309077
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2808440882
Short name T246
Test name
Test status
Simulation time 203962312 ps
CPU time 3.63 seconds
Started Jul 06 04:48:20 PM PDT 24
Finished Jul 06 04:48:25 PM PDT 24
Peak memory 218060 kb
Host smart-617f7b5e-350f-4332-a616-7a773a7d2c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808440882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2808440882
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1616994614
Short name T663
Test name
Test status
Simulation time 99991065 ps
CPU time 3.29 seconds
Started Jul 06 04:48:52 PM PDT 24
Finished Jul 06 04:48:56 PM PDT 24
Peak memory 207936 kb
Host smart-296e49e2-426f-40c9-86ab-f458a1ed0ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616994614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1616994614
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3736724789
Short name T840
Test name
Test status
Simulation time 107416637 ps
CPU time 2.27 seconds
Started Jul 06 04:48:36 PM PDT 24
Finished Jul 06 04:48:39 PM PDT 24
Peak memory 206812 kb
Host smart-e376351b-27cd-416f-b9c2-980260fa93a1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736724789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3736724789
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3731603581
Short name T841
Test name
Test status
Simulation time 23603472 ps
CPU time 1.92 seconds
Started Jul 06 04:48:21 PM PDT 24
Finished Jul 06 04:48:23 PM PDT 24
Peak memory 208584 kb
Host smart-0b86635d-db93-400a-808a-2a977a0cfbe1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731603581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3731603581
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3003881684
Short name T870
Test name
Test status
Simulation time 124934138 ps
CPU time 3.51 seconds
Started Jul 06 04:48:21 PM PDT 24
Finished Jul 06 04:48:25 PM PDT 24
Peak memory 208180 kb
Host smart-f2aa5aee-8c28-49ba-a5fc-1dd2937b4bc6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003881684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3003881684
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.87439740
Short name T592
Test name
Test status
Simulation time 277041403 ps
CPU time 2.78 seconds
Started Jul 06 04:48:29 PM PDT 24
Finished Jul 06 04:48:32 PM PDT 24
Peak memory 208500 kb
Host smart-9f76f868-a66b-441e-b539-c65b71afbfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87439740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.87439740
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2753426783
Short name T668
Test name
Test status
Simulation time 131442438 ps
CPU time 2.34 seconds
Started Jul 06 04:48:21 PM PDT 24
Finished Jul 06 04:48:24 PM PDT 24
Peak memory 207140 kb
Host smart-677ce048-997a-4a54-9d8a-9b4617874ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753426783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2753426783
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2298520272
Short name T659
Test name
Test status
Simulation time 83319552 ps
CPU time 3.9 seconds
Started Jul 06 04:48:21 PM PDT 24
Finished Jul 06 04:48:26 PM PDT 24
Peak memory 208736 kb
Host smart-236b847e-f7fb-430f-a8e5-17924bca5711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298520272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2298520272
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.4076843644
Short name T853
Test name
Test status
Simulation time 752847065 ps
CPU time 1.94 seconds
Started Jul 06 04:48:32 PM PDT 24
Finished Jul 06 04:48:34 PM PDT 24
Peak memory 209888 kb
Host smart-7c9e3ff0-fc9e-4094-9130-3da873625d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076843644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.4076843644
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3679005818
Short name T415
Test name
Test status
Simulation time 53930662 ps
CPU time 0.94 seconds
Started Jul 06 04:46:53 PM PDT 24
Finished Jul 06 04:46:55 PM PDT 24
Peak memory 205964 kb
Host smart-7f558a7f-0d6c-4c69-a415-8789565b6253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679005818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3679005818
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2509545394
Short name T39
Test name
Test status
Simulation time 571810729 ps
CPU time 6.55 seconds
Started Jul 06 04:46:49 PM PDT 24
Finished Jul 06 04:46:57 PM PDT 24
Peak memory 218388 kb
Host smart-b92e3bc3-a8fc-4cc3-92af-22e25af00d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509545394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2509545394
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1834310627
Short name T588
Test name
Test status
Simulation time 587776263 ps
CPU time 8.89 seconds
Started Jul 06 04:46:51 PM PDT 24
Finished Jul 06 04:47:01 PM PDT 24
Peak memory 214224 kb
Host smart-e498b028-c27c-43e5-8f16-2d4ef04959dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834310627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1834310627
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.4137776261
Short name T540
Test name
Test status
Simulation time 112746407 ps
CPU time 2.57 seconds
Started Jul 06 04:46:48 PM PDT 24
Finished Jul 06 04:46:52 PM PDT 24
Peak memory 214212 kb
Host smart-c39bd1bd-de0f-4830-94c5-055b1080ec00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137776261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.4137776261
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3532716111
Short name T784
Test name
Test status
Simulation time 67609086 ps
CPU time 3.01 seconds
Started Jul 06 04:46:52 PM PDT 24
Finished Jul 06 04:46:56 PM PDT 24
Peak memory 220116 kb
Host smart-2a45c910-8287-4143-8d17-d91fb4fa1d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532716111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3532716111
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.663375529
Short name T343
Test name
Test status
Simulation time 296814837 ps
CPU time 4.63 seconds
Started Jul 06 04:46:53 PM PDT 24
Finished Jul 06 04:46:58 PM PDT 24
Peak memory 208588 kb
Host smart-8a767a16-d216-42d3-b6e5-890aa2c7b0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663375529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.663375529
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1061982822
Short name T10
Test name
Test status
Simulation time 692334315 ps
CPU time 12.62 seconds
Started Jul 06 04:46:51 PM PDT 24
Finished Jul 06 04:47:05 PM PDT 24
Peak memory 237136 kb
Host smart-b0db1906-5f4e-4a4e-879f-db4d2ca5ff61
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061982822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1061982822
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.4156998015
Short name T266
Test name
Test status
Simulation time 72826822 ps
CPU time 3.13 seconds
Started Jul 06 04:46:50 PM PDT 24
Finished Jul 06 04:46:54 PM PDT 24
Peak memory 208640 kb
Host smart-2dfc7136-f61b-41ca-9535-44ff5ccb13b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156998015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.4156998015
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.4200345978
Short name T189
Test name
Test status
Simulation time 32677150 ps
CPU time 2.46 seconds
Started Jul 06 04:46:51 PM PDT 24
Finished Jul 06 04:46:54 PM PDT 24
Peak memory 208460 kb
Host smart-d166c051-b8ec-4f99-b095-d65d2018b11f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200345978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.4200345978
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1695773256
Short name T697
Test name
Test status
Simulation time 293028692 ps
CPU time 3.09 seconds
Started Jul 06 04:46:48 PM PDT 24
Finished Jul 06 04:46:51 PM PDT 24
Peak memory 206804 kb
Host smart-267c9c5b-cb00-4513-8c08-ad0e51bf9536
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695773256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1695773256
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2463180381
Short name T304
Test name
Test status
Simulation time 1039413587 ps
CPU time 8.04 seconds
Started Jul 06 04:46:51 PM PDT 24
Finished Jul 06 04:47:00 PM PDT 24
Peak memory 206836 kb
Host smart-80bd6813-99f4-4ed0-b08c-f812e01111d4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463180381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2463180381
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1939608149
Short name T859
Test name
Test status
Simulation time 345753838 ps
CPU time 4.33 seconds
Started Jul 06 04:46:49 PM PDT 24
Finished Jul 06 04:46:54 PM PDT 24
Peak memory 222288 kb
Host smart-083a0aa9-1830-4978-b90f-96a0c1d387a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939608149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1939608149
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3134872285
Short name T722
Test name
Test status
Simulation time 191414971 ps
CPU time 2.66 seconds
Started Jul 06 04:46:47 PM PDT 24
Finished Jul 06 04:46:50 PM PDT 24
Peak memory 208256 kb
Host smart-0f879ad8-3000-4dfd-b9b9-c3d07d5acdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134872285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3134872285
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3861120643
Short name T781
Test name
Test status
Simulation time 382265798 ps
CPU time 15.74 seconds
Started Jul 06 04:46:46 PM PDT 24
Finished Jul 06 04:47:02 PM PDT 24
Peak memory 222512 kb
Host smart-896093fa-d645-483d-bdea-6e18c10d7230
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861120643 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3861120643
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1496336603
Short name T635
Test name
Test status
Simulation time 37238022 ps
CPU time 2.46 seconds
Started Jul 06 04:46:48 PM PDT 24
Finished Jul 06 04:46:51 PM PDT 24
Peak memory 218356 kb
Host smart-494d35e9-7944-40a1-9b8f-a3cb65cd9182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496336603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1496336603
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1945416003
Short name T515
Test name
Test status
Simulation time 50792654 ps
CPU time 1.5 seconds
Started Jul 06 04:46:53 PM PDT 24
Finished Jul 06 04:46:56 PM PDT 24
Peak memory 209648 kb
Host smart-87e261b0-6185-4d92-9531-3b59f3fd1fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945416003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1945416003
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1371213854
Short name T391
Test name
Test status
Simulation time 33360676 ps
CPU time 0.81 seconds
Started Jul 06 04:48:51 PM PDT 24
Finished Jul 06 04:48:52 PM PDT 24
Peak memory 205892 kb
Host smart-6dc16001-e104-4be9-a508-f9b8450fd45e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371213854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1371213854
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2586704072
Short name T369
Test name
Test status
Simulation time 133430963 ps
CPU time 2.59 seconds
Started Jul 06 04:48:20 PM PDT 24
Finished Jul 06 04:48:24 PM PDT 24
Peak memory 214212 kb
Host smart-c6a04668-62bb-48e5-8fa2-6261546939bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2586704072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2586704072
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.801768084
Short name T413
Test name
Test status
Simulation time 168233882 ps
CPU time 3.39 seconds
Started Jul 06 04:48:40 PM PDT 24
Finished Jul 06 04:48:44 PM PDT 24
Peak memory 209192 kb
Host smart-37100c0c-d839-48be-85e1-b177334dfd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801768084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.801768084
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1262404106
Short name T428
Test name
Test status
Simulation time 92379676 ps
CPU time 3.09 seconds
Started Jul 06 04:48:20 PM PDT 24
Finished Jul 06 04:48:24 PM PDT 24
Peak memory 218224 kb
Host smart-b756c506-35d0-4ec6-aa3f-747e2fa58c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262404106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1262404106
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2006452896
Short name T587
Test name
Test status
Simulation time 517903004 ps
CPU time 7.83 seconds
Started Jul 06 04:48:33 PM PDT 24
Finished Jul 06 04:48:42 PM PDT 24
Peak memory 214200 kb
Host smart-24180137-4455-45c0-ae86-8ab849b665ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006452896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2006452896
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2674352168
Short name T763
Test name
Test status
Simulation time 111522657 ps
CPU time 3.89 seconds
Started Jul 06 04:48:27 PM PDT 24
Finished Jul 06 04:48:32 PM PDT 24
Peak memory 222208 kb
Host smart-08572fb8-c2b1-41f3-a98d-eb3e2ee3e849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674352168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2674352168
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1404300537
Short name T787
Test name
Test status
Simulation time 75953053 ps
CPU time 2.39 seconds
Started Jul 06 04:48:20 PM PDT 24
Finished Jul 06 04:48:23 PM PDT 24
Peak memory 214192 kb
Host smart-6c3376eb-9532-41a8-97dc-73dc7c896ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404300537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1404300537
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1080926528
Short name T265
Test name
Test status
Simulation time 574567054 ps
CPU time 6.56 seconds
Started Jul 06 04:48:25 PM PDT 24
Finished Jul 06 04:48:32 PM PDT 24
Peak memory 214168 kb
Host smart-cf804c62-cf90-4baf-b3f4-1c0d89b4e815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080926528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1080926528
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3024188190
Short name T423
Test name
Test status
Simulation time 62116279 ps
CPU time 2.94 seconds
Started Jul 06 04:48:21 PM PDT 24
Finished Jul 06 04:48:25 PM PDT 24
Peak memory 208452 kb
Host smart-4f1495e1-4c57-42ef-aa60-a72fac8ffa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024188190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3024188190
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3098534304
Short name T527
Test name
Test status
Simulation time 1575357378 ps
CPU time 19.16 seconds
Started Jul 06 04:48:34 PM PDT 24
Finished Jul 06 04:48:54 PM PDT 24
Peak memory 208480 kb
Host smart-134e4b9e-3f68-4ce9-8d8d-37c8b8290f4e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098534304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3098534304
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2249503305
Short name T434
Test name
Test status
Simulation time 332007440 ps
CPU time 8.92 seconds
Started Jul 06 04:48:20 PM PDT 24
Finished Jul 06 04:48:30 PM PDT 24
Peak memory 207960 kb
Host smart-d548952c-26f4-400f-9e2a-856f7562a642
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249503305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2249503305
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2463240299
Short name T44
Test name
Test status
Simulation time 203398332 ps
CPU time 6.58 seconds
Started Jul 06 04:48:24 PM PDT 24
Finished Jul 06 04:48:31 PM PDT 24
Peak memory 208496 kb
Host smart-5e96487f-6b05-49e3-93c9-66ab3dd962e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463240299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2463240299
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2831460044
Short name T33
Test name
Test status
Simulation time 88876912 ps
CPU time 2.9 seconds
Started Jul 06 04:48:26 PM PDT 24
Finished Jul 06 04:48:29 PM PDT 24
Peak memory 210084 kb
Host smart-b4960884-57f6-4c93-b985-a34464dfef06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831460044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2831460044
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.570313411
Short name T895
Test name
Test status
Simulation time 110643323 ps
CPU time 3.09 seconds
Started Jul 06 04:48:22 PM PDT 24
Finished Jul 06 04:48:26 PM PDT 24
Peak memory 208468 kb
Host smart-633d990c-298b-4172-87c7-f8be6a6a3aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570313411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.570313411
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1777230108
Short name T346
Test name
Test status
Simulation time 499302700 ps
CPU time 6.18 seconds
Started Jul 06 04:48:30 PM PDT 24
Finished Jul 06 04:48:36 PM PDT 24
Peak memory 207500 kb
Host smart-efa72c91-0782-4eed-9067-721828442e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777230108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1777230108
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.4088392864
Short name T846
Test name
Test status
Simulation time 1939600004 ps
CPU time 10.86 seconds
Started Jul 06 04:48:40 PM PDT 24
Finished Jul 06 04:48:52 PM PDT 24
Peak memory 210668 kb
Host smart-4d50d109-aef2-4ec5-9c6e-1ea8954e8d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088392864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.4088392864
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3957252385
Short name T425
Test name
Test status
Simulation time 27662992 ps
CPU time 0.84 seconds
Started Jul 06 04:48:53 PM PDT 24
Finished Jul 06 04:48:54 PM PDT 24
Peak memory 205868 kb
Host smart-63fb79cb-c04f-4d52-98db-55947e0bec2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957252385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3957252385
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2155151260
Short name T277
Test name
Test status
Simulation time 181044136 ps
CPU time 4.05 seconds
Started Jul 06 04:48:27 PM PDT 24
Finished Jul 06 04:48:31 PM PDT 24
Peak memory 214328 kb
Host smart-6071c741-a9c3-4318-86b9-7e5a1944d569
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2155151260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2155151260
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3889214433
Short name T416
Test name
Test status
Simulation time 1815970015 ps
CPU time 18.16 seconds
Started Jul 06 04:48:29 PM PDT 24
Finished Jul 06 04:48:47 PM PDT 24
Peak memory 208464 kb
Host smart-e2f97eee-41f4-4b1a-b62a-4e2e38852aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889214433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3889214433
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2452974724
Short name T760
Test name
Test status
Simulation time 311548573 ps
CPU time 2.75 seconds
Started Jul 06 04:48:29 PM PDT 24
Finished Jul 06 04:48:32 PM PDT 24
Peak memory 214228 kb
Host smart-df36e6cf-b450-4935-930c-4b5309462c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452974724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2452974724
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1882980094
Short name T701
Test name
Test status
Simulation time 312576773 ps
CPU time 2.91 seconds
Started Jul 06 04:48:26 PM PDT 24
Finished Jul 06 04:48:30 PM PDT 24
Peak memory 222336 kb
Host smart-02c88a8a-5bd3-4984-8b1a-97b86831021f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882980094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1882980094
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1183858355
Short name T740
Test name
Test status
Simulation time 453609482 ps
CPU time 3.99 seconds
Started Jul 06 04:48:28 PM PDT 24
Finished Jul 06 04:48:32 PM PDT 24
Peak memory 222464 kb
Host smart-9d3c7c9f-082c-4a53-b283-c44db4922f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183858355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1183858355
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3842545863
Short name T218
Test name
Test status
Simulation time 306278006 ps
CPU time 3.55 seconds
Started Jul 06 04:48:26 PM PDT 24
Finished Jul 06 04:48:30 PM PDT 24
Peak memory 209640 kb
Host smart-3de6d721-86f8-4502-9c98-6e9e8c4da410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842545863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3842545863
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1485758760
Short name T119
Test name
Test status
Simulation time 638508333 ps
CPU time 6.12 seconds
Started Jul 06 04:48:30 PM PDT 24
Finished Jul 06 04:48:36 PM PDT 24
Peak memory 208464 kb
Host smart-6dde805b-7c2e-4bc0-998d-4e264455121d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485758760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1485758760
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2250046016
Short name T795
Test name
Test status
Simulation time 143030319 ps
CPU time 3.54 seconds
Started Jul 06 04:48:43 PM PDT 24
Finished Jul 06 04:48:47 PM PDT 24
Peak memory 206716 kb
Host smart-0ed7f5f8-aa43-41dc-aa6c-081b9711c046
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250046016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2250046016
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2904547706
Short name T603
Test name
Test status
Simulation time 404613906 ps
CPU time 6.5 seconds
Started Jul 06 04:48:56 PM PDT 24
Finished Jul 06 04:49:03 PM PDT 24
Peak memory 207896 kb
Host smart-b97a7fb9-3644-42d5-92f5-f05635ecd392
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904547706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2904547706
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1388312024
Short name T72
Test name
Test status
Simulation time 169277973 ps
CPU time 3.52 seconds
Started Jul 06 04:48:28 PM PDT 24
Finished Jul 06 04:48:32 PM PDT 24
Peak memory 218224 kb
Host smart-a89af679-569d-4833-a80a-1d8df8719e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388312024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1388312024
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3992249679
Short name T883
Test name
Test status
Simulation time 381294942 ps
CPU time 3.6 seconds
Started Jul 06 04:48:44 PM PDT 24
Finished Jul 06 04:48:48 PM PDT 24
Peak memory 208752 kb
Host smart-d5dd9bfd-ddae-42ee-bf3a-36a1deae58d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992249679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3992249679
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1969935764
Short name T63
Test name
Test status
Simulation time 888593322 ps
CPU time 26.72 seconds
Started Jul 06 04:48:28 PM PDT 24
Finished Jul 06 04:48:55 PM PDT 24
Peak memory 216156 kb
Host smart-46505a02-9f93-4686-863d-aa4c4262cf8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969935764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1969935764
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3626867454
Short name T556
Test name
Test status
Simulation time 62463111 ps
CPU time 2.77 seconds
Started Jul 06 04:48:43 PM PDT 24
Finished Jul 06 04:48:46 PM PDT 24
Peak memory 207864 kb
Host smart-8bae32a8-5c1c-4f7a-ae94-388de0dad039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626867454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3626867454
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.4029913159
Short name T721
Test name
Test status
Simulation time 35857138 ps
CPU time 2.05 seconds
Started Jul 06 04:48:36 PM PDT 24
Finished Jul 06 04:48:39 PM PDT 24
Peak memory 209732 kb
Host smart-4788d398-8409-43aa-bb74-db65c9968d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029913159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.4029913159
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.4129502101
Short name T589
Test name
Test status
Simulation time 22933797 ps
CPU time 0.72 seconds
Started Jul 06 04:48:33 PM PDT 24
Finished Jul 06 04:48:35 PM PDT 24
Peak memory 205872 kb
Host smart-536bab37-5855-45d0-b8f1-d2f6c6affbd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129502101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.4129502101
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3289092693
Short name T209
Test name
Test status
Simulation time 63316394 ps
CPU time 3.76 seconds
Started Jul 06 04:48:51 PM PDT 24
Finished Jul 06 04:48:55 PM PDT 24
Peak memory 218336 kb
Host smart-af228018-fca0-42b1-8fdd-89c2bd3ed4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289092693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3289092693
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2064955392
Short name T294
Test name
Test status
Simulation time 372981906 ps
CPU time 2.43 seconds
Started Jul 06 04:48:26 PM PDT 24
Finished Jul 06 04:48:30 PM PDT 24
Peak memory 207052 kb
Host smart-79c86643-7d94-49ed-a232-9841870f2f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064955392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2064955392
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2312453112
Short name T298
Test name
Test status
Simulation time 185223836 ps
CPU time 3.11 seconds
Started Jul 06 04:48:35 PM PDT 24
Finished Jul 06 04:48:38 PM PDT 24
Peak memory 214132 kb
Host smart-fb3b3dbe-8841-48bd-8482-f316fd4557e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312453112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2312453112
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1089776891
Short name T342
Test name
Test status
Simulation time 379935194 ps
CPU time 4.77 seconds
Started Jul 06 04:48:29 PM PDT 24
Finished Jul 06 04:48:34 PM PDT 24
Peak memory 210564 kb
Host smart-fc724ba2-1ba0-49a3-b6d4-4072b828636d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089776891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1089776891
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2019098915
Short name T805
Test name
Test status
Simulation time 173128871 ps
CPU time 3.51 seconds
Started Jul 06 04:48:27 PM PDT 24
Finished Jul 06 04:48:31 PM PDT 24
Peak memory 210252 kb
Host smart-f576ab47-6bcc-4f91-992f-488caa98cff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019098915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2019098915
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2355386420
Short name T885
Test name
Test status
Simulation time 151956585 ps
CPU time 4.74 seconds
Started Jul 06 04:48:39 PM PDT 24
Finished Jul 06 04:48:45 PM PDT 24
Peak memory 208184 kb
Host smart-86c0e2a7-1f4a-4394-9acf-9eaa1f71db75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355386420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2355386420
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3463266723
Short name T580
Test name
Test status
Simulation time 175899693 ps
CPU time 2.41 seconds
Started Jul 06 04:48:38 PM PDT 24
Finished Jul 06 04:48:42 PM PDT 24
Peak memory 208092 kb
Host smart-925d48e9-253a-4b58-a361-3dca859a86ad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463266723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3463266723
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.836182811
Short name T314
Test name
Test status
Simulation time 28172032 ps
CPU time 2.14 seconds
Started Jul 06 04:48:29 PM PDT 24
Finished Jul 06 04:48:31 PM PDT 24
Peak memory 208584 kb
Host smart-5e545444-c5c3-4d1f-a6ec-48fd7cc0efc3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836182811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.836182811
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2599166201
Short name T487
Test name
Test status
Simulation time 257331205 ps
CPU time 4 seconds
Started Jul 06 04:48:38 PM PDT 24
Finished Jul 06 04:48:42 PM PDT 24
Peak memory 206848 kb
Host smart-4df15cee-5b91-4dbf-b066-08e39efeba4c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599166201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2599166201
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1850028387
Short name T582
Test name
Test status
Simulation time 35077152 ps
CPU time 2.28 seconds
Started Jul 06 04:48:35 PM PDT 24
Finished Jul 06 04:48:38 PM PDT 24
Peak memory 210092 kb
Host smart-270773a0-2d90-4b90-956e-a404262229c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850028387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1850028387
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.568350256
Short name T420
Test name
Test status
Simulation time 504031905 ps
CPU time 3.43 seconds
Started Jul 06 04:48:40 PM PDT 24
Finished Jul 06 04:48:44 PM PDT 24
Peak memory 208188 kb
Host smart-d14e5fd8-c21c-4f70-af4a-ec9f7c06e7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568350256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.568350256
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.4132741437
Short name T745
Test name
Test status
Simulation time 3511704034 ps
CPU time 32.09 seconds
Started Jul 06 04:48:45 PM PDT 24
Finished Jul 06 04:49:18 PM PDT 24
Peak memory 216424 kb
Host smart-6527ffce-3b40-4d90-8276-54ff90f45837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132741437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.4132741437
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.19059142
Short name T893
Test name
Test status
Simulation time 413915698 ps
CPU time 5.44 seconds
Started Jul 06 04:48:38 PM PDT 24
Finished Jul 06 04:48:44 PM PDT 24
Peak memory 208288 kb
Host smart-ac9351e7-e9f3-4383-af38-a7a81375c11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19059142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.19059142
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1620619396
Short name T786
Test name
Test status
Simulation time 132993915 ps
CPU time 1.9 seconds
Started Jul 06 04:48:42 PM PDT 24
Finished Jul 06 04:48:44 PM PDT 24
Peak memory 210072 kb
Host smart-4c054471-2aab-493b-abee-c4ea6429a9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620619396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1620619396
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.937099187
Short name T636
Test name
Test status
Simulation time 31860329 ps
CPU time 0.82 seconds
Started Jul 06 04:48:47 PM PDT 24
Finished Jul 06 04:48:49 PM PDT 24
Peak memory 205904 kb
Host smart-265cc073-c758-4148-a6d9-516d5507f2a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937099187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.937099187
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1248774691
Short name T366
Test name
Test status
Simulation time 61433425 ps
CPU time 4.66 seconds
Started Jul 06 04:48:34 PM PDT 24
Finished Jul 06 04:48:39 PM PDT 24
Peak memory 214228 kb
Host smart-b3ab6e4a-d7f9-467a-9dab-cfc58323d554
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248774691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1248774691
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.243667156
Short name T771
Test name
Test status
Simulation time 121526093 ps
CPU time 4.89 seconds
Started Jul 06 04:48:36 PM PDT 24
Finished Jul 06 04:48:42 PM PDT 24
Peak memory 222516 kb
Host smart-43348a76-c531-453a-a9dc-a412216ee96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243667156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.243667156
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3862692785
Short name T879
Test name
Test status
Simulation time 125200744 ps
CPU time 1.77 seconds
Started Jul 06 04:48:38 PM PDT 24
Finished Jul 06 04:48:40 PM PDT 24
Peak memory 207160 kb
Host smart-f34e637b-27fb-4fc8-a735-79950fd33bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862692785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3862692785
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.4199550309
Short name T85
Test name
Test status
Simulation time 369241592 ps
CPU time 4.26 seconds
Started Jul 06 04:48:36 PM PDT 24
Finished Jul 06 04:48:40 PM PDT 24
Peak memory 222468 kb
Host smart-7d210ceb-7255-4151-83e5-b463ff801f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199550309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.4199550309
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2527202548
Short name T911
Test name
Test status
Simulation time 149750867 ps
CPU time 2.71 seconds
Started Jul 06 04:48:34 PM PDT 24
Finished Jul 06 04:48:37 PM PDT 24
Peak memory 222040 kb
Host smart-1d64f837-dcd8-4a10-a17c-9cc002b8d1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527202548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2527202548
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.74321282
Short name T207
Test name
Test status
Simulation time 179682625 ps
CPU time 3.21 seconds
Started Jul 06 04:48:47 PM PDT 24
Finished Jul 06 04:48:51 PM PDT 24
Peak memory 214180 kb
Host smart-597951da-7f07-438b-822a-5628b62b5824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74321282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.74321282
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.633940646
Short name T536
Test name
Test status
Simulation time 726362867 ps
CPU time 6.17 seconds
Started Jul 06 04:48:47 PM PDT 24
Finished Jul 06 04:48:54 PM PDT 24
Peak memory 218272 kb
Host smart-83d98400-5041-4a45-966c-115dfcd656d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633940646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.633940646
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3224081228
Short name T900
Test name
Test status
Simulation time 1066753959 ps
CPU time 3.96 seconds
Started Jul 06 04:48:52 PM PDT 24
Finished Jul 06 04:48:56 PM PDT 24
Peak memory 206820 kb
Host smart-4d0ffe81-b82b-4edd-9a52-ef9e73b95153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224081228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3224081228
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3224227791
Short name T347
Test name
Test status
Simulation time 2675548260 ps
CPU time 6.76 seconds
Started Jul 06 04:48:56 PM PDT 24
Finished Jul 06 04:49:03 PM PDT 24
Peak memory 208004 kb
Host smart-61969f1d-bc73-4c3a-b4cf-08707596329c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224227791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3224227791
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3497518275
Short name T476
Test name
Test status
Simulation time 48945565 ps
CPU time 2.12 seconds
Started Jul 06 04:48:36 PM PDT 24
Finished Jul 06 04:48:39 PM PDT 24
Peak memory 208508 kb
Host smart-c2ca6c96-da34-465a-b8cd-956d34429961
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497518275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3497518275
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1590307145
Short name T335
Test name
Test status
Simulation time 106155428 ps
CPU time 3.06 seconds
Started Jul 06 04:48:34 PM PDT 24
Finished Jul 06 04:48:37 PM PDT 24
Peak memory 208792 kb
Host smart-24242cca-c0a9-4454-835e-e24145d2eba2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590307145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1590307145
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1052812159
Short name T757
Test name
Test status
Simulation time 214596994 ps
CPU time 4.77 seconds
Started Jul 06 04:48:47 PM PDT 24
Finished Jul 06 04:48:53 PM PDT 24
Peak memory 218224 kb
Host smart-91a637ec-b1dd-4e9b-acdb-17ea116e8f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052812159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1052812159
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2035413344
Short name T80
Test name
Test status
Simulation time 338426332 ps
CPU time 3.32 seconds
Started Jul 06 04:48:36 PM PDT 24
Finished Jul 06 04:48:39 PM PDT 24
Peak memory 208456 kb
Host smart-4e9c40d8-8a7b-4e56-8268-03b7893ce7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035413344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2035413344
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.4112574342
Short name T212
Test name
Test status
Simulation time 3837616079 ps
CPU time 21.49 seconds
Started Jul 06 04:48:52 PM PDT 24
Finished Jul 06 04:49:15 PM PDT 24
Peak memory 214908 kb
Host smart-47acad6a-90fa-4658-9e3f-a68daa07e178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112574342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.4112574342
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2411267293
Short name T785
Test name
Test status
Simulation time 177249471 ps
CPU time 4.24 seconds
Started Jul 06 04:48:35 PM PDT 24
Finished Jul 06 04:48:39 PM PDT 24
Peak memory 209864 kb
Host smart-71f728e4-e965-48b9-9b68-fc2a858b9288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411267293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2411267293
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2808728046
Short name T625
Test name
Test status
Simulation time 56418218 ps
CPU time 2.96 seconds
Started Jul 06 04:48:41 PM PDT 24
Finished Jul 06 04:48:45 PM PDT 24
Peak memory 210356 kb
Host smart-0bd37018-1a6f-4df8-a15f-180ffc5cc6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808728046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2808728046
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.769217810
Short name T827
Test name
Test status
Simulation time 15603797 ps
CPU time 0.78 seconds
Started Jul 06 04:48:35 PM PDT 24
Finished Jul 06 04:48:36 PM PDT 24
Peak memory 205820 kb
Host smart-f0475078-151c-4404-849e-890662d7cd45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769217810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.769217810
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.392384504
Short name T29
Test name
Test status
Simulation time 111851869 ps
CPU time 3.76 seconds
Started Jul 06 04:48:51 PM PDT 24
Finished Jul 06 04:48:55 PM PDT 24
Peak memory 222632 kb
Host smart-06aff58b-ac59-475f-bbc0-28d26ea1fc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392384504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.392384504
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2175342571
Short name T673
Test name
Test status
Simulation time 72710719 ps
CPU time 2.15 seconds
Started Jul 06 04:48:39 PM PDT 24
Finished Jul 06 04:48:42 PM PDT 24
Peak memory 207304 kb
Host smart-0e9d6653-1646-4980-8beb-8221f8b19d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175342571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2175342571
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2412515670
Short name T276
Test name
Test status
Simulation time 177730636 ps
CPU time 7.06 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:48:56 PM PDT 24
Peak memory 220556 kb
Host smart-aa040860-77dc-4e7e-9052-796f13c4fac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412515670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2412515670
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2980755198
Short name T224
Test name
Test status
Simulation time 143727065 ps
CPU time 4.03 seconds
Started Jul 06 04:48:36 PM PDT 24
Finished Jul 06 04:48:41 PM PDT 24
Peak memory 219064 kb
Host smart-790c23fe-856c-4dee-afbf-e07962cc3a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980755198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2980755198
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3468165863
Short name T876
Test name
Test status
Simulation time 153580500 ps
CPU time 2.23 seconds
Started Jul 06 04:48:38 PM PDT 24
Finished Jul 06 04:48:41 PM PDT 24
Peak memory 215068 kb
Host smart-2c247aa5-5ec3-4177-9764-f83d3b8f0d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468165863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3468165863
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2246181349
Short name T245
Test name
Test status
Simulation time 780560085 ps
CPU time 6.52 seconds
Started Jul 06 04:48:39 PM PDT 24
Finished Jul 06 04:48:47 PM PDT 24
Peak memory 218132 kb
Host smart-dbbfbb57-f48f-4d24-8f09-1922d75104cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246181349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2246181349
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2684294555
Short name T601
Test name
Test status
Simulation time 720534832 ps
CPU time 7.23 seconds
Started Jul 06 04:48:39 PM PDT 24
Finished Jul 06 04:48:47 PM PDT 24
Peak memory 208592 kb
Host smart-94341adc-817d-4b03-9680-4e226e05e115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684294555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2684294555
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2634999054
Short name T817
Test name
Test status
Simulation time 116728346 ps
CPU time 4.75 seconds
Started Jul 06 04:48:42 PM PDT 24
Finished Jul 06 04:48:47 PM PDT 24
Peak memory 206808 kb
Host smart-75a299bd-9be8-4f71-9483-6d131b92dfcd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634999054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2634999054
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.936278989
Short name T194
Test name
Test status
Simulation time 523354857 ps
CPU time 17.44 seconds
Started Jul 06 04:48:35 PM PDT 24
Finished Jul 06 04:48:52 PM PDT 24
Peak memory 208516 kb
Host smart-9743aea6-78a7-4317-9f0d-68c71f3d1988
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936278989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.936278989
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1031121505
Short name T554
Test name
Test status
Simulation time 2808289095 ps
CPU time 5.46 seconds
Started Jul 06 04:48:45 PM PDT 24
Finished Jul 06 04:48:50 PM PDT 24
Peak memory 206876 kb
Host smart-abb6b9f4-1b20-458e-9277-517af58921f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031121505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1031121505
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3992517168
Short name T484
Test name
Test status
Simulation time 146607234 ps
CPU time 1.98 seconds
Started Jul 06 04:48:36 PM PDT 24
Finished Jul 06 04:48:39 PM PDT 24
Peak memory 207500 kb
Host smart-e282d431-5b75-46bb-9d9c-d784335e3f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992517168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3992517168
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2260081242
Short name T725
Test name
Test status
Simulation time 99023199 ps
CPU time 2.15 seconds
Started Jul 06 04:48:33 PM PDT 24
Finished Jul 06 04:48:36 PM PDT 24
Peak memory 206804 kb
Host smart-e9ab96a3-43a3-4d71-b1f9-a71f8f49d044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260081242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2260081242
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.446560190
Short name T221
Test name
Test status
Simulation time 985747703 ps
CPU time 33.11 seconds
Started Jul 06 04:48:50 PM PDT 24
Finished Jul 06 04:49:24 PM PDT 24
Peak memory 222388 kb
Host smart-eedabfab-ca9e-4247-9959-f1356bd81443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446560190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.446560190
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1285214137
Short name T890
Test name
Test status
Simulation time 571053686 ps
CPU time 13.69 seconds
Started Jul 06 04:48:37 PM PDT 24
Finished Jul 06 04:48:51 PM PDT 24
Peak memory 222800 kb
Host smart-f272923c-4bdf-4585-b69c-08b1f3bd8344
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285214137 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1285214137
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3110006121
Short name T501
Test name
Test status
Simulation time 159986385 ps
CPU time 3.88 seconds
Started Jul 06 04:48:38 PM PDT 24
Finished Jul 06 04:48:42 PM PDT 24
Peak memory 208980 kb
Host smart-cb2d6e16-8509-4fa7-bf4f-c4523253cfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110006121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3110006121
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.4139529120
Short name T886
Test name
Test status
Simulation time 86340430 ps
CPU time 1.53 seconds
Started Jul 06 04:48:58 PM PDT 24
Finished Jul 06 04:49:00 PM PDT 24
Peak memory 209440 kb
Host smart-6440a302-8340-461f-b672-76952d35f584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139529120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.4139529120
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.903698939
Short name T899
Test name
Test status
Simulation time 17436766 ps
CPU time 0.78 seconds
Started Jul 06 04:48:58 PM PDT 24
Finished Jul 06 04:48:59 PM PDT 24
Peak memory 205852 kb
Host smart-7ee0f72b-03b3-4211-8595-658135547111
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903698939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.903698939
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3888175058
Short name T286
Test name
Test status
Simulation time 151137520 ps
CPU time 3.06 seconds
Started Jul 06 04:48:52 PM PDT 24
Finished Jul 06 04:48:55 PM PDT 24
Peak memory 214888 kb
Host smart-f03b43b6-12ec-48a7-af34-8b14e3afd249
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888175058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3888175058
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2141024547
Short name T782
Test name
Test status
Simulation time 446848926 ps
CPU time 2.07 seconds
Started Jul 06 04:48:39 PM PDT 24
Finished Jul 06 04:48:42 PM PDT 24
Peak memory 217820 kb
Host smart-fc3fdb42-295e-49df-a439-2d8ab42c9c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141024547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2141024547
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.4038533463
Short name T454
Test name
Test status
Simulation time 187781529 ps
CPU time 2.22 seconds
Started Jul 06 04:48:39 PM PDT 24
Finished Jul 06 04:48:42 PM PDT 24
Peak memory 208172 kb
Host smart-2e5dac60-a4e0-4d20-8880-29a74a75bd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038533463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.4038533463
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3428386876
Short name T83
Test name
Test status
Simulation time 28653860 ps
CPU time 1.82 seconds
Started Jul 06 04:48:38 PM PDT 24
Finished Jul 06 04:48:41 PM PDT 24
Peak memory 214208 kb
Host smart-fc9b7976-7832-4fe7-9cff-c7c463edaa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428386876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3428386876
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.728354424
Short name T529
Test name
Test status
Simulation time 161124841 ps
CPU time 3.08 seconds
Started Jul 06 04:48:34 PM PDT 24
Finished Jul 06 04:48:38 PM PDT 24
Peak memory 205556 kb
Host smart-627535ee-a3b5-40f2-9e3f-d3873a90b344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728354424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.728354424
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.38497924
Short name T4
Test name
Test status
Simulation time 107923671 ps
CPU time 3.26 seconds
Started Jul 06 04:48:47 PM PDT 24
Finished Jul 06 04:48:51 PM PDT 24
Peak memory 209556 kb
Host smart-20f834b5-6b62-4d25-a3f7-1ca2e0457f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38497924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.38497924
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2270878582
Short name T906
Test name
Test status
Simulation time 607907202 ps
CPU time 7.99 seconds
Started Jul 06 04:48:39 PM PDT 24
Finished Jul 06 04:48:48 PM PDT 24
Peak memory 209284 kb
Host smart-9be3eb10-0544-476a-b417-a272cf8798e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270878582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2270878582
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2741194598
Short name T461
Test name
Test status
Simulation time 171916203 ps
CPU time 5.12 seconds
Started Jul 06 04:48:39 PM PDT 24
Finished Jul 06 04:48:45 PM PDT 24
Peak memory 208188 kb
Host smart-3fbd97e3-949a-4c12-9c9e-07300a02134e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741194598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2741194598
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2515467331
Short name T664
Test name
Test status
Simulation time 145827724 ps
CPU time 3.91 seconds
Started Jul 06 04:48:38 PM PDT 24
Finished Jul 06 04:48:42 PM PDT 24
Peak memory 208996 kb
Host smart-4eb80bfa-6d8d-41b2-acfe-9c702e787f78
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515467331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2515467331
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.217771499
Short name T684
Test name
Test status
Simulation time 90077630 ps
CPU time 3.95 seconds
Started Jul 06 04:48:45 PM PDT 24
Finished Jul 06 04:48:49 PM PDT 24
Peak memory 208544 kb
Host smart-30f9e599-b6d5-41c2-803c-322547ae4d16
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217771499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.217771499
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1161641716
Short name T326
Test name
Test status
Simulation time 652966008 ps
CPU time 16.65 seconds
Started Jul 06 04:48:33 PM PDT 24
Finished Jul 06 04:48:50 PM PDT 24
Peak memory 207976 kb
Host smart-25c0e8b0-ee1c-47a3-be66-d4243ab7d1b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161641716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1161641716
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3918621095
Short name T880
Test name
Test status
Simulation time 101704734 ps
CPU time 1.92 seconds
Started Jul 06 04:48:36 PM PDT 24
Finished Jul 06 04:48:38 PM PDT 24
Peak memory 208600 kb
Host smart-36bb9252-18e0-4c73-a162-c186b51b2826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918621095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3918621095
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.4183473440
Short name T670
Test name
Test status
Simulation time 159853473 ps
CPU time 4.52 seconds
Started Jul 06 04:48:39 PM PDT 24
Finished Jul 06 04:48:44 PM PDT 24
Peak memory 207796 kb
Host smart-a7047e19-b074-4353-a8bd-afa07ceda9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183473440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.4183473440
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3734758812
Short name T444
Test name
Test status
Simulation time 831281003 ps
CPU time 14.68 seconds
Started Jul 06 04:48:36 PM PDT 24
Finished Jul 06 04:48:51 PM PDT 24
Peak memory 222484 kb
Host smart-8195b07b-8cb0-4c3b-bf4d-73581c663063
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734758812 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3734758812
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3308810387
Short name T188
Test name
Test status
Simulation time 1508095029 ps
CPU time 6.82 seconds
Started Jul 06 04:48:38 PM PDT 24
Finished Jul 06 04:48:46 PM PDT 24
Peak memory 208984 kb
Host smart-0db3c85a-d85e-4b21-b18c-96ddd263b87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308810387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3308810387
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2517569112
Short name T751
Test name
Test status
Simulation time 154041414 ps
CPU time 1.53 seconds
Started Jul 06 04:48:36 PM PDT 24
Finished Jul 06 04:48:38 PM PDT 24
Peak memory 209904 kb
Host smart-a0300fd9-66ce-42d7-bb1b-b17d0b6845da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517569112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2517569112
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2399344446
Short name T623
Test name
Test status
Simulation time 13476011 ps
CPU time 0.78 seconds
Started Jul 06 04:48:39 PM PDT 24
Finished Jul 06 04:48:40 PM PDT 24
Peak memory 205888 kb
Host smart-65d3a822-8bd3-4b23-aad4-4683ed170d4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399344446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2399344446
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2316974132
Short name T816
Test name
Test status
Simulation time 49232159 ps
CPU time 3.55 seconds
Started Jul 06 04:48:39 PM PDT 24
Finished Jul 06 04:48:43 PM PDT 24
Peak memory 214336 kb
Host smart-44a1687f-15aa-4432-94b0-a4319c1c9f2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2316974132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2316974132
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1602597675
Short name T468
Test name
Test status
Simulation time 33811768 ps
CPU time 2.14 seconds
Started Jul 06 04:48:52 PM PDT 24
Finished Jul 06 04:48:54 PM PDT 24
Peak memory 208932 kb
Host smart-1e18331f-5866-4131-8e8d-91e999491bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602597675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1602597675
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.239206423
Short name T834
Test name
Test status
Simulation time 188748103 ps
CPU time 4.33 seconds
Started Jul 06 04:48:41 PM PDT 24
Finished Jul 06 04:48:46 PM PDT 24
Peak memory 210096 kb
Host smart-44e2929d-4f6f-40ed-b508-c5fc3c8a2c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239206423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.239206423
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3212853566
Short name T735
Test name
Test status
Simulation time 33654730 ps
CPU time 1.93 seconds
Started Jul 06 04:48:43 PM PDT 24
Finished Jul 06 04:48:45 PM PDT 24
Peak memory 214124 kb
Host smart-f8d4036a-739c-4b88-8b8c-7af0abeac331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212853566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3212853566
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.605941793
Short name T798
Test name
Test status
Simulation time 48440220 ps
CPU time 2.81 seconds
Started Jul 06 04:48:38 PM PDT 24
Finished Jul 06 04:48:42 PM PDT 24
Peak memory 215140 kb
Host smart-80464e12-ae2f-4e7f-bb56-4b9cd64d2a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605941793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.605941793
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1826283640
Short name T896
Test name
Test status
Simulation time 1582770401 ps
CPU time 12.21 seconds
Started Jul 06 04:48:38 PM PDT 24
Finished Jul 06 04:48:52 PM PDT 24
Peak memory 214340 kb
Host smart-c2626b04-1bdd-4df4-a5d9-e74b3678ea45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826283640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1826283640
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1336608189
Short name T775
Test name
Test status
Simulation time 102627055 ps
CPU time 3.94 seconds
Started Jul 06 04:48:47 PM PDT 24
Finished Jul 06 04:48:52 PM PDT 24
Peak memory 206788 kb
Host smart-9ef7bcd5-1118-4781-a74b-0aef45a94be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336608189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1336608189
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.884223489
Short name T139
Test name
Test status
Simulation time 92605800 ps
CPU time 3.07 seconds
Started Jul 06 04:48:42 PM PDT 24
Finished Jul 06 04:48:46 PM PDT 24
Peak memory 207292 kb
Host smart-9f7ff2bb-e4f8-431e-9e1b-c053d02d17d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884223489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.884223489
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.796505395
Short name T463
Test name
Test status
Simulation time 181828894 ps
CPU time 4.6 seconds
Started Jul 06 04:48:44 PM PDT 24
Finished Jul 06 04:48:49 PM PDT 24
Peak memory 208980 kb
Host smart-0f564a9a-4e96-4b4e-8e5e-c90ab94f310f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796505395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.796505395
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2229262342
Short name T446
Test name
Test status
Simulation time 318274021 ps
CPU time 4.04 seconds
Started Jul 06 04:48:39 PM PDT 24
Finished Jul 06 04:48:44 PM PDT 24
Peak memory 208736 kb
Host smart-38f51289-5de8-423f-ab01-950d9732357a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229262342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2229262342
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.4242783585
Short name T494
Test name
Test status
Simulation time 1452978469 ps
CPU time 5.51 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:48:55 PM PDT 24
Peak memory 208284 kb
Host smart-c6256e82-15a7-4fef-bea5-edd59b0b3e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242783585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.4242783585
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3230128679
Short name T138
Test name
Test status
Simulation time 108849807 ps
CPU time 3.62 seconds
Started Jul 06 04:48:44 PM PDT 24
Finished Jul 06 04:48:49 PM PDT 24
Peak memory 208264 kb
Host smart-52fb59b5-bee5-4a19-be62-8f09bd180c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230128679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3230128679
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.822757619
Short name T281
Test name
Test status
Simulation time 375014145 ps
CPU time 12.3 seconds
Started Jul 06 04:49:00 PM PDT 24
Finished Jul 06 04:49:13 PM PDT 24
Peak memory 222456 kb
Host smart-16d4a11e-fe6e-4bc7-8ff0-8e1a829a14a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822757619 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.822757619
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2007522866
Short name T881
Test name
Test status
Simulation time 1967153634 ps
CPU time 70.77 seconds
Started Jul 06 04:48:42 PM PDT 24
Finished Jul 06 04:49:54 PM PDT 24
Peak memory 214608 kb
Host smart-dabb1dec-261b-4b98-9a4a-2eb339684b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007522866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2007522866
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1866703415
Short name T164
Test name
Test status
Simulation time 277607115 ps
CPU time 2.16 seconds
Started Jul 06 04:48:40 PM PDT 24
Finished Jul 06 04:48:43 PM PDT 24
Peak memory 210524 kb
Host smart-3e54b131-6615-47c3-ac28-9f3cfa532cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866703415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1866703415
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.243657748
Short name T526
Test name
Test status
Simulation time 25388457 ps
CPU time 0.86 seconds
Started Jul 06 04:48:43 PM PDT 24
Finished Jul 06 04:48:44 PM PDT 24
Peak memory 205860 kb
Host smart-f7dba1cf-e9e6-444b-b118-f23881c19c18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243657748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.243657748
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1418337125
Short name T251
Test name
Test status
Simulation time 558959539 ps
CPU time 11.12 seconds
Started Jul 06 04:48:56 PM PDT 24
Finished Jul 06 04:49:08 PM PDT 24
Peak memory 214288 kb
Host smart-713c3cde-23a6-4e66-8f96-7437284143e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1418337125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1418337125
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2274324012
Short name T24
Test name
Test status
Simulation time 198368640 ps
CPU time 5.28 seconds
Started Jul 06 04:48:47 PM PDT 24
Finished Jul 06 04:48:54 PM PDT 24
Peak memory 221308 kb
Host smart-8148181d-7659-4ca2-a789-6da6a6a4d26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274324012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2274324012
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3546346160
Short name T642
Test name
Test status
Simulation time 52780813 ps
CPU time 1.99 seconds
Started Jul 06 04:48:51 PM PDT 24
Finished Jul 06 04:48:54 PM PDT 24
Peak memory 207400 kb
Host smart-28b372a3-6bc8-4503-a598-5af5b7668e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546346160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3546346160
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1028856962
Short name T316
Test name
Test status
Simulation time 1015063044 ps
CPU time 21.45 seconds
Started Jul 06 04:48:40 PM PDT 24
Finished Jul 06 04:49:02 PM PDT 24
Peak memory 214212 kb
Host smart-b87f7784-e8f5-48ef-8712-65d070ee5bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028856962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1028856962
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1760885176
Short name T271
Test name
Test status
Simulation time 113560872 ps
CPU time 4.36 seconds
Started Jul 06 04:48:42 PM PDT 24
Finished Jul 06 04:48:47 PM PDT 24
Peak memory 211684 kb
Host smart-6b615cfd-b148-4a33-b3da-b10eb98fd3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760885176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1760885176
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.663410943
Short name T830
Test name
Test status
Simulation time 506250196 ps
CPU time 5.97 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:48:55 PM PDT 24
Peak memory 214296 kb
Host smart-1a70707e-8163-44d8-8c5c-3cff9cddee9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663410943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.663410943
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2406955556
Short name T337
Test name
Test status
Simulation time 554983796 ps
CPU time 5.59 seconds
Started Jul 06 04:48:49 PM PDT 24
Finished Jul 06 04:48:56 PM PDT 24
Peak memory 209008 kb
Host smart-81467eb0-d8b5-4851-8d64-6840329695ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406955556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2406955556
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1150964508
Short name T404
Test name
Test status
Simulation time 123136592 ps
CPU time 2.44 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:48:51 PM PDT 24
Peak memory 206764 kb
Host smart-4f019c43-39db-4c92-8258-290e599bb3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150964508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1150964508
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2215316639
Short name T916
Test name
Test status
Simulation time 899192589 ps
CPU time 7.24 seconds
Started Jul 06 04:48:39 PM PDT 24
Finished Jul 06 04:48:47 PM PDT 24
Peak memory 207896 kb
Host smart-7ac32e48-af36-4f5c-b55d-02314d3984ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215316639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2215316639
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2984516319
Short name T910
Test name
Test status
Simulation time 674511628 ps
CPU time 7.67 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:48:57 PM PDT 24
Peak memory 207012 kb
Host smart-a811c521-3605-4da5-9047-a22169194058
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984516319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2984516319
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2863020701
Short name T516
Test name
Test status
Simulation time 69431045 ps
CPU time 3.29 seconds
Started Jul 06 04:48:40 PM PDT 24
Finished Jul 06 04:48:44 PM PDT 24
Peak memory 207964 kb
Host smart-48e5181a-f632-4951-b4d0-ba0b34a9ba5a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863020701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2863020701
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3403097002
Short name T794
Test name
Test status
Simulation time 79613339 ps
CPU time 2.73 seconds
Started Jul 06 04:48:37 PM PDT 24
Finished Jul 06 04:48:40 PM PDT 24
Peak memory 209292 kb
Host smart-f34213cb-36db-4fd8-a7d0-bb2a59dfd1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403097002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3403097002
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3491302820
Short name T801
Test name
Test status
Simulation time 621023110 ps
CPU time 11.92 seconds
Started Jul 06 04:48:44 PM PDT 24
Finished Jul 06 04:48:57 PM PDT 24
Peak memory 208424 kb
Host smart-a46c443d-ad58-4400-8650-8e9bbe509b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491302820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3491302820
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2648014983
Short name T643
Test name
Test status
Simulation time 106429426 ps
CPU time 4.86 seconds
Started Jul 06 04:48:41 PM PDT 24
Finished Jul 06 04:48:46 PM PDT 24
Peak memory 215104 kb
Host smart-e1dbeaa0-4bb0-485a-9e3f-22e23444e22e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648014983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2648014983
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.278406831
Short name T250
Test name
Test status
Simulation time 3764346791 ps
CPU time 17.17 seconds
Started Jul 06 04:48:50 PM PDT 24
Finished Jul 06 04:49:07 PM PDT 24
Peak memory 222608 kb
Host smart-e6fa0461-dc7a-4399-a43d-9cf28e527c00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278406831 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.278406831
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4155867327
Short name T264
Test name
Test status
Simulation time 472136040 ps
CPU time 5.56 seconds
Started Jul 06 04:48:51 PM PDT 24
Finished Jul 06 04:48:57 PM PDT 24
Peak memory 209556 kb
Host smart-ac1456dc-9048-4ec0-9d4c-41c6b68e3831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155867327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4155867327
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.772928842
Short name T613
Test name
Test status
Simulation time 158351429 ps
CPU time 1.63 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:48:51 PM PDT 24
Peak memory 209800 kb
Host smart-94c171bd-7fa2-4f68-b91d-8d01daf4cfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772928842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.772928842
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1603085185
Short name T614
Test name
Test status
Simulation time 22766620 ps
CPU time 0.79 seconds
Started Jul 06 04:48:51 PM PDT 24
Finished Jul 06 04:48:52 PM PDT 24
Peak memory 205908 kb
Host smart-2f94646f-e824-4ea0-91f8-ab28b4e65dfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603085185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1603085185
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3267633589
Short name T901
Test name
Test status
Simulation time 55367204 ps
CPU time 2.88 seconds
Started Jul 06 04:48:45 PM PDT 24
Finished Jul 06 04:48:48 PM PDT 24
Peak memory 209140 kb
Host smart-84763c92-a03e-459a-92c6-408513a52f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267633589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3267633589
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.446730021
Short name T259
Test name
Test status
Simulation time 122230492 ps
CPU time 3.76 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:48:53 PM PDT 24
Peak memory 222112 kb
Host smart-680cb770-7518-4137-b97d-6a9b082e90df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446730021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.446730021
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3545066924
Short name T306
Test name
Test status
Simulation time 321596191 ps
CPU time 3.41 seconds
Started Jul 06 04:48:38 PM PDT 24
Finished Jul 06 04:48:42 PM PDT 24
Peak memory 220080 kb
Host smart-c3f20832-853d-42bb-87a6-bb3f3a253f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545066924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3545066924
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2827967775
Short name T383
Test name
Test status
Simulation time 182800295 ps
CPU time 5.29 seconds
Started Jul 06 04:48:40 PM PDT 24
Finished Jul 06 04:48:46 PM PDT 24
Peak memory 209856 kb
Host smart-ed6207d9-bfb5-4ad2-831a-a78e1a27025b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827967775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2827967775
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2764034426
Short name T253
Test name
Test status
Simulation time 43629344 ps
CPU time 2.63 seconds
Started Jul 06 04:48:43 PM PDT 24
Finished Jul 06 04:48:46 PM PDT 24
Peak memory 208704 kb
Host smart-be6762b5-c749-45d9-8030-ae53f028b7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764034426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2764034426
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1482443168
Short name T707
Test name
Test status
Simulation time 147037322 ps
CPU time 3.76 seconds
Started Jul 06 04:48:47 PM PDT 24
Finished Jul 06 04:48:52 PM PDT 24
Peak memory 208704 kb
Host smart-fc1e2e7b-2ee5-40ce-a4ae-3d7545682995
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482443168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1482443168
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.87558566
Short name T524
Test name
Test status
Simulation time 21453414 ps
CPU time 1.87 seconds
Started Jul 06 04:48:55 PM PDT 24
Finished Jul 06 04:48:58 PM PDT 24
Peak memory 207272 kb
Host smart-d4912866-cff0-4c2e-907c-ef2a55d74482
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87558566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.87558566
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3063016147
Short name T268
Test name
Test status
Simulation time 637529946 ps
CPU time 16.71 seconds
Started Jul 06 04:48:47 PM PDT 24
Finished Jul 06 04:49:05 PM PDT 24
Peak memory 208296 kb
Host smart-464db022-2c9c-4e9a-8baa-e81c6b00ba79
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063016147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3063016147
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1015708730
Short name T557
Test name
Test status
Simulation time 192432075 ps
CPU time 4.65 seconds
Started Jul 06 04:48:50 PM PDT 24
Finished Jul 06 04:48:55 PM PDT 24
Peak memory 209104 kb
Host smart-bf38828c-9352-416d-b457-2bcb80cadfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015708730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1015708730
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3691801840
Short name T710
Test name
Test status
Simulation time 36589734 ps
CPU time 2.4 seconds
Started Jul 06 04:48:40 PM PDT 24
Finished Jul 06 04:48:43 PM PDT 24
Peak memory 208212 kb
Host smart-5f11a7f8-6ba7-4db7-88df-fc1b48dfa953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691801840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3691801840
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.57910973
Short name T639
Test name
Test status
Simulation time 572962532 ps
CPU time 5.03 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:48:54 PM PDT 24
Peak memory 207452 kb
Host smart-bfb160e6-7127-4c54-8eb4-2943a9a1d02d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57910973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.57910973
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3436443364
Short name T170
Test name
Test status
Simulation time 604558385 ps
CPU time 24.49 seconds
Started Jul 06 04:48:47 PM PDT 24
Finished Jul 06 04:49:12 PM PDT 24
Peak memory 222936 kb
Host smart-2e10b779-052e-4df4-badf-8ab5b99c703c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436443364 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3436443364
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2014068275
Short name T797
Test name
Test status
Simulation time 413983455 ps
CPU time 4.61 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:48:54 PM PDT 24
Peak memory 208296 kb
Host smart-fd572002-0704-4420-9b6d-698b0319896d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014068275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2014068275
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2088275527
Short name T912
Test name
Test status
Simulation time 752994129 ps
CPU time 3.29 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:48:53 PM PDT 24
Peak memory 209848 kb
Host smart-e51ce036-9d2f-437a-b8f0-c8be9070ed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088275527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2088275527
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1788257157
Short name T513
Test name
Test status
Simulation time 13422347 ps
CPU time 0.76 seconds
Started Jul 06 04:48:52 PM PDT 24
Finished Jul 06 04:48:54 PM PDT 24
Peak memory 205868 kb
Host smart-2ab897cd-eefb-4af6-9ec5-5393a02428bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788257157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1788257157
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1030942024
Short name T124
Test name
Test status
Simulation time 210596298 ps
CPU time 2.56 seconds
Started Jul 06 04:49:02 PM PDT 24
Finished Jul 06 04:49:05 PM PDT 24
Peak memory 214216 kb
Host smart-ac5a8277-33e7-48e1-a970-44b1f1d58af7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1030942024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1030942024
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1806227863
Short name T776
Test name
Test status
Simulation time 81583485 ps
CPU time 3.63 seconds
Started Jul 06 04:49:01 PM PDT 24
Finished Jul 06 04:49:05 PM PDT 24
Peak memory 214204 kb
Host smart-bdd64bad-cda8-4c58-9220-4985e4d70ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806227863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1806227863
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.716804630
Short name T237
Test name
Test status
Simulation time 238233351 ps
CPU time 4.78 seconds
Started Jul 06 04:48:53 PM PDT 24
Finished Jul 06 04:48:58 PM PDT 24
Peak memory 222248 kb
Host smart-94ddb1de-9320-459d-a1bb-c81c198e897c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716804630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.716804630
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.4157564264
Short name T628
Test name
Test status
Simulation time 445164200 ps
CPU time 13.25 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:49:02 PM PDT 24
Peak memory 222368 kb
Host smart-68e3d90c-2663-4fcb-9549-996753fab4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157564264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.4157564264
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2100940349
Short name T844
Test name
Test status
Simulation time 330539680 ps
CPU time 5.98 seconds
Started Jul 06 04:49:00 PM PDT 24
Finished Jul 06 04:49:06 PM PDT 24
Peak memory 208976 kb
Host smart-fa62714e-1bad-4f60-b36b-12b79fbed868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100940349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2100940349
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3968279841
Short name T469
Test name
Test status
Simulation time 1118766152 ps
CPU time 3.87 seconds
Started Jul 06 04:48:47 PM PDT 24
Finished Jul 06 04:48:52 PM PDT 24
Peak memory 207964 kb
Host smart-30d10ea2-bb75-46e4-8478-158dc4fcbe16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968279841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3968279841
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.4188282547
Short name T882
Test name
Test status
Simulation time 196491093 ps
CPU time 5.66 seconds
Started Jul 06 04:49:01 PM PDT 24
Finished Jul 06 04:49:07 PM PDT 24
Peak memory 208532 kb
Host smart-6f062aa6-3951-456d-ad9f-c387b3982389
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188282547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4188282547
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3787814819
Short name T485
Test name
Test status
Simulation time 142310380 ps
CPU time 3.72 seconds
Started Jul 06 04:48:49 PM PDT 24
Finished Jul 06 04:48:53 PM PDT 24
Peak memory 208636 kb
Host smart-68341556-313c-4771-afc9-f6888eb43943
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787814819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3787814819
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3218107229
Short name T568
Test name
Test status
Simulation time 120256078 ps
CPU time 4.06 seconds
Started Jul 06 04:48:46 PM PDT 24
Finished Jul 06 04:48:51 PM PDT 24
Peak memory 208512 kb
Host smart-7b08dec6-a53c-4280-ada2-7a06194e5a48
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218107229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3218107229
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2351595748
Short name T14
Test name
Test status
Simulation time 59324123 ps
CPU time 1.77 seconds
Started Jul 06 04:48:47 PM PDT 24
Finished Jul 06 04:48:49 PM PDT 24
Peak memory 207356 kb
Host smart-ae11a8c6-97e7-45c0-b42c-c888c0ac9d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351595748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2351595748
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.4146515816
Short name T743
Test name
Test status
Simulation time 106074700 ps
CPU time 2.53 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:48:51 PM PDT 24
Peak memory 207012 kb
Host smart-cf3c0aa1-e9ba-488a-8081-958a2b469772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146515816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.4146515816
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.4001328050
Short name T195
Test name
Test status
Simulation time 418225006 ps
CPU time 13.42 seconds
Started Jul 06 04:48:54 PM PDT 24
Finished Jul 06 04:49:08 PM PDT 24
Peak memory 209360 kb
Host smart-babf746c-3d69-417f-8fd8-3a5ae62ebd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001328050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.4001328050
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2883225829
Short name T479
Test name
Test status
Simulation time 46056683 ps
CPU time 1.99 seconds
Started Jul 06 04:49:00 PM PDT 24
Finished Jul 06 04:49:02 PM PDT 24
Peak memory 209736 kb
Host smart-9a5694f4-5898-4bf5-881b-ae49a39a2e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883225829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2883225829
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2635470969
Short name T421
Test name
Test status
Simulation time 13834478 ps
CPU time 0.93 seconds
Started Jul 06 04:46:53 PM PDT 24
Finished Jul 06 04:46:54 PM PDT 24
Peak memory 205964 kb
Host smart-9a9e10b3-ecbd-48dd-9374-f0f8560d08c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635470969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2635470969
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1946839519
Short name T126
Test name
Test status
Simulation time 386239333 ps
CPU time 6.14 seconds
Started Jul 06 04:46:58 PM PDT 24
Finished Jul 06 04:47:04 PM PDT 24
Peak memory 214832 kb
Host smart-88a02b52-8c95-407c-84ea-d8c43b289129
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1946839519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1946839519
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1036713913
Short name T842
Test name
Test status
Simulation time 183494846 ps
CPU time 3.23 seconds
Started Jul 06 04:46:51 PM PDT 24
Finished Jul 06 04:46:55 PM PDT 24
Peak memory 208532 kb
Host smart-0cc1b31c-bf9f-4b10-a747-7c082e386981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036713913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1036713913
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.227118270
Short name T445
Test name
Test status
Simulation time 112921718 ps
CPU time 3.7 seconds
Started Jul 06 04:46:51 PM PDT 24
Finished Jul 06 04:46:55 PM PDT 24
Peak memory 209948 kb
Host smart-cf579ab3-dccf-40e1-a37e-55935ce20455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227118270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.227118270
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.936134234
Short name T431
Test name
Test status
Simulation time 142201033 ps
CPU time 5.05 seconds
Started Jul 06 04:46:47 PM PDT 24
Finished Jul 06 04:46:52 PM PDT 24
Peak memory 214200 kb
Host smart-98505eea-6b18-472e-84c2-e4b609a12e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936134234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.936134234
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3910507326
Short name T679
Test name
Test status
Simulation time 46743091 ps
CPU time 3.38 seconds
Started Jul 06 04:46:50 PM PDT 24
Finished Jul 06 04:46:54 PM PDT 24
Peak memory 222484 kb
Host smart-62e5a35c-cb50-4f4c-bd68-13b9724c1c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910507326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3910507326
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.927337949
Short name T718
Test name
Test status
Simulation time 605395372 ps
CPU time 4.6 seconds
Started Jul 06 04:46:52 PM PDT 24
Finished Jul 06 04:46:57 PM PDT 24
Peak memory 222372 kb
Host smart-cdd7eb3e-f399-4e0c-a476-39db5e0f7f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927337949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.927337949
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3356466043
Short name T824
Test name
Test status
Simulation time 76046057 ps
CPU time 4.21 seconds
Started Jul 06 04:46:53 PM PDT 24
Finished Jul 06 04:46:58 PM PDT 24
Peak memory 209780 kb
Host smart-ec09a097-5677-48a6-ac46-ac730393b3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356466043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3356466043
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.4073794926
Short name T345
Test name
Test status
Simulation time 172904154 ps
CPU time 6.49 seconds
Started Jul 06 04:46:50 PM PDT 24
Finished Jul 06 04:46:57 PM PDT 24
Peak memory 206688 kb
Host smart-cebb0791-9f5e-4ce1-9b00-bb24306c3a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073794926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.4073794926
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2302192766
Short name T493
Test name
Test status
Simulation time 72062978 ps
CPU time 3.48 seconds
Started Jul 06 04:46:49 PM PDT 24
Finished Jul 06 04:46:53 PM PDT 24
Peak memory 208636 kb
Host smart-0b8de82e-238b-442c-97d6-a3641c7be72c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302192766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2302192766
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2555547517
Short name T442
Test name
Test status
Simulation time 1803783817 ps
CPU time 13.41 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:47:09 PM PDT 24
Peak memory 208832 kb
Host smart-b67c5b4f-e0d5-41bb-9cde-c5e480669de5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555547517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2555547517
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1802230728
Short name T739
Test name
Test status
Simulation time 121060074 ps
CPU time 2.3 seconds
Started Jul 06 04:46:49 PM PDT 24
Finished Jul 06 04:46:52 PM PDT 24
Peak memory 206784 kb
Host smart-f0c0ea38-3363-42c9-86d1-5a9aebf07e1a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802230728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1802230728
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1113323027
Short name T647
Test name
Test status
Simulation time 234035395 ps
CPU time 2.99 seconds
Started Jul 06 04:46:48 PM PDT 24
Finished Jul 06 04:46:52 PM PDT 24
Peak memory 218116 kb
Host smart-a3dec5f9-95fb-4ec4-a91e-5a424bf5f6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113323027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1113323027
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3535296420
Short name T486
Test name
Test status
Simulation time 141437562 ps
CPU time 4.05 seconds
Started Jul 06 04:46:48 PM PDT 24
Finished Jul 06 04:46:53 PM PDT 24
Peak memory 206700 kb
Host smart-797fc4f2-e2fa-4ba5-8b76-e4b5345d6dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535296420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3535296420
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1687259917
Short name T47
Test name
Test status
Simulation time 1286987728 ps
CPU time 17.88 seconds
Started Jul 06 04:46:49 PM PDT 24
Finished Jul 06 04:47:07 PM PDT 24
Peak memory 216668 kb
Host smart-143354d1-1f03-4ff2-85dc-074efac6c3d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687259917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1687259917
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3907219150
Short name T871
Test name
Test status
Simulation time 954588527 ps
CPU time 7.24 seconds
Started Jul 06 04:46:49 PM PDT 24
Finished Jul 06 04:46:57 PM PDT 24
Peak memory 209328 kb
Host smart-32cfb2f3-a05f-447e-b9bb-b80914176864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907219150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3907219150
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2632055853
Short name T156
Test name
Test status
Simulation time 83758594 ps
CPU time 2.69 seconds
Started Jul 06 04:46:51 PM PDT 24
Finished Jul 06 04:46:54 PM PDT 24
Peak memory 210624 kb
Host smart-614086e8-4e79-4e20-a7ca-0c9bfec21236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632055853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2632055853
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.545380513
Short name T851
Test name
Test status
Simulation time 12155548 ps
CPU time 0.86 seconds
Started Jul 06 04:46:53 PM PDT 24
Finished Jul 06 04:46:56 PM PDT 24
Peak memory 205896 kb
Host smart-b2cb98b5-571d-43d4-b076-46f00ec5b0df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545380513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.545380513
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1611213053
Short name T637
Test name
Test status
Simulation time 303429424 ps
CPU time 5.99 seconds
Started Jul 06 04:46:52 PM PDT 24
Finished Jul 06 04:46:59 PM PDT 24
Peak memory 218144 kb
Host smart-f03c468a-b6ae-433f-8c3e-b2847a0e7e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611213053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1611213053
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.4100580409
Short name T789
Test name
Test status
Simulation time 198151225 ps
CPU time 3.07 seconds
Started Jul 06 04:46:50 PM PDT 24
Finished Jul 06 04:46:54 PM PDT 24
Peak memory 210300 kb
Host smart-f72218b8-2887-4190-a304-c0fc9f107c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100580409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.4100580409
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3925052237
Short name T302
Test name
Test status
Simulation time 515865347 ps
CPU time 6.09 seconds
Started Jul 06 04:46:50 PM PDT 24
Finished Jul 06 04:46:57 PM PDT 24
Peak memory 215476 kb
Host smart-9b5a5bdb-e5fc-4a66-b7b4-9161928dc1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925052237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3925052237
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1999934760
Short name T448
Test name
Test status
Simulation time 190708150 ps
CPU time 2.5 seconds
Started Jul 06 04:46:48 PM PDT 24
Finished Jul 06 04:46:52 PM PDT 24
Peak memory 220000 kb
Host smart-674107a0-021c-4430-bbe4-5a1ccf3688a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999934760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1999934760
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.32984513
Short name T283
Test name
Test status
Simulation time 131703680 ps
CPU time 5.5 seconds
Started Jul 06 04:46:49 PM PDT 24
Finished Jul 06 04:46:55 PM PDT 24
Peak memory 218128 kb
Host smart-c4185d8d-1498-498b-8e83-5510f395b734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32984513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.32984513
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.168817889
Short name T599
Test name
Test status
Simulation time 520284893 ps
CPU time 15.18 seconds
Started Jul 06 04:46:51 PM PDT 24
Finished Jul 06 04:47:07 PM PDT 24
Peak memory 207988 kb
Host smart-de3994b8-3c89-4433-827d-8f23c03e2612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168817889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.168817889
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1840819517
Short name T443
Test name
Test status
Simulation time 240919995 ps
CPU time 3.02 seconds
Started Jul 06 04:46:58 PM PDT 24
Finished Jul 06 04:47:01 PM PDT 24
Peak memory 206880 kb
Host smart-a1ff861d-e911-4d8c-ad87-ffc60ea806af
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840819517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1840819517
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.684155051
Short name T607
Test name
Test status
Simulation time 688962283 ps
CPU time 15.51 seconds
Started Jul 06 04:46:49 PM PDT 24
Finished Jul 06 04:47:05 PM PDT 24
Peak memory 207820 kb
Host smart-8f3c00f5-cf99-433c-963b-e509f1f48889
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684155051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.684155051
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.880897550
Short name T318
Test name
Test status
Simulation time 111126430 ps
CPU time 1.81 seconds
Started Jul 06 04:46:51 PM PDT 24
Finished Jul 06 04:46:54 PM PDT 24
Peak memory 207028 kb
Host smart-69f55608-fb08-4c25-82ed-121f3f442654
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880897550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.880897550
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1436522526
Short name T323
Test name
Test status
Simulation time 386032867 ps
CPU time 4.42 seconds
Started Jul 06 04:46:53 PM PDT 24
Finished Jul 06 04:46:58 PM PDT 24
Peak memory 208228 kb
Host smart-ba4f53c1-a588-4017-bb04-9c779e68bc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436522526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1436522526
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.584348619
Short name T412
Test name
Test status
Simulation time 31690446 ps
CPU time 2.13 seconds
Started Jul 06 04:46:58 PM PDT 24
Finished Jul 06 04:47:00 PM PDT 24
Peak memory 206388 kb
Host smart-71c29d45-4989-453e-b57f-671c48ed944f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584348619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.584348619
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3657576479
Short name T822
Test name
Test status
Simulation time 1478722213 ps
CPU time 13.97 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:47:10 PM PDT 24
Peak memory 220400 kb
Host smart-02d559dd-b0fd-4d85-a341-b494486c7e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657576479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3657576479
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3092939222
Short name T116
Test name
Test status
Simulation time 368958189 ps
CPU time 13.54 seconds
Started Jul 06 04:46:55 PM PDT 24
Finished Jul 06 04:47:10 PM PDT 24
Peak memory 222596 kb
Host smart-e7ae4f33-19f5-409a-8d0d-c290eaac0e01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092939222 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3092939222
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.500524318
Short name T571
Test name
Test status
Simulation time 836252925 ps
CPU time 8.94 seconds
Started Jul 06 04:46:52 PM PDT 24
Finished Jul 06 04:47:02 PM PDT 24
Peak memory 207408 kb
Host smart-423e7937-cc9a-4689-8339-0fe371b7e34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500524318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.500524318
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2642101485
Short name T441
Test name
Test status
Simulation time 835782370 ps
CPU time 4.76 seconds
Started Jul 06 04:46:56 PM PDT 24
Finished Jul 06 04:47:02 PM PDT 24
Peak memory 210912 kb
Host smart-3b6c5a1a-12fc-42b2-9196-b4819624db4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642101485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2642101485
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2546076172
Short name T465
Test name
Test status
Simulation time 47094059 ps
CPU time 0.75 seconds
Started Jul 06 04:46:53 PM PDT 24
Finished Jul 06 04:46:56 PM PDT 24
Peak memory 205844 kb
Host smart-e999a815-78e4-42a6-875e-e362d4162c55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546076172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2546076172
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.861445824
Short name T378
Test name
Test status
Simulation time 113393836 ps
CPU time 2.46 seconds
Started Jul 06 04:46:53 PM PDT 24
Finished Jul 06 04:46:58 PM PDT 24
Peak memory 214228 kb
Host smart-0d0385e5-4de9-47c7-95d4-b0b215a47c87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=861445824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.861445824
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2859984412
Short name T736
Test name
Test status
Simulation time 182831697 ps
CPU time 3.5 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:46:59 PM PDT 24
Peak memory 221332 kb
Host smart-dafca7cf-9ec2-43e3-b915-65d81e42cf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859984412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2859984412
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.262893313
Short name T73
Test name
Test status
Simulation time 120582043 ps
CPU time 4.62 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:47:01 PM PDT 24
Peak memory 209640 kb
Host smart-85d05f5c-b672-4399-a44a-9bafcbbc6eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262893313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.262893313
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2538755931
Short name T236
Test name
Test status
Simulation time 124149594 ps
CPU time 3.72 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:46:59 PM PDT 24
Peak memory 214692 kb
Host smart-d52f1ed9-4139-4564-abb9-d65c8e4a9bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538755931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2538755931
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3614102131
Short name T273
Test name
Test status
Simulation time 2328049831 ps
CPU time 4.93 seconds
Started Jul 06 04:46:55 PM PDT 24
Finished Jul 06 04:47:01 PM PDT 24
Peak memory 214224 kb
Host smart-876daf61-a21c-46d0-9e05-6c1a7456357d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614102131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3614102131
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1006028005
Short name T803
Test name
Test status
Simulation time 150549895 ps
CPU time 2.55 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:46:58 PM PDT 24
Peak memory 215516 kb
Host smart-07edbf04-9c9c-4e4f-91f6-fad2544f0974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006028005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1006028005
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.4017856739
Short name T510
Test name
Test status
Simulation time 819077930 ps
CPU time 5.71 seconds
Started Jul 06 04:46:53 PM PDT 24
Finished Jul 06 04:46:59 PM PDT 24
Peak memory 206632 kb
Host smart-f5cbe40f-11a2-416b-b3c5-5c398a01030e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017856739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.4017856739
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2048343990
Short name T741
Test name
Test status
Simulation time 396120607 ps
CPU time 3.51 seconds
Started Jul 06 04:46:55 PM PDT 24
Finished Jul 06 04:47:00 PM PDT 24
Peak memory 208292 kb
Host smart-348d8f92-00af-4cbc-b286-d43d60322c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048343990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2048343990
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1991136692
Short name T321
Test name
Test status
Simulation time 36899240 ps
CPU time 2.48 seconds
Started Jul 06 04:46:55 PM PDT 24
Finished Jul 06 04:46:59 PM PDT 24
Peak memory 206964 kb
Host smart-5ebf83ae-c1d2-4427-b11d-ab6c1e8eb426
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991136692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1991136692
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1252953204
Short name T229
Test name
Test status
Simulation time 24648404 ps
CPU time 1.79 seconds
Started Jul 06 04:46:53 PM PDT 24
Finished Jul 06 04:46:57 PM PDT 24
Peak memory 206864 kb
Host smart-cdb5c5c4-ac4c-45ed-a749-68f860e0ef61
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252953204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1252953204
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1845699319
Short name T279
Test name
Test status
Simulation time 159361268 ps
CPU time 4.92 seconds
Started Jul 06 04:47:09 PM PDT 24
Finished Jul 06 04:47:14 PM PDT 24
Peak memory 208048 kb
Host smart-fe204bb5-9ef4-4ac0-9a62-7552ce232cf6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845699319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1845699319
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1202453397
Short name T815
Test name
Test status
Simulation time 856261914 ps
CPU time 4.66 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:47:01 PM PDT 24
Peak memory 214208 kb
Host smart-e09b2e06-3c9f-48f1-93f1-c46af7be84b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202453397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1202453397
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2567399041
Short name T744
Test name
Test status
Simulation time 133682867 ps
CPU time 2.42 seconds
Started Jul 06 04:46:53 PM PDT 24
Finished Jul 06 04:46:58 PM PDT 24
Peak memory 206772 kb
Host smart-dc1bd137-f2a9-4e1c-9a34-8efe6c4eec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567399041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2567399041
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2114010562
Short name T706
Test name
Test status
Simulation time 417453877 ps
CPU time 20.37 seconds
Started Jul 06 04:46:55 PM PDT 24
Finished Jul 06 04:47:17 PM PDT 24
Peak memory 216516 kb
Host smart-4c424748-48af-4133-a9c3-1d4adf366f41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114010562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2114010562
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2886770474
Short name T375
Test name
Test status
Simulation time 2377228676 ps
CPU time 50.84 seconds
Started Jul 06 04:46:55 PM PDT 24
Finished Jul 06 04:47:47 PM PDT 24
Peak memory 209556 kb
Host smart-2753c2ea-ca7a-45a3-ac0c-68b74a3ce59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886770474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2886770474
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2490840358
Short name T569
Test name
Test status
Simulation time 136273007 ps
CPU time 2.62 seconds
Started Jul 06 04:46:53 PM PDT 24
Finished Jul 06 04:46:56 PM PDT 24
Peak memory 209760 kb
Host smart-5cd59420-f7d9-4580-a0e7-b1512659a586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490840358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2490840358
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1368611277
Short name T397
Test name
Test status
Simulation time 37254917 ps
CPU time 0.78 seconds
Started Jul 06 04:47:02 PM PDT 24
Finished Jul 06 04:47:03 PM PDT 24
Peak memory 205792 kb
Host smart-4a031520-93bb-4100-8dfd-2a0c02691504
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368611277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1368611277
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.740679255
Short name T241
Test name
Test status
Simulation time 253129454 ps
CPU time 4.22 seconds
Started Jul 06 04:47:04 PM PDT 24
Finished Jul 06 04:47:09 PM PDT 24
Peak memory 218656 kb
Host smart-05888944-e8c0-4a9f-aee3-7ceec9967960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740679255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.740679255
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3489225607
Short name T504
Test name
Test status
Simulation time 643505400 ps
CPU time 18.64 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:47:15 PM PDT 24
Peak memory 209020 kb
Host smart-03773d57-b599-4227-a17e-89f68f8db343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489225607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3489225607
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2918870621
Short name T3
Test name
Test status
Simulation time 782091933 ps
CPU time 7.75 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:47:03 PM PDT 24
Peak memory 222348 kb
Host smart-93873398-b9a7-4888-8ac2-7a8e1ce0242f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918870621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2918870621
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3384971692
Short name T634
Test name
Test status
Simulation time 174624969 ps
CPU time 3.14 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:46:59 PM PDT 24
Peak memory 214128 kb
Host smart-e8348ba0-da42-4d95-af95-def4f4ad932e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384971692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3384971692
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1831331627
Short name T572
Test name
Test status
Simulation time 190684663 ps
CPU time 2.61 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:46:58 PM PDT 24
Peak memory 218612 kb
Host smart-5ba456ba-869a-40cb-802f-3168508b31ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831331627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1831331627
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2734049770
Short name T852
Test name
Test status
Simulation time 935154099 ps
CPU time 9.48 seconds
Started Jul 06 04:46:55 PM PDT 24
Finished Jul 06 04:47:06 PM PDT 24
Peak memory 209660 kb
Host smart-f78b3c49-8b77-485b-a15e-a62bfd39f0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734049770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2734049770
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.4115447368
Short name T141
Test name
Test status
Simulation time 316778630 ps
CPU time 11.98 seconds
Started Jul 06 04:46:55 PM PDT 24
Finished Jul 06 04:47:09 PM PDT 24
Peak memory 206748 kb
Host smart-f1ee8335-b823-4996-b3de-0eb7b7b66258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115447368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.4115447368
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1510161120
Short name T804
Test name
Test status
Simulation time 58925306 ps
CPU time 2.89 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:46:59 PM PDT 24
Peak memory 207032 kb
Host smart-cf233b81-6e75-402f-bdf9-a9e15eabbf2a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510161120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1510161120
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2356405077
Short name T606
Test name
Test status
Simulation time 80054390 ps
CPU time 3.53 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:46:59 PM PDT 24
Peak memory 208636 kb
Host smart-ecd0525f-c8cc-41fa-b991-6868b00085c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356405077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2356405077
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1557742153
Short name T714
Test name
Test status
Simulation time 256977015 ps
CPU time 4.09 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:47:00 PM PDT 24
Peak memory 206788 kb
Host smart-efe8c762-fe0d-490c-9f1b-8baa52c1ce90
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557742153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1557742153
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3674505006
Short name T498
Test name
Test status
Simulation time 132092335 ps
CPU time 4.42 seconds
Started Jul 06 04:47:05 PM PDT 24
Finished Jul 06 04:47:11 PM PDT 24
Peak memory 216140 kb
Host smart-8c1b03c0-b7b6-4fb3-bdae-20615592358c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674505006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3674505006
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2597861670
Short name T626
Test name
Test status
Simulation time 219079722 ps
CPU time 2.58 seconds
Started Jul 06 04:46:56 PM PDT 24
Finished Jul 06 04:46:59 PM PDT 24
Peak memory 206664 kb
Host smart-3808630b-d71a-47ba-87c4-b45727f517fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597861670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2597861670
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2431888384
Short name T756
Test name
Test status
Simulation time 2602381009 ps
CPU time 18.61 seconds
Started Jul 06 04:47:04 PM PDT 24
Finished Jul 06 04:47:24 PM PDT 24
Peak memory 215560 kb
Host smart-0fda2f81-fc2b-472e-865e-97af5a992381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431888384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2431888384
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2968032162
Short name T418
Test name
Test status
Simulation time 9535347215 ps
CPU time 65.46 seconds
Started Jul 06 04:46:54 PM PDT 24
Finished Jul 06 04:48:02 PM PDT 24
Peak memory 218696 kb
Host smart-fa724680-b2e5-40d8-9e5b-e7cf537038ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968032162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2968032162
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.434262571
Short name T438
Test name
Test status
Simulation time 107107427 ps
CPU time 3.45 seconds
Started Jul 06 04:47:02 PM PDT 24
Finished Jul 06 04:47:06 PM PDT 24
Peak memory 210400 kb
Host smart-6a978ad4-f2c7-4f02-a47c-1878c1b5bde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434262571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.434262571
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3203347614
Short name T392
Test name
Test status
Simulation time 16786098 ps
CPU time 0.76 seconds
Started Jul 06 04:47:07 PM PDT 24
Finished Jul 06 04:47:09 PM PDT 24
Peak memory 205956 kb
Host smart-49cd05ce-d50d-44b1-882b-fe005ab305d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203347614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3203347614
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3207205863
Short name T767
Test name
Test status
Simulation time 396133439 ps
CPU time 6.72 seconds
Started Jul 06 04:46:59 PM PDT 24
Finished Jul 06 04:47:06 PM PDT 24
Peak memory 215172 kb
Host smart-801e63bf-a739-4e7d-ba9d-2613c47a888c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3207205863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3207205863
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3927044453
Short name T761
Test name
Test status
Simulation time 120387024 ps
CPU time 5.51 seconds
Started Jul 06 04:47:02 PM PDT 24
Finished Jul 06 04:47:08 PM PDT 24
Peak memory 221052 kb
Host smart-49af198e-f5d3-439b-9505-4e9ce9c07c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927044453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3927044453
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3562186335
Short name T908
Test name
Test status
Simulation time 167356720 ps
CPU time 3.22 seconds
Started Jul 06 04:46:59 PM PDT 24
Finished Jul 06 04:47:02 PM PDT 24
Peak memory 209956 kb
Host smart-509e6d8e-eab8-44e9-9276-4fc12f3dd15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562186335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3562186335
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2893088945
Short name T349
Test name
Test status
Simulation time 96986953 ps
CPU time 3.7 seconds
Started Jul 06 04:47:00 PM PDT 24
Finished Jul 06 04:47:04 PM PDT 24
Peak memory 214192 kb
Host smart-9a28c673-812b-4562-b777-bf1e8c31c3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893088945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2893088945
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.433471785
Short name T630
Test name
Test status
Simulation time 117372299 ps
CPU time 3.34 seconds
Started Jul 06 04:47:02 PM PDT 24
Finished Jul 06 04:47:06 PM PDT 24
Peak memory 214472 kb
Host smart-f4faabee-51f8-40fa-b079-59f902dbd245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433471785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.433471785
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2442731312
Short name T53
Test name
Test status
Simulation time 181707411 ps
CPU time 3.7 seconds
Started Jul 06 04:47:02 PM PDT 24
Finished Jul 06 04:47:06 PM PDT 24
Peak memory 210156 kb
Host smart-9f42bdd3-c3f3-4341-aefe-b04d22e46489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442731312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2442731312
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2700452833
Short name T352
Test name
Test status
Simulation time 666908404 ps
CPU time 2.87 seconds
Started Jul 06 04:47:01 PM PDT 24
Finished Jul 06 04:47:04 PM PDT 24
Peak memory 208112 kb
Host smart-5abda54c-1ca6-40aa-aa15-38c0ece644ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700452833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2700452833
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.310332291
Short name T500
Test name
Test status
Simulation time 431441877 ps
CPU time 5.44 seconds
Started Jul 06 04:47:03 PM PDT 24
Finished Jul 06 04:47:09 PM PDT 24
Peak memory 207844 kb
Host smart-d2b6abbc-c87b-46da-8f77-4750d2a07dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310332291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.310332291
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2640063274
Short name T542
Test name
Test status
Simulation time 1683932644 ps
CPU time 4.78 seconds
Started Jul 06 04:47:06 PM PDT 24
Finished Jul 06 04:47:12 PM PDT 24
Peak memory 208096 kb
Host smart-070e1587-5ecf-45c7-a059-5f99e9e9a1d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640063274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2640063274
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2307445402
Short name T699
Test name
Test status
Simulation time 69604494 ps
CPU time 2.73 seconds
Started Jul 06 04:47:04 PM PDT 24
Finished Jul 06 04:47:07 PM PDT 24
Peak memory 208580 kb
Host smart-d856a2f7-1bc0-4350-9d1d-de2a6b4d3515
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307445402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2307445402
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.505100782
Short name T681
Test name
Test status
Simulation time 200630999 ps
CPU time 2.69 seconds
Started Jul 06 04:47:02 PM PDT 24
Finished Jul 06 04:47:05 PM PDT 24
Peak memory 208500 kb
Host smart-8899fc23-5300-4d35-87dc-80eb8cbf6104
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505100782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.505100782
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.612541143
Short name T538
Test name
Test status
Simulation time 189323541 ps
CPU time 2.12 seconds
Started Jul 06 04:47:06 PM PDT 24
Finished Jul 06 04:47:09 PM PDT 24
Peak memory 209004 kb
Host smart-1417ac75-73d0-4511-a3f6-7c3adfc2609b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612541143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.612541143
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2357831734
Short name T537
Test name
Test status
Simulation time 253634620 ps
CPU time 2.33 seconds
Started Jul 06 04:47:04 PM PDT 24
Finished Jul 06 04:47:06 PM PDT 24
Peak memory 206016 kb
Host smart-bf6f9e62-9368-4f9e-b2e0-86de36f840ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357831734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2357831734
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1696450601
Short name T66
Test name
Test status
Simulation time 6514066814 ps
CPU time 39.42 seconds
Started Jul 06 04:47:04 PM PDT 24
Finished Jul 06 04:47:44 PM PDT 24
Peak memory 222652 kb
Host smart-849ffdda-b2e2-4be8-b83a-aa15b578de5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696450601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1696450601
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3857859603
Short name T531
Test name
Test status
Simulation time 95090482 ps
CPU time 4.03 seconds
Started Jul 06 04:47:05 PM PDT 24
Finished Jul 06 04:47:10 PM PDT 24
Peak memory 214288 kb
Host smart-5dcf0ac3-920a-42f9-bfc4-3c5ac596d80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857859603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3857859603
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1891545082
Short name T180
Test name
Test status
Simulation time 35843779 ps
CPU time 1.54 seconds
Started Jul 06 04:47:05 PM PDT 24
Finished Jul 06 04:47:07 PM PDT 24
Peak memory 209608 kb
Host smart-37a739a4-dc0c-44bd-8318-df5b4b49431b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891545082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1891545082
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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