Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4713

1

T2

2

T3

6

T4

12

auto[1]

546

1

T43

3

T40

1

T44

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4713

1

T2

2

T3

6

T4

12

auto[1]

546

1

T43

3

T40

1

T44

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4715

1

T2

2

T3

6

T4

10

auto[1]

544

1

T4

2

T93

3

T203

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4715

1

T2

2

T3

6

T4

10

auto[1]

544

1

T4

2

T93

3

T203

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	424	1			T3	1		T14	1		T32	1
auto[OpGenId]	1133	1			T2	2		T3	2		T14	6
auto[OpGenSwOut]	1146	1			T3	1		T14	3		T32	2
auto[OpGenHwOut]	2496	1			T3	2		T4	12		T14	2
auto[OpDisable]	60	1			T33	1		T62	1		T70	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	424	1			T3	1		T14	1		T32	1
auto[OpGenId]	1133	1			T2	2		T3	2		T14	6
auto[OpGenSwOut]	1146	1			T3	1		T14	3		T32	2
auto[OpGenHwOut]	2496	1			T3	2		T4	12		T14	2
auto[OpDisable]	60	1			T33	1		T62	1		T70	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4689

1

T2

2

T3

6

T4

12

auto[1]

570

1

T16

1

T40

3

T41

2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4689

1

T2

2

T3

6

T4

12

auto[1]

570

1

T16

1

T40

3

T41

2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5002

1

T2

2

T3

6

T4

12

auto[1]

257

1

T114

4

T117

5

T141

11

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1811	1			T2	1		T3	3		T4	3
auto[1]	735	1			T2	1		T3	1		T4	3
auto[2]	670	1			T3	2		T4	1		T14	1
auto[3]	717	1			T14	3		T43	3		T91	1
auto[4]	331	1			T4	2		T93	1		T203	3
auto[5]	314	1			T4	2		T14	1		T91	1
auto[6]	373	1			T15	1		T16	1		T45	1
auto[7]	308	1			T4	1		T91	1		T41	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1326	1			T4	5		T14	1		T15	1
clear_one[1]	735	1			T2	1		T3	1		T4	3
clear_one[2]	670	1			T3	2		T4	1		T14	1
clear_one[3]	717	1			T14	3		T43	3		T91	1
clear_none	1811	1			T2	1		T3	3		T4	3

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1015	1			T2	2		T3	4		T4	4
auto[StInit]	665	1			T3	1		T4	1		T15	1
auto[StCreatorRootKey]	552	1			T3	1		T4	1		T15	1
auto[StOwnerIntKey]	494	1			T4	1		T43	1		T41	2
auto[StOwnerKey]	472	1			T4	1		T16	1		T43	1
auto[StDisabled]	1753	1			T4	4		T43	3		T91	3
auto[StInvalid]	308	1			T14	5		T47	4		T49	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1015	1			T2	2		T3	4		T4	4
auto[StInit]	665	1			T3	1		T4	1		T15	1
auto[StCreatorRootKey]	552	1			T3	1		T4	1		T15	1
auto[StOwnerIntKey]	494	1			T4	1		T43	1		T41	2
auto[StOwnerKey]	472	1			T4	1		T16	1		T43	1
auto[StDisabled]	1753	1			T4	4		T43	3		T91	3
auto[StInvalid]	308	1			T14	5		T47	4		T49	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3] - auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[3] - auto[4]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[3] - auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[3] - auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StOwnerIntKey]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[6] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[6] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	1	1			T234	1		-	-		-	-
auto[0]	auto[StReset]	auto[OpGenId]	156	1			T2	1		T14	2		T45	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	179	1			T32	1		T61	1		T18	2
auto[0]	auto[StReset]	auto[OpGenHwOut]	233	1			T3	2		T4	2		T210	1
auto[0]	auto[StInit]	auto[OpAdvance]	50	1			T32	1		T41	1		T19	1
auto[0]	auto[StInit]	auto[OpGenId]	103	1			T3	1		T16	1		T93	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	99	1			T61	1		T159	1		T33	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	157	1			T15	1		T91	1		T44	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	19	1			T40	1		T24	1		T53	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	58	1			T43	1		T44	1		T41	2
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	32	1			T33	1		T235	1		T130	2
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	67	1			T114	1		T33	2		T141	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	13	1			T236	1		T71	1		T237	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	27	1			T161	1		T33	1		T238	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	32	1			T61	1		T25	1		T33	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	48	1			T92	1		T33	1		T116	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	13	1			T114	1		T200	1		T239	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	27	1			T93	1		T33	1		T112	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	25	1			T240	1		T241	1		T242	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	47	1			T4	1		T16	1		T115	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	25	1			T114	1		T132	1		T241	1
auto[0]	auto[StDisabled]	auto[OpGenId]	62	1			T93	1		T158	1		T160	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	70	1			T40	1		T24	1		T114	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	168	1			T41	1		T210	1		T160	1
auto[0]	auto[StDisabled]	auto[OpDisable]	14	1			T33	1		T73	1		T243	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	12	1			T14	1		T98	1		T244	1
auto[0]	auto[StInvalid]	auto[OpGenId]	27	1			T38	1		T97	1		T99	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	24	1			T14	1		T47	1		T54	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	23	1			T49	1		T100	1		T95	1
auto[1]	auto[StReset]	auto[OpGenId]	22	1			T2	1		T14	1		T158	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	23	1			T3	1		T131	1		T33	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	45	1			T4	1		T14	1		T210	1
auto[1]	auto[StInit]	auto[OpAdvance]	2	1			T78	1		T245	1		-	-
auto[1]	auto[StInit]	auto[OpGenId]	10	1			T130	1		T76	2		T211	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	6	1			T33	1		T20	1		T21	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	23	1			T4	1		T210	1		T246	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	12	1			T20	1		T247	2		T216	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T159	1		T33	1		T51	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T51	1		T248	1		T211	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	39	1			T61	1		T208	1		T246	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T33	1		T133	1		T249	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T250	1		T247	2		T251	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	19	1			T131	1		T112	1		T130	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T43	1		T202	1		T235	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	12	1			T252	1		T253	1		T167	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	17	1			T160	1		T112	1		T51	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T33	1		T199	1		T254	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T201	1		T255	1		T85	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	26	1			T33	1		T256	1		T134	1
auto[1]	auto[StDisabled]	auto[OpGenId]	61	1			T41	1		T159	1		T25	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	61	1			T40	1		T33	4		T197	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	161	1			T4	1		T41	1		T210	1
auto[1]	auto[StDisabled]	auto[OpDisable]	7	1			T70	1		T46	1		T257	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	9	1			T97	1		T258	1		T259	1
auto[1]	auto[StInvalid]	auto[OpGenId]	12	1			T47	1		T50	1		T89	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T97	1		T260	1		T261	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T14	1		T38	1		T100	1
auto[2]	auto[StReset]	auto[OpAdvance]	2	1			T262	1		T263	1		-	-
auto[2]	auto[StReset]	auto[OpGenId]	18	1			T3	1		T51	1		T72	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	26	1			T14	1		T32	1		T33	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	55	1			T41	1		T203	1		T56	1
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T117	1		T96	1		T34	1
auto[2]	auto[StInit]	auto[OpGenId]	9	1			T20	1		T21	1		T264	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	15	1			T33	1		T19	1		T96	3
auto[2]	auto[StInit]	auto[OpGenHwOut]	20	1			T203	1		T158	1		T162	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T3	1		T56	1		T265	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	23	1			T33	2		T207	1		T51	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	19	1			T33	1		T70	1		T130	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	42	1			T210	1		T61	1		T19	2
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T266	1		T267	1		T268	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T33	1		T51	2		T60	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T41	1		T33	1		T117	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T41	1		T164	1		T115	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T46	1		T106	1		T102	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	10	1			T133	1		T57	1		T176	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T33	2		T51	2		T46	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	27	1			T204	1		T235	1		T269	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	13	1			T158	1		T131	1		T133	1
auto[2]	auto[StDisabled]	auto[OpGenId]	37	1			T33	1		T112	1		T7	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	48	1			T43	1		T40	1		T160	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T4	1		T92	1		T210	1
auto[2]	auto[StDisabled]	auto[OpDisable]	10	1			T71	1		T60	2		T77	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	7	1			T49	1		T54	1		T209	1
auto[2]	auto[StInvalid]	auto[OpGenId]	14	1			T49	1		T97	1		T261	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T97	1		T270	1		T271	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T272	1		T273	1		T274	1
auto[3]	auto[StReset]	auto[OpGenId]	29	1			T14	1		T275	1		T97	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	27	1			T14	1		T131	1		T51	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	45	1			T210	1		T203	2		T158	1
auto[3]	auto[StInit]	auto[OpAdvance]	4	1			T276	1		T277	1		T278	1
auto[3]	auto[StInit]	auto[OpGenId]	9	1			T59	1		T21	1		T108	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	17	1			T56	1		T20	2		T212	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	27	1			T33	1		T116	1		T279	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T59	1		T68	1		T280	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T33	1		T215	1		T76	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T41	1		T71	1		T46	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T203	1		T33	1		T116	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T237	1		T277	1		T267	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T90	1		T130	1		T46	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	20	1			T33	1		T51	1		T62	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	35	1			T210	1		T281	1		T204	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T141	1		T282	1		T283	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	20	1			T141	1		T52	1		T284	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T141	2		T248	1		T68	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	31	1			T43	1		T92	1		T210	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	24	1			T141	1		T285	1		T286	2
auto[3]	auto[StDisabled]	auto[OpGenId]	63	1			T43	1		T91	1		T41	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	54	1			T161	1		T33	1		T238	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	150	1			T43	1		T41	1		T92	1
auto[3]	auto[StDisabled]	auto[OpDisable]	5	1			T74	1		T77	1		T287	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	8	1			T272	1		T288	1		T289	1
auto[3]	auto[StInvalid]	auto[OpGenId]	12	1			T14	1		T97	1		T261	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T49	1		T38	1		T98	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	17	1			T54	2		T290	1		T209	1
auto[4]	auto[StReset]	auto[OpGenId]	11	1			T209	1		T77	1		T75	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	5	1			T235	1		T72	1		T211	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	16	1			T116	1		T291	1		T292	1
auto[4]	auto[StInit]	auto[OpAdvance]	2	1			T293	1		T294	1		-	-
auto[4]	auto[StInit]	auto[OpGenId]	4	1			T48	1		T168	1		T81	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T26	1		T295	1		T296	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	14	1			T33	1		T76	1		T297	2
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T298	1		-	-		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T158	1		T293	1		T299	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T77	1		T216	1		T296	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	28	1			T115	1		T204	1		T279	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T300	1		T301	1		T302	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T303	1		T233	1		T230	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T197	1		T51	1		T60	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T4	1		T158	1		T205	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T117	2		T144	1		T304	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	6	1			T60	1		T220	1		T305	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T51	1		T233	1		T306	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T203	1		T33	1		T238	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	11	1			T307	1		T300	2		T106	1
auto[4]	auto[StDisabled]	auto[OpGenId]	20	1			T117	1		T112	1		T235	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	20	1			T112	1		T46	2		T248	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	73	1			T4	1		T93	1		T203	2
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T62	1		T65	1		T76	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T49	1		T308	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	3	1			T309	1		T289	1		T310	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T54	1		T100	1		T311	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T47	1		T309	1		T312	1
auto[5]	auto[StReset]	auto[OpGenId]	6	1			T133	1		T275	1		T313	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	12	1			T88	1		T314	1		T258	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	23	1			T4	1		T210	1		T85	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T96	1		T226	1		T315	1
auto[5]	auto[StInit]	auto[OpGenId]	4	1			T316	1		T306	1		T102	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	8	1			T20	1		T277	2		T108	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	14	1			T25	1		T115	1		T71	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T282	1		T317	1		T318	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T319	1		T320	1		T321	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T25	1		T322	1		T295	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T4	1		T92	1		T255	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T68	1		T76	1		T167	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T33	1		T57	1		T72	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T203	1		T279	1		T255	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T307	1		T323	1		T324	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	11	1			T41	1		T65	1		T90	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T33	1		T228	1		T226	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T33	1		T291	1		T325	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	11	1			T158	1		T134	2		T326	1
auto[5]	auto[StDisabled]	auto[OpGenId]	19	1			T73	1		T327	2		T78	2
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	19	1			T133	1		T68	1		T76	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	71	1			T91	1		T41	1		T92	1
auto[5]	auto[StDisabled]	auto[OpDisable]	6	1			T328	1		T329	1		T48	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T330	1		T331	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	6	1			T14	1		T95	1		T289	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T38	1		T95	1		T290	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T50	1		T258	1		T259	1
auto[6]	auto[StReset]	auto[OpGenId]	8	1			T130	1		T60	1		T103	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	7	1			T45	1		T276	1		T332	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	23	1			T33	1		T71	1		T292	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T333	1		T228	1		T334	1
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T77	1		T107	1		T335	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	7	1			T41	1		T78	1		T336	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	20	1			T337	1		T338	1		T85	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T268	1		T231	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T339	1		T266	1		T29	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T340	1		T227	1		T333	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	31	1			T15	1		T16	1		T205	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T19	1		T266	1		T341	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T211	1		T78	1		T167	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T33	2		T307	1		T68	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T342	1		T343	1		T344	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T285	1		T345	1		T346	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	4	1			T159	1		T220	1		T347	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T167	1		T348	1		T233	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	24	1			T164	1		T338	1		T349	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	14	1			T93	1		T33	1		T198	1
auto[6]	auto[StDisabled]	auto[OpGenId]	34	1			T33	1		T238	1		T112	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	19	1			T131	1		T284	1		T240	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T210	1		T205	1		T281	1
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T267	1		T167	1		T81	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	6	1			T54	1		T50	1		T89	1
auto[6]	auto[StInvalid]	auto[OpGenId]	11	1			T261	1		T258	1		T309	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T38	1		T89	1		T350	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T274	1		T351	1		T352	1
auto[7]	auto[StReset]	auto[OpGenId]	9	1			T51	1		T212	1		T353	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	8	1			T209	1		T130	1		T77	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	26	1			T210	1		T6	1		T276	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T354	1		T72	1		T67	1
auto[7]	auto[StInit]	auto[OpGenId]	6	1			T60	1		T355	1		T356	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	1	1			T357	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenHwOut]	11	1			T358	1		T78	1		T299	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T19	1		T359	1		T245	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T77	1		T78	1		T227	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T33	1		T220	1		T360	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	12	1			T164	1		T361	1		T362	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T114	1		T363	1		T296	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T235	1		T132	1		T130	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T160	1		T168	1		T364	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	15	1			T112	1		T51	1		T365	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T236	1		T366	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	2	1			T367	1		T368	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T302	3		T369	1		T278	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T158	1		T337	1		T370	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	15	1			T114	1		T33	2		T132	1
auto[7]	auto[StDisabled]	auto[OpGenId]	24	1			T91	1		T112	1		T90	2
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	21	1			T241	1		T237	1		T76	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	69	1			T4	1		T41	1		T92	1
auto[7]	auto[StDisabled]	auto[OpDisable]	7	1			T72	1		T176	1		T78	2
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T371	1		T289	1		T372	1
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T95	1		T99	1		T272	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T99	1		T273	1		T373	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T47	1		T100	1		T312	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1326

1

T4

5

T14

1

T15

1

clear_one[1]

auto[0]

auto[0]

auto[0]

426

1

T2

1

T3

1

T4

2

clear_one[1]

auto[0]

auto[0]

auto[1]

133

1

T40

1

T41

1

T210

1

clear_one[1]

auto[0]

auto[1]

auto[0]

128

1

T4

1

T203

1

T61

1

clear_one[1]

auto[0]

auto[1]

auto[1]

48

1

T33

1

T51

1

T236

1

clear_one[2]

auto[0]

auto[0]

auto[0]

396

1

T3

2

T4

1

T14

1

clear_one[2]

auto[0]

auto[0]

auto[1]

119

1

T40

1

T41

1

T92

1

clear_one[2]

auto[1]

auto[0]

auto[0]

117

1

T43

1

T202

1

T201

3

clear_one[2]

auto[1]

auto[0]

auto[1]

38

1

T158

1

T33

1

T241

1

clear_one[3]

auto[0]

auto[0]

auto[0]

425

1

T14

3

T43

1

T91

1

clear_one[3]

auto[0]

auto[1]

auto[0]

103

1

T203

1

T25

1

T204

2

clear_one[3]

auto[1]

auto[0]

auto[0]

136

1

T43

2

T41

1

T159

1

clear_one[3]

auto[1]

auto[1]

auto[0]

53

1

T93

1

T33

1

T141

8

clear_none

auto[0]

auto[0]

auto[0]

1318

1

T2

1

T3

3

T4

2

clear_none

auto[0]

auto[0]

auto[1]

125

1

T16

1

T92

1

T210

1

clear_none

auto[0]

auto[1]

auto[0]

123

1

T4

1

T93

1

T160

1

clear_none

auto[0]

auto[1]

auto[1]

43

1

T33

1

T199

2

T133

1

clear_none

auto[1]

auto[0]

auto[0]

116

1

T44

1

T41

1

T24

1

clear_none

auto[1]

auto[0]

auto[1]

40

1

T40

1

T33

1

T285

1

clear_none

auto[1]

auto[1]

auto[0]

22

1

T93

1

T141

1

T197

1

clear_none

auto[1]

auto[1]

auto[1]

24

1

T158

1

T33

1

T276

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1272	1			T4	5		T14	1		T15	1
clear_all	auto[1]	54	1			T117	3		T132	1		T134	2
clear_one[1]	auto[0]	685	1			T2	1		T3	1		T4	3
clear_one[1]	auto[1]	50	1			T132	1		T134	1		T297	4
clear_one[2]	auto[0]	647	1			T3	2		T4	1		T14	1
clear_one[2]	auto[1]	23	1			T117	2		T266	1		T277	2
clear_one[3]	auto[0]	673	1			T14	3		T43	3		T91	1
clear_one[3]	auto[1]	44	1			T141	6		T237	1		T266	2
clear_none	auto[0]	1725	1			T2	1		T3	3		T4	3
clear_none	auto[1]	86	1			T114	4		T141	5		T132	2