Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10866

1

T1

8

T2

15

T3

19

auto[Attestation]

7339

1

T1

1

T3

18

T4

6

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2602	1			T1	2		T2	5		T3	5
auto[Aes]	3279	1			T2	3		T3	8		T13	1
auto[Kmac]	3231	1			T1	2		T2	1		T3	7
auto[Otbn]	3254	1			T1	3		T3	7		T5	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7459	1			T1	3		T2	1		T3	11
auto[OpGenId]	5839	1			T1	2		T2	6		T3	10
auto[OpGenSwOut]	5680	1			T1	2		T2	2		T3	19
auto[OpGenHwOut]	6686	1			T1	5		T2	7		T3	8
auto[OpDisable]	126	1			T3	1		T41	1		T33	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10188

1

T1

5

T3

12

T4

8

auto[OpDoneFail]

15602

1

T1

7

T2

16

T3

37

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6516	1			T1	7		T2	16		T3	20
auto[StInit]	3601	1			T1	2		T3	13		T4	2
auto[StCreatorRootKey]	3051	1			T1	2		T3	2		T4	2
auto[StOwnerIntKey]	2623	1			T1	1		T3	2		T4	2
auto[StOwnerKey]	2384	1			T3	2		T4	2		T12	2
auto[StDisabled]	7615	1			T3	10		T4	7		T12	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	351	1			T3	1		T14	3		T32	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	120	1			T61	1		T159	1		T162	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	82	1			T91	1		T44	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	57	1			T1	1		T33	1		T141	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	59	1			T25	1		T196	1		T51	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	200	1			T43	1		T158	1		T33	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	361	1			T2	1		T14	3		T32	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	88	1			T3	2		T14	1		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	68	1			T93	1		T63	1		T141	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	62	1			T112	1		T197	1		T51	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	65	1			T41	1		T161	1		T198	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	195	1			T41	1		T159	1		T161	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	335	1			T2	1		T3	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	83	1			T3	1		T14	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	62	1			T33	2		T19	1		T51	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	62	1			T41	1		T93	1		T158	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	58	1			T41	1		T33	3		T51	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	215	1			T3	3		T40	1		T93	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	317	1			T1	1		T14	2		T41	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	91	1			T12	1		T61	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	77	1			T3	1		T41	1		T33	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	67	1			T16	1		T93	1		T33	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	68	1			T93	1		T33	2		T51	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	206	1			T3	1		T40	1		T158	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	71	1			T3	1		T41	1		T33	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	99	1			T5	2		T14	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	68	1			T41	1		T33	2		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	70	1			T41	1		T58	1		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	72	1			T3	1		T12	1		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	198	1			T43	1		T40	2		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	68	1			T3	1		T41	3		T33	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	102	1			T3	1		T13	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	86	1			T61	2		T114	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	74	1			T159	1		T160	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	63	1			T41	1		T33	3		T141	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	214	1			T3	1		T41	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	73	1			T41	2		T33	4		T72	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	92	1			T3	1		T44	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	95	1			T44	1		T61	3		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	63	1			T16	1		T61	1		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	53	1			T33	4		T141	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	195	1			T40	2		T93	1		T159	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	74	1			T3	2		T41	3		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	97	1			T5	1		T15	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	75	1			T37	1		T51	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	77	1			T16	1		T159	1		T33	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	51	1			T24	1		T33	3		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	201	1			T3	1		T41	1		T161	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	268	1			T1	1		T2	5		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	67	1			T15	1		T41	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	74	1			T15	1		T114	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	49	1			T33	1		T62	1		T179	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	52	1			T33	1		T63	1		T117	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	172	1			T93	1		T158	1		T159	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	468	1			T2	2		T3	2		T41	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	109	1			T91	1		T159	1		T116	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	105	1			T162	1		T33	4		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	86	1			T158	1		T33	1		T202	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	97	1			T40	1		T24	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	271	1			T91	1		T41	1		T93	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	449	1			T3	1		T4	11		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	126	1			T1	1		T203	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	96	1			T44	1		T162	1		T141	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	88	1			T4	1		T131	1		T33	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	91	1			T25	1		T33	1		T204	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	293	1			T4	1		T40	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	481	1			T1	2		T3	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	127	1			T3	1		T13	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	110	1			T15	2		T92	1		T162	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	80	1			T158	1		T205	1		T206	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	85	1			T16	1		T92	1		T164	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	262	1			T40	1		T41	1		T92	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	50	1			T3	2		T33	1		T51	5
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	100	1			T61	1		T158	1		T162	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	65	1			T160	1		T33	1		T207	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	48	1			T43	1		T33	1		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	40	1			T43	1		T158	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	170	1			T40	2		T159	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	37	1			T33	1		T51	3		T72	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	126	1			T3	1		T61	1		T158	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	108	1			T15	2		T44	3		T162	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	81	1			T131	1		T116	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	75	1			T159	1		T201	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	270	1			T43	1		T41	2		T93	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	57	1			T33	1		T51	2		T209	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	104	1			T4	1		T5	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	107	1			T1	1		T4	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	93	1			T93	1		T203	1		T33	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	82	1			T4	1		T203	1		T159	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	259	1			T4	3		T40	1		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	55	1			T33	1		T51	2		T72	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	106	1			T92	1		T18	1		T114	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	95	1			T16	1		T210	1		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	103	1			T16	1		T41	1		T92	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	88	1			T40	1		T210	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	261	1			T41	1		T92	2		T210	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	175	1			T1	1		T91	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	694	1			T3	1		T14	3		T32	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	176	1			T41	1		T93	1		T161	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	663	1			T2	1		T3	2		T14	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	162	1			T41	2		T93	1		T158	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	653	1			T2	1		T3	5		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	195	1			T3	1		T16	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	631	1			T1	1		T3	1		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	196	1			T3	1		T12	1		T41	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	382	1			T3	1		T5	2		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	205	1			T41	1		T61	2		T159	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	402	1			T3	3		T13	1		T41	5
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	196	1			T16	1		T44	1		T61	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	375	1			T3	1		T40	2		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	192	1			T16	1		T159	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	383	1			T3	3		T5	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	156	1			T15	1		T114	1		T33	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	526	1			T1	1		T2	5		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	274	1			T40	1		T158	1		T162	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	862	1			T2	2		T3	2		T91	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	252	1			T4	1		T44	1		T162	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	891	1			T1	1		T3	1		T4	12
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	255	1			T15	2		T16	1		T92	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	890	1			T1	2		T3	2		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	143	1			T43	2		T158	1		T160	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	330	1			T3	2		T40	2		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	253	1			T15	2		T44	3		T159	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	444	1			T3	1		T43	1		T41	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	268	1			T1	1		T4	2		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	434	1			T4	4		T5	1		T40	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	269	1			T16	2		T40	1		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	439	1			T41	1		T92	3		T210	2