Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31833

1

T1

13

T2

16

T3

57

auto[1]

231

1

T114

4

T117

2

T141

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31840	1			T1	13		T2	16		T3	57
auto[134217728:268435455]	7	1			T132	1		T133	1		T327	1
auto[268435456:402653183]	6	1			T141	1		T134	1		T237	2
auto[402653184:536870911]	9	1			T307	1		T247	1		T396	1
auto[536870912:671088639]	6	1			T293	1		T397	1		T398	2
auto[671088640:805306367]	7	1			T132	1		T134	2		T266	1
auto[805306368:939524095]	5	1			T307	1		T266	1		T399	1
auto[939524096:1073741823]	10	1			T114	1		T117	1		T141	1
auto[1073741824:1207959551]	7	1			T134	1		T277	1		T300	1
auto[1207959552:1342177279]	5	1			T117	1		T141	1		T300	1
auto[1342177280:1476395007]	9	1			T114	1		T237	1		T277	1
auto[1476395008:1610612735]	8	1			T132	1		T297	1		T400	1
auto[1610612736:1744830463]	5	1			T253	1		T401	1		T402	1
auto[1744830464:1879048191]	11	1			T237	1		T382	1		T293	2
auto[1879048192:2013265919]	6	1			T134	1		T293	1		T397	1
auto[2013265920:2147483647]	6	1			T237	1		T307	1		T301	1
auto[2147483648:2281701375]	6	1			T114	1		T301	1		T396	1
auto[2281701376:2415919103]	12	1			T297	2		T277	1		T382	1
auto[2415919104:2550136831]	9	1			T300	1		T247	1		T400	1
auto[2550136832:2684354559]	11	1			T302	1		T397	1		T403	1
auto[2684354560:2818572287]	8	1			T134	2		T307	1		T303	1
auto[2818572288:2952790015]	4	1			T300	1		T247	1		T404	1
auto[2952790016:3087007743]	2	1			T297	1		T401	1		-	-
auto[3087007744:3221225471]	10	1			T114	1		T134	1		T237	1
auto[3221225472:3355443199]	6	1			T141	1		T277	1		T396	1
auto[3355443200:3489660927]	8	1			T285	1		T134	1		T396	1
auto[3489660928:3623878655]	4	1			T301	1		T247	1		T234	1
auto[3623878656:3758096383]	3	1			T247	1		T403	1		T405	1
auto[3758096384:3892314111]	9	1			T285	1		T247	2		T293	1
auto[3892314112:4026531839]	7	1			T297	1		T382	1		T247	1
auto[4026531840:4160749567]	10	1			T134	1		T300	1		T303	1
auto[4160749568:4294967295]	8	1			T307	2		T277	2		T300	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31833	1			T1	13		T2	16		T3	57
auto[0:134217727]	auto[1]	7	1			T141	1		T132	2		T327	1
auto[134217728:268435455]	auto[1]	7	1			T132	1		T133	1		T327	1
auto[268435456:402653183]	auto[1]	6	1			T141	1		T134	1		T237	2
auto[402653184:536870911]	auto[1]	9	1			T307	1		T247	1		T396	1
auto[536870912:671088639]	auto[1]	6	1			T293	1		T397	1		T398	2
auto[671088640:805306367]	auto[1]	7	1			T132	1		T134	2		T266	1
auto[805306368:939524095]	auto[1]	5	1			T307	1		T266	1		T399	1
auto[939524096:1073741823]	auto[1]	10	1			T114	1		T117	1		T141	1
auto[1073741824:1207959551]	auto[1]	7	1			T134	1		T277	1		T300	1
auto[1207959552:1342177279]	auto[1]	5	1			T117	1		T141	1		T300	1
auto[1342177280:1476395007]	auto[1]	9	1			T114	1		T237	1		T277	1
auto[1476395008:1610612735]	auto[1]	8	1			T132	1		T297	1		T400	1
auto[1610612736:1744830463]	auto[1]	5	1			T253	1		T401	1		T402	1
auto[1744830464:1879048191]	auto[1]	11	1			T237	1		T382	1		T293	2
auto[1879048192:2013265919]	auto[1]	6	1			T134	1		T293	1		T397	1
auto[2013265920:2147483647]	auto[1]	6	1			T237	1		T307	1		T301	1
auto[2147483648:2281701375]	auto[1]	6	1			T114	1		T301	1		T396	1
auto[2281701376:2415919103]	auto[1]	12	1			T297	2		T277	1		T382	1
auto[2415919104:2550136831]	auto[1]	9	1			T300	1		T247	1		T400	1
auto[2550136832:2684354559]	auto[1]	11	1			T302	1		T397	1		T403	1
auto[2684354560:2818572287]	auto[1]	8	1			T134	2		T307	1		T303	1
auto[2818572288:2952790015]	auto[1]	4	1			T300	1		T247	1		T404	1
auto[2952790016:3087007743]	auto[1]	2	1			T297	1		T401	1		-	-
auto[3087007744:3221225471]	auto[1]	10	1			T114	1		T134	1		T237	1
auto[3221225472:3355443199]	auto[1]	6	1			T141	1		T277	1		T396	1
auto[3355443200:3489660927]	auto[1]	8	1			T285	1		T134	1		T396	1
auto[3489660928:3623878655]	auto[1]	4	1			T301	1		T247	1		T234	1
auto[3623878656:3758096383]	auto[1]	3	1			T247	1		T403	1		T405	1
auto[3758096384:3892314111]	auto[1]	9	1			T285	1		T247	2		T293	1
auto[3892314112:4026531839]	auto[1]	7	1			T297	1		T382	1		T247	1
auto[4026531840:4160749567]	auto[1]	10	1			T134	1		T300	1		T303	1
auto[4160749568:4294967295]	auto[1]	8	1			T307	2		T277	2		T300	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1577

1

T2

10

T3

7

T14

9

auto[1]

1687

1

T3

1

T13

2

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T2	1		T13	1		T16	1
auto[134217728:268435455]	80	1			T2	1		T3	1		T53	1
auto[268435456:402653183]	90	1			T162	1		T24	1		T131	1
auto[402653184:536870911]	109	1			T45	1		T158	2		T131	2
auto[536870912:671088639]	105	1			T45	1		T114	1		T33	2
auto[671088640:805306367]	117	1			T14	1		T61	1		T33	2
auto[805306368:939524095]	104	1			T14	1		T53	1		T51	1
auto[939524096:1073741823]	104	1			T3	1		T131	1		T33	2
auto[1073741824:1207959551]	99	1			T23	1		T61	1		T158	2
auto[1207959552:1342177279]	99	1			T14	2		T41	1		T18	1
auto[1342177280:1476395007]	121	1			T16	1		T61	1		T33	1
auto[1476395008:1610612735]	98	1			T2	1		T25	2		T114	1
auto[1610612736:1744830463]	109	1			T158	1		T159	1		T114	1
auto[1744830464:1879048191]	107	1			T3	1		T14	1		T61	1
auto[1879048192:2013265919]	91	1			T2	1		T16	1		T40	1
auto[2013265920:2147483647]	111	1			T3	1		T14	1		T93	1
auto[2147483648:2281701375]	101	1			T2	1		T3	2		T16	1
auto[2281701376:2415919103]	107	1			T40	2		T61	1		T141	1
auto[2415919104:2550136831]	99	1			T2	1		T14	1		T16	1
auto[2550136832:2684354559]	101	1			T14	1		T41	2		T159	1
auto[2684354560:2818572287]	99	1			T159	1		T33	1		T70	1
auto[2818572288:2952790015]	92	1			T32	1		T114	1		T33	1
auto[2952790016:3087007743]	114	1			T2	1		T3	1		T112	1
auto[3087007744:3221225471]	107	1			T14	1		T40	1		T24	1
auto[3221225472:3355443199]	99	1			T32	2		T40	1		T162	1
auto[3355443200:3489660927]	103	1			T2	2		T93	1		T131	2
auto[3489660928:3623878655]	80	1			T2	1		T3	1		T16	1
auto[3623878656:3758096383]	106	1			T23	1		T56	1		T33	1
auto[3758096384:3892314111]	101	1			T32	1		T45	1		T51	2
auto[3892314112:4026531839]	100	1			T159	1		T33	1		T19	1
auto[4026531840:4160749567]	113	1			T14	1		T45	1		T93	1
auto[4160749568:4294967295]	99	1			T13	1		T14	1		T162	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T2	1		T18	1		T158	1
auto[0:134217727]	auto[1]	47	1			T13	1		T16	1		T41	1
auto[134217728:268435455]	auto[0]	46	1			T2	1		T3	1		T53	1
auto[134217728:268435455]	auto[1]	34	1			T51	1		T284	1		T21	1
auto[268435456:402653183]	auto[0]	40	1			T162	1		T24	1		T33	2
auto[268435456:402653183]	auto[1]	50	1			T131	1		T25	1		T117	1
auto[402653184:536870911]	auto[0]	50	1			T45	1		T158	2		T131	1
auto[402653184:536870911]	auto[1]	59	1			T131	1		T238	1		T235	1
auto[536870912:671088639]	auto[0]	53	1			T45	1		T114	1		T33	1
auto[536870912:671088639]	auto[1]	52	1			T33	1		T132	1		T65	1
auto[671088640:805306367]	auto[0]	60	1			T19	1		T52	1		T100	1
auto[671088640:805306367]	auto[1]	57	1			T14	1		T61	1		T33	2
auto[805306368:939524095]	auto[0]	51	1			T14	1		T51	1		T49	1
auto[805306368:939524095]	auto[1]	53	1			T53	1		T7	1		T256	1
auto[939524096:1073741823]	auto[0]	44	1			T3	1		T33	1		T47	1
auto[939524096:1073741823]	auto[1]	60	1			T131	1		T33	1		T275	1
auto[1073741824:1207959551]	auto[0]	46	1			T61	1		T158	1		T162	1
auto[1073741824:1207959551]	auto[1]	53	1			T23	1		T158	1		T33	1
auto[1207959552:1342177279]	auto[0]	47	1			T14	2		T236	1		T38	1
auto[1207959552:1342177279]	auto[1]	52	1			T41	1		T18	1		T56	1
auto[1342177280:1476395007]	auto[0]	65	1			T197	1		T49	1		T50	1
auto[1342177280:1476395007]	auto[1]	56	1			T16	1		T61	1		T33	1
auto[1476395008:1610612735]	auto[0]	46	1			T2	1		T25	2		T114	1
auto[1476395008:1610612735]	auto[1]	52	1			T33	2		T141	1		T17	1
auto[1610612736:1744830463]	auto[0]	45	1			T158	1		T33	1		T117	1
auto[1610612736:1744830463]	auto[1]	64	1			T159	1		T114	1		T33	1
auto[1744830464:1879048191]	auto[0]	55	1			T3	1		T14	1		T162	1
auto[1744830464:1879048191]	auto[1]	52	1			T61	1		T33	2		T47	1
auto[1879048192:2013265919]	auto[0]	42	1			T2	1		T40	1		T51	2
auto[1879048192:2013265919]	auto[1]	49	1			T16	1		T276	1		T212	1
auto[2013265920:2147483647]	auto[0]	49	1			T3	1		T14	1		T131	1
auto[2013265920:2147483647]	auto[1]	62	1			T93	1		T61	2		T33	2
auto[2147483648:2281701375]	auto[0]	58	1			T2	1		T3	2		T16	1
auto[2147483648:2281701375]	auto[1]	43	1			T61	1		T17	1		T235	2
auto[2281701376:2415919103]	auto[0]	46	1			T141	1		T51	2		T20	1
auto[2281701376:2415919103]	auto[1]	61	1			T40	2		T61	1		T50	1
auto[2415919104:2550136831]	auto[0]	49	1			T2	1		T16	1		T44	1
auto[2415919104:2550136831]	auto[1]	50	1			T14	1		T93	1		T33	2
auto[2550136832:2684354559]	auto[0]	53	1			T14	1		T41	1		T56	1
auto[2550136832:2684354559]	auto[1]	48	1			T41	1		T159	1		T25	1
auto[2684354560:2818572287]	auto[0]	52	1			T33	1		T198	1		T275	1
auto[2684354560:2818572287]	auto[1]	47	1			T159	1		T70	1		T198	1
auto[2818572288:2952790015]	auto[0]	44	1			T32	1		T49	1		T90	1
auto[2818572288:2952790015]	auto[1]	48	1			T114	1		T33	1		T197	1
auto[2952790016:3087007743]	auto[0]	65	1			T2	1		T3	1		T51	1
auto[2952790016:3087007743]	auto[1]	49	1			T112	1		T57	1		T84	1
auto[3087007744:3221225471]	auto[0]	39	1			T14	1		T47	1		T98	1
auto[3087007744:3221225471]	auto[1]	68	1			T40	1		T24	1		T131	1
auto[3221225472:3355443199]	auto[0]	51	1			T32	2		T40	1		T117	1
auto[3221225472:3355443199]	auto[1]	48	1			T162	1		T132	1		T200	1
auto[3355443200:3489660927]	auto[0]	65	1			T2	2		T93	1		T131	2
auto[3355443200:3489660927]	auto[1]	38	1			T33	1		T235	1		T51	1
auto[3489660928:3623878655]	auto[0]	37	1			T2	1		T158	1		T24	1
auto[3489660928:3623878655]	auto[1]	43	1			T3	1		T16	1		T41	1
auto[3623878656:3758096383]	auto[0]	49	1			T23	1		T56	1		T117	1
auto[3623878656:3758096383]	auto[1]	57	1			T33	1		T197	2		T236	1
auto[3758096384:3892314111]	auto[0]	42	1			T32	1		T45	1		T62	1
auto[3758096384:3892314111]	auto[1]	59	1			T51	2		T198	1		T200	1
auto[3892314112:4026531839]	auto[0]	48	1			T33	1		T19	1		T51	1
auto[3892314112:4026531839]	auto[1]	52	1			T159	1		T6	1		T200	1
auto[4026531840:4160749567]	auto[0]	45	1			T14	1		T45	1		T51	1
auto[4026531840:4160749567]	auto[1]	68	1			T93	1		T33	1		T51	1
auto[4160749568:4294967295]	auto[0]	43	1			T14	1		T162	2		T56	1
auto[4160749568:4294967295]	auto[1]	56	1			T13	1		T25	1		T47	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1585

1

T2

10

T3

8

T14

9

auto[1]

1679

1

T13

2

T14

2

T16

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	91	1			T93	1		T235	1		T200	1
auto[134217728:268435455]	92	1			T3	1		T45	1		T61	1
auto[268435456:402653183]	113	1			T2	1		T25	2		T53	1
auto[402653184:536870911]	94	1			T159	1		T162	1		T24	1
auto[536870912:671088639]	97	1			T2	2		T14	1		T41	1
auto[671088640:805306367]	98	1			T2	1		T93	1		T158	1
auto[805306368:939524095]	110	1			T33	3		T207	1		T141	1
auto[939524096:1073741823]	94	1			T41	1		T61	1		T158	1
auto[1073741824:1207959551]	114	1			T33	1		T19	1		T51	2
auto[1207959552:1342177279]	98	1			T2	1		T14	1		T33	1
auto[1342177280:1476395007]	104	1			T2	1		T16	1		T40	1
auto[1476395008:1610612735]	116	1			T3	1		T16	1		T41	1
auto[1610612736:1744830463]	105	1			T3	1		T14	1		T61	1
auto[1744830464:1879048191]	104	1			T14	1		T158	1		T238	1
auto[1879048192:2013265919]	92	1			T16	1		T93	1		T61	1
auto[2013265920:2147483647]	105	1			T2	1		T14	2		T32	1
auto[2147483648:2281701375]	95	1			T40	1		T207	1		T141	1
auto[2281701376:2415919103]	120	1			T13	1		T24	1		T131	1
auto[2415919104:2550136831]	109	1			T32	1		T162	1		T56	1
auto[2550136832:2684354559]	113	1			T14	1		T32	1		T45	1
auto[2684354560:2818572287]	104	1			T13	1		T14	1		T61	1
auto[2818572288:2952790015]	101	1			T14	2		T16	1		T61	1
auto[2952790016:3087007743]	92	1			T2	1		T32	1		T45	2
auto[3087007744:3221225471]	100	1			T3	1		T41	1		T18	1
auto[3221225472:3355443199]	103	1			T3	1		T23	2		T33	1
auto[3355443200:3489660927]	89	1			T2	1		T61	1		T158	1
auto[3489660928:3623878655]	101	1			T2	1		T16	1		T40	2
auto[3623878656:3758096383]	116	1			T40	1		T45	1		T131	1
auto[3758096384:3892314111]	109	1			T16	1		T53	1		T33	3
auto[3892314112:4026531839]	95	1			T3	1		T14	1		T158	1
auto[4026531840:4160749567]	106	1			T44	1		T45	1		T159	1
auto[4160749568:4294967295]	84	1			T3	2		T158	1		T33	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T235	1		T134	1		T329	1
auto[0:134217727]	auto[1]	48	1			T93	1		T200	1		T275	1
auto[134217728:268435455]	auto[0]	42	1			T3	1		T45	1		T18	1
auto[134217728:268435455]	auto[1]	50	1			T61	1		T100	1		T71	1
auto[268435456:402653183]	auto[0]	58	1			T2	1		T25	1		T53	1
auto[268435456:402653183]	auto[1]	55	1			T25	1		T51	1		T54	1
auto[402653184:536870911]	auto[0]	54	1			T162	1		T24	1		T33	2
auto[402653184:536870911]	auto[1]	40	1			T159	1		T33	1		T235	1
auto[536870912:671088639]	auto[0]	44	1			T2	2		T14	1		T33	2
auto[536870912:671088639]	auto[1]	53	1			T41	1		T33	1		T117	1
auto[671088640:805306367]	auto[0]	48	1			T2	1		T235	1		T49	1
auto[671088640:805306367]	auto[1]	50	1			T93	1		T158	1		T51	1
auto[805306368:939524095]	auto[0]	49	1			T33	2		T207	1		T133	1
auto[805306368:939524095]	auto[1]	61	1			T33	1		T141	1		T200	1
auto[939524096:1073741823]	auto[0]	47	1			T61	1		T158	1		T131	1
auto[939524096:1073741823]	auto[1]	47	1			T41	1		T17	1		T236	1
auto[1073741824:1207959551]	auto[0]	58	1			T51	1		T275	1		T71	1
auto[1073741824:1207959551]	auto[1]	56	1			T33	1		T19	1		T51	1
auto[1207959552:1342177279]	auto[0]	50	1			T2	1		T14	1		T59	1
auto[1207959552:1342177279]	auto[1]	48	1			T33	1		T197	1		T7	1
auto[1342177280:1476395007]	auto[0]	51	1			T2	1		T16	1		T40	1
auto[1342177280:1476395007]	auto[1]	53	1			T33	1		T117	1		T200	1
auto[1476395008:1610612735]	auto[0]	56	1			T3	1		T41	1		T158	1
auto[1476395008:1610612735]	auto[1]	60	1			T16	1		T114	1		T33	2
auto[1610612736:1744830463]	auto[0]	54	1			T3	1		T14	1		T207	1
auto[1610612736:1744830463]	auto[1]	51	1			T61	1		T52	1		T133	1
auto[1744830464:1879048191]	auto[0]	49	1			T14	1		T158	1		T112	1
auto[1744830464:1879048191]	auto[1]	55	1			T238	1		T252	1		T72	1
auto[1879048192:2013265919]	auto[0]	51	1			T16	1		T93	1		T47	1
auto[1879048192:2013265919]	auto[1]	41	1			T61	1		T25	1		T33	1
auto[2013265920:2147483647]	auto[0]	45	1			T2	1		T14	2		T32	1
auto[2013265920:2147483647]	auto[1]	60	1			T41	1		T141	1		T38	1
auto[2147483648:2281701375]	auto[0]	47	1			T51	1		T49	1		T100	1
auto[2147483648:2281701375]	auto[1]	48	1			T40	1		T207	1		T141	1
auto[2281701376:2415919103]	auto[0]	58	1			T24	1		T131	1		T33	1
auto[2281701376:2415919103]	auto[1]	62	1			T13	1		T33	1		T236	1
auto[2415919104:2550136831]	auto[0]	49	1			T32	1		T162	1		T49	1
auto[2415919104:2550136831]	auto[1]	60	1			T56	1		T33	3		T51	2
auto[2550136832:2684354559]	auto[0]	52	1			T45	1		T33	1		T52	1
auto[2550136832:2684354559]	auto[1]	61	1			T14	1		T32	1		T61	1
auto[2684354560:2818572287]	auto[0]	57	1			T14	1		T61	1		T162	1
auto[2684354560:2818572287]	auto[1]	47	1			T13	1		T19	1		T51	1
auto[2818572288:2952790015]	auto[0]	46	1			T14	2		T16	1		T56	1
auto[2818572288:2952790015]	auto[1]	55	1			T61	1		T131	1		T51	1
auto[2952790016:3087007743]	auto[0]	47	1			T2	1		T32	1		T45	2
auto[2952790016:3087007743]	auto[1]	45	1			T159	1		T56	1		T131	1
auto[3087007744:3221225471]	auto[0]	51	1			T3	1		T18	1		T131	1
auto[3087007744:3221225471]	auto[1]	49	1			T41	1		T159	1		T51	2
auto[3221225472:3355443199]	auto[0]	54	1			T3	1		T23	1		T33	1
auto[3221225472:3355443199]	auto[1]	49	1			T23	1		T6	1		T198	1
auto[3355443200:3489660927]	auto[0]	52	1			T2	1		T158	1		T114	1
auto[3355443200:3489660927]	auto[1]	37	1			T61	1		T162	1		T24	1
auto[3489660928:3623878655]	auto[0]	50	1			T2	1		T40	1		T19	1
auto[3489660928:3623878655]	auto[1]	51	1			T16	1		T40	1		T93	1
auto[3623878656:3758096383]	auto[0]	51	1			T45	1		T131	1		T98	1
auto[3623878656:3758096383]	auto[1]	65	1			T40	1		T17	1		T235	1
auto[3758096384:3892314111]	auto[0]	45	1			T33	1		T59	1		T49	1
auto[3758096384:3892314111]	auto[1]	64	1			T16	1		T53	1		T33	2
auto[3892314112:4026531839]	auto[0]	36	1			T3	1		T131	1		T33	2
auto[3892314112:4026531839]	auto[1]	59	1			T14	1		T158	1		T112	1
auto[4026531840:4160749567]	auto[0]	51	1			T44	1		T45	1		T159	1
auto[4026531840:4160749567]	auto[1]	55	1			T131	1		T114	1		T33	1
auto[4160749568:4294967295]	auto[0]	40	1			T3	2		T33	2		T51	1
auto[4160749568:4294967295]	auto[1]	44	1			T158	1		T33	1		T197	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1556

1

T2

10

T3

7

T14

9

auto[1]

1709

1

T3

1

T13

2

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T3	1		T14	1		T44	1
auto[134217728:268435455]	109	1			T3	1		T14	1		T159	1
auto[268435456:402653183]	94	1			T3	1		T13	1		T14	1
auto[402653184:536870911]	82	1			T2	1		T3	1		T40	1
auto[536870912:671088639]	102	1			T14	1		T158	1		T56	2
auto[671088640:805306367]	103	1			T2	1		T14	1		T16	2
auto[805306368:939524095]	125	1			T40	1		T61	1		T159	1
auto[939524096:1073741823]	91	1			T14	1		T40	1		T45	1
auto[1073741824:1207959551]	99	1			T2	1		T117	1		T112	1
auto[1207959552:1342177279]	108	1			T14	1		T23	1		T162	1
auto[1342177280:1476395007]	104	1			T2	2		T53	1		T33	1
auto[1476395008:1610612735]	112	1			T2	1		T14	1		T23	1
auto[1610612736:1744830463]	107	1			T16	1		T159	1		T162	1
auto[1744830464:1879048191]	116	1			T159	1		T162	1		T53	1
auto[1879048192:2013265919]	92	1			T14	1		T61	1		T51	1
auto[2013265920:2147483647]	106	1			T45	1		T56	1		T131	1
auto[2147483648:2281701375]	98	1			T3	1		T13	1		T61	1
auto[2281701376:2415919103]	105	1			T51	1		T236	1		T198	1
auto[2415919104:2550136831]	95	1			T158	1		T162	1		T25	1
auto[2550136832:2684354559]	105	1			T41	1		T158	1		T33	1
auto[2684354560:2818572287]	106	1			T2	1		T3	1		T32	1
auto[2818572288:2952790015]	118	1			T33	4		T207	1		T47	1
auto[2952790016:3087007743]	96	1			T14	1		T41	1		T53	1
auto[3087007744:3221225471]	91	1			T3	1		T32	2		T61	1
auto[3221225472:3355443199]	98	1			T45	2		T61	1		T18	1
auto[3355443200:3489660927]	107	1			T16	1		T93	1		T158	1
auto[3489660928:3623878655]	117	1			T2	1		T3	1		T131	1
auto[3623878656:3758096383]	93	1			T32	1		T207	1		T200	1
auto[3758096384:3892314111]	88	1			T2	1		T16	2		T41	1
auto[3892314112:4026531839]	117	1			T14	1		T40	1		T45	1
auto[4026531840:4160749567]	92	1			T93	1		T61	1		T47	1
auto[4160749568:4294967295]	85	1			T2	1		T61	1		T18	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T3	1		T14	1		T33	2
auto[0:134217727]	auto[1]	61	1			T44	1		T112	1		T51	3
auto[134217728:268435455]	auto[0]	59	1			T3	1		T14	1		T56	1
auto[134217728:268435455]	auto[1]	50	1			T159	1		T141	1		T71	1
auto[268435456:402653183]	auto[0]	43	1			T3	1		T114	1		T33	1
auto[268435456:402653183]	auto[1]	51	1			T13	1		T14	1		T41	2
auto[402653184:536870911]	auto[0]	38	1			T2	1		T3	1		T40	1
auto[402653184:536870911]	auto[1]	44	1			T158	1		T6	1		T65	1
auto[536870912:671088639]	auto[0]	48	1			T14	1		T158	1		T56	1
auto[536870912:671088639]	auto[1]	54	1			T56	1		T114	1		T33	1
auto[671088640:805306367]	auto[0]	49	1			T2	1		T14	1		T16	1
auto[671088640:805306367]	auto[1]	54	1			T16	1		T40	1		T51	1
auto[805306368:939524095]	auto[0]	63	1			T33	2		T235	1		T51	1
auto[805306368:939524095]	auto[1]	62	1			T40	1		T61	1		T159	1
auto[939524096:1073741823]	auto[0]	48	1			T40	1		T45	1		T51	1
auto[939524096:1073741823]	auto[1]	43	1			T14	1		T71	1		T72	1
auto[1073741824:1207959551]	auto[0]	53	1			T2	1		T49	1		T198	1
auto[1073741824:1207959551]	auto[1]	46	1			T117	1		T112	1		T197	1
auto[1207959552:1342177279]	auto[0]	50	1			T14	1		T23	1		T162	1
auto[1207959552:1342177279]	auto[1]	58	1			T197	1		T51	1		T54	1
auto[1342177280:1476395007]	auto[0]	45	1			T2	2		T53	1		T141	1
auto[1342177280:1476395007]	auto[1]	59	1			T33	1		T51	1		T236	1
auto[1476395008:1610612735]	auto[0]	51	1			T2	1		T14	1		T24	1
auto[1476395008:1610612735]	auto[1]	61	1			T23	1		T131	2		T114	1
auto[1610612736:1744830463]	auto[0]	56	1			T162	1		T24	1		T33	1
auto[1610612736:1744830463]	auto[1]	51	1			T16	1		T159	1		T33	2
auto[1744830464:1879048191]	auto[0]	62	1			T162	1		T33	2		T117	1
auto[1744830464:1879048191]	auto[1]	54	1			T159	1		T53	1		T19	1
auto[1879048192:2013265919]	auto[0]	43	1			T14	1		T50	1		T26	1
auto[1879048192:2013265919]	auto[1]	49	1			T61	1		T51	1		T88	1
auto[2013265920:2147483647]	auto[0]	56	1			T45	1		T51	1		T95	1
auto[2013265920:2147483647]	auto[1]	50	1			T56	1		T131	1		T207	1
auto[2147483648:2281701375]	auto[0]	49	1			T3	1		T158	1		T47	1
auto[2147483648:2281701375]	auto[1]	49	1			T13	1		T61	1		T51	2
auto[2281701376:2415919103]	auto[0]	39	1			T97	1		T72	1		T209	1
auto[2281701376:2415919103]	auto[1]	66	1			T51	1		T236	1		T198	1
auto[2415919104:2550136831]	auto[0]	44	1			T158	1		T162	1		T47	1
auto[2415919104:2550136831]	auto[1]	51	1			T25	1		T33	1		T141	1
auto[2550136832:2684354559]	auto[0]	45	1			T158	1		T117	1		T112	1
auto[2550136832:2684354559]	auto[1]	60	1			T41	1		T33	1		T6	1
auto[2684354560:2818572287]	auto[0]	50	1			T2	1		T3	1		T32	1
auto[2684354560:2818572287]	auto[1]	56	1			T61	1		T162	1		T24	1
auto[2818572288:2952790015]	auto[0]	43	1			T207	1		T19	1		T7	2
auto[2818572288:2952790015]	auto[1]	75	1			T33	4		T47	1		T90	2
auto[2952790016:3087007743]	auto[0]	43	1			T14	1		T114	1		T33	1
auto[2952790016:3087007743]	auto[1]	53	1			T41	1		T53	1		T33	2
auto[3087007744:3221225471]	auto[0]	49	1			T3	1		T32	1		T158	1
auto[3087007744:3221225471]	auto[1]	42	1			T32	1		T61	1		T33	1
auto[3221225472:3355443199]	auto[0]	52	1			T45	1		T61	1		T18	1
auto[3221225472:3355443199]	auto[1]	46	1			T45	1		T33	1		T17	1
auto[3355443200:3489660927]	auto[0]	50	1			T16	1		T158	1		T33	1
auto[3355443200:3489660927]	auto[1]	57	1			T93	1		T33	1		T19	1
auto[3489660928:3623878655]	auto[0]	54	1			T2	1		T131	1		T51	1
auto[3489660928:3623878655]	auto[1]	63	1			T3	1		T25	1		T33	2
auto[3623878656:3758096383]	auto[0]	48	1			T32	1		T207	1		T89	1
auto[3623878656:3758096383]	auto[1]	45	1			T200	1		T71	1		T7	1
auto[3758096384:3892314111]	auto[0]	43	1			T2	1		T16	2		T131	1
auto[3758096384:3892314111]	auto[1]	45	1			T41	1		T93	1		T33	2
auto[3892314112:4026531839]	auto[0]	58	1			T14	1		T45	1		T51	2
auto[3892314112:4026531839]	auto[1]	59	1			T40	1		T131	1		T141	1
auto[4026531840:4160749567]	auto[0]	43	1			T47	1		T19	1		T197	1
auto[4026531840:4160749567]	auto[1]	49	1			T93	1		T61	1		T198	1
auto[4160749568:4294967295]	auto[0]	39	1			T2	1		T51	1		T20	1
auto[4160749568:4294967295]	auto[1]	46	1			T61	1		T18	1		T33	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1575

1

T2

9

T3

8

T14

8

auto[1]

1689

1

T2

1

T13

2

T14

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	110	1			T131	1		T33	2		T17	1
auto[134217728:268435455]	85	1			T41	2		T93	1		T158	1
auto[268435456:402653183]	117	1			T32	1		T61	1		T158	1
auto[402653184:536870911]	103	1			T16	1		T33	1		T141	1
auto[536870912:671088639]	115	1			T2	1		T40	1		T114	1
auto[671088640:805306367]	95	1			T3	1		T14	1		T16	1
auto[805306368:939524095]	111	1			T158	1		T33	1		T47	1
auto[939524096:1073741823]	109	1			T2	1		T3	1		T16	1
auto[1073741824:1207959551]	107	1			T2	1		T3	1		T14	1
auto[1207959552:1342177279]	104	1			T61	1		T131	1		T33	2
auto[1342177280:1476395007]	99	1			T14	1		T41	1		T61	1
auto[1476395008:1610612735]	96	1			T13	1		T32	1		T47	1
auto[1610612736:1744830463]	92	1			T3	1		T40	1		T117	1
auto[1744830464:1879048191]	96	1			T2	1		T45	1		T158	1
auto[1879048192:2013265919]	90	1			T56	1		T33	3		T19	1
auto[2013265920:2147483647]	99	1			T2	1		T3	1		T32	1
auto[2147483648:2281701375]	87	1			T2	1		T16	1		T61	1
auto[2281701376:2415919103]	106	1			T3	1		T162	1		T117	1
auto[2415919104:2550136831]	91	1			T3	1		T23	1		T45	1
auto[2550136832:2684354559]	100	1			T40	1		T158	1		T159	1
auto[2684354560:2818572287]	107	1			T14	1		T45	1		T93	1
auto[2818572288:2952790015]	110	1			T2	2		T14	1		T93	1
auto[2952790016:3087007743]	110	1			T2	1		T23	1		T45	2
auto[3087007744:3221225471]	104	1			T44	1		T51	1		T38	1
auto[3221225472:3355443199]	105	1			T2	1		T14	1		T16	1
auto[3355443200:3489660927]	103	1			T61	1		T25	1		T114	1
auto[3489660928:3623878655]	114	1			T14	2		T93	1		T24	2
auto[3623878656:3758096383]	95	1			T45	1		T41	1		T159	1
auto[3758096384:3892314111]	97	1			T14	1		T41	1		T24	1
auto[3892314112:4026531839]	105	1			T14	1		T61	1		T158	1
auto[4026531840:4160749567]	106	1			T3	1		T13	1		T14	1
auto[4160749568:4294967295]	96	1			T131	1		T17	1		T51	1