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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4388 1 T2 20 T3 14 T13 4
auto[1] 2142 1 T3 2 T14 8 T16 2



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 224 1 T32 2 T159 2 T162 2
auto[134217728:268435455] 214 1 T3 2 T41 2 T33 4
auto[268435456:402653183] 222 1 T3 2 T14 2 T40 2
auto[402653184:536870911] 204 1 T13 2 T32 2 T45 2
auto[536870912:671088639] 178 1 T93 2 T141 2 T62 2
auto[671088640:805306367] 210 1 T2 2 T14 2 T41 2
auto[805306368:939524095] 220 1 T40 2 T45 4 T61 2
auto[939524096:1073741823] 210 1 T61 4 T131 2 T33 4
auto[1073741824:1207959551] 216 1 T2 2 T158 2 T162 2
auto[1207959552:1342177279] 196 1 T13 2 T162 2 T24 2
auto[1342177280:1476395007] 192 1 T2 6 T14 2 T41 2
auto[1476395008:1610612735] 216 1 T14 2 T23 2 T41 2
auto[1610612736:1744830463] 186 1 T32 2 T40 2 T158 2
auto[1744830464:1879048191] 194 1 T131 2 T33 2 T47 2
auto[1879048192:2013265919] 194 1 T3 2 T16 2 T158 2
auto[2013265920:2147483647] 210 1 T2 2 T14 2 T16 2
auto[2147483648:2281701375] 236 1 T16 2 T33 2 T59 2
auto[2281701376:2415919103] 196 1 T3 2 T16 2 T51 2
auto[2415919104:2550136831] 224 1 T53 2 T33 4 T207 4
auto[2550136832:2684354559] 198 1 T2 4 T45 2 T61 2
auto[2684354560:2818572287] 184 1 T3 2 T16 2 T40 2
auto[2818572288:2952790015] 222 1 T3 2 T45 2 T18 2
auto[2952790016:3087007743] 200 1 T2 2 T131 2 T114 2
auto[3087007744:3221225471] 190 1 T2 2 T14 2 T45 2
auto[3221225472:3355443199] 230 1 T14 2 T32 2 T40 2
auto[3355443200:3489660927] 174 1 T16 2 T44 2 T25 2
auto[3489660928:3623878655] 228 1 T33 4 T47 2 T235 2
auto[3623878656:3758096383] 224 1 T14 2 T61 2 T117 2
auto[3758096384:3892314111] 168 1 T3 2 T93 2 T158 4
auto[3892314112:4026531839] 162 1 T14 4 T114 2 T33 2
auto[4026531840:4160749567] 208 1 T3 2 T14 2 T23 2
auto[4160749568:4294967295] 200 1 T61 2 T56 2 T235 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 178 1 T159 2 T162 2 T131 2
auto[0:134217727] auto[1] 46 1 T32 2 T112 4 T73 2
auto[134217728:268435455] auto[0] 128 1 T3 2 T33 4 T235 2
auto[134217728:268435455] auto[1] 86 1 T41 2 T70 2 T71 4
auto[268435456:402653183] auto[0] 170 1 T3 2 T40 2 T93 2
auto[268435456:402653183] auto[1] 52 1 T14 2 T33 2 T117 2
auto[402653184:536870911] auto[0] 140 1 T13 2 T32 2 T45 2
auto[402653184:536870911] auto[1] 64 1 T33 2 T19 2 T197 2
auto[536870912:671088639] auto[0] 104 1 T93 2 T141 2 T199 2
auto[536870912:671088639] auto[1] 74 1 T62 2 T49 2 T54 2
auto[671088640:805306367] auto[0] 138 1 T2 2 T41 2 T159 2
auto[671088640:805306367] auto[1] 72 1 T14 2 T235 2 T197 2
auto[805306368:939524095] auto[0] 150 1 T40 2 T45 4 T6 2
auto[805306368:939524095] auto[1] 70 1 T61 2 T286 2 T239 4
auto[939524096:1073741823] auto[0] 158 1 T131 2 T33 4 T235 2
auto[939524096:1073741823] auto[1] 52 1 T61 4 T52 4 T100 2
auto[1073741824:1207959551] auto[0] 136 1 T2 2 T158 2 T53 2
auto[1073741824:1207959551] auto[1] 80 1 T162 2 T56 2 T33 2
auto[1207959552:1342177279] auto[0] 126 1 T13 2 T162 2 T24 2
auto[1207959552:1342177279] auto[1] 70 1 T52 2 T406 2 T7 2
auto[1342177280:1476395007] auto[0] 134 1 T2 6 T14 2 T158 2
auto[1342177280:1476395007] auto[1] 58 1 T41 2 T24 2 T200 4
auto[1476395008:1610612735] auto[0] 142 1 T14 2 T23 2 T25 2
auto[1476395008:1610612735] auto[1] 74 1 T41 2 T61 2 T18 2
auto[1610612736:1744830463] auto[0] 132 1 T32 2 T40 2 T158 2
auto[1610612736:1744830463] auto[1] 54 1 T100 2 T74 2 T60 4
auto[1744830464:1879048191] auto[0] 126 1 T33 2 T47 2 T198 2
auto[1744830464:1879048191] auto[1] 68 1 T131 2 T252 2 T84 2
auto[1879048192:2013265919] auto[0] 136 1 T3 2 T16 2 T158 2
auto[1879048192:2013265919] auto[1] 58 1 T97 2 T134 2 T77 2
auto[2013265920:2147483647] auto[0] 150 1 T2 2 T14 2 T162 2
auto[2013265920:2147483647] auto[1] 60 1 T16 2 T51 2 T236 2
auto[2147483648:2281701375] auto[0] 166 1 T16 2 T33 2 T59 2
auto[2147483648:2281701375] auto[1] 70 1 T275 2 T254 2 T260 2
auto[2281701376:2415919103] auto[0] 132 1 T3 2 T16 2 T51 2
auto[2281701376:2415919103] auto[1] 64 1 T284 2 T176 4 T77 2
auto[2415919104:2550136831] auto[0] 152 1 T33 2 T207 2 T26 2
auto[2415919104:2550136831] auto[1] 72 1 T53 2 T33 2 T207 2
auto[2550136832:2684354559] auto[0] 136 1 T2 4 T45 2 T159 2
auto[2550136832:2684354559] auto[1] 62 1 T61 2 T62 2 T20 2
auto[2684354560:2818572287] auto[0] 120 1 T3 2 T16 2 T40 2
auto[2684354560:2818572287] auto[1] 64 1 T41 2 T25 2 T19 2
auto[2818572288:2952790015] auto[0] 134 1 T3 2 T45 2 T158 2
auto[2818572288:2952790015] auto[1] 88 1 T18 2 T131 2 T33 2
auto[2952790016:3087007743] auto[0] 130 1 T2 2 T131 2 T114 2
auto[2952790016:3087007743] auto[1] 70 1 T33 2 T141 2 T19 2
auto[3087007744:3221225471] auto[0] 132 1 T2 2 T45 2 T131 2
auto[3087007744:3221225471] auto[1] 58 1 T14 2 T59 2 T133 2
auto[3221225472:3355443199] auto[0] 164 1 T14 2 T32 2 T40 2
auto[3221225472:3355443199] auto[1] 66 1 T33 2 T47 2 T276 2
auto[3355443200:3489660927] auto[0] 110 1 T16 2 T44 2 T25 2
auto[3355443200:3489660927] auto[1] 64 1 T197 2 T59 2 T57 2
auto[3489660928:3623878655] auto[0] 154 1 T47 2 T235 2 T51 2
auto[3489660928:3623878655] auto[1] 74 1 T33 4 T38 2 T199 2
auto[3623878656:3758096383] auto[0] 140 1 T117 2 T235 2 T51 4
auto[3623878656:3758096383] auto[1] 84 1 T14 2 T61 2 T17 2
auto[3758096384:3892314111] auto[0] 98 1 T93 2 T158 4 T24 2
auto[3758096384:3892314111] auto[1] 70 1 T3 2 T19 2 T57 2
auto[3892314112:4026531839] auto[0] 92 1 T14 4 T47 2 T51 2
auto[3892314112:4026531839] auto[1] 70 1 T114 2 T33 2 T51 2
auto[4026531840:4160749567] auto[0] 152 1 T3 2 T14 2 T93 2
auto[4026531840:4160749567] auto[1] 56 1 T23 2 T25 2 T114 2
auto[4160749568:4294967295] auto[0] 128 1 T61 2 T56 2 T235 2
auto[4160749568:4294967295] auto[1] 72 1 T51 2 T209 2 T260 2

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