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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1591 1 T2 9 T3 5 T14 9
auto[1] 1674 1 T2 1 T3 3 T13 2


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 120 1 T2 1 T3 1 T40 2
auto[134217728:268435455] 98 1 T3 1 T93 1 T131 1
auto[268435456:402653183] 103 1 T14 1 T32 1 T18 1
auto[402653184:536870911] 86 1 T3 1 T131 1 T114 1
auto[536870912:671088639] 109 1 T2 1 T14 1 T159 1
auto[671088640:805306367] 113 1 T45 1 T41 1 T33 1
auto[805306368:939524095] 109 1 T16 1 T40 1 T45 1
auto[939524096:1073741823] 110 1 T14 1 T159 1 T141 1
auto[1073741824:1207959551] 88 1 T2 1 T14 1 T16 1
auto[1207959552:1342177279] 97 1 T13 1 T131 1 T33 2
auto[1342177280:1476395007] 131 1 T2 2 T3 1 T162 1
auto[1476395008:1610612735] 107 1 T41 1 T162 1 T33 2
auto[1610612736:1744830463] 87 1 T45 1 T61 1 T18 1
auto[1744830464:1879048191] 98 1 T3 1 T23 1 T40 1
auto[1879048192:2013265919] 108 1 T33 2 T141 1 T51 2
auto[2013265920:2147483647] 88 1 T14 2 T158 1 T25 2
auto[2147483648:2281701375] 98 1 T61 1 T24 1 T200 2
auto[2281701376:2415919103] 90 1 T61 1 T158 1 T114 1
auto[2415919104:2550136831] 94 1 T2 1 T3 1 T14 1
auto[2550136832:2684354559] 103 1 T45 1 T56 1 T25 1
auto[2684354560:2818572287] 91 1 T2 1 T16 1 T61 1
auto[2818572288:2952790015] 94 1 T2 1 T45 1 T162 1
auto[2952790016:3087007743] 110 1 T16 1 T32 1 T158 1
auto[3087007744:3221225471] 103 1 T3 1 T14 2 T16 1
auto[3221225472:3355443199] 113 1 T93 1 T33 2 T117 1
auto[3355443200:3489660927] 106 1 T3 1 T14 2 T19 1
auto[3489660928:3623878655] 111 1 T2 1 T23 1 T44 1
auto[3623878656:3758096383] 98 1 T40 1 T41 1 T158 1
auto[3758096384:3892314111] 104 1 T41 1 T61 1 T33 1
auto[3892314112:4026531839] 110 1 T2 1 T13 1 T32 1
auto[4026531840:4160749567] 93 1 T93 1 T158 1 T159 1
auto[4160749568:4294967295] 95 1 T61 1 T33 1 T19 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 62 1 T40 1 T162 1 T33 2
auto[0:134217727] auto[1] 58 1 T2 1 T3 1 T40 1
auto[134217728:268435455] auto[0] 44 1 T3 1 T33 1 T47 1
auto[134217728:268435455] auto[1] 54 1 T93 1 T131 1 T6 1
auto[268435456:402653183] auto[0] 57 1 T14 1 T32 1 T18 1
auto[268435456:402653183] auto[1] 46 1 T117 1 T197 1 T50 1
auto[402653184:536870911] auto[0] 43 1 T3 1 T131 1 T33 1
auto[402653184:536870911] auto[1] 43 1 T114 1 T17 1 T198 1
auto[536870912:671088639] auto[0] 56 1 T2 1 T14 1 T162 1
auto[536870912:671088639] auto[1] 53 1 T159 1 T131 1 T141 1
auto[671088640:805306367] auto[0] 56 1 T45 1 T49 1 T199 1
auto[671088640:805306367] auto[1] 57 1 T41 1 T33 1 T19 1
auto[805306368:939524095] auto[0] 51 1 T16 1 T45 1 T117 1
auto[805306368:939524095] auto[1] 58 1 T40 1 T41 1 T61 1
auto[939524096:1073741823] auto[0] 52 1 T14 1 T59 1 T52 1
auto[939524096:1073741823] auto[1] 58 1 T159 1 T141 1 T199 1
auto[1073741824:1207959551] auto[0] 49 1 T2 1 T14 1 T33 1
auto[1073741824:1207959551] auto[1] 39 1 T16 1 T33 2 T235 1
auto[1207959552:1342177279] auto[0] 44 1 T131 1 T49 1 T20 1
auto[1207959552:1342177279] auto[1] 53 1 T13 1 T33 2 T51 1
auto[1342177280:1476395007] auto[0] 56 1 T2 2 T3 1 T162 1
auto[1342177280:1476395007] auto[1] 75 1 T131 1 T6 1 T197 1
auto[1476395008:1610612735] auto[0] 43 1 T162 1 T33 1 T207 2
auto[1476395008:1610612735] auto[1] 64 1 T41 1 T33 1 T112 1
auto[1610612736:1744830463] auto[0] 41 1 T45 1 T114 1 T51 2
auto[1610612736:1744830463] auto[1] 46 1 T61 1 T18 1 T33 3
auto[1744830464:1879048191] auto[0] 55 1 T3 1 T23 1 T162 1
auto[1744830464:1879048191] auto[1] 43 1 T40 1 T61 1 T33 1
auto[1879048192:2013265919] auto[0] 50 1 T33 1 T236 1 T198 1
auto[1879048192:2013265919] auto[1] 58 1 T33 1 T141 1 T51 2
auto[2013265920:2147483647] auto[0] 41 1 T25 1 T112 1 T236 1
auto[2013265920:2147483647] auto[1] 47 1 T14 2 T158 1 T25 1
auto[2147483648:2281701375] auto[0] 47 1 T284 1 T100 1 T90 1
auto[2147483648:2281701375] auto[1] 51 1 T61 1 T24 1 T200 2
auto[2281701376:2415919103] auto[0] 49 1 T61 1 T158 1 T114 1
auto[2281701376:2415919103] auto[1] 41 1 T33 1 T19 1 T51 1
auto[2415919104:2550136831] auto[0] 51 1 T2 1 T3 1 T14 1
auto[2415919104:2550136831] auto[1] 43 1 T16 1 T33 1 T132 1
auto[2550136832:2684354559] auto[0] 48 1 T45 1 T56 1 T51 1
auto[2550136832:2684354559] auto[1] 55 1 T25 1 T207 1 T47 1
auto[2684354560:2818572287] auto[0] 41 1 T2 1 T16 1 T53 1
auto[2684354560:2818572287] auto[1] 50 1 T61 1 T159 1 T112 2
auto[2818572288:2952790015] auto[0] 43 1 T2 1 T45 1 T162 1
auto[2818572288:2952790015] auto[1] 51 1 T51 1 T50 1 T252 1
auto[2952790016:3087007743] auto[0] 53 1 T16 1 T32 1 T158 1
auto[2952790016:3087007743] auto[1] 57 1 T53 1 T132 1 T38 1
auto[3087007744:3221225471] auto[0] 44 1 T14 2 T53 1 T51 1
auto[3087007744:3221225471] auto[1] 59 1 T3 1 T16 1 T93 1
auto[3221225472:3355443199] auto[0] 53 1 T33 1 T112 1 T51 1
auto[3221225472:3355443199] auto[1] 60 1 T93 1 T33 1 T117 1
auto[3355443200:3489660927] auto[0] 60 1 T14 2 T19 1 T51 1
auto[3355443200:3489660927] auto[1] 46 1 T3 1 T51 1 T132 1
auto[3489660928:3623878655] auto[0] 57 1 T2 1 T59 1 T49 1
auto[3489660928:3623878655] auto[1] 54 1 T23 1 T44 1 T24 1
auto[3623878656:3758096383] auto[0] 46 1 T41 1 T158 1 T38 1
auto[3623878656:3758096383] auto[1] 52 1 T40 1 T65 1 T52 2
auto[3758096384:3892314111] auto[0] 58 1 T207 1 T51 2 T38 1
auto[3758096384:3892314111] auto[1] 46 1 T41 1 T61 1 T33 1
auto[3892314112:4026531839] auto[0] 50 1 T2 1 T45 1 T51 2
auto[3892314112:4026531839] auto[1] 60 1 T13 1 T32 1 T17 1
auto[4026531840:4160749567] auto[0] 42 1 T158 1 T56 1 T25 1
auto[4026531840:4160749567] auto[1] 51 1 T93 1 T159 1 T56 1
auto[4160749568:4294967295] auto[0] 49 1 T33 1 T20 1 T209 1
auto[4160749568:4294967295] auto[1] 46 1 T61 1 T19 1 T51 1

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