Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6639

1

T2

6

T3

15

T13

2

auto[1]

267

1

T114

6

T117

4

T141

9

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2794	1			T2	3		T3	6		T13	1
auto[134217728:268435455]	159	1			T13	1		T32	1		T158	1
auto[268435456:402653183]	132	1			T16	1		T162	1		T24	1
auto[402653184:536870911]	154	1			T3	1		T40	1		T45	1
auto[536870912:671088639]	145	1			T131	1		T33	2		T197	1
auto[671088640:805306367]	122	1			T14	1		T16	1		T41	1
auto[805306368:939524095]	140	1			T2	1		T3	1		T61	1
auto[939524096:1073741823]	150	1			T3	1		T18	1		T162	1
auto[1073741824:1207959551]	130	1			T3	1		T14	1		T41	2
auto[1207959552:1342177279]	133	1			T131	1		T33	1		T117	1
auto[1342177280:1476395007]	145	1			T14	1		T61	2		T159	1
auto[1476395008:1610612735]	127	1			T14	1		T41	2		T159	1
auto[1610612736:1744830463]	149	1			T3	1		T14	1		T158	1
auto[1744830464:1879048191]	161	1			T61	1		T33	3		T49	1
auto[1879048192:2013265919]	118	1			T3	1		T33	1		T207	1
auto[2013265920:2147483647]	116	1			T53	1		T117	1		T284	1
auto[2147483648:2281701375]	117	1			T14	2		T40	1		T61	2
auto[2281701376:2415919103]	145	1			T25	1		T114	2		T33	1
auto[2415919104:2550136831]	136	1			T93	1		T158	1		T24	1
auto[2550136832:2684354559]	124	1			T40	1		T45	1		T158	1
auto[2684354560:2818572287]	135	1			T16	1		T159	1		T24	1
auto[2818572288:2952790015]	140	1			T3	1		T23	1		T93	1
auto[2952790016:3087007743]	112	1			T131	1		T33	3		T207	1
auto[3087007744:3221225471]	106	1			T3	1		T33	1		T19	1
auto[3221225472:3355443199]	125	1			T2	1		T14	2		T32	1
auto[3355443200:3489660927]	106	1			T162	1		T33	2		T117	1
auto[3489660928:3623878655]	131	1			T33	4		T49	1		T199	1
auto[3623878656:3758096383]	118	1			T61	1		T33	3		T141	1
auto[3758096384:3892314111]	119	1			T2	1		T14	2		T44	1
auto[3892314112:4026531839]	136	1			T40	2		T33	2		T112	2
auto[4026531840:4160749567]	131	1			T3	1		T45	1		T41	1
auto[4160749568:4294967295]	150	1			T162	1		T131	1		T25	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2782	1			T2	3		T3	6		T13	1
auto[0:134217727]	auto[1]	12	1			T237	1		T277	1		T300	1
auto[134217728:268435455]	auto[0]	150	1			T13	1		T32	1		T158	1
auto[134217728:268435455]	auto[1]	9	1			T114	1		T132	1		T134	2
auto[268435456:402653183]	auto[0]	128	1			T16	1		T162	1		T24	1
auto[268435456:402653183]	auto[1]	4	1			T277	1		T399	1		T398	1
auto[402653184:536870911]	auto[0]	148	1			T3	1		T40	1		T45	1
auto[402653184:536870911]	auto[1]	6	1			T266	1		T303	1		T247	1
auto[536870912:671088639]	auto[0]	132	1			T131	1		T33	2		T197	1
auto[536870912:671088639]	auto[1]	13	1			T134	2		T135	1		T327	1
auto[671088640:805306367]	auto[0]	116	1			T14	1		T16	1		T41	1
auto[671088640:805306367]	auto[1]	6	1			T242	1		T404	1		T317	1
auto[805306368:939524095]	auto[0]	134	1			T2	1		T3	1		T61	1
auto[805306368:939524095]	auto[1]	6	1			T117	1		T237	1		T301	1
auto[939524096:1073741823]	auto[0]	143	1			T3	1		T18	1		T162	1
auto[939524096:1073741823]	auto[1]	7	1			T141	1		T327	1		T297	1
auto[1073741824:1207959551]	auto[0]	122	1			T3	1		T14	1		T41	2
auto[1073741824:1207959551]	auto[1]	8	1			T114	2		T253	1		T242	1
auto[1207959552:1342177279]	auto[0]	124	1			T131	1		T33	1		T47	1
auto[1207959552:1342177279]	auto[1]	9	1			T117	1		T396	1		T293	1
auto[1342177280:1476395007]	auto[0]	135	1			T14	1		T61	2		T159	1
auto[1342177280:1476395007]	auto[1]	10	1			T114	1		T141	2		T237	1
auto[1476395008:1610612735]	auto[0]	114	1			T14	1		T41	2		T159	1
auto[1476395008:1610612735]	auto[1]	13	1			T114	1		T141	2		T307	1
auto[1610612736:1744830463]	auto[0]	139	1			T3	1		T14	1		T158	1
auto[1610612736:1744830463]	auto[1]	10	1			T114	1		T134	2		T297	1
auto[1744830464:1879048191]	auto[0]	150	1			T61	1		T33	3		T49	1
auto[1744830464:1879048191]	auto[1]	11	1			T285	1		T297	1		T407	1
auto[1879048192:2013265919]	auto[0]	111	1			T3	1		T33	1		T207	1
auto[1879048192:2013265919]	auto[1]	7	1			T132	1		T134	2		T302	1
auto[2013265920:2147483647]	auto[0]	103	1			T53	1		T284	1		T252	1
auto[2013265920:2147483647]	auto[1]	13	1			T117	1		T237	1		T307	1
auto[2147483648:2281701375]	auto[0]	113	1			T14	2		T40	1		T61	2
auto[2147483648:2281701375]	auto[1]	4	1			T247	1		T408	1		T283	1
auto[2281701376:2415919103]	auto[0]	132	1			T25	1		T114	2		T33	1
auto[2281701376:2415919103]	auto[1]	13	1			T141	1		T277	1		T396	1
auto[2415919104:2550136831]	auto[0]	128	1			T93	1		T158	1		T24	1
auto[2415919104:2550136831]	auto[1]	8	1			T132	1		T134	2		T237	1
auto[2550136832:2684354559]	auto[0]	118	1			T40	1		T45	1		T158	1
auto[2550136832:2684354559]	auto[1]	6	1			T327	1		T262	1		T399	1
auto[2684354560:2818572287]	auto[0]	126	1			T16	1		T159	1		T24	1
auto[2684354560:2818572287]	auto[1]	9	1			T307	1		T303	1		T301	1
auto[2818572288:2952790015]	auto[0]	131	1			T3	1		T23	1		T93	1
auto[2818572288:2952790015]	auto[1]	9	1			T141	1		T297	1		T382	1
auto[2952790016:3087007743]	auto[0]	108	1			T131	1		T33	3		T207	1
auto[2952790016:3087007743]	auto[1]	4	1			T247	1		T404	1		T409	1
auto[3087007744:3221225471]	auto[0]	98	1			T3	1		T33	1		T19	1
auto[3087007744:3221225471]	auto[1]	8	1			T297	1		T383	2		T404	1
auto[3221225472:3355443199]	auto[0]	119	1			T2	1		T14	2		T32	1
auto[3221225472:3355443199]	auto[1]	6	1			T117	1		T297	1		T293	1
auto[3355443200:3489660927]	auto[0]	101	1			T162	1		T33	2		T117	1
auto[3355443200:3489660927]	auto[1]	5	1			T132	1		T247	1		T396	1
auto[3489660928:3623878655]	auto[0]	127	1			T33	4		T49	1		T199	1
auto[3489660928:3623878655]	auto[1]	4	1			T327	1		T396	1		T410	2
auto[3623878656:3758096383]	auto[0]	109	1			T61	1		T33	3		T141	1
auto[3623878656:3758096383]	auto[1]	9	1			T327	1		T247	1		T293	1
auto[3758096384:3892314111]	auto[0]	112	1			T2	1		T14	2		T44	1
auto[3758096384:3892314111]	auto[1]	7	1			T297	1		T300	1		T399	1
auto[3892314112:4026531839]	auto[0]	127	1			T40	2		T33	2		T112	2
auto[3892314112:4026531839]	auto[1]	9	1			T134	1		T307	1		T247	2
auto[4026531840:4160749567]	auto[0]	123	1			T3	1		T45	1		T41	1
auto[4026531840:4160749567]	auto[1]	8	1			T141	1		T277	1		T247	1
auto[4160749568:4294967295]	auto[0]	136	1			T162	1		T131	1		T25	1
auto[4160749568:4294967295]	auto[1]	14	1			T141	1		T132	1		T237	2