Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.40 99.00 98.23 98.42 97.67 98.93 98.41 91.14


Total test records in report: 1082
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T1005 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.302789269 Jul 07 04:52:33 PM PDT 24 Jul 07 04:52:35 PM PDT 24 95386248 ps
T1006 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2059184660 Jul 07 04:52:33 PM PDT 24 Jul 07 04:52:37 PM PDT 24 161009931 ps
T1007 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1480931269 Jul 07 04:53:07 PM PDT 24 Jul 07 04:53:08 PM PDT 24 12428185 ps
T1008 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2857927643 Jul 07 04:52:55 PM PDT 24 Jul 07 04:52:58 PM PDT 24 151320299 ps
T1009 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1339291986 Jul 07 04:53:11 PM PDT 24 Jul 07 04:53:12 PM PDT 24 47753296 ps
T1010 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2501553318 Jul 07 04:52:38 PM PDT 24 Jul 07 04:52:42 PM PDT 24 120816388 ps
T1011 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.274249133 Jul 07 04:53:11 PM PDT 24 Jul 07 04:53:12 PM PDT 24 9406755 ps
T1012 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2521326283 Jul 07 04:52:51 PM PDT 24 Jul 07 04:52:55 PM PDT 24 41011612 ps
T1013 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2282670820 Jul 07 04:53:11 PM PDT 24 Jul 07 04:53:13 PM PDT 24 24583566 ps
T1014 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2298546822 Jul 07 04:52:50 PM PDT 24 Jul 07 04:52:51 PM PDT 24 35163241 ps
T1015 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3908604170 Jul 07 04:52:51 PM PDT 24 Jul 07 04:52:54 PM PDT 24 142250106 ps
T1016 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.103849434 Jul 07 04:52:47 PM PDT 24 Jul 07 04:52:48 PM PDT 24 22701605 ps
T1017 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1875157035 Jul 07 04:52:41 PM PDT 24 Jul 07 04:52:42 PM PDT 24 11543178 ps
T1018 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3728079452 Jul 07 04:52:44 PM PDT 24 Jul 07 04:52:46 PM PDT 24 67297697 ps
T1019 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3848434570 Jul 07 04:52:50 PM PDT 24 Jul 07 04:52:55 PM PDT 24 154029480 ps
T1020 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1832664045 Jul 07 04:52:39 PM PDT 24 Jul 07 04:52:40 PM PDT 24 58385625 ps
T1021 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3901440288 Jul 07 04:52:34 PM PDT 24 Jul 07 04:52:36 PM PDT 24 21944279 ps
T1022 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2167202477 Jul 07 04:52:54 PM PDT 24 Jul 07 04:52:57 PM PDT 24 49047465 ps
T181 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2991124298 Jul 07 04:52:30 PM PDT 24 Jul 07 04:52:36 PM PDT 24 506023250 ps
T1023 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.293627159 Jul 07 04:52:53 PM PDT 24 Jul 07 04:52:54 PM PDT 24 40216450 ps
T1024 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1484432891 Jul 07 04:53:05 PM PDT 24 Jul 07 04:53:06 PM PDT 24 98884667 ps
T192 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3379474439 Jul 07 04:52:56 PM PDT 24 Jul 07 04:53:01 PM PDT 24 989372477 ps
T1025 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.4274414480 Jul 07 04:53:13 PM PDT 24 Jul 07 04:53:14 PM PDT 24 13890445 ps
T1026 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.392523712 Jul 07 04:52:30 PM PDT 24 Jul 07 04:52:31 PM PDT 24 36728719 ps
T1027 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1735199677 Jul 07 04:53:00 PM PDT 24 Jul 07 04:53:02 PM PDT 24 22351396 ps
T1028 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.311647318 Jul 07 04:53:11 PM PDT 24 Jul 07 04:53:12 PM PDT 24 9696204 ps
T1029 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2339271608 Jul 07 04:52:41 PM PDT 24 Jul 07 04:52:43 PM PDT 24 26546888 ps
T1030 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3380467028 Jul 07 04:53:12 PM PDT 24 Jul 07 04:53:13 PM PDT 24 39478364 ps
T1031 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2864975851 Jul 07 04:52:54 PM PDT 24 Jul 07 04:52:56 PM PDT 24 199206274 ps
T1032 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3928988246 Jul 07 04:52:29 PM PDT 24 Jul 07 04:52:32 PM PDT 24 101222693 ps
T182 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.542576617 Jul 07 04:52:49 PM PDT 24 Jul 07 04:52:54 PM PDT 24 141741427 ps
T1033 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3486596532 Jul 07 04:52:55 PM PDT 24 Jul 07 04:52:56 PM PDT 24 92642671 ps
T1034 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2495343576 Jul 07 04:53:00 PM PDT 24 Jul 07 04:53:01 PM PDT 24 10801465 ps
T1035 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.878476748 Jul 07 04:52:29 PM PDT 24 Jul 07 04:52:33 PM PDT 24 48264261 ps
T184 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3127495426 Jul 07 04:52:50 PM PDT 24 Jul 07 04:52:56 PM PDT 24 142693849 ps
T1036 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.4190029072 Jul 07 04:52:49 PM PDT 24 Jul 07 04:53:04 PM PDT 24 426603617 ps
T1037 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.4241037602 Jul 07 04:53:07 PM PDT 24 Jul 07 04:53:08 PM PDT 24 41976333 ps
T1038 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.416510821 Jul 07 04:53:10 PM PDT 24 Jul 07 04:53:11 PM PDT 24 8594963 ps
T1039 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2829705389 Jul 07 04:52:51 PM PDT 24 Jul 07 04:52:54 PM PDT 24 239399534 ps
T1040 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2100146511 Jul 07 04:53:13 PM PDT 24 Jul 07 04:53:14 PM PDT 24 17253500 ps
T1041 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1438035155 Jul 07 04:52:50 PM PDT 24 Jul 07 04:52:51 PM PDT 24 101596331 ps
T1042 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3663376049 Jul 07 04:52:37 PM PDT 24 Jul 07 04:52:39 PM PDT 24 33350500 ps
T1043 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1774083075 Jul 07 04:53:07 PM PDT 24 Jul 07 04:53:08 PM PDT 24 11298641 ps
T1044 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.449127372 Jul 07 04:52:49 PM PDT 24 Jul 07 04:52:53 PM PDT 24 162777175 ps
T1045 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1046019363 Jul 07 04:53:04 PM PDT 24 Jul 07 04:53:08 PM PDT 24 51952445 ps
T1046 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3813139466 Jul 07 04:52:43 PM PDT 24 Jul 07 04:52:45 PM PDT 24 26120962 ps
T1047 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.785739891 Jul 07 04:52:34 PM PDT 24 Jul 07 04:52:42 PM PDT 24 441377532 ps
T1048 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3537869570 Jul 07 04:52:50 PM PDT 24 Jul 07 04:52:54 PM PDT 24 227828644 ps
T1049 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.378662563 Jul 07 04:52:40 PM PDT 24 Jul 07 04:52:45 PM PDT 24 125561068 ps
T1050 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2248272347 Jul 07 04:52:57 PM PDT 24 Jul 07 04:53:07 PM PDT 24 2304629463 ps
T1051 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.4085403776 Jul 07 04:52:53 PM PDT 24 Jul 07 04:52:55 PM PDT 24 25140511 ps
T1052 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1513853289 Jul 07 04:52:50 PM PDT 24 Jul 07 04:52:53 PM PDT 24 51486171 ps
T1053 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2228633813 Jul 07 04:52:49 PM PDT 24 Jul 07 04:52:53 PM PDT 24 176836973 ps
T1054 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2314932130 Jul 07 04:53:10 PM PDT 24 Jul 07 04:53:11 PM PDT 24 19413447 ps
T1055 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1854113923 Jul 07 04:52:41 PM PDT 24 Jul 07 04:52:43 PM PDT 24 114450834 ps
T1056 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3869745013 Jul 07 04:52:50 PM PDT 24 Jul 07 04:52:52 PM PDT 24 84382942 ps
T1057 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.553168882 Jul 07 04:52:55 PM PDT 24 Jul 07 04:52:59 PM PDT 24 99856329 ps
T1058 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3661958213 Jul 07 04:52:59 PM PDT 24 Jul 07 04:53:00 PM PDT 24 104518005 ps
T1059 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2010862973 Jul 07 04:52:57 PM PDT 24 Jul 07 04:52:59 PM PDT 24 67551622 ps
T1060 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3190392302 Jul 07 04:52:50 PM PDT 24 Jul 07 04:52:56 PM PDT 24 681987234 ps
T1061 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2029828634 Jul 07 04:52:35 PM PDT 24 Jul 07 04:52:40 PM PDT 24 75366819 ps
T1062 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2201196241 Jul 07 04:52:40 PM PDT 24 Jul 07 04:52:42 PM PDT 24 83151095 ps
T1063 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.10494422 Jul 07 04:52:43 PM PDT 24 Jul 07 04:52:44 PM PDT 24 16576777 ps
T1064 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2368929459 Jul 07 04:53:00 PM PDT 24 Jul 07 04:53:01 PM PDT 24 52070534 ps
T1065 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2372179454 Jul 07 04:52:36 PM PDT 24 Jul 07 04:52:37 PM PDT 24 20098401 ps
T1066 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1299395415 Jul 07 04:52:52 PM PDT 24 Jul 07 04:52:56 PM PDT 24 326892941 ps
T1067 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2160384107 Jul 07 04:53:13 PM PDT 24 Jul 07 04:53:14 PM PDT 24 213493273 ps
T1068 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3973141046 Jul 07 04:52:39 PM PDT 24 Jul 07 04:52:40 PM PDT 24 18078006 ps
T1069 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3113314181 Jul 07 04:53:10 PM PDT 24 Jul 07 04:53:11 PM PDT 24 8504840 ps
T1070 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2624555921 Jul 07 04:52:49 PM PDT 24 Jul 07 04:52:52 PM PDT 24 126498317 ps
T1071 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1289707821 Jul 07 04:52:38 PM PDT 24 Jul 07 04:52:56 PM PDT 24 8549240377 ps
T1072 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1047774815 Jul 07 04:52:52 PM PDT 24 Jul 07 04:52:55 PM PDT 24 94696484 ps
T1073 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1864510305 Jul 07 04:52:59 PM PDT 24 Jul 07 04:53:03 PM PDT 24 419438786 ps
T1074 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3526768281 Jul 07 04:52:47 PM PDT 24 Jul 07 04:52:50 PM PDT 24 202931998 ps
T1075 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3175938131 Jul 07 04:52:40 PM PDT 24 Jul 07 04:52:49 PM PDT 24 389796439 ps
T1076 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.4098319416 Jul 07 04:52:37 PM PDT 24 Jul 07 04:52:43 PM PDT 24 258484098 ps
T1077 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3779795837 Jul 07 04:52:37 PM PDT 24 Jul 07 04:53:03 PM PDT 24 3553068815 ps
T1078 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.23059061 Jul 07 04:52:44 PM PDT 24 Jul 07 04:52:46 PM PDT 24 29472743 ps
T1079 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1566252505 Jul 07 04:52:45 PM PDT 24 Jul 07 04:52:48 PM PDT 24 51582049 ps
T1080 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1056383131 Jul 07 04:52:38 PM PDT 24 Jul 07 04:52:40 PM PDT 24 21938359 ps
T1081 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.4217954799 Jul 07 04:52:42 PM PDT 24 Jul 07 04:52:54 PM PDT 24 446414028 ps
T1082 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.791950187 Jul 07 04:52:40 PM PDT 24 Jul 07 04:52:41 PM PDT 24 24155381 ps

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3294958316
Short name T3
Test name
Test status
Simulation time 234465468 ps
CPU time 9.85 seconds
Started Jul 07 05:06:49 PM PDT 24
Finished Jul 07 05:07:00 PM PDT 24
Peak memory 220592 kb
Host smart-b3d21477-f3e9-42b4-8ca9-2be1afb68a7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294958316 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3294958316
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1653754011
Short name T51
Test name
Test status
Simulation time 29196661183 ps
CPU time 317.67 seconds
Started Jul 07 05:08:08 PM PDT 24
Finished Jul 07 05:13:27 PM PDT 24
Peak memory 222648 kb
Host smart-aa08b0a3-198b-44bb-8fba-5c3c7f9ac907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653754011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1653754011
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.70267413
Short name T61
Test name
Test status
Simulation time 236428183 ps
CPU time 8.23 seconds
Started Jul 07 05:09:23 PM PDT 24
Finished Jul 07 05:09:32 PM PDT 24
Peak memory 222604 kb
Host smart-1d6bba7c-9fc9-4ecd-9e7d-09417bf56e3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70267413 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.70267413
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2927592960
Short name T33
Test name
Test status
Simulation time 3721610545 ps
CPU time 52.72 seconds
Started Jul 07 05:07:05 PM PDT 24
Finished Jul 07 05:07:58 PM PDT 24
Peak memory 222500 kb
Host smart-aa8d4654-716e-4e51-83c4-489c69501cee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927592960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2927592960
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1262060004
Short name T9
Test name
Test status
Simulation time 2077862801 ps
CPU time 12.52 seconds
Started Jul 07 05:06:29 PM PDT 24
Finished Jul 07 05:06:42 PM PDT 24
Peak memory 231236 kb
Host smart-9a3f9928-37a5-4dbf-b0d5-adcfd29e18fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262060004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1262060004
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2548655567
Short name T77
Test name
Test status
Simulation time 34234963842 ps
CPU time 403.55 seconds
Started Jul 07 05:08:28 PM PDT 24
Finished Jul 07 05:15:12 PM PDT 24
Peak memory 222460 kb
Host smart-bae6b33b-ecb0-4635-b09c-5fc5b69bf2e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548655567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2548655567
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.200479107
Short name T14
Test name
Test status
Simulation time 330610796 ps
CPU time 4.6 seconds
Started Jul 07 05:09:07 PM PDT 24
Finished Jul 07 05:09:12 PM PDT 24
Peak memory 214228 kb
Host smart-25f1dad3-d745-4134-9a00-2dc87bfde548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200479107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.200479107
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1406677919
Short name T60
Test name
Test status
Simulation time 1067680267 ps
CPU time 38.65 seconds
Started Jul 07 05:09:24 PM PDT 24
Finished Jul 07 05:10:03 PM PDT 24
Peak memory 215136 kb
Host smart-13051913-853d-49b7-b092-834d05a72435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406677919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1406677919
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3596199169
Short name T49
Test name
Test status
Simulation time 481059525 ps
CPU time 5.21 seconds
Started Jul 07 05:08:18 PM PDT 24
Finished Jul 07 05:08:24 PM PDT 24
Peak memory 222376 kb
Host smart-31b40b36-8989-42c0-9355-cd6e0e9c1679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596199169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3596199169
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1515402326
Short name T134
Test name
Test status
Simulation time 650275509 ps
CPU time 9.23 seconds
Started Jul 07 05:08:35 PM PDT 24
Finished Jul 07 05:08:45 PM PDT 24
Peak memory 214224 kb
Host smart-bb8f2fc3-9564-40db-8a1c-e0509debceb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515402326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1515402326
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3563672133
Short name T119
Test name
Test status
Simulation time 293585741 ps
CPU time 3.55 seconds
Started Jul 07 04:52:59 PM PDT 24
Finished Jul 07 04:53:03 PM PDT 24
Peak memory 213932 kb
Host smart-e39f9b0d-a036-491b-b020-fa8d6111c68d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563672133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3563672133
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.881520506
Short name T141
Test name
Test status
Simulation time 1818477097 ps
CPU time 6.49 seconds
Started Jul 07 05:09:23 PM PDT 24
Finished Jul 07 05:09:30 PM PDT 24
Peak memory 215128 kb
Host smart-cc546324-a2d5-4eca-844c-e0638c05e659
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=881520506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.881520506
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2028166164
Short name T247
Test name
Test status
Simulation time 1148038437 ps
CPU time 14.82 seconds
Started Jul 07 05:08:26 PM PDT 24
Finished Jul 07 05:08:42 PM PDT 24
Peak memory 222424 kb
Host smart-b36056cb-a218-41b6-9f1d-b38e7f1bfe46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2028166164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2028166164
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.3738268074
Short name T41
Test name
Test status
Simulation time 394439948 ps
CPU time 15.77 seconds
Started Jul 07 05:07:21 PM PDT 24
Finished Jul 07 05:07:37 PM PDT 24
Peak memory 222620 kb
Host smart-59d27bb3-f474-4112-b993-f4b64ce1944d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738268074 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.3738268074
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1532946868
Short name T13
Test name
Test status
Simulation time 172153192 ps
CPU time 3.25 seconds
Started Jul 07 05:08:52 PM PDT 24
Finished Jul 07 05:08:55 PM PDT 24
Peak memory 214552 kb
Host smart-c8df9073-b10a-497d-bb9a-8aa5ea3c84e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532946868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1532946868
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1202812688
Short name T19
Test name
Test status
Simulation time 116418571 ps
CPU time 5.11 seconds
Started Jul 07 05:07:26 PM PDT 24
Finished Jul 07 05:07:31 PM PDT 24
Peak memory 222440 kb
Host smart-d9f53c04-ea05-4a2e-8355-c79c3521133c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202812688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1202812688
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.4280640793
Short name T409
Test name
Test status
Simulation time 1228955820 ps
CPU time 16.35 seconds
Started Jul 07 05:09:16 PM PDT 24
Finished Jul 07 05:09:33 PM PDT 24
Peak memory 222416 kb
Host smart-a5633770-0be1-4c3e-9451-dbceec6e9439
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4280640793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.4280640793
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3913324663
Short name T46
Test name
Test status
Simulation time 22973217697 ps
CPU time 214.16 seconds
Started Jul 07 05:09:24 PM PDT 24
Finished Jul 07 05:12:59 PM PDT 24
Peak memory 221824 kb
Host smart-3230c4aa-f987-4102-9e39-393f37f93fb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913324663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3913324663
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1288558283
Short name T128
Test name
Test status
Simulation time 1487293524 ps
CPU time 9.08 seconds
Started Jul 07 04:52:35 PM PDT 24
Finished Jul 07 04:52:45 PM PDT 24
Peak memory 219740 kb
Host smart-148f865d-8bdb-46bb-a855-9ff6114b7f3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288558283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1288558283
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3493652518
Short name T52
Test name
Test status
Simulation time 452122443 ps
CPU time 10.89 seconds
Started Jul 07 05:07:47 PM PDT 24
Finished Jul 07 05:07:59 PM PDT 24
Peak memory 222620 kb
Host smart-2207be7b-5db2-447d-8677-881fbb9a30bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493652518 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3493652518
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2055341799
Short name T21
Test name
Test status
Simulation time 3787664621 ps
CPU time 67.45 seconds
Started Jul 07 05:06:34 PM PDT 24
Finished Jul 07 05:07:42 PM PDT 24
Peak memory 214300 kb
Host smart-d3efe073-6962-4c01-bc99-ce0113d924ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055341799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2055341799
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1559826069
Short name T297
Test name
Test status
Simulation time 311357792 ps
CPU time 16.36 seconds
Started Jul 07 05:08:07 PM PDT 24
Finished Jul 07 05:08:24 PM PDT 24
Peak memory 215420 kb
Host smart-7a6f22c2-72c1-4cf2-990d-45babe208862
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559826069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1559826069
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.253246051
Short name T133
Test name
Test status
Simulation time 42581005 ps
CPU time 3.15 seconds
Started Jul 07 05:07:27 PM PDT 24
Finished Jul 07 05:07:30 PM PDT 24
Peak memory 215480 kb
Host smart-f7d60ae8-0479-4319-b5a6-96e6392f72c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=253246051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.253246051
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3926189150
Short name T36
Test name
Test status
Simulation time 567404762 ps
CPU time 4.93 seconds
Started Jul 07 05:07:54 PM PDT 24
Finished Jul 07 05:08:00 PM PDT 24
Peak memory 210612 kb
Host smart-c6bca01a-20bb-47e1-b68d-4ce64af1cdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926189150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3926189150
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1738540990
Short name T144
Test name
Test status
Simulation time 238299222 ps
CPU time 6.6 seconds
Started Jul 07 05:06:44 PM PDT 24
Finished Jul 07 05:06:51 PM PDT 24
Peak memory 222660 kb
Host smart-df73132e-b702-4119-99bf-d8f4badc1fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738540990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1738540990
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3087537135
Short name T410
Test name
Test status
Simulation time 257089043 ps
CPU time 13.54 seconds
Started Jul 07 05:08:13 PM PDT 24
Finished Jul 07 05:08:27 PM PDT 24
Peak memory 214336 kb
Host smart-186adfdf-f71a-45a2-9e13-aafe633806d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3087537135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3087537135
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3633691426
Short name T300
Test name
Test status
Simulation time 172532230 ps
CPU time 9.7 seconds
Started Jul 07 05:07:52 PM PDT 24
Finished Jul 07 05:08:02 PM PDT 24
Peak memory 214584 kb
Host smart-6667d2d9-24fd-46d1-81b4-65eb8d72eb3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3633691426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3633691426
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.4266522153
Short name T29
Test name
Test status
Simulation time 66238642 ps
CPU time 2.36 seconds
Started Jul 07 05:08:52 PM PDT 24
Finished Jul 07 05:08:55 PM PDT 24
Peak memory 214184 kb
Host smart-fd036301-3bb3-428a-8a9b-015cf01ed49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266522153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.4266522153
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2362562537
Short name T71
Test name
Test status
Simulation time 439603581 ps
CPU time 12.99 seconds
Started Jul 07 05:08:28 PM PDT 24
Finished Jul 07 05:08:42 PM PDT 24
Peak memory 220296 kb
Host smart-af2c418c-4a3a-4ab5-a8f0-1d3d9c99ab64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362562537 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2362562537
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2025043337
Short name T1
Test name
Test status
Simulation time 291932136 ps
CPU time 2.53 seconds
Started Jul 07 05:08:21 PM PDT 24
Finished Jul 07 05:08:24 PM PDT 24
Peak memory 210068 kb
Host smart-731bb716-64ab-40bd-9672-a3157d8cf477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025043337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2025043337
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2285854823
Short name T78
Test name
Test status
Simulation time 1700344949 ps
CPU time 58.03 seconds
Started Jul 07 05:07:21 PM PDT 24
Finished Jul 07 05:08:20 PM PDT 24
Peak memory 217136 kb
Host smart-9a9e2502-2c99-45de-af92-4c6ea4921433
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285854823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2285854823
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2223949837
Short name T293
Test name
Test status
Simulation time 128588699 ps
CPU time 4.2 seconds
Started Jul 07 05:09:07 PM PDT 24
Finished Jul 07 05:09:11 PM PDT 24
Peak memory 214288 kb
Host smart-3bfc16e4-29a9-40aa-b768-70b2bb3bd82f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223949837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2223949837
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3183011959
Short name T132
Test name
Test status
Simulation time 154532469 ps
CPU time 4.59 seconds
Started Jul 07 05:08:19 PM PDT 24
Finished Jul 07 05:08:24 PM PDT 24
Peak memory 214332 kb
Host smart-da19fea7-7d28-4865-9bbd-528129c32d14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3183011959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3183011959
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.4256520458
Short name T420
Test name
Test status
Simulation time 82018306 ps
CPU time 0.81 seconds
Started Jul 07 05:06:10 PM PDT 24
Finished Jul 07 05:06:11 PM PDT 24
Peak memory 205912 kb
Host smart-15798f8e-028a-4a9c-a0ff-2d54139d447e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256520458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.4256520458
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.224442668
Short name T97
Test name
Test status
Simulation time 785227279 ps
CPU time 3.85 seconds
Started Jul 07 05:06:46 PM PDT 24
Finished Jul 07 05:06:50 PM PDT 24
Peak memory 214220 kb
Host smart-1faa0a0d-705f-434b-96da-43616f98044f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224442668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.224442668
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3516581129
Short name T189
Test name
Test status
Simulation time 103084449 ps
CPU time 2.68 seconds
Started Jul 07 04:52:54 PM PDT 24
Finished Jul 07 04:52:58 PM PDT 24
Peak memory 205388 kb
Host smart-c3c4f132-6800-46b4-b21d-f34ad9869604
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516581129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3516581129
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3595591648
Short name T48
Test name
Test status
Simulation time 1377958886 ps
CPU time 51 seconds
Started Jul 07 05:08:28 PM PDT 24
Finished Jul 07 05:09:19 PM PDT 24
Peak memory 215256 kb
Host smart-591f149f-15fc-47e3-92e5-1fd5e80180c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595591648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3595591648
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.575147792
Short name T76
Test name
Test status
Simulation time 1312792898 ps
CPU time 18.55 seconds
Started Jul 07 05:08:47 PM PDT 24
Finished Jul 07 05:09:06 PM PDT 24
Peak memory 215916 kb
Host smart-bc6717e3-5024-46f7-bd7d-cc9756d66a0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575147792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.575147792
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2086985111
Short name T27
Test name
Test status
Simulation time 170916207 ps
CPU time 5.04 seconds
Started Jul 07 05:07:52 PM PDT 24
Finished Jul 07 05:07:57 PM PDT 24
Peak memory 214676 kb
Host smart-c6a15efe-64e4-4d32-9ebd-148d8d3eedb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086985111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2086985111
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.4272415410
Short name T267
Test name
Test status
Simulation time 2609181985 ps
CPU time 26.13 seconds
Started Jul 07 05:06:31 PM PDT 24
Finished Jul 07 05:06:58 PM PDT 24
Peak memory 214376 kb
Host smart-d94d08aa-8f41-4073-a203-aaa8610ef294
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272415410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.4272415410
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.711689585
Short name T396
Test name
Test status
Simulation time 743004663 ps
CPU time 6.89 seconds
Started Jul 07 05:08:20 PM PDT 24
Finished Jul 07 05:08:28 PM PDT 24
Peak memory 214300 kb
Host smart-bab242d2-90b2-43a3-9fa2-1c86585ca34a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=711689585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.711689585
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.542576617
Short name T182
Test name
Test status
Simulation time 141741427 ps
CPU time 4.57 seconds
Started Jul 07 04:52:49 PM PDT 24
Finished Jul 07 04:52:54 PM PDT 24
Peak memory 213732 kb
Host smart-bdb5b92c-346e-46ba-aa21-93102e49b3ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542576617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.542576617
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1730274751
Short name T72
Test name
Test status
Simulation time 2416480520 ps
CPU time 28.1 seconds
Started Jul 07 05:07:45 PM PDT 24
Finished Jul 07 05:08:13 PM PDT 24
Peak memory 220896 kb
Host smart-cb9bdeb9-1b9b-47ab-b313-0e7ae6ce6295
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730274751 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1730274751
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3962658478
Short name T7
Test name
Test status
Simulation time 1530161761 ps
CPU time 20.93 seconds
Started Jul 07 05:08:27 PM PDT 24
Finished Jul 07 05:08:48 PM PDT 24
Peak memory 217172 kb
Host smart-826b82e6-2bac-444a-a9fb-285e9cce8a24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962658478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3962658478
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3868177927
Short name T191
Test name
Test status
Simulation time 140762416 ps
CPU time 5.96 seconds
Started Jul 07 04:53:05 PM PDT 24
Finished Jul 07 04:53:11 PM PDT 24
Peak memory 213520 kb
Host smart-61383621-d719-4238-bd74-144aed3d19f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868177927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3868177927
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2637028817
Short name T211
Test name
Test status
Simulation time 3317172928 ps
CPU time 33.38 seconds
Started Jul 07 05:08:07 PM PDT 24
Finished Jul 07 05:08:41 PM PDT 24
Peak memory 222592 kb
Host smart-0b8670aa-420f-4f6a-96c3-f0c525a183cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637028817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2637028817
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1185394606
Short name T174
Test name
Test status
Simulation time 106006596 ps
CPU time 5.39 seconds
Started Jul 07 04:52:49 PM PDT 24
Finished Jul 07 04:52:55 PM PDT 24
Peak memory 213596 kb
Host smart-7eb2d740-ec51-4488-9416-008ac8bcf6f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185394606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1185394606
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3596090806
Short name T54
Test name
Test status
Simulation time 424817570 ps
CPU time 3.35 seconds
Started Jul 07 05:07:55 PM PDT 24
Finished Jul 07 05:07:59 PM PDT 24
Peak memory 222232 kb
Host smart-8779c35e-a3f7-4e19-aa9b-59390cf16787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596090806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3596090806
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.28523499
Short name T120
Test name
Test status
Simulation time 409801722 ps
CPU time 3.8 seconds
Started Jul 07 04:52:33 PM PDT 24
Finished Jul 07 04:52:37 PM PDT 24
Peak memory 213900 kb
Host smart-0afa95b4-de4d-4817-81a0-b1d134dee1ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28523499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.ke
ymgr_shadow_reg_errors_with_csr_rw.28523499
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2884273859
Short name T230
Test name
Test status
Simulation time 1290785465 ps
CPU time 22 seconds
Started Jul 07 05:07:09 PM PDT 24
Finished Jul 07 05:07:31 PM PDT 24
Peak memory 222476 kb
Host smart-c923e670-8a7a-423f-b31b-4a5893c60837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884273859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2884273859
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2230549932
Short name T272
Test name
Test status
Simulation time 102967077 ps
CPU time 2.84 seconds
Started Jul 07 05:07:14 PM PDT 24
Finished Jul 07 05:07:17 PM PDT 24
Peak memory 222480 kb
Host smart-d79ef401-d1c4-47a9-b693-7dac89c7090a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230549932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2230549932
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3231650453
Short name T309
Test name
Test status
Simulation time 133082172 ps
CPU time 6.31 seconds
Started Jul 07 05:07:42 PM PDT 24
Finished Jul 07 05:07:49 PM PDT 24
Peak memory 222308 kb
Host smart-cb18c40c-eda7-4bde-93ba-9480c0e23c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231650453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3231650453
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.905917850
Short name T263
Test name
Test status
Simulation time 1855127765 ps
CPU time 38.26 seconds
Started Jul 07 05:08:06 PM PDT 24
Finished Jul 07 05:08:45 PM PDT 24
Peak memory 215528 kb
Host smart-96e4fac2-04a5-408e-8c62-723cd2ffdd7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=905917850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.905917850
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1067498189
Short name T208
Test name
Test status
Simulation time 202178904 ps
CPU time 6.18 seconds
Started Jul 07 05:08:04 PM PDT 24
Finished Jul 07 05:08:10 PM PDT 24
Peak memory 207908 kb
Host smart-2c87452f-daa3-4a0e-8523-7fb545bdda10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067498189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1067498189
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.4044137138
Short name T227
Test name
Test status
Simulation time 1098855645 ps
CPU time 15.97 seconds
Started Jul 07 05:09:03 PM PDT 24
Finished Jul 07 05:09:19 PM PDT 24
Peak memory 216528 kb
Host smart-370dad03-ef2a-402c-9fd2-408d752224d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044137138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.4044137138
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3358485537
Short name T147
Test name
Test status
Simulation time 339932537 ps
CPU time 2.76 seconds
Started Jul 07 05:09:23 PM PDT 24
Finished Jul 07 05:09:26 PM PDT 24
Peak memory 218128 kb
Host smart-115b0c81-09dd-4897-83f5-58e4c7a9a7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358485537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3358485537
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2991124298
Short name T181
Test name
Test status
Simulation time 506023250 ps
CPU time 5.87 seconds
Started Jul 07 04:52:30 PM PDT 24
Finished Jul 07 04:52:36 PM PDT 24
Peak memory 213692 kb
Host smart-df349d6f-f275-4480-a6d2-ea53a2b80bab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991124298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2991124298
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1850421447
Short name T234
Test name
Test status
Simulation time 150663332 ps
CPU time 9 seconds
Started Jul 07 05:07:01 PM PDT 24
Finished Jul 07 05:07:11 PM PDT 24
Peak memory 214332 kb
Host smart-034285d2-a995-45d9-b655-592c8ff83adf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1850421447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1850421447
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.118516296
Short name T408
Test name
Test status
Simulation time 125768009 ps
CPU time 6.56 seconds
Started Jul 07 05:07:14 PM PDT 24
Finished Jul 07 05:07:21 PM PDT 24
Peak memory 215428 kb
Host smart-5cc090ac-4476-4055-9ed3-11dac034aa69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=118516296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.118516296
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1579960378
Short name T316
Test name
Test status
Simulation time 1900860573 ps
CPU time 9.94 seconds
Started Jul 07 05:06:22 PM PDT 24
Finished Jul 07 05:06:32 PM PDT 24
Peak memory 218080 kb
Host smart-33490686-af63-4d82-8525-70f785e9fc6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579960378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1579960378
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1008564247
Short name T231
Test name
Test status
Simulation time 412521183 ps
CPU time 10.27 seconds
Started Jul 07 05:06:23 PM PDT 24
Finished Jul 07 05:06:33 PM PDT 24
Peak memory 219968 kb
Host smart-1f7d9572-1294-459d-a2b8-20f7b4c17f4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008564247 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1008564247
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.4266493470
Short name T330
Test name
Test status
Simulation time 114979975 ps
CPU time 4.01 seconds
Started Jul 07 05:08:24 PM PDT 24
Finished Jul 07 05:08:29 PM PDT 24
Peak memory 214256 kb
Host smart-1159d6c7-e354-476b-bc17-c2cd0638dce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266493470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.4266493470
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.979789594
Short name T688
Test name
Test status
Simulation time 867959955 ps
CPU time 2.94 seconds
Started Jul 07 05:08:43 PM PDT 24
Finished Jul 07 05:08:46 PM PDT 24
Peak memory 210332 kb
Host smart-fd3e3d3f-22d3-4e02-9d4d-259d5b71b95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979789594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.979789594
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3780597003
Short name T277
Test name
Test status
Simulation time 226524928 ps
CPU time 4.18 seconds
Started Jul 07 05:06:53 PM PDT 24
Finished Jul 07 05:06:58 PM PDT 24
Peak memory 215152 kb
Host smart-ebe433f3-60c8-4b21-a795-fc3ae22ee2de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3780597003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3780597003
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3175295319
Short name T180
Test name
Test status
Simulation time 303446707 ps
CPU time 7.07 seconds
Started Jul 07 04:53:07 PM PDT 24
Finished Jul 07 04:53:14 PM PDT 24
Peak memory 213696 kb
Host smart-3a3428c3-0e4d-45f9-845b-0bb8f377b703
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175295319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3175295319
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3106174223
Short name T186
Test name
Test status
Simulation time 1021380962 ps
CPU time 4.97 seconds
Started Jul 07 05:08:12 PM PDT 24
Finished Jul 07 05:08:17 PM PDT 24
Peak memory 210476 kb
Host smart-22a26519-76c3-4a6b-969d-f63a0824b0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106174223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3106174223
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.556319270
Short name T146
Test name
Test status
Simulation time 142536869 ps
CPU time 3.14 seconds
Started Jul 07 05:07:10 PM PDT 24
Finished Jul 07 05:07:14 PM PDT 24
Peak memory 217436 kb
Host smart-13ddd85e-c1fc-41ac-a259-1962a16c7cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556319270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.556319270
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2044223169
Short name T67
Test name
Test status
Simulation time 130268359 ps
CPU time 5.63 seconds
Started Jul 07 05:09:12 PM PDT 24
Finished Jul 07 05:09:18 PM PDT 24
Peak memory 222692 kb
Host smart-cd81b042-a8fd-4718-a801-95f6131e144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044223169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2044223169
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2337467821
Short name T145
Test name
Test status
Simulation time 54208552 ps
CPU time 2.43 seconds
Started Jul 07 05:07:03 PM PDT 24
Finished Jul 07 05:07:06 PM PDT 24
Peak memory 222700 kb
Host smart-f353f4d7-d012-423a-89d5-dd3d4712a8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337467821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2337467821
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.1797743456
Short name T245
Test name
Test status
Simulation time 584179537 ps
CPU time 21.62 seconds
Started Jul 07 05:07:17 PM PDT 24
Finished Jul 07 05:07:39 PM PDT 24
Peak memory 222468 kb
Host smart-d56653bd-8fed-443b-abea-7a5df72b0b07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797743456 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.1797743456
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1697924597
Short name T167
Test name
Test status
Simulation time 3209570464 ps
CPU time 25.41 seconds
Started Jul 07 05:07:18 PM PDT 24
Finished Jul 07 05:07:44 PM PDT 24
Peak memory 222624 kb
Host smart-0c966cfe-160a-4e83-954a-d0576ce3fa87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697924597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1697924597
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.28285268
Short name T333
Test name
Test status
Simulation time 1276057154 ps
CPU time 70.96 seconds
Started Jul 07 05:07:23 PM PDT 24
Finished Jul 07 05:08:35 PM PDT 24
Peak memory 215540 kb
Host smart-5fa3d382-55a7-4ce9-89e7-03947df53b5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28285268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.28285268
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3153081088
Short name T371
Test name
Test status
Simulation time 117471996 ps
CPU time 2.26 seconds
Started Jul 07 05:07:27 PM PDT 24
Finished Jul 07 05:07:30 PM PDT 24
Peak memory 221256 kb
Host smart-74219ac7-e3df-48a4-a118-d4c75883c75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153081088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3153081088
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3975040180
Short name T296
Test name
Test status
Simulation time 418998925 ps
CPU time 8.73 seconds
Started Jul 07 05:07:31 PM PDT 24
Finished Jul 07 05:07:41 PM PDT 24
Peak memory 214420 kb
Host smart-21461b61-0b3f-46ef-bfa5-2bef4c9766d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975040180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3975040180
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3933107611
Short name T281
Test name
Test status
Simulation time 144322926 ps
CPU time 3.7 seconds
Started Jul 07 05:07:54 PM PDT 24
Finished Jul 07 05:07:59 PM PDT 24
Peak memory 206760 kb
Host smart-ad5a6292-46df-4d5b-88e7-80080d944652
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933107611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3933107611
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.4096973858
Short name T374
Test name
Test status
Simulation time 34245922 ps
CPU time 2.61 seconds
Started Jul 07 05:08:41 PM PDT 24
Finished Jul 07 05:08:45 PM PDT 24
Peak memory 209424 kb
Host smart-5915f9c0-8f2c-48d9-bf89-13db96aa76ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096973858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.4096973858
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1699912047
Short name T236
Test name
Test status
Simulation time 314460200 ps
CPU time 5.25 seconds
Started Jul 07 05:09:32 PM PDT 24
Finished Jul 07 05:09:37 PM PDT 24
Peak memory 208896 kb
Host smart-ca95fabe-0733-48ea-b305-0c175fea97f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699912047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1699912047
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1578437376
Short name T168
Test name
Test status
Simulation time 3187010303 ps
CPU time 41.24 seconds
Started Jul 07 05:06:54 PM PDT 24
Finished Jul 07 05:07:36 PM PDT 24
Peak memory 222580 kb
Host smart-e73ce037-1e42-401c-9dec-9e019f6127c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578437376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1578437376
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2655528394
Short name T183
Test name
Test status
Simulation time 488715073 ps
CPU time 3.78 seconds
Started Jul 07 04:52:51 PM PDT 24
Finished Jul 07 04:52:55 PM PDT 24
Peak memory 213592 kb
Host smart-4d9441ea-2bb0-4b91-a3ac-9edc17cb033b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655528394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2655528394
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3379474439
Short name T192
Test name
Test status
Simulation time 989372477 ps
CPU time 5 seconds
Started Jul 07 04:52:56 PM PDT 24
Finished Jul 07 04:53:01 PM PDT 24
Peak memory 213712 kb
Host smart-eafecfc7-a0b8-470a-8e4e-a38dffc4b0f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379474439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3379474439
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3778565921
Short name T178
Test name
Test status
Simulation time 203207978 ps
CPU time 3.42 seconds
Started Jul 07 04:53:02 PM PDT 24
Finished Jul 07 04:53:05 PM PDT 24
Peak memory 205604 kb
Host smart-b47d7f06-8b66-4ffd-ae9b-3e0d3e4f9037
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778565921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3778565921
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3530875197
Short name T173
Test name
Test status
Simulation time 4364287318 ps
CPU time 9.17 seconds
Started Jul 07 04:52:44 PM PDT 24
Finished Jul 07 04:52:54 PM PDT 24
Peak memory 213620 kb
Host smart-8f22cc88-4f17-4019-a347-9fbea3308103
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530875197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3530875197
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.983935726
Short name T185
Test name
Test status
Simulation time 134977267 ps
CPU time 4.34 seconds
Started Jul 07 04:52:54 PM PDT 24
Finished Jul 07 04:52:59 PM PDT 24
Peak memory 205228 kb
Host smart-07d2c3e8-d337-4de7-86e6-836a9abbde2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983935726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
983935726
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3884390678
Short name T150
Test name
Test status
Simulation time 117227817 ps
CPU time 2.89 seconds
Started Jul 07 05:06:20 PM PDT 24
Finished Jul 07 05:06:24 PM PDT 24
Peak memory 222652 kb
Host smart-63fc0cab-a96b-436f-8203-403f56be3e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884390678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3884390678
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2577383043
Short name T59
Test name
Test status
Simulation time 90201654 ps
CPU time 4.67 seconds
Started Jul 07 05:08:40 PM PDT 24
Finished Jul 07 05:08:45 PM PDT 24
Peak memory 218408 kb
Host smart-52fdfb4c-569d-4ed4-898e-3ce0331fd243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577383043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2577383043
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2651411915
Short name T149
Test name
Test status
Simulation time 73385648 ps
CPU time 4.21 seconds
Started Jul 07 05:09:33 PM PDT 24
Finished Jul 07 05:09:38 PM PDT 24
Peak memory 218468 kb
Host smart-4e9a3ffe-8619-4818-a155-078d46ed0a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651411915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2651411915
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2528741727
Short name T148
Test name
Test status
Simulation time 492540764 ps
CPU time 6.95 seconds
Started Jul 07 05:07:13 PM PDT 24
Finished Jul 07 05:07:20 PM PDT 24
Peak memory 222656 kb
Host smart-6ccb7375-3835-463a-8fa5-9af3fee30f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528741727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2528741727
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.184799065
Short name T38
Test name
Test status
Simulation time 293359666 ps
CPU time 2.86 seconds
Started Jul 07 05:06:09 PM PDT 24
Finished Jul 07 05:06:12 PM PDT 24
Peak memory 220672 kb
Host smart-7656cbbe-2275-4f88-bf69-86ca75c9f069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184799065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.184799065
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.691283808
Short name T88
Test name
Test status
Simulation time 172881676 ps
CPU time 6.67 seconds
Started Jul 07 05:07:05 PM PDT 24
Finished Jul 07 05:07:12 PM PDT 24
Peak memory 214316 kb
Host smart-fc2123ea-4f91-4688-8963-d6612e131a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691283808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.691283808
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3225192483
Short name T259
Test name
Test status
Simulation time 667901066 ps
CPU time 5.01 seconds
Started Jul 07 05:07:05 PM PDT 24
Finished Jul 07 05:07:10 PM PDT 24
Peak memory 214184 kb
Host smart-ff700aff-d295-4683-be68-9e2c0f6837c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225192483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3225192483
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.851692208
Short name T677
Test name
Test status
Simulation time 98217175 ps
CPU time 2.9 seconds
Started Jul 07 05:07:22 PM PDT 24
Finished Jul 07 05:07:25 PM PDT 24
Peak memory 214256 kb
Host smart-28ea449b-0641-4fde-a1ea-9cded80732e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851692208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.851692208
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.289351844
Short name T357
Test name
Test status
Simulation time 150610107 ps
CPU time 3.15 seconds
Started Jul 07 05:07:30 PM PDT 24
Finished Jul 07 05:07:33 PM PDT 24
Peak memory 222452 kb
Host smart-eba08727-dfe9-48a7-8768-8dff4b4ca019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289351844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.289351844
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3425558762
Short name T345
Test name
Test status
Simulation time 117002808 ps
CPU time 4.34 seconds
Started Jul 07 05:07:36 PM PDT 24
Finished Jul 07 05:07:41 PM PDT 24
Peak memory 207644 kb
Host smart-263123fa-dc0d-4728-b420-9bbc51ffcc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425558762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3425558762
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3544832443
Short name T217
Test name
Test status
Simulation time 132654191 ps
CPU time 6.69 seconds
Started Jul 07 05:07:40 PM PDT 24
Finished Jul 07 05:07:47 PM PDT 24
Peak memory 222520 kb
Host smart-38b8a88e-3316-4a31-acff-f97501c13746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544832443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3544832443
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3618628241
Short name T830
Test name
Test status
Simulation time 322352956 ps
CPU time 5.34 seconds
Started Jul 07 05:07:41 PM PDT 24
Finished Jul 07 05:07:46 PM PDT 24
Peak memory 208444 kb
Host smart-235a45e5-a846-4fde-94d1-1f379db0ef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618628241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3618628241
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.474965526
Short name T232
Test name
Test status
Simulation time 2197847950 ps
CPU time 16.41 seconds
Started Jul 07 05:07:44 PM PDT 24
Finished Jul 07 05:08:02 PM PDT 24
Peak memory 214852 kb
Host smart-5cc48ffa-58fa-40cc-b019-593bba8b27b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474965526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.474965526
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.353004473
Short name T342
Test name
Test status
Simulation time 263046017 ps
CPU time 2.75 seconds
Started Jul 07 05:07:44 PM PDT 24
Finished Jul 07 05:07:48 PM PDT 24
Peak memory 207184 kb
Host smart-098451e9-5849-4b7f-ad5e-64c83787e6b4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353004473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.353004473
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.4040513902
Short name T303
Test name
Test status
Simulation time 69055033 ps
CPU time 4.48 seconds
Started Jul 07 05:06:24 PM PDT 24
Finished Jul 07 05:06:29 PM PDT 24
Peak memory 215240 kb
Host smart-35386c03-5801-4eb1-bfe7-af6becdf3b74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040513902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.4040513902
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.627077791
Short name T368
Test name
Test status
Simulation time 1044659261 ps
CPU time 10.98 seconds
Started Jul 07 05:07:51 PM PDT 24
Finished Jul 07 05:08:03 PM PDT 24
Peak memory 222628 kb
Host smart-59a9f2b4-04e7-4e12-9b5d-be1d63b34792
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627077791 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.627077791
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.580911954
Short name T320
Test name
Test status
Simulation time 1370856871 ps
CPU time 47.78 seconds
Started Jul 07 05:07:56 PM PDT 24
Finished Jul 07 05:08:44 PM PDT 24
Peak memory 216120 kb
Host smart-e7e93e54-735a-42ae-b9c4-d7952d418766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580911954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.580911954
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.4139579468
Short name T283
Test name
Test status
Simulation time 231781482 ps
CPU time 4.4 seconds
Started Jul 07 05:07:59 PM PDT 24
Finished Jul 07 05:08:04 PM PDT 24
Peak memory 214280 kb
Host smart-bd6e4aa8-4081-40a1-8417-1fe694240414
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4139579468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.4139579468
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1166283872
Short name T428
Test name
Test status
Simulation time 334713178 ps
CPU time 3.51 seconds
Started Jul 07 05:08:01 PM PDT 24
Finished Jul 07 05:08:05 PM PDT 24
Peak memory 209012 kb
Host smart-2833eb86-3982-4394-8f26-01f166451a1d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166283872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1166283872
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2249907237
Short name T16
Test name
Test status
Simulation time 392439468 ps
CPU time 5.57 seconds
Started Jul 07 05:08:10 PM PDT 24
Finished Jul 07 05:08:16 PM PDT 24
Peak memory 209020 kb
Host smart-d98d66f3-0a3e-4974-a1c3-ebcfa3319e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249907237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2249907237
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3745381485
Short name T278
Test name
Test status
Simulation time 88458711 ps
CPU time 3.85 seconds
Started Jul 07 05:08:11 PM PDT 24
Finished Jul 07 05:08:16 PM PDT 24
Peak memory 214312 kb
Host smart-6f69c44c-ede2-47d0-bd43-276e6b5b80d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745381485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3745381485
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.2886443675
Short name T130
Test name
Test status
Simulation time 1312108340 ps
CPU time 26.27 seconds
Started Jul 07 05:08:25 PM PDT 24
Finished Jul 07 05:08:52 PM PDT 24
Peak memory 222608 kb
Host smart-d34910c1-4604-4fa4-84d2-18fdeda09c00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886443675 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.2886443675
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1257613259
Short name T318
Test name
Test status
Simulation time 1085648506 ps
CPU time 5.27 seconds
Started Jul 07 05:08:57 PM PDT 24
Finished Jul 07 05:09:02 PM PDT 24
Peak memory 209824 kb
Host smart-54fe2912-ee5a-4002-9893-8ee7e6aee383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257613259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1257613259
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.4245767070
Short name T298
Test name
Test status
Simulation time 295910813 ps
CPU time 7.48 seconds
Started Jul 07 05:06:35 PM PDT 24
Finished Jul 07 05:06:43 PM PDT 24
Peak memory 208584 kb
Host smart-4aa0ae8f-8944-4fe4-8e3a-b1734f48eb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245767070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.4245767070
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2363004168
Short name T30
Test name
Test status
Simulation time 90316849 ps
CPU time 3.64 seconds
Started Jul 07 05:09:08 PM PDT 24
Finished Jul 07 05:09:12 PM PDT 24
Peak memory 207848 kb
Host smart-50546072-fe9e-4c90-a1ef-e961f7d20671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363004168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2363004168
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2029828634
Short name T1061
Test name
Test status
Simulation time 75366819 ps
CPU time 3.9 seconds
Started Jul 07 04:52:35 PM PDT 24
Finished Jul 07 04:52:40 PM PDT 24
Peak memory 205480 kb
Host smart-d1fecb98-ddc3-455d-a53d-86e314c1c3ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029828634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
029828634
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.4098319416
Short name T1076
Test name
Test status
Simulation time 258484098 ps
CPU time 6.39 seconds
Started Jul 07 04:52:37 PM PDT 24
Finished Jul 07 04:52:43 PM PDT 24
Peak memory 205452 kb
Host smart-4b15b02b-816d-417e-9fa7-9e3bd3366c53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098319416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.4
098319416
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2690462295
Short name T953
Test name
Test status
Simulation time 58588623 ps
CPU time 1.08 seconds
Started Jul 07 04:52:35 PM PDT 24
Finished Jul 07 04:52:37 PM PDT 24
Peak memory 205312 kb
Host smart-55d87cd3-fc4f-4b00-824a-dfb179b1d506
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690462295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
690462295
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.302789269
Short name T1005
Test name
Test status
Simulation time 95386248 ps
CPU time 1.15 seconds
Started Jul 07 04:52:33 PM PDT 24
Finished Jul 07 04:52:35 PM PDT 24
Peak memory 205612 kb
Host smart-fd359bac-03af-48af-ae8a-7f86b9e82475
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302789269 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.302789269
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3901440288
Short name T1021
Test name
Test status
Simulation time 21944279 ps
CPU time 1.01 seconds
Started Jul 07 04:52:34 PM PDT 24
Finished Jul 07 04:52:36 PM PDT 24
Peak memory 205388 kb
Host smart-ca1028ed-d209-4216-94a7-704a60b55d4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901440288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3901440288
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.392523712
Short name T1026
Test name
Test status
Simulation time 36728719 ps
CPU time 0.81 seconds
Started Jul 07 04:52:30 PM PDT 24
Finished Jul 07 04:52:31 PM PDT 24
Peak memory 205208 kb
Host smart-e87e68be-7185-4f56-993d-8204ed353e92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392523712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.392523712
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3721910958
Short name T978
Test name
Test status
Simulation time 123430080 ps
CPU time 2.72 seconds
Started Jul 07 04:52:35 PM PDT 24
Finished Jul 07 04:52:39 PM PDT 24
Peak memory 205516 kb
Host smart-5df4321e-9aaf-4b3e-a86a-14093a5a7261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721910958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3721910958
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3928988246
Short name T1032
Test name
Test status
Simulation time 101222693 ps
CPU time 2.37 seconds
Started Jul 07 04:52:29 PM PDT 24
Finished Jul 07 04:52:32 PM PDT 24
Peak memory 218600 kb
Host smart-3fb567b8-5fb7-4809-a7a1-e72c731fc7fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928988246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3928988246
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.878476748
Short name T1035
Test name
Test status
Simulation time 48264261 ps
CPU time 2.55 seconds
Started Jul 07 04:52:29 PM PDT 24
Finished Jul 07 04:52:33 PM PDT 24
Peak memory 215816 kb
Host smart-ac5e0846-f254-4876-bb54-539e9e191e5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878476748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.878476748
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1201830670
Short name T932
Test name
Test status
Simulation time 2239274838 ps
CPU time 5.6 seconds
Started Jul 07 04:52:36 PM PDT 24
Finished Jul 07 04:52:42 PM PDT 24
Peak memory 205480 kb
Host smart-07a6cc71-651a-4e7d-a47d-1a9d439d2c1e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201830670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
201830670
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.785739891
Short name T1047
Test name
Test status
Simulation time 441377532 ps
CPU time 7.37 seconds
Started Jul 07 04:52:34 PM PDT 24
Finished Jul 07 04:52:42 PM PDT 24
Peak memory 205412 kb
Host smart-f00f1c65-be70-46de-b710-4700243af9d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785739891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.785739891
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2481822794
Short name T930
Test name
Test status
Simulation time 11771885 ps
CPU time 0.85 seconds
Started Jul 07 04:52:35 PM PDT 24
Finished Jul 07 04:52:36 PM PDT 24
Peak memory 205320 kb
Host smart-bfbbc570-adfe-42cc-a0dd-0aabc8e14c3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481822794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
481822794
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.241397278
Short name T952
Test name
Test status
Simulation time 33932195 ps
CPU time 1.33 seconds
Started Jul 07 04:52:33 PM PDT 24
Finished Jul 07 04:52:35 PM PDT 24
Peak memory 213696 kb
Host smart-09387e25-4d2e-4b6e-b5b6-89eb7b5e1428
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241397278 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.241397278
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1974759555
Short name T964
Test name
Test status
Simulation time 36630506 ps
CPU time 1.03 seconds
Started Jul 07 04:52:34 PM PDT 24
Finished Jul 07 04:52:36 PM PDT 24
Peak memory 205512 kb
Host smart-ac4aeee7-a2bf-4e05-ba21-90244f2049d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974759555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1974759555
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2372179454
Short name T1065
Test name
Test status
Simulation time 20098401 ps
CPU time 0.87 seconds
Started Jul 07 04:52:36 PM PDT 24
Finished Jul 07 04:52:37 PM PDT 24
Peak memory 205216 kb
Host smart-659d6034-a909-41b1-a106-fa497247369b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372179454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2372179454
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1566627973
Short name T981
Test name
Test status
Simulation time 40432575 ps
CPU time 2.59 seconds
Started Jul 07 04:52:34 PM PDT 24
Finished Jul 07 04:52:37 PM PDT 24
Peak memory 205320 kb
Host smart-a15c9d25-7ea6-4884-935b-e912ea1351f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566627973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1566627973
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2653435800
Short name T125
Test name
Test status
Simulation time 179734665 ps
CPU time 4.89 seconds
Started Jul 07 04:52:34 PM PDT 24
Finished Jul 07 04:52:39 PM PDT 24
Peak memory 213772 kb
Host smart-b42c83f1-c4eb-44c7-9704-97a03e79c846
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653435800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2653435800
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2059184660
Short name T1006
Test name
Test status
Simulation time 161009931 ps
CPU time 3.74 seconds
Started Jul 07 04:52:33 PM PDT 24
Finished Jul 07 04:52:37 PM PDT 24
Peak memory 213724 kb
Host smart-b3cb328f-341d-4282-a101-357ac03d3375
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059184660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2059184660
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3755928363
Short name T918
Test name
Test status
Simulation time 40272045 ps
CPU time 3 seconds
Started Jul 07 04:52:38 PM PDT 24
Finished Jul 07 04:52:41 PM PDT 24
Peak memory 213704 kb
Host smart-01219c0b-b18d-4dda-b636-8083e0fbc463
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755928363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3755928363
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.678040270
Short name T977
Test name
Test status
Simulation time 212921053 ps
CPU time 5.11 seconds
Started Jul 07 04:52:36 PM PDT 24
Finished Jul 07 04:52:41 PM PDT 24
Peak memory 213560 kb
Host smart-1c3781d4-d556-425f-9e7d-c5887b4558c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678040270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
678040270
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2521326283
Short name T1012
Test name
Test status
Simulation time 41011612 ps
CPU time 2.73 seconds
Started Jul 07 04:52:51 PM PDT 24
Finished Jul 07 04:52:55 PM PDT 24
Peak memory 213760 kb
Host smart-51429b63-080c-43d6-9580-fb5e8be396f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521326283 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2521326283
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.342165855
Short name T976
Test name
Test status
Simulation time 32291653 ps
CPU time 1.71 seconds
Started Jul 07 04:52:45 PM PDT 24
Finished Jul 07 04:52:47 PM PDT 24
Peak memory 205384 kb
Host smart-0cff93ce-7112-4599-9910-d1b4a03fc5fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342165855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.342165855
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.293627159
Short name T1023
Test name
Test status
Simulation time 40216450 ps
CPU time 0.75 seconds
Started Jul 07 04:52:53 PM PDT 24
Finished Jul 07 04:52:54 PM PDT 24
Peak memory 204892 kb
Host smart-b3736e5b-04bf-4987-92a1-445c91da8056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293627159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.293627159
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2084803523
Short name T936
Test name
Test status
Simulation time 316006975 ps
CPU time 3.26 seconds
Started Jul 07 04:52:54 PM PDT 24
Finished Jul 07 04:52:59 PM PDT 24
Peak memory 205376 kb
Host smart-3b3bb828-547d-43dc-b546-563470f170b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084803523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2084803523
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.172307432
Short name T963
Test name
Test status
Simulation time 90151950 ps
CPU time 1.77 seconds
Started Jul 07 04:52:49 PM PDT 24
Finished Jul 07 04:52:52 PM PDT 24
Peak memory 214060 kb
Host smart-b9e10ad5-9de1-4850-b2c1-d5f88d84d089
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172307432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.172307432
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1641863042
Short name T124
Test name
Test status
Simulation time 413102356 ps
CPU time 15.22 seconds
Started Jul 07 04:52:47 PM PDT 24
Finished Jul 07 04:53:03 PM PDT 24
Peak memory 214008 kb
Host smart-7717fc0e-8789-48c9-a721-ae9f5c371469
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641863042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1641863042
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2624555921
Short name T1070
Test name
Test status
Simulation time 126498317 ps
CPU time 2.52 seconds
Started Jul 07 04:52:49 PM PDT 24
Finished Jul 07 04:52:52 PM PDT 24
Peak memory 213712 kb
Host smart-16d189e1-40a4-4fab-b8e0-caf45cd8daff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624555921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2624555921
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2190908207
Short name T979
Test name
Test status
Simulation time 28279129 ps
CPU time 1.29 seconds
Started Jul 07 04:52:52 PM PDT 24
Finished Jul 07 04:52:54 PM PDT 24
Peak memory 205516 kb
Host smart-7af7e859-b71f-4d34-9afc-79b8fc328af8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190908207 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2190908207
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3585616780
Short name T157
Test name
Test status
Simulation time 431602425 ps
CPU time 1.58 seconds
Started Jul 07 04:52:52 PM PDT 24
Finished Jul 07 04:52:54 PM PDT 24
Peak memory 205408 kb
Host smart-13acbb8f-e0a1-4801-8b1a-71854521e81b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585616780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3585616780
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3869745013
Short name T1056
Test name
Test status
Simulation time 84382942 ps
CPU time 0.76 seconds
Started Jul 07 04:52:50 PM PDT 24
Finished Jul 07 04:52:52 PM PDT 24
Peak memory 205576 kb
Host smart-a3a97d0a-f668-4fcf-8d58-2c8e22876749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869745013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3869745013
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3000505095
Short name T939
Test name
Test status
Simulation time 81304739 ps
CPU time 2.13 seconds
Started Jul 07 04:52:54 PM PDT 24
Finished Jul 07 04:52:57 PM PDT 24
Peak memory 205316 kb
Host smart-6ac9d94f-27ae-4837-b0d0-751831ad8f1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000505095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3000505095
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2228633813
Short name T1053
Test name
Test status
Simulation time 176836973 ps
CPU time 2.93 seconds
Started Jul 07 04:52:49 PM PDT 24
Finished Jul 07 04:52:53 PM PDT 24
Peak memory 213908 kb
Host smart-4bf105f4-b7c1-4a5d-ad34-2803d86582ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228633813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2228633813
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2447339101
Short name T139
Test name
Test status
Simulation time 737054902 ps
CPU time 5.18 seconds
Started Jul 07 04:52:46 PM PDT 24
Finished Jul 07 04:52:51 PM PDT 24
Peak memory 214000 kb
Host smart-5bb89beb-a7dc-413f-a60d-3e63bad8cf84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447339101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2447339101
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1054983679
Short name T165
Test name
Test status
Simulation time 113401134 ps
CPU time 3.93 seconds
Started Jul 07 04:52:49 PM PDT 24
Finished Jul 07 04:52:53 PM PDT 24
Peak memory 213552 kb
Host smart-b8547fce-e160-4f21-b83d-7809058ca3f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054983679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1054983679
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.548733251
Short name T993
Test name
Test status
Simulation time 448207688 ps
CPU time 2.34 seconds
Started Jul 07 04:52:50 PM PDT 24
Finished Jul 07 04:52:54 PM PDT 24
Peak memory 213664 kb
Host smart-4dddd7d4-b906-4145-ab16-225f8e63cf4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548733251 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.548733251
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2394463231
Short name T975
Test name
Test status
Simulation time 77578821 ps
CPU time 1.13 seconds
Started Jul 07 04:52:50 PM PDT 24
Finished Jul 07 04:52:53 PM PDT 24
Peak memory 205388 kb
Host smart-05bab3ad-7a2b-4d4b-b2a0-87bb3dc2d188
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394463231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2394463231
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2931096482
Short name T949
Test name
Test status
Simulation time 16951138 ps
CPU time 0.83 seconds
Started Jul 07 04:52:50 PM PDT 24
Finished Jul 07 04:52:51 PM PDT 24
Peak memory 205300 kb
Host smart-91c674f8-692c-43cd-a354-1ad3f8777aec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931096482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2931096482
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3908604170
Short name T1015
Test name
Test status
Simulation time 142250106 ps
CPU time 2.1 seconds
Started Jul 07 04:52:51 PM PDT 24
Finished Jul 07 04:52:54 PM PDT 24
Peak memory 205392 kb
Host smart-f8a19cf7-90cd-44fe-b22f-f4aa4f20f49e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908604170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3908604170
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2955791682
Short name T998
Test name
Test status
Simulation time 182993015 ps
CPU time 1.77 seconds
Started Jul 07 04:52:51 PM PDT 24
Finished Jul 07 04:52:54 PM PDT 24
Peak memory 214036 kb
Host smart-e2850393-efe9-4c5c-b18e-cfb70083b6e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955791682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2955791682
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3848434570
Short name T1019
Test name
Test status
Simulation time 154029480 ps
CPU time 4.39 seconds
Started Jul 07 04:52:50 PM PDT 24
Finished Jul 07 04:52:55 PM PDT 24
Peak memory 219840 kb
Host smart-e4d51dc2-a6f8-4f16-8b8f-42020191442b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848434570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3848434570
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1299395415
Short name T1066
Test name
Test status
Simulation time 326892941 ps
CPU time 3.72 seconds
Started Jul 07 04:52:52 PM PDT 24
Finished Jul 07 04:52:56 PM PDT 24
Peak memory 221692 kb
Host smart-bca23ffe-32eb-4f62-b95f-8008221a7022
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299395415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1299395415
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2010862973
Short name T1059
Test name
Test status
Simulation time 67551622 ps
CPU time 1.72 seconds
Started Jul 07 04:52:57 PM PDT 24
Finished Jul 07 04:52:59 PM PDT 24
Peak memory 213660 kb
Host smart-e10119c4-fff2-4fe3-9445-15e250964be6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010862973 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2010862973
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.448077319
Short name T938
Test name
Test status
Simulation time 65070513 ps
CPU time 0.96 seconds
Started Jul 07 04:52:56 PM PDT 24
Finished Jul 07 04:52:58 PM PDT 24
Peak memory 205264 kb
Host smart-3e5d2c39-7eb3-4357-800b-d6a96b86ffc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448077319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.448077319
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3486596532
Short name T1033
Test name
Test status
Simulation time 92642671 ps
CPU time 0.8 seconds
Started Jul 07 04:52:55 PM PDT 24
Finished Jul 07 04:52:56 PM PDT 24
Peak memory 205220 kb
Host smart-18ba45f1-d6b1-43fc-a3f7-c7f82347ea32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486596532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3486596532
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.779956553
Short name T927
Test name
Test status
Simulation time 254839242 ps
CPU time 2.66 seconds
Started Jul 07 04:52:56 PM PDT 24
Finished Jul 07 04:52:59 PM PDT 24
Peak memory 205392 kb
Host smart-27115836-c4e7-4b00-b49f-f91939d0a651
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779956553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.779956553
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2829705389
Short name T1039
Test name
Test status
Simulation time 239399534 ps
CPU time 1.8 seconds
Started Jul 07 04:52:51 PM PDT 24
Finished Jul 07 04:52:54 PM PDT 24
Peak memory 213932 kb
Host smart-103fa56f-d16a-47d2-a598-767765fc67df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829705389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2829705389
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3314382210
Short name T121
Test name
Test status
Simulation time 1454081558 ps
CPU time 4.39 seconds
Started Jul 07 04:52:54 PM PDT 24
Finished Jul 07 04:52:59 PM PDT 24
Peak memory 213960 kb
Host smart-4e09ef00-49fc-4963-9f7a-dd57a7226108
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314382210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3314382210
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1186880064
Short name T972
Test name
Test status
Simulation time 104143454 ps
CPU time 2.14 seconds
Started Jul 07 04:52:49 PM PDT 24
Finished Jul 07 04:52:52 PM PDT 24
Peak memory 216800 kb
Host smart-79279cab-dd04-4703-b816-c0d827b4b5b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186880064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1186880064
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3127495426
Short name T184
Test name
Test status
Simulation time 142693849 ps
CPU time 4.89 seconds
Started Jul 07 04:52:50 PM PDT 24
Finished Jul 07 04:52:56 PM PDT 24
Peak memory 213580 kb
Host smart-74979456-595e-494e-8623-6b6d07861ed3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127495426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3127495426
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2857927643
Short name T1008
Test name
Test status
Simulation time 151320299 ps
CPU time 2.18 seconds
Started Jul 07 04:52:55 PM PDT 24
Finished Jul 07 04:52:58 PM PDT 24
Peak memory 213692 kb
Host smart-8dbce6f6-e057-494a-a1e9-9f934d6ab240
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857927643 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2857927643
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2864975851
Short name T1031
Test name
Test status
Simulation time 199206274 ps
CPU time 0.98 seconds
Started Jul 07 04:52:54 PM PDT 24
Finished Jul 07 04:52:56 PM PDT 24
Peak memory 205328 kb
Host smart-ab39cacd-248f-4935-bf78-88ec998cbb52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864975851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2864975851
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2320881077
Short name T973
Test name
Test status
Simulation time 11791778 ps
CPU time 0.8 seconds
Started Jul 07 04:52:56 PM PDT 24
Finished Jul 07 04:52:57 PM PDT 24
Peak memory 205616 kb
Host smart-7d18f4e1-10be-454b-8448-5e0b6e116620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320881077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2320881077
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2435795795
Short name T140
Test name
Test status
Simulation time 131904026 ps
CPU time 2.11 seconds
Started Jul 07 04:52:55 PM PDT 24
Finished Jul 07 04:52:58 PM PDT 24
Peak memory 205512 kb
Host smart-0d616a96-c072-46b7-b2dd-de7b86ed89d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435795795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2435795795
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.4007729711
Short name T992
Test name
Test status
Simulation time 155740458 ps
CPU time 4.46 seconds
Started Jul 07 04:52:54 PM PDT 24
Finished Jul 07 04:52:59 PM PDT 24
Peak memory 213908 kb
Host smart-b43b94c4-d86e-40ea-9707-d7628ad69138
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007729711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.4007729711
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.109152348
Short name T933
Test name
Test status
Simulation time 191435781 ps
CPU time 4.91 seconds
Started Jul 07 04:52:55 PM PDT 24
Finished Jul 07 04:53:01 PM PDT 24
Peak memory 214040 kb
Host smart-203e7a19-73c4-4095-8ac1-8a8a6f1e05b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109152348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.109152348
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2624879357
Short name T986
Test name
Test status
Simulation time 68075664 ps
CPU time 2.65 seconds
Started Jul 07 04:52:56 PM PDT 24
Finished Jul 07 04:52:59 PM PDT 24
Peak memory 216016 kb
Host smart-83149854-a085-4c93-8075-f6e968708e51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624879357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2624879357
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3661958213
Short name T1058
Test name
Test status
Simulation time 104518005 ps
CPU time 1.13 seconds
Started Jul 07 04:52:59 PM PDT 24
Finished Jul 07 04:53:00 PM PDT 24
Peak memory 205420 kb
Host smart-9f1afc25-9b3a-4ae8-936c-076b06c7a8aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661958213 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3661958213
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3986323057
Short name T960
Test name
Test status
Simulation time 47494283 ps
CPU time 1.12 seconds
Started Jul 07 04:53:01 PM PDT 24
Finished Jul 07 04:53:02 PM PDT 24
Peak memory 205420 kb
Host smart-21309e2f-a454-4081-b720-bd28ea6d7d2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986323057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3986323057
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2495343576
Short name T1034
Test name
Test status
Simulation time 10801465 ps
CPU time 0.77 seconds
Started Jul 07 04:53:00 PM PDT 24
Finished Jul 07 04:53:01 PM PDT 24
Peak memory 205320 kb
Host smart-6f03bfcc-cb1b-43b7-bf04-c75ac48d4558
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495343576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2495343576
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3045183540
Short name T951
Test name
Test status
Simulation time 407016207 ps
CPU time 1.62 seconds
Started Jul 07 04:53:00 PM PDT 24
Finished Jul 07 04:53:02 PM PDT 24
Peak memory 205392 kb
Host smart-02098bfa-ee04-47eb-ab04-ba2e98a1595b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045183540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3045183540
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.553168882
Short name T1057
Test name
Test status
Simulation time 99856329 ps
CPU time 3.76 seconds
Started Jul 07 04:52:55 PM PDT 24
Finished Jul 07 04:52:59 PM PDT 24
Peak memory 214004 kb
Host smart-32f59fb8-b8eb-41c0-8bfc-86d099cabe51
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553168882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.553168882
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2248272347
Short name T1050
Test name
Test status
Simulation time 2304629463 ps
CPU time 9.95 seconds
Started Jul 07 04:52:57 PM PDT 24
Finished Jul 07 04:53:07 PM PDT 24
Peak memory 213892 kb
Host smart-8c772a08-84f0-44a3-b3bc-70897f20fb84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248272347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2248272347
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2167202477
Short name T1022
Test name
Test status
Simulation time 49047465 ps
CPU time 2.34 seconds
Started Jul 07 04:52:54 PM PDT 24
Finished Jul 07 04:52:57 PM PDT 24
Peak memory 213720 kb
Host smart-fe5362dc-8720-416a-a89a-8ff2a49e1bc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167202477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2167202477
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1976064794
Short name T142
Test name
Test status
Simulation time 145755436 ps
CPU time 6.23 seconds
Started Jul 07 04:52:56 PM PDT 24
Finished Jul 07 04:53:03 PM PDT 24
Peak memory 205576 kb
Host smart-cd612421-6337-4c21-859a-dbaf16db0e17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976064794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1976064794
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3454199945
Short name T984
Test name
Test status
Simulation time 67195131 ps
CPU time 1.26 seconds
Started Jul 07 04:53:01 PM PDT 24
Finished Jul 07 04:53:02 PM PDT 24
Peak memory 213756 kb
Host smart-c992c39a-f8b2-4992-a79d-7b613fa625a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454199945 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3454199945
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3171390828
Short name T1002
Test name
Test status
Simulation time 41028359 ps
CPU time 1.34 seconds
Started Jul 07 04:53:01 PM PDT 24
Finished Jul 07 04:53:03 PM PDT 24
Peak memory 205404 kb
Host smart-064b5081-390c-452b-a42a-ed4d6e76f515
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171390828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3171390828
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2368929459
Short name T1064
Test name
Test status
Simulation time 52070534 ps
CPU time 0.82 seconds
Started Jul 07 04:53:00 PM PDT 24
Finished Jul 07 04:53:01 PM PDT 24
Peak memory 205224 kb
Host smart-e6501fe3-6941-48e9-a86c-ee0ac9ec2ac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368929459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2368929459
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1735199677
Short name T1027
Test name
Test status
Simulation time 22351396 ps
CPU time 1.74 seconds
Started Jul 07 04:53:00 PM PDT 24
Finished Jul 07 04:53:02 PM PDT 24
Peak memory 205420 kb
Host smart-92091f03-6f0c-4e3f-aeec-7692b749a55b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735199677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1735199677
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.280373689
Short name T957
Test name
Test status
Simulation time 78255052 ps
CPU time 2.46 seconds
Started Jul 07 04:53:00 PM PDT 24
Finished Jul 07 04:53:03 PM PDT 24
Peak memory 213908 kb
Host smart-1187d836-9d58-4f95-8ca8-d04021e43078
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280373689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.280373689
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1864510305
Short name T1073
Test name
Test status
Simulation time 419438786 ps
CPU time 4.34 seconds
Started Jul 07 04:52:59 PM PDT 24
Finished Jul 07 04:53:03 PM PDT 24
Peak memory 216040 kb
Host smart-87984d73-41af-448d-bd70-0c144bda1e8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864510305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1864510305
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1358434921
Short name T958
Test name
Test status
Simulation time 64641786 ps
CPU time 2.1 seconds
Started Jul 07 04:53:04 PM PDT 24
Finished Jul 07 04:53:06 PM PDT 24
Peak memory 213592 kb
Host smart-f7255b21-bb4d-4c7a-a1bc-89ec70571338
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358434921 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1358434921
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2519845593
Short name T968
Test name
Test status
Simulation time 46946108 ps
CPU time 1.1 seconds
Started Jul 07 04:53:03 PM PDT 24
Finished Jul 07 04:53:04 PM PDT 24
Peak memory 205320 kb
Host smart-02fec666-f3e6-46f2-9bce-3e6282f4f1a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519845593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2519845593
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2314932130
Short name T1054
Test name
Test status
Simulation time 19413447 ps
CPU time 0.83 seconds
Started Jul 07 04:53:10 PM PDT 24
Finished Jul 07 04:53:11 PM PDT 24
Peak memory 205252 kb
Host smart-27a0e81e-2739-400a-8db2-d027a9833c35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314932130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2314932130
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1667092776
Short name T136
Test name
Test status
Simulation time 42024568 ps
CPU time 2.14 seconds
Started Jul 07 04:53:04 PM PDT 24
Finished Jul 07 04:53:07 PM PDT 24
Peak memory 205396 kb
Host smart-396d5851-727a-4f87-8f56-f5ad878a8ceb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667092776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1667092776
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2617568686
Short name T123
Test name
Test status
Simulation time 1027152257 ps
CPU time 2.66 seconds
Started Jul 07 04:53:02 PM PDT 24
Finished Jul 07 04:53:05 PM PDT 24
Peak memory 214304 kb
Host smart-6a64c426-fc7a-4a3e-a937-8363a95fda81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617568686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2617568686
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.537623418
Short name T950
Test name
Test status
Simulation time 340778168 ps
CPU time 4.6 seconds
Started Jul 07 04:53:03 PM PDT 24
Finished Jul 07 04:53:08 PM PDT 24
Peak memory 220148 kb
Host smart-1da0596b-86db-498b-b21a-98828761f656
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537623418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.537623418
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1625126006
Short name T934
Test name
Test status
Simulation time 76141818 ps
CPU time 3.35 seconds
Started Jul 07 04:53:04 PM PDT 24
Finished Jul 07 04:53:08 PM PDT 24
Peak memory 214008 kb
Host smart-6c26f96b-4e35-4de5-b96b-ca244856ed07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625126006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1625126006
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.4247556945
Short name T917
Test name
Test status
Simulation time 359441847 ps
CPU time 3.66 seconds
Started Jul 07 04:53:08 PM PDT 24
Finished Jul 07 04:53:12 PM PDT 24
Peak memory 213440 kb
Host smart-05ca76ef-ab62-400c-9fbc-308f5daeb33b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247556945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.4247556945
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1022137632
Short name T923
Test name
Test status
Simulation time 129254571 ps
CPU time 1.53 seconds
Started Jul 07 04:53:05 PM PDT 24
Finished Jul 07 04:53:07 PM PDT 24
Peak memory 205468 kb
Host smart-b4364ccc-7324-4c1e-b5e0-b9309da0cdca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022137632 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1022137632
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2351239952
Short name T926
Test name
Test status
Simulation time 41880181 ps
CPU time 1.01 seconds
Started Jul 07 04:53:06 PM PDT 24
Finished Jul 07 04:53:08 PM PDT 24
Peak memory 205416 kb
Host smart-92357fb5-5f37-4342-a722-44317342fb96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351239952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2351239952
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.536310887
Short name T922
Test name
Test status
Simulation time 24934091 ps
CPU time 0.79 seconds
Started Jul 07 04:53:03 PM PDT 24
Finished Jul 07 04:53:04 PM PDT 24
Peak memory 205272 kb
Host smart-f44439a0-c4ad-4263-99f4-ed76ca6ecd6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536310887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.536310887
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1484432891
Short name T1024
Test name
Test status
Simulation time 98884667 ps
CPU time 1.57 seconds
Started Jul 07 04:53:05 PM PDT 24
Finished Jul 07 04:53:06 PM PDT 24
Peak memory 205884 kb
Host smart-8f2654e3-1ebf-452c-9bcf-4e800cbb6020
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484432891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1484432891
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1647779070
Short name T1003
Test name
Test status
Simulation time 233003754 ps
CPU time 2.26 seconds
Started Jul 07 04:53:04 PM PDT 24
Finished Jul 07 04:53:07 PM PDT 24
Peak memory 213912 kb
Host smart-61cbd26d-3a91-4762-bcbd-4249bbd17a7c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647779070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1647779070
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.191616880
Short name T1000
Test name
Test status
Simulation time 2009711185 ps
CPU time 8.32 seconds
Started Jul 07 04:53:04 PM PDT 24
Finished Jul 07 04:53:12 PM PDT 24
Peak memory 213964 kb
Host smart-9c341628-d3a1-45a6-925a-a75f30a910cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191616880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.191616880
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1046019363
Short name T1045
Test name
Test status
Simulation time 51952445 ps
CPU time 3.05 seconds
Started Jul 07 04:53:04 PM PDT 24
Finished Jul 07 04:53:08 PM PDT 24
Peak memory 213680 kb
Host smart-b19afdbb-db40-45a8-86e0-c6d97bb3de55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046019363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1046019363
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1359277397
Short name T982
Test name
Test status
Simulation time 32472821 ps
CPU time 1.48 seconds
Started Jul 07 04:53:07 PM PDT 24
Finished Jul 07 04:53:08 PM PDT 24
Peak memory 213748 kb
Host smart-0428641a-db68-405c-a84b-551ff26b620a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359277397 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1359277397
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1136359122
Short name T997
Test name
Test status
Simulation time 22798199 ps
CPU time 1.24 seconds
Started Jul 07 04:53:10 PM PDT 24
Finished Jul 07 04:53:12 PM PDT 24
Peak memory 205420 kb
Host smart-61f9c4ce-7502-499e-a1d3-1858c001a9c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136359122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1136359122
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2842916294
Short name T929
Test name
Test status
Simulation time 40042278 ps
CPU time 0.67 seconds
Started Jul 07 04:53:07 PM PDT 24
Finished Jul 07 04:53:08 PM PDT 24
Peak memory 205100 kb
Host smart-f97e415f-fe31-4f77-804b-8e3dc41d33ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842916294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2842916294
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1475346798
Short name T138
Test name
Test status
Simulation time 312761006 ps
CPU time 2.55 seconds
Started Jul 07 04:53:08 PM PDT 24
Finished Jul 07 04:53:11 PM PDT 24
Peak memory 205496 kb
Host smart-fc028773-464d-41a1-b1c4-c148d6283c6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475346798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1475346798
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.922130368
Short name T1004
Test name
Test status
Simulation time 175792708 ps
CPU time 2.34 seconds
Started Jul 07 04:53:11 PM PDT 24
Finished Jul 07 04:53:13 PM PDT 24
Peak memory 213892 kb
Host smart-81eded31-4779-49ca-8a5b-f4e0e24c4fe5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922130368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.922130368
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3693279348
Short name T991
Test name
Test status
Simulation time 151883778 ps
CPU time 7.45 seconds
Started Jul 07 04:53:06 PM PDT 24
Finished Jul 07 04:53:13 PM PDT 24
Peak memory 213896 kb
Host smart-77e6fdeb-3cde-4ace-ae52-d1b029354f3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693279348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3693279348
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.518846417
Short name T943
Test name
Test status
Simulation time 56903516 ps
CPU time 2.16 seconds
Started Jul 07 04:53:07 PM PDT 24
Finished Jul 07 04:53:09 PM PDT 24
Peak memory 213672 kb
Host smart-a430445e-c254-4729-b0d8-a6d3f2876940
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518846417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.518846417
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.986353709
Short name T980
Test name
Test status
Simulation time 774291247 ps
CPU time 5.02 seconds
Started Jul 07 04:52:38 PM PDT 24
Finished Jul 07 04:52:44 PM PDT 24
Peak memory 205548 kb
Host smart-14281fec-9fc2-43c0-bb95-28f57763bdc8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986353709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.986353709
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.390728607
Short name T947
Test name
Test status
Simulation time 855945924 ps
CPU time 14.58 seconds
Started Jul 07 04:52:38 PM PDT 24
Finished Jul 07 04:52:53 PM PDT 24
Peak memory 205316 kb
Host smart-7720040b-042d-4895-91a6-d8094178c529
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390728607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.390728607
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3663376049
Short name T1042
Test name
Test status
Simulation time 33350500 ps
CPU time 1.03 seconds
Started Jul 07 04:52:37 PM PDT 24
Finished Jul 07 04:52:39 PM PDT 24
Peak memory 205412 kb
Host smart-5ee669fa-80eb-430f-ac8c-b811b6d84b65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663376049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
663376049
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2858870986
Short name T966
Test name
Test status
Simulation time 33620083 ps
CPU time 1.55 seconds
Started Jul 07 04:52:41 PM PDT 24
Finished Jul 07 04:52:43 PM PDT 24
Peak memory 213608 kb
Host smart-c2566069-23aa-4f86-8d9f-bd0c5545068b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858870986 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2858870986
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2201196241
Short name T1062
Test name
Test status
Simulation time 83151095 ps
CPU time 1.28 seconds
Started Jul 07 04:52:40 PM PDT 24
Finished Jul 07 04:52:42 PM PDT 24
Peak memory 205404 kb
Host smart-4c5c2f47-8dba-4847-8d51-8f71215bd435
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201196241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2201196241
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3128106095
Short name T988
Test name
Test status
Simulation time 45241690 ps
CPU time 0.86 seconds
Started Jul 07 04:52:40 PM PDT 24
Finished Jul 07 04:52:41 PM PDT 24
Peak memory 205216 kb
Host smart-d97ca218-b7e2-4353-b5b5-7584f7e207e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128106095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3128106095
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.352297806
Short name T969
Test name
Test status
Simulation time 356729013 ps
CPU time 3.46 seconds
Started Jul 07 04:52:38 PM PDT 24
Finished Jul 07 04:52:42 PM PDT 24
Peak memory 205356 kb
Host smart-7361321a-c8d9-414d-8a72-a11d0d210ee7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352297806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.352297806
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.854002355
Short name T127
Test name
Test status
Simulation time 567922124 ps
CPU time 1.75 seconds
Started Jul 07 04:52:33 PM PDT 24
Finished Jul 07 04:52:35 PM PDT 24
Peak memory 213880 kb
Host smart-19cec255-fa05-4b5f-ae08-b3f07e6986d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854002355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.854002355
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2243927423
Short name T156
Test name
Test status
Simulation time 559761700 ps
CPU time 3.21 seconds
Started Jul 07 04:52:35 PM PDT 24
Finished Jul 07 04:52:39 PM PDT 24
Peak memory 213760 kb
Host smart-1004b8e9-abbc-4e5a-a4e9-326b164aefcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243927423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2243927423
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2593170452
Short name T190
Test name
Test status
Simulation time 134723408 ps
CPU time 3.45 seconds
Started Jul 07 04:52:36 PM PDT 24
Finished Jul 07 04:52:40 PM PDT 24
Peak memory 213652 kb
Host smart-d757fa06-064e-46d1-b2d6-52b923693fe0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593170452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2593170452
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3194436416
Short name T954
Test name
Test status
Simulation time 69245477 ps
CPU time 0.89 seconds
Started Jul 07 04:53:11 PM PDT 24
Finished Jul 07 04:53:13 PM PDT 24
Peak memory 205220 kb
Host smart-250b3a0f-1c6e-4c97-95f1-166416006bc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194436416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3194436416
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2640436793
Short name T994
Test name
Test status
Simulation time 31893575 ps
CPU time 0.83 seconds
Started Jul 07 04:53:10 PM PDT 24
Finished Jul 07 04:53:11 PM PDT 24
Peak memory 205252 kb
Host smart-f4b82fe8-c329-4ad8-a478-7f88502a4b4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640436793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2640436793
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1480931269
Short name T1007
Test name
Test status
Simulation time 12428185 ps
CPU time 0.72 seconds
Started Jul 07 04:53:07 PM PDT 24
Finished Jul 07 04:53:08 PM PDT 24
Peak memory 205284 kb
Host smart-72c367e8-7a18-4464-8443-e5069a38d7d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480931269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1480931269
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.4246280649
Short name T920
Test name
Test status
Simulation time 36562720 ps
CPU time 0.84 seconds
Started Jul 07 04:53:12 PM PDT 24
Finished Jul 07 04:53:13 PM PDT 24
Peak memory 205220 kb
Host smart-b69f193c-4dfc-4598-a946-5a84f8a8860c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246280649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.4246280649
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.4241037602
Short name T1037
Test name
Test status
Simulation time 41976333 ps
CPU time 0.85 seconds
Started Jul 07 04:53:07 PM PDT 24
Finished Jul 07 04:53:08 PM PDT 24
Peak memory 205284 kb
Host smart-268298f9-45f2-455c-8681-c77246da47c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241037602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.4241037602
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3313462331
Short name T999
Test name
Test status
Simulation time 21139603 ps
CPU time 0.92 seconds
Started Jul 07 04:53:12 PM PDT 24
Finished Jul 07 04:53:14 PM PDT 24
Peak memory 205144 kb
Host smart-7258b491-39e5-46cc-955e-0a7bc8dcc60c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313462331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3313462331
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.218504895
Short name T937
Test name
Test status
Simulation time 24992422 ps
CPU time 0.79 seconds
Started Jul 07 04:53:10 PM PDT 24
Finished Jul 07 04:53:11 PM PDT 24
Peak memory 205232 kb
Host smart-cffb9c24-35a7-4f23-947c-8c760c11e4fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218504895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.218504895
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1339291986
Short name T1009
Test name
Test status
Simulation time 47753296 ps
CPU time 0.75 seconds
Started Jul 07 04:53:11 PM PDT 24
Finished Jul 07 04:53:12 PM PDT 24
Peak memory 205144 kb
Host smart-af4da01a-7bea-4b8b-bd18-60ff14ef3461
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339291986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1339291986
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1826172388
Short name T965
Test name
Test status
Simulation time 89230751 ps
CPU time 0.71 seconds
Started Jul 07 04:53:08 PM PDT 24
Finished Jul 07 04:53:09 PM PDT 24
Peak memory 205140 kb
Host smart-f8902668-b1b9-45a4-b8e2-4a5e00b133c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826172388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1826172388
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1634900488
Short name T919
Test name
Test status
Simulation time 15261457 ps
CPU time 0.86 seconds
Started Jul 07 04:53:11 PM PDT 24
Finished Jul 07 04:53:13 PM PDT 24
Peak memory 205220 kb
Host smart-965690f4-8e4c-401e-b4fd-a2e2379bc8b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634900488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1634900488
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2627713827
Short name T990
Test name
Test status
Simulation time 368108379 ps
CPU time 4.26 seconds
Started Jul 07 04:52:40 PM PDT 24
Finished Jul 07 04:52:44 PM PDT 24
Peak memory 205452 kb
Host smart-fe98941e-8c34-43d9-a0b8-b25e630705a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627713827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
627713827
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3779795837
Short name T1077
Test name
Test status
Simulation time 3553068815 ps
CPU time 25.59 seconds
Started Jul 07 04:52:37 PM PDT 24
Finished Jul 07 04:53:03 PM PDT 24
Peak memory 205476 kb
Host smart-75f899d2-fd30-48ee-8028-dc46ca25d68c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779795837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
779795837
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1832664045
Short name T1020
Test name
Test status
Simulation time 58385625 ps
CPU time 0.89 seconds
Started Jul 07 04:52:39 PM PDT 24
Finished Jul 07 04:52:40 PM PDT 24
Peak memory 205264 kb
Host smart-dd036114-cb2c-4258-a6c7-f31143729220
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832664045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
832664045
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.791950187
Short name T1082
Test name
Test status
Simulation time 24155381 ps
CPU time 1.54 seconds
Started Jul 07 04:52:40 PM PDT 24
Finished Jul 07 04:52:41 PM PDT 24
Peak memory 218004 kb
Host smart-6c6bc246-a213-4bed-b5d5-1e65e97d2551
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791950187 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.791950187
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1679220861
Short name T944
Test name
Test status
Simulation time 25256830 ps
CPU time 1.53 seconds
Started Jul 07 04:52:40 PM PDT 24
Finished Jul 07 04:52:42 PM PDT 24
Peak memory 205384 kb
Host smart-ac788986-8cfe-43a6-bcf7-865f8f79cfcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679220861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1679220861
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3973141046
Short name T1068
Test name
Test status
Simulation time 18078006 ps
CPU time 0.69 seconds
Started Jul 07 04:52:39 PM PDT 24
Finished Jul 07 04:52:40 PM PDT 24
Peak memory 205244 kb
Host smart-e6be972b-7e6c-4967-8ca5-beeaffa3fda0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973141046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3973141046
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1854113923
Short name T1055
Test name
Test status
Simulation time 114450834 ps
CPU time 1.59 seconds
Started Jul 07 04:52:41 PM PDT 24
Finished Jul 07 04:52:43 PM PDT 24
Peak memory 205296 kb
Host smart-39a83e65-e870-4064-8917-a8328245d8c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854113923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1854113923
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3080160618
Short name T962
Test name
Test status
Simulation time 67123296 ps
CPU time 1.47 seconds
Started Jul 07 04:52:40 PM PDT 24
Finished Jul 07 04:52:42 PM PDT 24
Peak memory 213876 kb
Host smart-7c95f832-0bed-4700-9324-187c90af3e75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080160618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3080160618
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1437166447
Short name T126
Test name
Test status
Simulation time 82584305 ps
CPU time 4.1 seconds
Started Jul 07 04:52:38 PM PDT 24
Finished Jul 07 04:52:43 PM PDT 24
Peak memory 213888 kb
Host smart-a3ea4a33-2ec0-411b-8064-f214f7be0c44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437166447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1437166447
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.378662563
Short name T1049
Test name
Test status
Simulation time 125561068 ps
CPU time 4.6 seconds
Started Jul 07 04:52:40 PM PDT 24
Finished Jul 07 04:52:45 PM PDT 24
Peak memory 215720 kb
Host smart-91e0faad-d69a-4a9b-aad5-06bc24ba5408
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378662563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.378662563
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3889380808
Short name T188
Test name
Test status
Simulation time 145200931 ps
CPU time 4.59 seconds
Started Jul 07 04:52:52 PM PDT 24
Finished Jul 07 04:52:57 PM PDT 24
Peak memory 214880 kb
Host smart-46e868b5-6104-4271-8276-de3a0db86197
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889380808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3889380808
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1774083075
Short name T1043
Test name
Test status
Simulation time 11298641 ps
CPU time 0.74 seconds
Started Jul 07 04:53:07 PM PDT 24
Finished Jul 07 04:53:08 PM PDT 24
Peak memory 205208 kb
Host smart-e939c541-f6e5-4317-a6fb-ed9d75b01aa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774083075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1774083075
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.416510821
Short name T1038
Test name
Test status
Simulation time 8594963 ps
CPU time 0.79 seconds
Started Jul 07 04:53:10 PM PDT 24
Finished Jul 07 04:53:11 PM PDT 24
Peak memory 205140 kb
Host smart-ba8d4aad-3ae3-4580-b22d-93466c0d522e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416510821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.416510821
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3113314181
Short name T1069
Test name
Test status
Simulation time 8504840 ps
CPU time 0.72 seconds
Started Jul 07 04:53:10 PM PDT 24
Finished Jul 07 04:53:11 PM PDT 24
Peak memory 205328 kb
Host smart-a9138229-3bb3-42e7-9920-e2761548dc41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113314181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3113314181
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.851957356
Short name T935
Test name
Test status
Simulation time 137940074 ps
CPU time 0.95 seconds
Started Jul 07 04:53:09 PM PDT 24
Finished Jul 07 04:53:10 PM PDT 24
Peak memory 205288 kb
Host smart-b55cc7a7-7d00-41c2-ab62-f450ad27de74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851957356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.851957356
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3018097692
Short name T961
Test name
Test status
Simulation time 44119409 ps
CPU time 0.81 seconds
Started Jul 07 04:53:06 PM PDT 24
Finished Jul 07 04:53:07 PM PDT 24
Peak memory 205212 kb
Host smart-acb08fe2-09a6-447e-ae8e-8da559c5bab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018097692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3018097692
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.311647318
Short name T1028
Test name
Test status
Simulation time 9696204 ps
CPU time 0.87 seconds
Started Jul 07 04:53:11 PM PDT 24
Finished Jul 07 04:53:12 PM PDT 24
Peak memory 205296 kb
Host smart-7520852d-07c0-4af6-aaf8-f8460e7c0362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311647318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.311647318
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2694354595
Short name T974
Test name
Test status
Simulation time 39201094 ps
CPU time 0.78 seconds
Started Jul 07 04:53:10 PM PDT 24
Finished Jul 07 04:53:11 PM PDT 24
Peak memory 205328 kb
Host smart-5625ba06-5dd7-4ea4-8768-20bdf682c2eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694354595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2694354595
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4151008821
Short name T940
Test name
Test status
Simulation time 141474850 ps
CPU time 0.79 seconds
Started Jul 07 04:53:09 PM PDT 24
Finished Jul 07 04:53:10 PM PDT 24
Peak memory 205148 kb
Host smart-e9c6f864-21c9-4888-8b48-78ad3cfb3517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151008821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.4151008821
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2160384107
Short name T1067
Test name
Test status
Simulation time 213493273 ps
CPU time 0.85 seconds
Started Jul 07 04:53:13 PM PDT 24
Finished Jul 07 04:53:14 PM PDT 24
Peak memory 205252 kb
Host smart-85efb36b-508f-4483-830e-4eaa213cc0ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160384107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2160384107
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.4274414480
Short name T1025
Test name
Test status
Simulation time 13890445 ps
CPU time 0.89 seconds
Started Jul 07 04:53:13 PM PDT 24
Finished Jul 07 04:53:14 PM PDT 24
Peak memory 205220 kb
Host smart-219efb5d-a9dd-4694-b0b3-065d63d37c27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274414480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.4274414480
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.4210022207
Short name T1001
Test name
Test status
Simulation time 459679790 ps
CPU time 9.64 seconds
Started Jul 07 04:52:39 PM PDT 24
Finished Jul 07 04:52:49 PM PDT 24
Peak memory 205532 kb
Host smart-1d881702-29c6-4c58-88fc-284c2ab72272
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210022207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.4
210022207
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1289707821
Short name T1071
Test name
Test status
Simulation time 8549240377 ps
CPU time 16.83 seconds
Started Jul 07 04:52:38 PM PDT 24
Finished Jul 07 04:52:56 PM PDT 24
Peak memory 205380 kb
Host smart-b8c2182d-d0e2-4ad8-afbf-9e4d322b9515
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289707821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
289707821
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.566166189
Short name T925
Test name
Test status
Simulation time 42458378 ps
CPU time 0.97 seconds
Started Jul 07 04:52:40 PM PDT 24
Finished Jul 07 04:52:41 PM PDT 24
Peak memory 205332 kb
Host smart-c387e1aa-2d5b-4824-bc00-da21d9b3e15b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566166189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.566166189
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2339271608
Short name T1029
Test name
Test status
Simulation time 26546888 ps
CPU time 1.17 seconds
Started Jul 07 04:52:41 PM PDT 24
Finished Jul 07 04:52:43 PM PDT 24
Peak memory 205564 kb
Host smart-953f6d59-6585-4b2b-8283-dbb7b1604ab4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339271608 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2339271608
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1056383131
Short name T1080
Test name
Test status
Simulation time 21938359 ps
CPU time 1.16 seconds
Started Jul 07 04:52:38 PM PDT 24
Finished Jul 07 04:52:40 PM PDT 24
Peak memory 205512 kb
Host smart-f835ce50-5b54-4bd3-9d4b-0b3888298ace
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056383131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1056383131
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1875157035
Short name T1017
Test name
Test status
Simulation time 11543178 ps
CPU time 0.86 seconds
Started Jul 07 04:52:41 PM PDT 24
Finished Jul 07 04:52:42 PM PDT 24
Peak memory 205220 kb
Host smart-b0ca9b19-094b-48ac-9ffc-c43e134d267d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875157035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1875157035
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2501553318
Short name T1010
Test name
Test status
Simulation time 120816388 ps
CPU time 3.48 seconds
Started Jul 07 04:52:38 PM PDT 24
Finished Jul 07 04:52:42 PM PDT 24
Peak memory 205364 kb
Host smart-a7587387-5ddc-4b59-956c-1c48de722019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501553318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2501553318
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1047774815
Short name T1072
Test name
Test status
Simulation time 94696484 ps
CPU time 1.88 seconds
Started Jul 07 04:52:52 PM PDT 24
Finished Jul 07 04:52:55 PM PDT 24
Peak memory 213828 kb
Host smart-f5feb9bf-51bc-4869-8ac9-1e7b6458bff1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047774815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1047774815
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3175938131
Short name T1075
Test name
Test status
Simulation time 389796439 ps
CPU time 9.02 seconds
Started Jul 07 04:52:40 PM PDT 24
Finished Jul 07 04:52:49 PM PDT 24
Peak memory 220024 kb
Host smart-9605f294-1d40-4a7a-8003-393bb723f5bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175938131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3175938131
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.883435900
Short name T921
Test name
Test status
Simulation time 236012782 ps
CPU time 4.87 seconds
Started Jul 07 04:52:42 PM PDT 24
Finished Jul 07 04:52:48 PM PDT 24
Peak memory 214864 kb
Host smart-9ff47d09-81f7-4a44-aa3e-9bfcd5b81390
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883435900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.883435900
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3930653588
Short name T175
Test name
Test status
Simulation time 113609969 ps
CPU time 4.81 seconds
Started Jul 07 04:52:49 PM PDT 24
Finished Jul 07 04:52:54 PM PDT 24
Peak memory 213636 kb
Host smart-b6198d15-a4dd-4fea-8321-1a0ede048526
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930653588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3930653588
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3380467028
Short name T1030
Test name
Test status
Simulation time 39478364 ps
CPU time 0.73 seconds
Started Jul 07 04:53:12 PM PDT 24
Finished Jul 07 04:53:13 PM PDT 24
Peak memory 205244 kb
Host smart-dd242fac-32a3-44ff-91c5-7bbb82bc6a3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380467028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3380467028
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3392888692
Short name T914
Test name
Test status
Simulation time 24786160 ps
CPU time 0.81 seconds
Started Jul 07 04:53:13 PM PDT 24
Finished Jul 07 04:53:14 PM PDT 24
Peak memory 205300 kb
Host smart-7e08406a-916b-4f6d-8826-a9dd0b7b04cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392888692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3392888692
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1651353003
Short name T928
Test name
Test status
Simulation time 28727438 ps
CPU time 0.74 seconds
Started Jul 07 04:53:12 PM PDT 24
Finished Jul 07 04:53:14 PM PDT 24
Peak memory 205224 kb
Host smart-2f2cc045-f118-4b98-a8ee-38d760bb4002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651353003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1651353003
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2100146511
Short name T1040
Test name
Test status
Simulation time 17253500 ps
CPU time 0.81 seconds
Started Jul 07 04:53:13 PM PDT 24
Finished Jul 07 04:53:14 PM PDT 24
Peak memory 205320 kb
Host smart-4cc7b7f4-fd9a-4bee-b8db-7545a8cfaf57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100146511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2100146511
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2282670820
Short name T1013
Test name
Test status
Simulation time 24583566 ps
CPU time 0.75 seconds
Started Jul 07 04:53:11 PM PDT 24
Finished Jul 07 04:53:13 PM PDT 24
Peak memory 205268 kb
Host smart-d25db8aa-4623-48e6-a257-87503f1cebd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282670820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2282670820
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.274835452
Short name T915
Test name
Test status
Simulation time 29857663 ps
CPU time 0.83 seconds
Started Jul 07 04:53:11 PM PDT 24
Finished Jul 07 04:53:12 PM PDT 24
Peak memory 205212 kb
Host smart-b53d0595-7381-4f8e-b1d6-da1c54d36b5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274835452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.274835452
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2671262746
Short name T946
Test name
Test status
Simulation time 32952352 ps
CPU time 0.7 seconds
Started Jul 07 04:53:11 PM PDT 24
Finished Jul 07 04:53:12 PM PDT 24
Peak memory 205140 kb
Host smart-a028978b-edb0-4a55-8010-f87c5c6feb9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671262746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2671262746
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1030758397
Short name T924
Test name
Test status
Simulation time 44925342 ps
CPU time 0.76 seconds
Started Jul 07 04:53:11 PM PDT 24
Finished Jul 07 04:53:12 PM PDT 24
Peak memory 205320 kb
Host smart-83a4058b-00e5-492f-916e-3975440cfe7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030758397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1030758397
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.274249133
Short name T1011
Test name
Test status
Simulation time 9406755 ps
CPU time 0.87 seconds
Started Jul 07 04:53:11 PM PDT 24
Finished Jul 07 04:53:12 PM PDT 24
Peak memory 205228 kb
Host smart-0175b2b1-7e31-4719-b484-5d1cca2d40ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274249133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.274249133
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.4164684211
Short name T916
Test name
Test status
Simulation time 10547502 ps
CPU time 0.74 seconds
Started Jul 07 04:53:14 PM PDT 24
Finished Jul 07 04:53:15 PM PDT 24
Peak memory 205100 kb
Host smart-0e9d3174-fd8f-4e39-b065-d30473e05b7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164684211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.4164684211
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3813139466
Short name T1046
Test name
Test status
Simulation time 26120962 ps
CPU time 1.69 seconds
Started Jul 07 04:52:43 PM PDT 24
Finished Jul 07 04:52:45 PM PDT 24
Peak memory 213772 kb
Host smart-803f046c-3df2-4414-9a64-9e15ef73c5d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813139466 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3813139466
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1874792802
Short name T137
Test name
Test status
Simulation time 46169693 ps
CPU time 1.26 seconds
Started Jul 07 04:52:42 PM PDT 24
Finished Jul 07 04:52:44 PM PDT 24
Peak memory 205496 kb
Host smart-45d17445-a146-44c5-91be-4f27031801ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874792802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1874792802
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2298546822
Short name T1014
Test name
Test status
Simulation time 35163241 ps
CPU time 0.72 seconds
Started Jul 07 04:52:50 PM PDT 24
Finished Jul 07 04:52:51 PM PDT 24
Peak memory 205220 kb
Host smart-cea58ac3-a48c-4a31-ab23-fdf830667e99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298546822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2298546822
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2463441688
Short name T945
Test name
Test status
Simulation time 100756825 ps
CPU time 2.11 seconds
Started Jul 07 04:52:45 PM PDT 24
Finished Jul 07 04:52:48 PM PDT 24
Peak memory 205484 kb
Host smart-1d99519e-39d7-429e-b500-fee26902a2bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463441688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2463441688
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1182073963
Short name T122
Test name
Test status
Simulation time 107036217 ps
CPU time 1.88 seconds
Started Jul 07 04:52:44 PM PDT 24
Finished Jul 07 04:52:47 PM PDT 24
Peak memory 213852 kb
Host smart-a022d9c9-a441-484b-afac-f319b65f604c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182073963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1182073963
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.4217954799
Short name T1081
Test name
Test status
Simulation time 446414028 ps
CPU time 11.17 seconds
Started Jul 07 04:52:42 PM PDT 24
Finished Jul 07 04:52:54 PM PDT 24
Peak memory 213956 kb
Host smart-7a54fbec-1d9c-41fd-862d-2dd462443d4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217954799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.4217954799
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.449127372
Short name T1044
Test name
Test status
Simulation time 162777175 ps
CPU time 2.94 seconds
Started Jul 07 04:52:49 PM PDT 24
Finished Jul 07 04:52:53 PM PDT 24
Peak memory 213616 kb
Host smart-46310e15-0e96-4c91-bfc4-2563a6008c00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449127372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.449127372
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3728079452
Short name T1018
Test name
Test status
Simulation time 67297697 ps
CPU time 2.05 seconds
Started Jul 07 04:52:44 PM PDT 24
Finished Jul 07 04:52:46 PM PDT 24
Peak memory 213568 kb
Host smart-be509f2d-282d-4394-8b15-4f5fbad0d7e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728079452 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3728079452
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3983028792
Short name T987
Test name
Test status
Simulation time 120084812 ps
CPU time 1.62 seconds
Started Jul 07 04:52:42 PM PDT 24
Finished Jul 07 04:52:44 PM PDT 24
Peak memory 205376 kb
Host smart-1dcf3925-d496-48e1-b55f-f07c2adda3c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983028792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3983028792
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.10494422
Short name T1063
Test name
Test status
Simulation time 16576777 ps
CPU time 0.9 seconds
Started Jul 07 04:52:43 PM PDT 24
Finished Jul 07 04:52:44 PM PDT 24
Peak memory 205216 kb
Host smart-a5d4eba9-e51f-448d-8423-746bdacafea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10494422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.10494422
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2415632991
Short name T948
Test name
Test status
Simulation time 648401266 ps
CPU time 2.92 seconds
Started Jul 07 04:52:45 PM PDT 24
Finished Jul 07 04:52:49 PM PDT 24
Peak memory 205416 kb
Host smart-4174726b-9bbf-41a8-ba72-b82c1cd67c75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415632991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2415632991
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.390951354
Short name T985
Test name
Test status
Simulation time 97182420 ps
CPU time 1.83 seconds
Started Jul 07 04:52:42 PM PDT 24
Finished Jul 07 04:52:44 PM PDT 24
Peak memory 213904 kb
Host smart-c36600be-2eac-4896-9d44-aede0b270d49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390951354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.390951354
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3772597429
Short name T983
Test name
Test status
Simulation time 555496999 ps
CPU time 9.81 seconds
Started Jul 07 04:52:42 PM PDT 24
Finished Jul 07 04:52:53 PM PDT 24
Peak memory 213852 kb
Host smart-34d52a52-d19e-4658-b1d0-19f1ca7e65a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772597429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3772597429
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3190972466
Short name T967
Test name
Test status
Simulation time 100825823 ps
CPU time 3.81 seconds
Started Jul 07 04:52:44 PM PDT 24
Finished Jul 07 04:52:48 PM PDT 24
Peak memory 213508 kb
Host smart-563e01a4-2aac-410d-93e5-42403d63cefe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190972466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3190972466
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2426164808
Short name T187
Test name
Test status
Simulation time 341589508 ps
CPU time 5.26 seconds
Started Jul 07 04:52:42 PM PDT 24
Finished Jul 07 04:52:48 PM PDT 24
Peak memory 213600 kb
Host smart-f3ef9f71-2be2-4f5a-a51f-43254afe5c98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426164808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2426164808
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2272485064
Short name T959
Test name
Test status
Simulation time 56938666 ps
CPU time 1.6 seconds
Started Jul 07 04:52:43 PM PDT 24
Finished Jul 07 04:52:45 PM PDT 24
Peak memory 205400 kb
Host smart-6259970b-8333-47d3-a60a-78319c259b22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272485064 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2272485064
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.23059061
Short name T1078
Test name
Test status
Simulation time 29472743 ps
CPU time 0.91 seconds
Started Jul 07 04:52:44 PM PDT 24
Finished Jul 07 04:52:46 PM PDT 24
Peak memory 205344 kb
Host smart-f6104cc9-9466-4ef8-8e09-6bbd342c1e7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23059061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.23059061
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.898648394
Short name T942
Test name
Test status
Simulation time 12865547 ps
CPU time 0.89 seconds
Started Jul 07 04:52:43 PM PDT 24
Finished Jul 07 04:52:45 PM PDT 24
Peak memory 205216 kb
Host smart-3e9ce07f-ceac-474f-a5f1-98510eaa4c18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898648394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.898648394
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1648045173
Short name T956
Test name
Test status
Simulation time 47236733 ps
CPU time 1.94 seconds
Started Jul 07 04:52:54 PM PDT 24
Finished Jul 07 04:52:57 PM PDT 24
Peak memory 205312 kb
Host smart-a73583e5-118f-493e-8506-7858a72826c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648045173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1648045173
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2636083873
Short name T129
Test name
Test status
Simulation time 233958787 ps
CPU time 3.19 seconds
Started Jul 07 04:52:44 PM PDT 24
Finished Jul 07 04:52:48 PM PDT 24
Peak memory 213756 kb
Host smart-698b7f59-9395-4754-ae53-2a6dc4319bb8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636083873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2636083873
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3435331453
Short name T996
Test name
Test status
Simulation time 790353502 ps
CPU time 5.38 seconds
Started Jul 07 04:52:49 PM PDT 24
Finished Jul 07 04:52:55 PM PDT 24
Peak memory 219980 kb
Host smart-1fe40ca2-a2ef-4800-a052-ca6b376ab701
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435331453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3435331453
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1970738068
Short name T989
Test name
Test status
Simulation time 148551065 ps
CPU time 2.01 seconds
Started Jul 07 04:52:52 PM PDT 24
Finished Jul 07 04:52:55 PM PDT 24
Peak memory 213628 kb
Host smart-810f0e44-1fa1-426f-b512-c9be44d86d4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970738068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1970738068
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.314634904
Short name T971
Test name
Test status
Simulation time 100030169 ps
CPU time 1.52 seconds
Started Jul 07 04:52:46 PM PDT 24
Finished Jul 07 04:52:48 PM PDT 24
Peak memory 213644 kb
Host smart-a1d74c9d-923b-4424-8c87-05919e319893
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314634904 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.314634904
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.103849434
Short name T1016
Test name
Test status
Simulation time 22701605 ps
CPU time 0.98 seconds
Started Jul 07 04:52:47 PM PDT 24
Finished Jul 07 04:52:48 PM PDT 24
Peak memory 205244 kb
Host smart-b1ef051c-c2de-4c5a-a3fc-e612d3910603
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103849434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.103849434
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2985387795
Short name T970
Test name
Test status
Simulation time 11813498 ps
CPU time 0.72 seconds
Started Jul 07 04:52:49 PM PDT 24
Finished Jul 07 04:52:50 PM PDT 24
Peak memory 205108 kb
Host smart-6bdd6dea-d828-4020-9dbc-e77e357e92e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985387795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2985387795
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1738933250
Short name T995
Test name
Test status
Simulation time 21620555 ps
CPU time 1.5 seconds
Started Jul 07 04:52:50 PM PDT 24
Finished Jul 07 04:52:53 PM PDT 24
Peak memory 205392 kb
Host smart-6169fcc4-1000-4261-b56a-79790a46dc32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738933250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1738933250
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3537869570
Short name T1048
Test name
Test status
Simulation time 227828644 ps
CPU time 3.15 seconds
Started Jul 07 04:52:50 PM PDT 24
Finished Jul 07 04:52:54 PM PDT 24
Peak memory 213904 kb
Host smart-6272f0a3-c8f9-47af-a837-d386809df2b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537869570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3537869570
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3190392302
Short name T1060
Test name
Test status
Simulation time 681987234 ps
CPU time 4.93 seconds
Started Jul 07 04:52:50 PM PDT 24
Finished Jul 07 04:52:56 PM PDT 24
Peak memory 213908 kb
Host smart-d0af1c31-10d6-4334-9990-1ff0011aa856
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190392302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3190392302
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.4085403776
Short name T1051
Test name
Test status
Simulation time 25140511 ps
CPU time 1.62 seconds
Started Jul 07 04:52:53 PM PDT 24
Finished Jul 07 04:52:55 PM PDT 24
Peak memory 213288 kb
Host smart-ee39e399-8c7e-4f53-8ba3-6981209e4e4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085403776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.4085403776
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1438035155
Short name T1041
Test name
Test status
Simulation time 101596331 ps
CPU time 1.09 seconds
Started Jul 07 04:52:50 PM PDT 24
Finished Jul 07 04:52:51 PM PDT 24
Peak memory 213640 kb
Host smart-545c6f69-7fff-42f2-a2e5-80b8ae8075bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438035155 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1438035155
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1513853289
Short name T1052
Test name
Test status
Simulation time 51486171 ps
CPU time 1.55 seconds
Started Jul 07 04:52:50 PM PDT 24
Finished Jul 07 04:52:53 PM PDT 24
Peak memory 205396 kb
Host smart-22bde08a-6ea2-45f2-aeee-573ff508874b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513853289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1513853289
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3007944042
Short name T955
Test name
Test status
Simulation time 30643389 ps
CPU time 0.71 seconds
Started Jul 07 04:52:46 PM PDT 24
Finished Jul 07 04:52:47 PM PDT 24
Peak memory 205220 kb
Host smart-2141aae3-0ac1-4331-83b1-86fb8aab9340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007944042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3007944042
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2129976371
Short name T931
Test name
Test status
Simulation time 93730666 ps
CPU time 3.69 seconds
Started Jul 07 04:52:51 PM PDT 24
Finished Jul 07 04:52:56 PM PDT 24
Peak memory 205412 kb
Host smart-c3489cf2-d33a-4f3a-878a-513a0f84df80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129976371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2129976371
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3526768281
Short name T1074
Test name
Test status
Simulation time 202931998 ps
CPU time 3.16 seconds
Started Jul 07 04:52:47 PM PDT 24
Finished Jul 07 04:52:50 PM PDT 24
Peak memory 213904 kb
Host smart-6c35964d-0d10-4b9e-926f-f7a22db68740
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526768281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3526768281
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.4190029072
Short name T1036
Test name
Test status
Simulation time 426603617 ps
CPU time 14.79 seconds
Started Jul 07 04:52:49 PM PDT 24
Finished Jul 07 04:53:04 PM PDT 24
Peak memory 213800 kb
Host smart-9371746f-3625-4644-8687-b3c6caa626a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190029072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.4190029072
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1566252505
Short name T1079
Test name
Test status
Simulation time 51582049 ps
CPU time 2.85 seconds
Started Jul 07 04:52:45 PM PDT 24
Finished Jul 07 04:52:48 PM PDT 24
Peak memory 213636 kb
Host smart-2dcac244-bdcf-454f-8b2d-451debb09bf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566252505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1566252505
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2091011805
Short name T941
Test name
Test status
Simulation time 443921241 ps
CPU time 6.59 seconds
Started Jul 07 04:52:53 PM PDT 24
Finished Jul 07 04:53:00 PM PDT 24
Peak memory 213516 kb
Host smart-0f3c0279-b814-457e-ab87-6060ba35974d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091011805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2091011805
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.106666776
Short name T301
Test name
Test status
Simulation time 181673604 ps
CPU time 3.77 seconds
Started Jul 07 05:06:07 PM PDT 24
Finished Jul 07 05:06:11 PM PDT 24
Peak memory 214224 kb
Host smart-24f57c4e-0993-4703-9bb2-cf47f9f8cd0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106666776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.106666776
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.4272851953
Short name T737
Test name
Test status
Simulation time 104117423 ps
CPU time 2 seconds
Started Jul 07 05:06:07 PM PDT 24
Finished Jul 07 05:06:09 PM PDT 24
Peak memory 216384 kb
Host smart-99f7ca46-fa58-4aee-a427-eda2fdcc2bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272851953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.4272851953
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3627079197
Short name T243
Test name
Test status
Simulation time 74983971 ps
CPU time 3.2 seconds
Started Jul 07 05:06:06 PM PDT 24
Finished Jul 07 05:06:09 PM PDT 24
Peak memory 214300 kb
Host smart-1fc93333-664e-4d49-9b58-61d56f3c6497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627079197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3627079197
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3892991709
Short name T724
Test name
Test status
Simulation time 593107404 ps
CPU time 5.52 seconds
Started Jul 07 05:06:06 PM PDT 24
Finished Jul 07 05:06:12 PM PDT 24
Peak memory 208596 kb
Host smart-92956bf7-edbd-4406-a686-08fce2e0e915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892991709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3892991709
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2487582071
Short name T765
Test name
Test status
Simulation time 677285155 ps
CPU time 19.11 seconds
Started Jul 07 05:06:06 PM PDT 24
Finished Jul 07 05:06:25 PM PDT 24
Peak memory 210616 kb
Host smart-fb914455-d897-43e8-bc70-2c5cb9adbebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487582071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2487582071
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.649965081
Short name T684
Test name
Test status
Simulation time 144966611 ps
CPU time 2.75 seconds
Started Jul 07 05:06:04 PM PDT 24
Finished Jul 07 05:06:07 PM PDT 24
Peak memory 208060 kb
Host smart-5c65ee12-d98b-4069-99f4-5bd011a91d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649965081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.649965081
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1753477790
Short name T10
Test name
Test status
Simulation time 1526659776 ps
CPU time 12.59 seconds
Started Jul 07 05:06:10 PM PDT 24
Finished Jul 07 05:06:23 PM PDT 24
Peak memory 231036 kb
Host smart-16d79ff7-b5c0-41bd-a8b6-c5ca658bdbbb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753477790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1753477790
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.47528855
Short name T662
Test name
Test status
Simulation time 2776961083 ps
CPU time 27.5 seconds
Started Jul 07 05:06:04 PM PDT 24
Finished Jul 07 05:06:32 PM PDT 24
Peak memory 208488 kb
Host smart-c1588b51-425d-40be-85d3-987162bb490a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47528855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.47528855
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.481205534
Short name T668
Test name
Test status
Simulation time 217592516 ps
CPU time 2.89 seconds
Started Jul 07 05:06:05 PM PDT 24
Finished Jul 07 05:06:08 PM PDT 24
Peak memory 206896 kb
Host smart-b4d793a4-9cf2-4728-86e3-80af9bfc4bf3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481205534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.481205534
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.579827298
Short name T337
Test name
Test status
Simulation time 251160912 ps
CPU time 3.11 seconds
Started Jul 07 05:06:06 PM PDT 24
Finished Jul 07 05:06:10 PM PDT 24
Peak memory 208532 kb
Host smart-c3a6aa57-8c9e-4ab4-8390-b71064b9d570
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579827298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.579827298
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2062192163
Short name T868
Test name
Test status
Simulation time 2498013976 ps
CPU time 17.87 seconds
Started Jul 07 05:06:07 PM PDT 24
Finished Jul 07 05:06:25 PM PDT 24
Peak memory 208068 kb
Host smart-919ecaf9-9877-47ad-9d9b-5d2cc7b55797
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062192163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2062192163
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2554368570
Short name T15
Test name
Test status
Simulation time 61765513 ps
CPU time 2.03 seconds
Started Jul 07 05:06:06 PM PDT 24
Finished Jul 07 05:06:08 PM PDT 24
Peak memory 207688 kb
Host smart-b5ea3ce7-05d3-4569-a65c-fb751dbdbde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554368570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2554368570
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3368959875
Short name T424
Test name
Test status
Simulation time 139402910 ps
CPU time 3.97 seconds
Started Jul 07 05:06:07 PM PDT 24
Finished Jul 07 05:06:11 PM PDT 24
Peak memory 207896 kb
Host smart-eef597da-c440-4c6f-a0f1-91521411d891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368959875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3368959875
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1566514957
Short name T347
Test name
Test status
Simulation time 1773958419 ps
CPU time 13.08 seconds
Started Jul 07 05:06:12 PM PDT 24
Finished Jul 07 05:06:25 PM PDT 24
Peak memory 222404 kb
Host smart-d9e53e9c-b328-4eee-b248-c4bbe9170847
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566514957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1566514957
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1103252644
Short name T57
Test name
Test status
Simulation time 378989017 ps
CPU time 12.05 seconds
Started Jul 07 05:06:11 PM PDT 24
Finished Jul 07 05:06:23 PM PDT 24
Peak memory 222496 kb
Host smart-132cdc48-271a-4905-bca3-ff98003718b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103252644 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1103252644
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1221594497
Short name T589
Test name
Test status
Simulation time 139780652 ps
CPU time 4.38 seconds
Started Jul 07 05:06:05 PM PDT 24
Finished Jul 07 05:06:09 PM PDT 24
Peak memory 207776 kb
Host smart-ff383f01-2877-4fe7-bfde-8bb54bd842f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221594497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1221594497
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.322228876
Short name T510
Test name
Test status
Simulation time 108110638 ps
CPU time 2.61 seconds
Started Jul 07 05:06:11 PM PDT 24
Finished Jul 07 05:06:14 PM PDT 24
Peak memory 210636 kb
Host smart-881fb8c5-62ef-4a13-a24f-e50df56f341e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322228876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.322228876
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1805066714
Short name T892
Test name
Test status
Simulation time 14999134 ps
CPU time 0.98 seconds
Started Jul 07 05:06:17 PM PDT 24
Finished Jul 07 05:06:18 PM PDT 24
Peak memory 206016 kb
Host smart-64b7c5f2-c67a-4091-9aa3-ea3f7b838cab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805066714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1805066714
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2480780800
Short name T871
Test name
Test status
Simulation time 294753530 ps
CPU time 2.97 seconds
Started Jul 07 05:06:11 PM PDT 24
Finished Jul 07 05:06:14 PM PDT 24
Peak memory 214308 kb
Host smart-cbc2bebb-8118-4d93-a18b-ce1d017634e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2480780800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2480780800
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2372694934
Short name T66
Test name
Test status
Simulation time 243937839 ps
CPU time 7.69 seconds
Started Jul 07 05:06:16 PM PDT 24
Finished Jul 07 05:06:24 PM PDT 24
Peak memory 221912 kb
Host smart-faa20b30-d10a-4d9a-aeb7-d52d80d6a462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372694934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2372694934
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2462655571
Short name T275
Test name
Test status
Simulation time 564992851 ps
CPU time 10.31 seconds
Started Jul 07 05:06:13 PM PDT 24
Finished Jul 07 05:06:23 PM PDT 24
Peak memory 214220 kb
Host smart-fa8a05f7-591a-40f6-b336-3f048255fbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462655571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2462655571
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1204646381
Short name T647
Test name
Test status
Simulation time 129298830 ps
CPU time 2.4 seconds
Started Jul 07 05:06:16 PM PDT 24
Finished Jul 07 05:06:19 PM PDT 24
Peak memory 214328 kb
Host smart-64f5083b-561b-4db8-9909-3d855f634972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204646381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1204646381
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.4199082918
Short name T803
Test name
Test status
Simulation time 798226044 ps
CPU time 3.54 seconds
Started Jul 07 05:06:17 PM PDT 24
Finished Jul 07 05:06:20 PM PDT 24
Peak memory 214236 kb
Host smart-8cbd6e42-4564-42aa-841f-decbf8bea89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199082918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.4199082918
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.391530461
Short name T583
Test name
Test status
Simulation time 618739536 ps
CPU time 8.17 seconds
Started Jul 07 05:06:12 PM PDT 24
Finished Jul 07 05:06:21 PM PDT 24
Peak memory 222376 kb
Host smart-212769fb-cfbf-4a9d-b962-3ffa1b8e3b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391530461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.391530461
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.66425147
Short name T839
Test name
Test status
Simulation time 154243995 ps
CPU time 3.08 seconds
Started Jul 07 05:06:11 PM PDT 24
Finished Jul 07 05:06:14 PM PDT 24
Peak memory 207920 kb
Host smart-c77acfe6-aedc-434f-87cf-c5315da562d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66425147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.66425147
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.4157329173
Short name T42
Test name
Test status
Simulation time 1487745371 ps
CPU time 32.1 seconds
Started Jul 07 05:06:16 PM PDT 24
Finished Jul 07 05:06:48 PM PDT 24
Peak memory 239572 kb
Host smart-ca70728c-ec92-4c67-af85-c2f4e0a595aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157329173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.4157329173
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.493980153
Short name T436
Test name
Test status
Simulation time 102482838 ps
CPU time 4.29 seconds
Started Jul 07 05:06:15 PM PDT 24
Finished Jul 07 05:06:20 PM PDT 24
Peak memory 206772 kb
Host smart-d93d984b-b4dc-4c73-b6e2-b8e810dae87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493980153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.493980153
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2433839426
Short name T649
Test name
Test status
Simulation time 82750848 ps
CPU time 3.34 seconds
Started Jul 07 05:06:13 PM PDT 24
Finished Jul 07 05:06:16 PM PDT 24
Peak memory 208536 kb
Host smart-4ad8d271-0e40-4444-b616-e9428989ddd4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433839426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2433839426
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3303331905
Short name T512
Test name
Test status
Simulation time 295518717 ps
CPU time 4.3 seconds
Started Jul 07 05:06:13 PM PDT 24
Finished Jul 07 05:06:17 PM PDT 24
Peak memory 207936 kb
Host smart-45b2d192-df30-45b5-88c8-cc6204a161c8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303331905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3303331905
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1200851321
Short name T752
Test name
Test status
Simulation time 75626182 ps
CPU time 3.44 seconds
Started Jul 07 05:06:14 PM PDT 24
Finished Jul 07 05:06:18 PM PDT 24
Peak memory 208492 kb
Host smart-6bea9c17-737d-4cfb-bc62-7a2007cfb4c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200851321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1200851321
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.4137350289
Short name T207
Test name
Test status
Simulation time 91545473 ps
CPU time 3.56 seconds
Started Jul 07 05:06:15 PM PDT 24
Finished Jul 07 05:06:19 PM PDT 24
Peak memory 209604 kb
Host smart-de166dab-72bb-415a-a735-72964d7716e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137350289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.4137350289
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2772354767
Short name T849
Test name
Test status
Simulation time 124422171 ps
CPU time 2.33 seconds
Started Jul 07 05:06:12 PM PDT 24
Finished Jul 07 05:06:14 PM PDT 24
Peak memory 208136 kb
Host smart-3fa238d0-faa1-40f0-b3e4-e210db2ecbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772354767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2772354767
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.4128931612
Short name T81
Test name
Test status
Simulation time 2193152337 ps
CPU time 10.09 seconds
Started Jul 07 05:06:17 PM PDT 24
Finished Jul 07 05:06:27 PM PDT 24
Peak memory 221208 kb
Host smart-1af5ae3f-27bf-4533-866d-50778502fbba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128931612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.4128931612
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3845678966
Short name T536
Test name
Test status
Simulation time 1387938311 ps
CPU time 8.17 seconds
Started Jul 07 05:06:15 PM PDT 24
Finished Jul 07 05:06:23 PM PDT 24
Peak memory 208356 kb
Host smart-72bda6e1-a544-4246-8724-e678df98f631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845678966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3845678966
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.617520203
Short name T777
Test name
Test status
Simulation time 98190820 ps
CPU time 3.8 seconds
Started Jul 07 05:06:16 PM PDT 24
Finished Jul 07 05:06:20 PM PDT 24
Peak memory 210396 kb
Host smart-4ee698d9-c07d-493c-ba3c-221ec6dc344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617520203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.617520203
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1160890953
Short name T445
Test name
Test status
Simulation time 36273014 ps
CPU time 0.85 seconds
Started Jul 07 05:07:08 PM PDT 24
Finished Jul 07 05:07:10 PM PDT 24
Peak memory 205948 kb
Host smart-f60dac72-5053-4e26-8cd5-0db8da6d348a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160890953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1160890953
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1437462748
Short name T219
Test name
Test status
Simulation time 408361550 ps
CPU time 6.11 seconds
Started Jul 07 05:07:04 PM PDT 24
Finished Jul 07 05:07:10 PM PDT 24
Peak memory 222752 kb
Host smart-7699f794-792c-4c15-b616-f1dbbdb5e73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437462748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1437462748
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2839174746
Short name T876
Test name
Test status
Simulation time 678440669 ps
CPU time 4.87 seconds
Started Jul 07 05:07:06 PM PDT 24
Finished Jul 07 05:07:11 PM PDT 24
Peak memory 220164 kb
Host smart-1c490d43-7b5b-4ba1-b3cf-3b8296bee425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839174746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2839174746
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3644900395
Short name T2
Test name
Test status
Simulation time 123964868 ps
CPU time 3.92 seconds
Started Jul 07 05:07:04 PM PDT 24
Finished Jul 07 05:07:08 PM PDT 24
Peak memory 214320 kb
Host smart-ce7d7f21-abf0-4ec3-a310-ca2d04624413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644900395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3644900395
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.742505854
Short name T874
Test name
Test status
Simulation time 143587233 ps
CPU time 6.28 seconds
Started Jul 07 05:07:05 PM PDT 24
Finished Jul 07 05:07:12 PM PDT 24
Peak memory 218504 kb
Host smart-74ee0d44-7237-4614-87b9-141a3569301d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742505854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.742505854
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1746194444
Short name T782
Test name
Test status
Simulation time 1093814496 ps
CPU time 5.36 seconds
Started Jul 07 05:07:02 PM PDT 24
Finished Jul 07 05:07:08 PM PDT 24
Peak memory 208256 kb
Host smart-02aaab80-c513-4c79-98af-ee7c26f05abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746194444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1746194444
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1329669920
Short name T599
Test name
Test status
Simulation time 565424103 ps
CPU time 6.9 seconds
Started Jul 07 05:07:01 PM PDT 24
Finished Jul 07 05:07:08 PM PDT 24
Peak memory 207024 kb
Host smart-8d6217be-bef0-4c37-8f68-d9289e169294
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329669920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1329669920
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2571673527
Short name T450
Test name
Test status
Simulation time 665430845 ps
CPU time 7.03 seconds
Started Jul 07 05:07:00 PM PDT 24
Finished Jul 07 05:07:08 PM PDT 24
Peak memory 208540 kb
Host smart-1649c5f5-8f4c-405a-a1bf-396d25f7a78c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571673527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2571673527
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2407118723
Short name T206
Test name
Test status
Simulation time 251942652 ps
CPU time 3.07 seconds
Started Jul 07 05:07:05 PM PDT 24
Finished Jul 07 05:07:09 PM PDT 24
Peak memory 207016 kb
Host smart-7f805e05-093e-4b10-a790-90c3d3c893d2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407118723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2407118723
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1647206529
Short name T795
Test name
Test status
Simulation time 808205353 ps
CPU time 3.48 seconds
Started Jul 07 05:07:04 PM PDT 24
Finished Jul 07 05:07:08 PM PDT 24
Peak memory 207940 kb
Host smart-4498bb15-c6a1-4547-bb08-32389e43d67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647206529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1647206529
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.294367698
Short name T581
Test name
Test status
Simulation time 67767326 ps
CPU time 3.22 seconds
Started Jul 07 05:07:02 PM PDT 24
Finished Jul 07 05:07:05 PM PDT 24
Peak memory 208488 kb
Host smart-c1a9b6f4-b8cc-48f6-b9a9-e5afe913c969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294367698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.294367698
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2336400581
Short name T826
Test name
Test status
Simulation time 1341434350 ps
CPU time 13.74 seconds
Started Jul 07 05:07:06 PM PDT 24
Finished Jul 07 05:07:20 PM PDT 24
Peak memory 219844 kb
Host smart-34aa4218-cfdd-430c-85f5-f7dcb802abf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336400581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2336400581
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2635587388
Short name T153
Test name
Test status
Simulation time 2668279292 ps
CPU time 22.96 seconds
Started Jul 07 05:07:09 PM PDT 24
Finished Jul 07 05:07:33 PM PDT 24
Peak memory 222532 kb
Host smart-bde961c7-42e7-4f29-aae1-a631a8d1b4c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635587388 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2635587388
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.576173225
Short name T265
Test name
Test status
Simulation time 371143071 ps
CPU time 4.01 seconds
Started Jul 07 05:07:04 PM PDT 24
Finished Jul 07 05:07:09 PM PDT 24
Peak memory 209104 kb
Host smart-288581a2-b93d-412a-8c19-961871883ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576173225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.576173225
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2701789187
Short name T94
Test name
Test status
Simulation time 11357943 ps
CPU time 0.85 seconds
Started Jul 07 05:07:10 PM PDT 24
Finished Jul 07 05:07:11 PM PDT 24
Peak memory 205984 kb
Host smart-1ea68d06-e32f-491f-be58-45cefd3dee37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701789187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2701789187
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3223114780
Short name T383
Test name
Test status
Simulation time 45461469 ps
CPU time 2.53 seconds
Started Jul 07 05:07:05 PM PDT 24
Finished Jul 07 05:07:09 PM PDT 24
Peak memory 214256 kb
Host smart-8178f911-7402-4ace-b52a-22598c104410
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3223114780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3223114780
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1858763821
Short name T519
Test name
Test status
Simulation time 409940685 ps
CPU time 4.85 seconds
Started Jul 07 05:07:08 PM PDT 24
Finished Jul 07 05:07:13 PM PDT 24
Peak memory 207380 kb
Host smart-56b940d0-a31c-44b1-96cd-49fd563fd773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858763821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1858763821
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3345795931
Short name T271
Test name
Test status
Simulation time 90717075 ps
CPU time 1.75 seconds
Started Jul 07 05:07:09 PM PDT 24
Finished Jul 07 05:07:12 PM PDT 24
Peak memory 214316 kb
Host smart-4ade1165-8bc8-446e-8b8f-83fa1b5cd6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345795931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3345795931
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1811877677
Short name T331
Test name
Test status
Simulation time 40871623 ps
CPU time 3.02 seconds
Started Jul 07 05:07:09 PM PDT 24
Finished Jul 07 05:07:12 PM PDT 24
Peak memory 211288 kb
Host smart-5b9ed589-24a1-4227-94c7-91d3d454f85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811877677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1811877677
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3083723764
Short name T221
Test name
Test status
Simulation time 125573403 ps
CPU time 2.22 seconds
Started Jul 07 05:07:07 PM PDT 24
Finished Jul 07 05:07:09 PM PDT 24
Peak memory 219884 kb
Host smart-1eaafa22-5fe8-48e9-805e-f357135eeb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083723764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3083723764
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1462268195
Short name T93
Test name
Test status
Simulation time 394250837 ps
CPU time 9.83 seconds
Started Jul 07 05:07:09 PM PDT 24
Finished Jul 07 05:07:19 PM PDT 24
Peak memory 207436 kb
Host smart-6a9136d8-9bbe-44cb-9001-52a28d7de299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462268195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1462268195
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.122895486
Short name T825
Test name
Test status
Simulation time 1356875706 ps
CPU time 14.06 seconds
Started Jul 07 05:07:05 PM PDT 24
Finished Jul 07 05:07:20 PM PDT 24
Peak memory 207864 kb
Host smart-a51ed6b1-f117-40ad-9a3a-ec07b9a82fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122895486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.122895486
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.4176137278
Short name T116
Test name
Test status
Simulation time 153969244 ps
CPU time 4.57 seconds
Started Jul 07 05:07:07 PM PDT 24
Finished Jul 07 05:07:12 PM PDT 24
Peak memory 208684 kb
Host smart-b45027bc-b284-49ad-aff4-029724fbb001
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176137278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.4176137278
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3266997885
Short name T788
Test name
Test status
Simulation time 34924806 ps
CPU time 2.44 seconds
Started Jul 07 05:07:05 PM PDT 24
Finished Jul 07 05:07:07 PM PDT 24
Peak memory 206900 kb
Host smart-03441021-87b8-4b79-ac80-af187536080b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266997885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3266997885
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.669997535
Short name T205
Test name
Test status
Simulation time 379207754 ps
CPU time 3.26 seconds
Started Jul 07 05:07:09 PM PDT 24
Finished Jul 07 05:07:13 PM PDT 24
Peak memory 208728 kb
Host smart-95ef25ec-dbf2-4e93-b214-65e2ab517235
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669997535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.669997535
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2067329559
Short name T828
Test name
Test status
Simulation time 900389743 ps
CPU time 4.18 seconds
Started Jul 07 05:07:09 PM PDT 24
Finished Jul 07 05:07:13 PM PDT 24
Peak memory 209604 kb
Host smart-afe667d3-bd7f-4962-9ece-790ed4e6f7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067329559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2067329559
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3681397443
Short name T648
Test name
Test status
Simulation time 159914912 ps
CPU time 2.46 seconds
Started Jul 07 05:07:04 PM PDT 24
Finished Jul 07 05:07:07 PM PDT 24
Peak memory 206112 kb
Host smart-b740d5cb-7122-497f-a4f1-a5cd3e534741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681397443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3681397443
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2053833319
Short name T254
Test name
Test status
Simulation time 129679942 ps
CPU time 6.47 seconds
Started Jul 07 05:07:10 PM PDT 24
Finished Jul 07 05:07:16 PM PDT 24
Peak memory 218320 kb
Host smart-a0a92dba-3f88-4c81-b85d-337a53752110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053833319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2053833319
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3791655765
Short name T697
Test name
Test status
Simulation time 44095835 ps
CPU time 2.59 seconds
Started Jul 07 05:07:09 PM PDT 24
Finished Jul 07 05:07:12 PM PDT 24
Peak memory 209984 kb
Host smart-ae2924cc-a9f1-4eb3-9c0a-8dc066bc089f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791655765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3791655765
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2804210027
Short name T515
Test name
Test status
Simulation time 64015703 ps
CPU time 0.84 seconds
Started Jul 07 05:07:18 PM PDT 24
Finished Jul 07 05:07:19 PM PDT 24
Peak memory 205964 kb
Host smart-ad6d95f2-d09d-4e53-a1e4-80539e7f399b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804210027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2804210027
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3570556758
Short name T800
Test name
Test status
Simulation time 1031546183 ps
CPU time 10.56 seconds
Started Jul 07 05:07:13 PM PDT 24
Finished Jul 07 05:07:24 PM PDT 24
Peak memory 214308 kb
Host smart-33619000-6d5d-4378-94ad-0f0c2a4370ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570556758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3570556758
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3066784916
Short name T310
Test name
Test status
Simulation time 214481288 ps
CPU time 2.28 seconds
Started Jul 07 05:07:15 PM PDT 24
Finished Jul 07 05:07:17 PM PDT 24
Peak memory 214256 kb
Host smart-c2d35603-62b3-4ad0-b100-f054089a1e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066784916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3066784916
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3822791510
Short name T218
Test name
Test status
Simulation time 263592927 ps
CPU time 3.8 seconds
Started Jul 07 05:07:13 PM PDT 24
Finished Jul 07 05:07:17 PM PDT 24
Peak memory 209820 kb
Host smart-81178268-ddbb-4959-9186-de58b4036744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822791510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3822791510
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.4246969148
Short name T276
Test name
Test status
Simulation time 401753348 ps
CPU time 4.65 seconds
Started Jul 07 05:07:15 PM PDT 24
Finished Jul 07 05:07:20 PM PDT 24
Peak memory 210396 kb
Host smart-7f23633e-801f-41ef-8c8c-0dec404edab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246969148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.4246969148
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.634955886
Short name T553
Test name
Test status
Simulation time 150604006 ps
CPU time 3.01 seconds
Started Jul 07 05:07:15 PM PDT 24
Finished Jul 07 05:07:18 PM PDT 24
Peak memory 206900 kb
Host smart-700cf7a2-2055-4418-8c30-a2be505f0129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634955886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.634955886
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3152386869
Short name T86
Test name
Test status
Simulation time 112483472 ps
CPU time 4.93 seconds
Started Jul 07 05:07:14 PM PDT 24
Finished Jul 07 05:07:20 PM PDT 24
Peak memory 208388 kb
Host smart-6c8c0bc3-aca2-4407-a343-62b897bd2191
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152386869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3152386869
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3162022850
Short name T764
Test name
Test status
Simulation time 151388476 ps
CPU time 4.1 seconds
Started Jul 07 05:07:15 PM PDT 24
Finished Jul 07 05:07:20 PM PDT 24
Peak memory 206936 kb
Host smart-4929f1b4-cafb-4a92-a59b-a9b9bfaa0e08
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162022850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3162022850
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2746137585
Short name T164
Test name
Test status
Simulation time 397477563 ps
CPU time 3.8 seconds
Started Jul 07 05:07:14 PM PDT 24
Finished Jul 07 05:07:19 PM PDT 24
Peak memory 206948 kb
Host smart-23b2bc68-4dbd-42ca-9720-71b6d1f8abe0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746137585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2746137585
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3037211564
Short name T354
Test name
Test status
Simulation time 392781964 ps
CPU time 6.91 seconds
Started Jul 07 05:07:15 PM PDT 24
Finished Jul 07 05:07:22 PM PDT 24
Peak memory 214260 kb
Host smart-b14bdbb6-6952-4746-a044-178b29e0a95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037211564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3037211564
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1863347883
Short name T605
Test name
Test status
Simulation time 239326849 ps
CPU time 4.62 seconds
Started Jul 07 05:07:11 PM PDT 24
Finished Jul 07 05:07:16 PM PDT 24
Peak memory 208852 kb
Host smart-8e1c585c-7f3d-4ab1-8117-9c263496220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863347883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1863347883
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1659941511
Short name T796
Test name
Test status
Simulation time 162261715 ps
CPU time 4.82 seconds
Started Jul 07 05:07:14 PM PDT 24
Finished Jul 07 05:07:19 PM PDT 24
Peak memory 208212 kb
Host smart-caf85cf1-7ca9-4300-9097-5a61a25d8f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659941511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1659941511
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3358312104
Short name T58
Test name
Test status
Simulation time 157124564 ps
CPU time 2.72 seconds
Started Jul 07 05:07:16 PM PDT 24
Finished Jul 07 05:07:19 PM PDT 24
Peak memory 210320 kb
Host smart-32f62281-c99a-4aa6-ba4e-635b1f6b16f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358312104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3358312104
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.4282283552
Short name T425
Test name
Test status
Simulation time 12906407 ps
CPU time 0.79 seconds
Started Jul 07 05:07:25 PM PDT 24
Finished Jul 07 05:07:26 PM PDT 24
Peak memory 205980 kb
Host smart-216e5600-f71e-4a8c-a881-4fe2662923ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282283552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.4282283552
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.221462264
Short name T114
Test name
Test status
Simulation time 147682462 ps
CPU time 2.93 seconds
Started Jul 07 05:07:20 PM PDT 24
Finished Jul 07 05:07:23 PM PDT 24
Peak memory 214332 kb
Host smart-26ec6a3b-e395-4ff7-84bb-351c5369045d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=221462264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.221462264
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3644421843
Short name T69
Test name
Test status
Simulation time 241781047 ps
CPU time 6.57 seconds
Started Jul 07 05:07:18 PM PDT 24
Finished Jul 07 05:07:25 PM PDT 24
Peak memory 218208 kb
Host smart-c125b6c5-5480-4564-b24c-9fcdac534d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644421843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3644421843
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3967257295
Short name T704
Test name
Test status
Simulation time 216096084 ps
CPU time 4.69 seconds
Started Jul 07 05:07:17 PM PDT 24
Finished Jul 07 05:07:22 PM PDT 24
Peak memory 208828 kb
Host smart-7aa5bf24-effc-411f-ae86-48e7ab4d3289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967257295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3967257295
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.598466539
Short name T608
Test name
Test status
Simulation time 174168857 ps
CPU time 3.89 seconds
Started Jul 07 05:07:21 PM PDT 24
Finished Jul 07 05:07:26 PM PDT 24
Peak memory 221332 kb
Host smart-7cefc3f0-7103-4947-be7c-64f4b9adeb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598466539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.598466539
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3675958260
Short name T47
Test name
Test status
Simulation time 79603657 ps
CPU time 1.75 seconds
Started Jul 07 05:07:18 PM PDT 24
Finished Jul 07 05:07:20 PM PDT 24
Peak memory 214256 kb
Host smart-10c1cb53-c7d7-4588-8cc2-96e142808e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675958260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3675958260
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1472643258
Short name T653
Test name
Test status
Simulation time 92859202 ps
CPU time 3.08 seconds
Started Jul 07 05:07:17 PM PDT 24
Finished Jul 07 05:07:21 PM PDT 24
Peak memory 209720 kb
Host smart-c15be814-ec94-4d90-a6fb-e98299f70587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472643258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1472643258
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3069925894
Short name T899
Test name
Test status
Simulation time 270416169 ps
CPU time 3.14 seconds
Started Jul 07 05:07:16 PM PDT 24
Finished Jul 07 05:07:19 PM PDT 24
Peak memory 214636 kb
Host smart-ceac0908-f736-47a5-8125-47ec1fffeb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069925894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3069925894
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2224793482
Short name T719
Test name
Test status
Simulation time 2654082298 ps
CPU time 16.83 seconds
Started Jul 07 05:07:18 PM PDT 24
Finished Jul 07 05:07:35 PM PDT 24
Peak memory 208868 kb
Host smart-2f03179d-85c3-4342-9a11-84ac12f12fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224793482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2224793482
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2933944411
Short name T478
Test name
Test status
Simulation time 107349355 ps
CPU time 2.42 seconds
Started Jul 07 05:07:18 PM PDT 24
Finished Jul 07 05:07:21 PM PDT 24
Peak memory 206904 kb
Host smart-63e5b092-d096-449c-9d5c-179cfecd0b96
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933944411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2933944411
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3224069466
Short name T809
Test name
Test status
Simulation time 134862179 ps
CPU time 2.28 seconds
Started Jul 07 05:07:18 PM PDT 24
Finished Jul 07 05:07:21 PM PDT 24
Peak memory 207412 kb
Host smart-521f0f31-d671-49c8-b182-4073d93f4c6e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224069466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3224069466
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.882493700
Short name T614
Test name
Test status
Simulation time 134125055 ps
CPU time 3.47 seconds
Started Jul 07 05:07:17 PM PDT 24
Finished Jul 07 05:07:21 PM PDT 24
Peak memory 208704 kb
Host smart-4b0a7790-9121-42e8-b48d-0b50bda107f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882493700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.882493700
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.505040286
Short name T707
Test name
Test status
Simulation time 196911130 ps
CPU time 1.9 seconds
Started Jul 07 05:07:20 PM PDT 24
Finished Jul 07 05:07:22 PM PDT 24
Peak memory 209396 kb
Host smart-57cde254-4633-44af-8a40-52d63e1912af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505040286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.505040286
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.4008852632
Short name T196
Test name
Test status
Simulation time 100270906 ps
CPU time 2.61 seconds
Started Jul 07 05:07:17 PM PDT 24
Finished Jul 07 05:07:20 PM PDT 24
Peak memory 208312 kb
Host smart-8850b5e0-b41a-41fe-86be-4572935e7940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008852632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.4008852632
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2955005980
Short name T798
Test name
Test status
Simulation time 4321427811 ps
CPU time 17.15 seconds
Started Jul 07 05:07:18 PM PDT 24
Finished Jul 07 05:07:35 PM PDT 24
Peak memory 209476 kb
Host smart-324da86c-5ddc-495d-a833-37dd4a952fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955005980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2955005980
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.466631617
Short name T195
Test name
Test status
Simulation time 157294719 ps
CPU time 1.44 seconds
Started Jul 07 05:07:21 PM PDT 24
Finished Jul 07 05:07:23 PM PDT 24
Peak memory 208600 kb
Host smart-2c4a5bbc-d138-41e4-83ec-0caca403e133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466631617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.466631617
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2704118452
Short name T846
Test name
Test status
Simulation time 46359947 ps
CPU time 0.92 seconds
Started Jul 07 05:07:25 PM PDT 24
Finished Jul 07 05:07:27 PM PDT 24
Peak memory 205924 kb
Host smart-e24a3aa3-0de6-4a4e-b022-2c5e0aeb6feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704118452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2704118452
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1942507555
Short name T304
Test name
Test status
Simulation time 219899053 ps
CPU time 4.32 seconds
Started Jul 07 05:07:24 PM PDT 24
Finished Jul 07 05:07:29 PM PDT 24
Peak memory 221840 kb
Host smart-17423052-e254-4007-b6f8-36cbea1f7455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942507555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1942507555
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1500468877
Short name T328
Test name
Test status
Simulation time 86549257 ps
CPU time 2.57 seconds
Started Jul 07 05:07:24 PM PDT 24
Finished Jul 07 05:07:27 PM PDT 24
Peak memory 208768 kb
Host smart-35478379-c310-4ce4-bdb6-efd98e7e0155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500468877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1500468877
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.773630120
Short name T109
Test name
Test status
Simulation time 119771243 ps
CPU time 2.63 seconds
Started Jul 07 05:07:24 PM PDT 24
Finished Jul 07 05:07:27 PM PDT 24
Peak memory 209116 kb
Host smart-221716ed-666c-4a0f-a60a-0da10a5a9509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773630120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.773630120
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3936387527
Short name T631
Test name
Test status
Simulation time 299267137 ps
CPU time 2.2 seconds
Started Jul 07 05:07:23 PM PDT 24
Finished Jul 07 05:07:25 PM PDT 24
Peak memory 214564 kb
Host smart-a804ce87-8fa4-4473-8681-54272209e72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936387527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3936387527
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.4203408479
Short name T772
Test name
Test status
Simulation time 246114954 ps
CPU time 3.42 seconds
Started Jul 07 05:07:22 PM PDT 24
Finished Jul 07 05:07:26 PM PDT 24
Peak memory 207268 kb
Host smart-86c515fb-ec3d-4634-a160-abd699f515b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203408479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4203408479
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3661466265
Short name T681
Test name
Test status
Simulation time 39641955 ps
CPU time 2.38 seconds
Started Jul 07 05:07:22 PM PDT 24
Finished Jul 07 05:07:25 PM PDT 24
Peak memory 206812 kb
Host smart-2c526bf3-3ddf-412f-a950-fee67c44d3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661466265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3661466265
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3881478149
Short name T507
Test name
Test status
Simulation time 668382440 ps
CPU time 7.36 seconds
Started Jul 07 05:07:23 PM PDT 24
Finished Jul 07 05:07:30 PM PDT 24
Peak memory 208136 kb
Host smart-c5102b9b-f11c-413a-9121-008a45981673
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881478149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3881478149
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3794085192
Short name T291
Test name
Test status
Simulation time 60727409 ps
CPU time 3.05 seconds
Started Jul 07 05:07:24 PM PDT 24
Finished Jul 07 05:07:27 PM PDT 24
Peak memory 208860 kb
Host smart-f1db36ab-9a4d-44ae-8cd6-684a4fc9ffff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794085192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3794085192
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3905592368
Short name T482
Test name
Test status
Simulation time 228643670 ps
CPU time 5.31 seconds
Started Jul 07 05:07:21 PM PDT 24
Finished Jul 07 05:07:27 PM PDT 24
Peak memory 207800 kb
Host smart-cc24afec-124b-4d7a-bae8-910c7c4db6f1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905592368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3905592368
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3367815863
Short name T441
Test name
Test status
Simulation time 2222263567 ps
CPU time 11.92 seconds
Started Jul 07 05:07:26 PM PDT 24
Finished Jul 07 05:07:38 PM PDT 24
Peak memory 208120 kb
Host smart-b4585e5c-651d-4695-8127-7f0c41226f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367815863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3367815863
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3347089700
Short name T385
Test name
Test status
Simulation time 79258864 ps
CPU time 2.41 seconds
Started Jul 07 05:07:22 PM PDT 24
Finished Jul 07 05:07:24 PM PDT 24
Peak memory 207128 kb
Host smart-a7503f9d-0f93-4723-aff9-7d1a997ebde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347089700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3347089700
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3826745151
Short name T629
Test name
Test status
Simulation time 90466408 ps
CPU time 4.44 seconds
Started Jul 07 05:07:26 PM PDT 24
Finished Jul 07 05:07:30 PM PDT 24
Peak memory 208136 kb
Host smart-5a05c047-05fa-483a-ab43-dd621e4f8112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826745151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3826745151
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.82157378
Short name T716
Test name
Test status
Simulation time 3400493526 ps
CPU time 13.45 seconds
Started Jul 07 05:07:27 PM PDT 24
Finished Jul 07 05:07:41 PM PDT 24
Peak memory 222672 kb
Host smart-1a03e2e9-9d63-4e43-b74d-c3f8b0215fb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82157378 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.82157378
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1556212178
Short name T250
Test name
Test status
Simulation time 209924523 ps
CPU time 5.01 seconds
Started Jul 07 05:07:23 PM PDT 24
Finished Jul 07 05:07:28 PM PDT 24
Peak memory 214312 kb
Host smart-39074a7e-0d28-4deb-8dee-a002ba4e382c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556212178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1556212178
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.178621284
Short name T875
Test name
Test status
Simulation time 333883803 ps
CPU time 2.02 seconds
Started Jul 07 05:07:27 PM PDT 24
Finished Jul 07 05:07:29 PM PDT 24
Peak memory 210152 kb
Host smart-17d954ea-eae4-4881-b996-dd2b707e1f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178621284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.178621284
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.462294285
Short name T562
Test name
Test status
Simulation time 12278245 ps
CPU time 0.75 seconds
Started Jul 07 05:07:31 PM PDT 24
Finished Jul 07 05:07:32 PM PDT 24
Peak memory 205988 kb
Host smart-c6a68bdc-5e85-46b9-86fc-b854b96f439b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462294285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.462294285
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1127632998
Short name T35
Test name
Test status
Simulation time 127709233 ps
CPU time 3.8 seconds
Started Jul 07 05:07:28 PM PDT 24
Finished Jul 07 05:07:32 PM PDT 24
Peak memory 208744 kb
Host smart-21918519-d234-4b26-99ac-64321fb83115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127632998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1127632998
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2462107856
Short name T62
Test name
Test status
Simulation time 300078920 ps
CPU time 6.14 seconds
Started Jul 07 05:07:27 PM PDT 24
Finished Jul 07 05:07:34 PM PDT 24
Peak memory 208784 kb
Host smart-31b12105-bb3f-42f4-9bdb-1389b8559e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462107856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2462107856
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_random.4159620128
Short name T248
Test name
Test status
Simulation time 165232909 ps
CPU time 2.71 seconds
Started Jul 07 05:07:26 PM PDT 24
Finished Jul 07 05:07:30 PM PDT 24
Peak memory 207596 kb
Host smart-7bf4a610-8cc6-4412-acc2-75ecfc15c565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159620128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.4159620128
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.778970182
Short name T584
Test name
Test status
Simulation time 50966215 ps
CPU time 2.91 seconds
Started Jul 07 05:07:30 PM PDT 24
Finished Jul 07 05:07:33 PM PDT 24
Peak memory 206888 kb
Host smart-05c5ceba-d664-4b81-aee3-668d7e94473a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778970182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.778970182
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3779007151
Short name T499
Test name
Test status
Simulation time 3211659502 ps
CPU time 56.32 seconds
Started Jul 07 05:07:25 PM PDT 24
Finished Jul 07 05:08:21 PM PDT 24
Peak memory 208372 kb
Host smart-a9f1c243-d979-43f2-a340-ef9e7be5f377
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779007151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3779007151
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.446520272
Short name T644
Test name
Test status
Simulation time 66262998 ps
CPU time 3.43 seconds
Started Jul 07 05:07:26 PM PDT 24
Finished Jul 07 05:07:30 PM PDT 24
Peak memory 208716 kb
Host smart-a411718f-5221-45b2-85cd-23cc6c1cb2e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446520272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.446520272
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.18566726
Short name T606
Test name
Test status
Simulation time 595432907 ps
CPU time 16.35 seconds
Started Jul 07 05:07:25 PM PDT 24
Finished Jul 07 05:07:42 PM PDT 24
Peak memory 207992 kb
Host smart-a261ee47-5ae6-4328-a70d-cbf00875dcd7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18566726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.18566726
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.537687695
Short name T322
Test name
Test status
Simulation time 111745715 ps
CPU time 2.04 seconds
Started Jul 07 05:07:30 PM PDT 24
Finished Jul 07 05:07:33 PM PDT 24
Peak memory 214220 kb
Host smart-a0b19906-1b34-47cd-bb0b-31ff14a6f31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537687695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.537687695
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1474753038
Short name T607
Test name
Test status
Simulation time 75244209 ps
CPU time 2.34 seconds
Started Jul 07 05:07:30 PM PDT 24
Finished Jul 07 05:07:33 PM PDT 24
Peak memory 207064 kb
Host smart-9a4fb267-eeab-48c9-9cab-209023ee5f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474753038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1474753038
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.350133532
Short name T913
Test name
Test status
Simulation time 3373688934 ps
CPU time 36.86 seconds
Started Jul 07 05:07:30 PM PDT 24
Finished Jul 07 05:08:08 PM PDT 24
Peak memory 222628 kb
Host smart-52b2eec4-f531-4e88-88a9-b1646543822d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350133532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.350133532
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1149788576
Short name T74
Test name
Test status
Simulation time 206131666 ps
CPU time 6.88 seconds
Started Jul 07 05:07:31 PM PDT 24
Finished Jul 07 05:07:38 PM PDT 24
Peak memory 222540 kb
Host smart-5933741c-9e86-4d33-b36c-3fa3e3fdb584
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149788576 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1149788576
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2350986086
Short name T847
Test name
Test status
Simulation time 702904959 ps
CPU time 6.83 seconds
Started Jul 07 05:07:29 PM PDT 24
Finished Jul 07 05:07:36 PM PDT 24
Peak memory 210528 kb
Host smart-5bfac9c7-2bd6-4418-8fe4-4dae493d5bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350986086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2350986086
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2478990806
Short name T377
Test name
Test status
Simulation time 66534817 ps
CPU time 2.39 seconds
Started Jul 07 05:07:36 PM PDT 24
Finished Jul 07 05:07:39 PM PDT 24
Peak memory 209200 kb
Host smart-ae4798e5-4dd2-48a1-93c8-4a876682f7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478990806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2478990806
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.4184897689
Short name T448
Test name
Test status
Simulation time 64877256 ps
CPU time 1.02 seconds
Started Jul 07 05:07:36 PM PDT 24
Finished Jul 07 05:07:37 PM PDT 24
Peak memory 206188 kb
Host smart-56007b8f-683f-4a9b-bf34-604735e9d42c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184897689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.4184897689
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2980370205
Short name T401
Test name
Test status
Simulation time 50429323 ps
CPU time 3.91 seconds
Started Jul 07 05:07:31 PM PDT 24
Finished Jul 07 05:07:35 PM PDT 24
Peak memory 214328 kb
Host smart-219b130c-4570-4629-881a-62fafc0fca11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2980370205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2980370205
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.4285914907
Short name T574
Test name
Test status
Simulation time 80861557 ps
CPU time 3.05 seconds
Started Jul 07 05:07:36 PM PDT 24
Finished Jul 07 05:07:40 PM PDT 24
Peak memory 213796 kb
Host smart-b23853dc-ba7d-4aed-a63e-97349034183a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285914907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.4285914907
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3309849498
Short name T565
Test name
Test status
Simulation time 409277142 ps
CPU time 3.67 seconds
Started Jul 07 05:07:31 PM PDT 24
Finished Jul 07 05:07:35 PM PDT 24
Peak memory 208184 kb
Host smart-2b769f5d-3c1b-4320-a0c8-57e2c5148e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309849498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3309849498
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3331832952
Short name T311
Test name
Test status
Simulation time 356825962 ps
CPU time 4.24 seconds
Started Jul 07 05:07:33 PM PDT 24
Finished Jul 07 05:07:38 PM PDT 24
Peak memory 214312 kb
Host smart-c072c971-8597-4b13-ba08-2b16b82c166b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331832952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3331832952
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.636313722
Short name T308
Test name
Test status
Simulation time 118200162 ps
CPU time 4.16 seconds
Started Jul 07 05:07:32 PM PDT 24
Finished Jul 07 05:07:37 PM PDT 24
Peak memory 214248 kb
Host smart-b305f67b-f629-4eb8-9829-a2e49c687b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636313722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.636313722
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3294774374
Short name T785
Test name
Test status
Simulation time 243400918 ps
CPU time 3.63 seconds
Started Jul 07 05:07:30 PM PDT 24
Finished Jul 07 05:07:34 PM PDT 24
Peak memory 217028 kb
Host smart-250e0208-e7e2-4c9b-aa93-ba56d50d0337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294774374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3294774374
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1789116004
Short name T240
Test name
Test status
Simulation time 153265058 ps
CPU time 2.23 seconds
Started Jul 07 05:07:32 PM PDT 24
Finished Jul 07 05:07:35 PM PDT 24
Peak memory 206856 kb
Host smart-fca4cfc6-faa5-4760-a6fd-e77d3323096d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789116004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1789116004
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3522513757
Short name T708
Test name
Test status
Simulation time 54017126 ps
CPU time 2.84 seconds
Started Jul 07 05:07:32 PM PDT 24
Finished Jul 07 05:07:35 PM PDT 24
Peak memory 207016 kb
Host smart-88206c2c-bb9d-44e1-9658-323f22e7de30
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522513757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3522513757
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.741381649
Short name T325
Test name
Test status
Simulation time 877668073 ps
CPU time 21.46 seconds
Started Jul 07 05:07:31 PM PDT 24
Finished Jul 07 05:07:53 PM PDT 24
Peak memory 208124 kb
Host smart-1ecf89cb-7ec2-4d0c-885d-1af8b9feb0ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741381649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.741381649
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2755660096
Short name T518
Test name
Test status
Simulation time 189672774 ps
CPU time 5.06 seconds
Started Jul 07 05:07:33 PM PDT 24
Finished Jul 07 05:07:38 PM PDT 24
Peak memory 208892 kb
Host smart-2c42bbbb-6256-45dc-a57c-a0b3db473ca2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755660096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2755660096
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3987220788
Short name T667
Test name
Test status
Simulation time 101601667 ps
CPU time 2.65 seconds
Started Jul 07 05:07:36 PM PDT 24
Finished Jul 07 05:07:39 PM PDT 24
Peak memory 208288 kb
Host smart-8f526580-6e79-4ef6-9752-589f0ab7d443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987220788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3987220788
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2008003677
Short name T776
Test name
Test status
Simulation time 172524226 ps
CPU time 5.36 seconds
Started Jul 07 05:07:30 PM PDT 24
Finished Jul 07 05:07:35 PM PDT 24
Peak memory 208212 kb
Host smart-8010d8fd-9571-40d3-ad74-ed05dfbcd4f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008003677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2008003677
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.4138806563
Short name T152
Test name
Test status
Simulation time 1197051595 ps
CPU time 9.88 seconds
Started Jul 07 05:07:32 PM PDT 24
Finished Jul 07 05:07:43 PM PDT 24
Peak memory 222544 kb
Host smart-c4a6fe3f-db60-4fda-9d37-a21e16300326
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138806563 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.4138806563
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3724647190
Short name T900
Test name
Test status
Simulation time 401189842 ps
CPU time 7.27 seconds
Started Jul 07 05:07:32 PM PDT 24
Finished Jul 07 05:07:39 PM PDT 24
Peak memory 209884 kb
Host smart-48a36d6f-fca5-430a-b164-007252be392e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724647190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3724647190
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.191893728
Short name T172
Test name
Test status
Simulation time 236831194 ps
CPU time 2.29 seconds
Started Jul 07 05:07:30 PM PDT 24
Finished Jul 07 05:07:32 PM PDT 24
Peak memory 210012 kb
Host smart-d8be7449-c2a8-4891-ba60-7a84dcf8d3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191893728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.191893728
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3460228143
Short name T113
Test name
Test status
Simulation time 12278011 ps
CPU time 0.86 seconds
Started Jul 07 05:07:40 PM PDT 24
Finished Jul 07 05:07:42 PM PDT 24
Peak memory 205984 kb
Host smart-58960882-2b10-4947-99a4-0eca86c7afe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460228143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3460228143
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1623763257
Short name T285
Test name
Test status
Simulation time 158716155 ps
CPU time 3.14 seconds
Started Jul 07 05:07:34 PM PDT 24
Finished Jul 07 05:07:37 PM PDT 24
Peak memory 214292 kb
Host smart-011be432-9163-4341-a9eb-ab8ce1b1ca12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1623763257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1623763257
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.977260587
Short name T22
Test name
Test status
Simulation time 84367376 ps
CPU time 3.53 seconds
Started Jul 07 05:07:41 PM PDT 24
Finished Jul 07 05:07:45 PM PDT 24
Peak memory 215964 kb
Host smart-9aa15934-3f1d-4067-a264-d5e6b06d2e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977260587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.977260587
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3801817209
Short name T666
Test name
Test status
Simulation time 21360828 ps
CPU time 1.75 seconds
Started Jul 07 05:07:40 PM PDT 24
Finished Jul 07 05:07:42 PM PDT 24
Peak memory 207824 kb
Host smart-1100a25f-5a35-423a-b376-a0d793aff2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801817209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3801817209
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.4131857218
Short name T100
Test name
Test status
Simulation time 74388823 ps
CPU time 4.08 seconds
Started Jul 07 05:07:39 PM PDT 24
Finished Jul 07 05:07:44 PM PDT 24
Peak memory 214308 kb
Host smart-5820c48f-6daa-465f-9096-f36018c927c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131857218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.4131857218
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2294370314
Short name T273
Test name
Test status
Simulation time 69406454 ps
CPU time 3.84 seconds
Started Jul 07 05:07:42 PM PDT 24
Finished Jul 07 05:07:46 PM PDT 24
Peak memory 218284 kb
Host smart-995f135e-0f91-46ef-a22c-32ca3a9d49c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294370314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2294370314
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_random.554256393
Short name T465
Test name
Test status
Simulation time 1000270461 ps
CPU time 7.99 seconds
Started Jul 07 05:07:36 PM PDT 24
Finished Jul 07 05:07:44 PM PDT 24
Peak memory 209760 kb
Host smart-51e9fde0-922f-4a46-b058-66919761887e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554256393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.554256393
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2706136115
Short name T889
Test name
Test status
Simulation time 127390663 ps
CPU time 3.77 seconds
Started Jul 07 05:07:35 PM PDT 24
Finished Jul 07 05:07:39 PM PDT 24
Peak memory 208496 kb
Host smart-0648d983-de07-420e-95e8-e2682c649d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706136115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2706136115
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3174491027
Short name T358
Test name
Test status
Simulation time 336632493 ps
CPU time 4.4 seconds
Started Jul 07 05:07:35 PM PDT 24
Finished Jul 07 05:07:40 PM PDT 24
Peak memory 208692 kb
Host smart-827fba61-19d7-4019-9fec-48a902f7f084
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174491027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3174491027
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3686077917
Short name T672
Test name
Test status
Simulation time 92905771 ps
CPU time 3.51 seconds
Started Jul 07 05:07:35 PM PDT 24
Finished Jul 07 05:07:39 PM PDT 24
Peak memory 206684 kb
Host smart-e3ed08a6-68da-41e0-8a2d-59c40faaded7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686077917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3686077917
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3461313676
Short name T755
Test name
Test status
Simulation time 1094991839 ps
CPU time 7.48 seconds
Started Jul 07 05:07:33 PM PDT 24
Finished Jul 07 05:07:41 PM PDT 24
Peak memory 208792 kb
Host smart-58301873-e425-4d36-be56-5cdcd9650398
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461313676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3461313676
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.222822289
Short name T447
Test name
Test status
Simulation time 50468756 ps
CPU time 3.48 seconds
Started Jul 07 05:07:40 PM PDT 24
Finished Jul 07 05:07:44 PM PDT 24
Peak memory 214292 kb
Host smart-7858044b-71d7-49af-86a7-93693b35c315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222822289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.222822289
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1698565900
Short name T87
Test name
Test status
Simulation time 97241580 ps
CPU time 2 seconds
Started Jul 07 05:07:35 PM PDT 24
Finished Jul 07 05:07:37 PM PDT 24
Peak memory 208736 kb
Host smart-c2911f6d-b279-4678-b185-d0f411d1adb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698565900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1698565900
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1593672603
Short name T228
Test name
Test status
Simulation time 6404552040 ps
CPU time 56.92 seconds
Started Jul 07 05:07:39 PM PDT 24
Finished Jul 07 05:08:36 PM PDT 24
Peak memory 216916 kb
Host smart-c3932846-aeb6-404f-ac0e-1f30ac6a6241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593672603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1593672603
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1268025916
Short name T723
Test name
Test status
Simulation time 141637289 ps
CPU time 2.93 seconds
Started Jul 07 05:07:40 PM PDT 24
Finished Jul 07 05:07:43 PM PDT 24
Peak memory 210356 kb
Host smart-669449ac-f83d-46fa-aadf-fb177759f96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268025916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1268025916
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2673253700
Short name T841
Test name
Test status
Simulation time 16221797 ps
CPU time 0.83 seconds
Started Jul 07 05:07:43 PM PDT 24
Finished Jul 07 05:07:45 PM PDT 24
Peak memory 206000 kb
Host smart-9d09711a-dfa1-4cf2-a4ec-01715f857650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673253700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2673253700
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1180701460
Short name T403
Test name
Test status
Simulation time 218955439 ps
CPU time 11.99 seconds
Started Jul 07 05:07:40 PM PDT 24
Finished Jul 07 05:07:52 PM PDT 24
Peak memory 214404 kb
Host smart-bb1c1ea1-6734-45e9-b14d-186cf71caade
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180701460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1180701460
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3665295917
Short name T781
Test name
Test status
Simulation time 141442680 ps
CPU time 2.92 seconds
Started Jul 07 05:07:39 PM PDT 24
Finished Jul 07 05:07:42 PM PDT 24
Peak memory 209536 kb
Host smart-a0623b26-6cbb-45ac-ba98-dbe4f2289804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665295917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3665295917
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.468840733
Short name T520
Test name
Test status
Simulation time 1670908891 ps
CPU time 5.33 seconds
Started Jul 07 05:07:39 PM PDT 24
Finished Jul 07 05:07:45 PM PDT 24
Peak memory 210160 kb
Host smart-fc76a1af-4f82-4754-ac0c-6a5638b73320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468840733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.468840733
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1730605936
Short name T852
Test name
Test status
Simulation time 179353094 ps
CPU time 2.85 seconds
Started Jul 07 05:07:43 PM PDT 24
Finished Jul 07 05:07:46 PM PDT 24
Peak memory 209108 kb
Host smart-e5b55c86-f767-4ef7-a32b-3d802e86b2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730605936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1730605936
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.855892611
Short name T758
Test name
Test status
Simulation time 45194831 ps
CPU time 2.86 seconds
Started Jul 07 05:07:43 PM PDT 24
Finished Jul 07 05:07:46 PM PDT 24
Peak memory 218968 kb
Host smart-f7c68af4-fdef-40f1-abc5-3a0bae60e915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855892611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.855892611
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2001944109
Short name T306
Test name
Test status
Simulation time 505948601 ps
CPU time 8.07 seconds
Started Jul 07 05:07:40 PM PDT 24
Finished Jul 07 05:07:49 PM PDT 24
Peak memory 209432 kb
Host smart-ad99d82e-fc80-458b-945a-516bcb2a1382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001944109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2001944109
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.4227742363
Short name T305
Test name
Test status
Simulation time 208797167 ps
CPU time 2.75 seconds
Started Jul 07 05:07:39 PM PDT 24
Finished Jul 07 05:07:42 PM PDT 24
Peak memory 206868 kb
Host smart-413c36b3-d6b6-4c27-8506-e892bad7a2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227742363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.4227742363
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3412721826
Short name T779
Test name
Test status
Simulation time 49180430 ps
CPU time 2.46 seconds
Started Jul 07 05:07:39 PM PDT 24
Finished Jul 07 05:07:42 PM PDT 24
Peak memory 208244 kb
Host smart-f1fa3432-6717-4fec-a2a3-eb1873e616f9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412721826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3412721826
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3552177689
Short name T833
Test name
Test status
Simulation time 1120216516 ps
CPU time 19.4 seconds
Started Jul 07 05:07:42 PM PDT 24
Finished Jul 07 05:08:02 PM PDT 24
Peak memory 208152 kb
Host smart-def2218c-56bc-44b5-8300-5f13b2b8f201
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552177689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3552177689
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.123334439
Short name T92
Test name
Test status
Simulation time 54921184 ps
CPU time 2.15 seconds
Started Jul 07 05:07:42 PM PDT 24
Finished Jul 07 05:07:44 PM PDT 24
Peak memory 206916 kb
Host smart-2e51ddc2-f9fd-472f-a48a-e0fe94cac36d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123334439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.123334439
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.343413570
Short name T458
Test name
Test status
Simulation time 43982325 ps
CPU time 2.51 seconds
Started Jul 07 05:07:43 PM PDT 24
Finished Jul 07 05:07:46 PM PDT 24
Peak memory 208744 kb
Host smart-4f202cc4-46be-4145-aecd-27e7c5dcb363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343413570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.343413570
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2516928604
Short name T118
Test name
Test status
Simulation time 173664434 ps
CPU time 4.18 seconds
Started Jul 07 05:07:43 PM PDT 24
Finished Jul 07 05:07:48 PM PDT 24
Peak memory 206792 kb
Host smart-c5bdc6f9-dbba-4245-9a53-cac2cfc0a317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516928604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2516928604
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3630492409
Short name T780
Test name
Test status
Simulation time 448984118 ps
CPU time 5.49 seconds
Started Jul 07 05:07:42 PM PDT 24
Finished Jul 07 05:07:48 PM PDT 24
Peak memory 207440 kb
Host smart-48c916b7-d6e4-4069-bcf3-17478e2df923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630492409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3630492409
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3899179810
Short name T177
Test name
Test status
Simulation time 83018467 ps
CPU time 1.76 seconds
Started Jul 07 05:07:44 PM PDT 24
Finished Jul 07 05:07:47 PM PDT 24
Peak memory 210252 kb
Host smart-57e93d04-d4ea-4ece-a363-000f63ca97b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899179810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3899179810
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3949474168
Short name T414
Test name
Test status
Simulation time 41078445 ps
CPU time 0.89 seconds
Started Jul 07 05:07:44 PM PDT 24
Finished Jul 07 05:07:46 PM PDT 24
Peak memory 205984 kb
Host smart-d0f02d76-bdc3-496f-aa1b-2293e0cb68da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949474168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3949474168
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3346314980
Short name T412
Test name
Test status
Simulation time 122198106 ps
CPU time 2.69 seconds
Started Jul 07 05:07:46 PM PDT 24
Finished Jul 07 05:07:49 PM PDT 24
Peak memory 214304 kb
Host smart-b1323555-8ac7-4326-a30e-8392f7843937
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3346314980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3346314980
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3768616723
Short name T287
Test name
Test status
Simulation time 308339455 ps
CPU time 4.35 seconds
Started Jul 07 05:07:44 PM PDT 24
Finished Jul 07 05:07:49 PM PDT 24
Peak memory 214328 kb
Host smart-cd7168b0-decd-4b35-b4ef-3372fd6687a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768616723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3768616723
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3944231487
Short name T487
Test name
Test status
Simulation time 133179830 ps
CPU time 2.81 seconds
Started Jul 07 05:07:45 PM PDT 24
Finished Jul 07 05:07:48 PM PDT 24
Peak memory 214016 kb
Host smart-7cd2bd48-d72c-4adc-b1d2-3eabb4a548c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944231487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3944231487
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.412036559
Short name T683
Test name
Test status
Simulation time 75626947 ps
CPU time 2.22 seconds
Started Jul 07 05:07:44 PM PDT 24
Finished Jul 07 05:07:47 PM PDT 24
Peak memory 207484 kb
Host smart-1634a63f-a23b-49fb-9e56-7df249744ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412036559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.412036559
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.4094335699
Short name T577
Test name
Test status
Simulation time 46710167 ps
CPU time 3.21 seconds
Started Jul 07 05:07:44 PM PDT 24
Finished Jul 07 05:07:48 PM PDT 24
Peak memory 207480 kb
Host smart-c50624e7-b8f2-4401-8d8e-76c53bd32213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094335699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.4094335699
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2446385948
Short name T911
Test name
Test status
Simulation time 42505351 ps
CPU time 1.88 seconds
Started Jul 07 05:07:43 PM PDT 24
Finished Jul 07 05:07:45 PM PDT 24
Peak memory 206956 kb
Host smart-0db0d34c-951d-4865-a2dd-57404973f194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446385948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2446385948
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1904078270
Short name T550
Test name
Test status
Simulation time 608148289 ps
CPU time 4.07 seconds
Started Jul 07 05:07:44 PM PDT 24
Finished Jul 07 05:07:49 PM PDT 24
Peak memory 208800 kb
Host smart-7259dfda-7089-44e1-8a4c-914ad7e6e12e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904078270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1904078270
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3223104744
Short name T469
Test name
Test status
Simulation time 227834392 ps
CPU time 7 seconds
Started Jul 07 05:07:42 PM PDT 24
Finished Jul 07 05:07:50 PM PDT 24
Peak memory 208368 kb
Host smart-cbd9bf25-260c-48b4-8d91-ebc47227fd8c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223104744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3223104744
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2488004773
Short name T625
Test name
Test status
Simulation time 32922278 ps
CPU time 2.09 seconds
Started Jul 07 05:07:44 PM PDT 24
Finished Jul 07 05:07:47 PM PDT 24
Peak memory 215868 kb
Host smart-6493de17-819e-4b2c-ad56-052b14ea9343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488004773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2488004773
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2751675861
Short name T433
Test name
Test status
Simulation time 216087652 ps
CPU time 3.52 seconds
Started Jul 07 05:07:44 PM PDT 24
Finished Jul 07 05:07:48 PM PDT 24
Peak memory 208724 kb
Host smart-82d70410-599b-4f41-97d7-3a78b2355c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751675861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2751675861
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3485958114
Short name T68
Test name
Test status
Simulation time 2508085648 ps
CPU time 24.47 seconds
Started Jul 07 05:07:43 PM PDT 24
Finished Jul 07 05:08:09 PM PDT 24
Peak memory 216056 kb
Host smart-7bfdda8a-ef5b-4a50-a3ad-c13c37f026c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485958114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3485958114
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.47558208
Short name T618
Test name
Test status
Simulation time 147322727 ps
CPU time 3.02 seconds
Started Jul 07 05:07:45 PM PDT 24
Finished Jul 07 05:07:48 PM PDT 24
Peak memory 209764 kb
Host smart-b826f877-eb0e-4cde-bf93-40862ff46138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47558208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.47558208
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1766867116
Short name T193
Test name
Test status
Simulation time 64980706 ps
CPU time 2.68 seconds
Started Jul 07 05:07:45 PM PDT 24
Finished Jul 07 05:07:48 PM PDT 24
Peak memory 210048 kb
Host smart-393e3180-db35-4503-99be-2ceec2c09feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766867116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1766867116
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.4174842986
Short name T413
Test name
Test status
Simulation time 38937008 ps
CPU time 0.71 seconds
Started Jul 07 05:06:27 PM PDT 24
Finished Jul 07 05:06:28 PM PDT 24
Peak memory 205972 kb
Host smart-075c5329-d221-4463-8eab-80ee01fda0d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174842986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.4174842986
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.152254661
Short name T790
Test name
Test status
Simulation time 229485341 ps
CPU time 2.81 seconds
Started Jul 07 05:06:20 PM PDT 24
Finished Jul 07 05:06:23 PM PDT 24
Peak memory 210344 kb
Host smart-fb72ee4c-5d38-4dd9-8fd1-291c65f194de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152254661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.152254661
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3296787212
Short name T96
Test name
Test status
Simulation time 222413493 ps
CPU time 5.2 seconds
Started Jul 07 05:06:22 PM PDT 24
Finished Jul 07 05:06:27 PM PDT 24
Peak memory 214300 kb
Host smart-130e325a-3bec-4e1f-9380-d67d5d3e19c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296787212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3296787212
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1107712524
Short name T274
Test name
Test status
Simulation time 903985291 ps
CPU time 8.6 seconds
Started Jul 07 05:06:21 PM PDT 24
Finished Jul 07 05:06:30 PM PDT 24
Peak memory 222340 kb
Host smart-8d906b7c-ec65-4690-9d45-73401a6d4222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107712524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1107712524
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2129217913
Short name T485
Test name
Test status
Simulation time 131361229 ps
CPU time 3.35 seconds
Started Jul 07 05:06:20 PM PDT 24
Finished Jul 07 05:06:24 PM PDT 24
Peak memory 220164 kb
Host smart-42e942c7-0e9f-4d1f-bfce-a3a55b49b76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129217913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2129217913
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.932325254
Short name T698
Test name
Test status
Simulation time 10113943405 ps
CPU time 77.53 seconds
Started Jul 07 05:06:24 PM PDT 24
Finished Jul 07 05:07:41 PM PDT 24
Peak memory 209644 kb
Host smart-5bb72aa3-c3f1-4e4e-9039-0dae3fdf3355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932325254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.932325254
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1415408628
Short name T11
Test name
Test status
Simulation time 1034704412 ps
CPU time 6.06 seconds
Started Jul 07 05:06:22 PM PDT 24
Finished Jul 07 05:06:28 PM PDT 24
Peak memory 230244 kb
Host smart-c2dbf44a-c15a-4f12-b0c4-a90c25ce2822
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415408628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1415408628
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1188412893
Short name T903
Test name
Test status
Simulation time 440321145 ps
CPU time 2.38 seconds
Started Jul 07 05:06:17 PM PDT 24
Finished Jul 07 05:06:20 PM PDT 24
Peak memory 206832 kb
Host smart-a110d39b-4c30-4cfc-bc86-8cd4a5ab05c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188412893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1188412893
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2163693810
Short name T560
Test name
Test status
Simulation time 37778283 ps
CPU time 2.51 seconds
Started Jul 07 05:06:16 PM PDT 24
Finished Jul 07 05:06:19 PM PDT 24
Peak memory 208684 kb
Host smart-cf075b67-9301-4292-b5be-a170a994176f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163693810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2163693810
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.4290916165
Short name T711
Test name
Test status
Simulation time 74908524 ps
CPU time 1.77 seconds
Started Jul 07 05:06:16 PM PDT 24
Finished Jul 07 05:06:18 PM PDT 24
Peak memory 206912 kb
Host smart-68f37dd5-de88-4f8d-aea3-a305c4c6fe6b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290916165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.4290916165
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2503222669
Short name T626
Test name
Test status
Simulation time 637258940 ps
CPU time 4.72 seconds
Started Jul 07 05:06:16 PM PDT 24
Finished Jul 07 05:06:21 PM PDT 24
Peak memory 208488 kb
Host smart-e7d2bbdf-40cc-498d-a628-afe6b00d9d6c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503222669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2503222669
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1271959276
Short name T622
Test name
Test status
Simulation time 248493289 ps
CPU time 4.14 seconds
Started Jul 07 05:06:21 PM PDT 24
Finished Jul 07 05:06:25 PM PDT 24
Peak memory 209512 kb
Host smart-9201b156-7bfa-4865-913a-fccbe9a4dc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271959276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1271959276
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3494668552
Short name T729
Test name
Test status
Simulation time 110774442 ps
CPU time 2.1 seconds
Started Jul 07 05:06:17 PM PDT 24
Finished Jul 07 05:06:19 PM PDT 24
Peak memory 208552 kb
Host smart-1303f1ad-15a8-4651-a434-be9cae24f576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494668552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3494668552
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2169589530
Short name T557
Test name
Test status
Simulation time 551581685 ps
CPU time 6.92 seconds
Started Jul 07 05:06:21 PM PDT 24
Finished Jul 07 05:06:28 PM PDT 24
Peak memory 207540 kb
Host smart-862e1a43-0ea1-4c55-9745-f2b8c3acd0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169589530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2169589530
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1559535302
Short name T5
Test name
Test status
Simulation time 156915707 ps
CPU time 2.05 seconds
Started Jul 07 05:06:22 PM PDT 24
Finished Jul 07 05:06:24 PM PDT 24
Peak memory 209952 kb
Host smart-b3daba98-ea10-497b-89df-1e2ea80dfc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559535302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1559535302
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.4165887860
Short name T417
Test name
Test status
Simulation time 19211868 ps
CPU time 1.05 seconds
Started Jul 07 05:07:47 PM PDT 24
Finished Jul 07 05:07:49 PM PDT 24
Peak memory 206104 kb
Host smart-aceb4fed-a252-4c1e-83b6-6c8d3f21e256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165887860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.4165887860
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3204885488
Short name T266
Test name
Test status
Simulation time 122599758 ps
CPU time 5.21 seconds
Started Jul 07 05:07:47 PM PDT 24
Finished Jul 07 05:07:52 PM PDT 24
Peak memory 214228 kb
Host smart-d7dbdd26-8620-4f6a-89f3-3c88f22bb03b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3204885488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3204885488
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1390624198
Short name T569
Test name
Test status
Simulation time 1187064659 ps
CPU time 3.15 seconds
Started Jul 07 05:07:47 PM PDT 24
Finished Jul 07 05:07:51 PM PDT 24
Peak memory 209044 kb
Host smart-cd52262d-870c-448c-a76b-bd805a01ba0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390624198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1390624198
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2171311143
Short name T290
Test name
Test status
Simulation time 101801850 ps
CPU time 1.99 seconds
Started Jul 07 05:07:50 PM PDT 24
Finished Jul 07 05:07:52 PM PDT 24
Peak memory 214280 kb
Host smart-d43b5843-2fac-4766-b613-74f12095c220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171311143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2171311143
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.18053276
Short name T312
Test name
Test status
Simulation time 177048349 ps
CPU time 3.27 seconds
Started Jul 07 05:07:49 PM PDT 24
Finished Jul 07 05:07:52 PM PDT 24
Peak memory 214192 kb
Host smart-a73bd3fa-08f5-43c5-8570-e0095822cb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18053276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.18053276
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.439709942
Short name T229
Test name
Test status
Simulation time 140134225 ps
CPU time 2.81 seconds
Started Jul 07 05:07:48 PM PDT 24
Finished Jul 07 05:07:52 PM PDT 24
Peak memory 209676 kb
Host smart-bb8c5aa2-d209-4728-9181-e727bd9f67aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439709942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.439709942
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.619206823
Short name T598
Test name
Test status
Simulation time 468708980 ps
CPU time 5.2 seconds
Started Jul 07 05:07:55 PM PDT 24
Finished Jul 07 05:08:00 PM PDT 24
Peak memory 218344 kb
Host smart-eb39e197-bab7-4336-8933-d1c29912fdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619206823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.619206823
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2339932943
Short name T497
Test name
Test status
Simulation time 489092834 ps
CPU time 3.96 seconds
Started Jul 07 05:07:45 PM PDT 24
Finished Jul 07 05:07:49 PM PDT 24
Peak memory 208116 kb
Host smart-7dae85c3-4f80-4508-9bdc-6c2d8b5ca107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339932943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2339932943
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3024909394
Short name T656
Test name
Test status
Simulation time 202011868 ps
CPU time 5.49 seconds
Started Jul 07 05:07:44 PM PDT 24
Finished Jul 07 05:07:50 PM PDT 24
Peak memory 208772 kb
Host smart-ef3d822e-8e92-405d-a2d4-501fffae085e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024909394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3024909394
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3729658587
Short name T700
Test name
Test status
Simulation time 66541871 ps
CPU time 3.48 seconds
Started Jul 07 05:07:43 PM PDT 24
Finished Jul 07 05:07:47 PM PDT 24
Peak memory 206996 kb
Host smart-be88ab2d-b649-4af9-9922-e37a893cfbd6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729658587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3729658587
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.444641544
Short name T503
Test name
Test status
Simulation time 197750153 ps
CPU time 2.45 seconds
Started Jul 07 05:07:55 PM PDT 24
Finished Jul 07 05:07:58 PM PDT 24
Peak memory 207012 kb
Host smart-1445686f-f9bc-4103-8de7-471389bdca25
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444641544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.444641544
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2680088523
Short name T391
Test name
Test status
Simulation time 54488612 ps
CPU time 1.76 seconds
Started Jul 07 05:07:48 PM PDT 24
Finished Jul 07 05:07:50 PM PDT 24
Peak memory 214324 kb
Host smart-2e2c7b5f-8a86-42ae-95f2-6e7ef27b056c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680088523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2680088523
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1774033767
Short name T459
Test name
Test status
Simulation time 77901772 ps
CPU time 2.77 seconds
Started Jul 07 05:07:55 PM PDT 24
Finished Jul 07 05:07:58 PM PDT 24
Peak memory 206748 kb
Host smart-03dd9137-03af-460f-9222-8c374e8aa032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774033767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1774033767
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1686065483
Short name T83
Test name
Test status
Simulation time 349433765 ps
CPU time 4.98 seconds
Started Jul 07 05:07:47 PM PDT 24
Finished Jul 07 05:07:53 PM PDT 24
Peak memory 215752 kb
Host smart-1fe7be59-de11-4fc0-835a-9e08a6c26e6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686065483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1686065483
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2357697514
Short name T24
Test name
Test status
Simulation time 291206401 ps
CPU time 7.1 seconds
Started Jul 07 05:07:49 PM PDT 24
Finished Jul 07 05:07:57 PM PDT 24
Peak memory 208536 kb
Host smart-3ec0fd7b-b8f2-4097-a00c-d7053b5ac421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357697514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2357697514
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.4021489977
Short name T63
Test name
Test status
Simulation time 125263435 ps
CPU time 3.12 seconds
Started Jul 07 05:07:47 PM PDT 24
Finished Jul 07 05:07:51 PM PDT 24
Peak memory 210520 kb
Host smart-2b908279-f0aa-4b0b-90aa-6f29aacb5f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021489977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.4021489977
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.751595193
Short name T909
Test name
Test status
Simulation time 13259772 ps
CPU time 0.74 seconds
Started Jul 07 05:07:58 PM PDT 24
Finished Jul 07 05:07:59 PM PDT 24
Peak memory 205952 kb
Host smart-3c348b1d-8e64-4f09-bc40-d35acd895e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751595193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.751595193
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.142891800
Short name T262
Test name
Test status
Simulation time 183338688 ps
CPU time 4.07 seconds
Started Jul 07 05:07:52 PM PDT 24
Finished Jul 07 05:07:57 PM PDT 24
Peak memory 214624 kb
Host smart-305a9adb-e1c6-4c54-93e0-cd37ccdb64f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=142891800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.142891800
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1815868565
Short name T701
Test name
Test status
Simulation time 145573027 ps
CPU time 5.56 seconds
Started Jul 07 05:07:55 PM PDT 24
Finished Jul 07 05:08:01 PM PDT 24
Peak memory 220584 kb
Host smart-48e0d275-9da7-415f-b821-e680b0f4f26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815868565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1815868565
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3933634792
Short name T880
Test name
Test status
Simulation time 27528520 ps
CPU time 2.1 seconds
Started Jul 07 05:07:52 PM PDT 24
Finished Jul 07 05:07:55 PM PDT 24
Peak memory 222432 kb
Host smart-0c3bed64-96c5-495b-a629-f178f8115d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933634792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3933634792
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2453861907
Short name T105
Test name
Test status
Simulation time 321743191 ps
CPU time 7.86 seconds
Started Jul 07 05:07:52 PM PDT 24
Finished Jul 07 05:08:00 PM PDT 24
Peak memory 209584 kb
Host smart-f3e56bc0-0404-401b-b793-7ec97f7a2ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453861907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2453861907
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.895809506
Short name T288
Test name
Test status
Simulation time 26631468 ps
CPU time 1.9 seconds
Started Jul 07 05:07:52 PM PDT 24
Finished Jul 07 05:07:55 PM PDT 24
Peak memory 214256 kb
Host smart-1b490fb3-0340-429f-a574-d5a5706173c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895809506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.895809506
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2779864797
Short name T797
Test name
Test status
Simulation time 164792536 ps
CPU time 4.26 seconds
Started Jul 07 05:07:51 PM PDT 24
Finished Jul 07 05:07:56 PM PDT 24
Peak memory 219812 kb
Host smart-c2e82bfc-79c8-4fdf-9a94-cbc2a597577c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779864797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2779864797
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2956078764
Short name T835
Test name
Test status
Simulation time 544354453 ps
CPU time 5.33 seconds
Started Jul 07 05:07:49 PM PDT 24
Finished Jul 07 05:07:55 PM PDT 24
Peak memory 218176 kb
Host smart-2cfd157c-3228-4007-a9e5-9dfbb677f058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956078764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2956078764
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1948874526
Short name T364
Test name
Test status
Simulation time 234556998 ps
CPU time 4.23 seconds
Started Jul 07 05:07:47 PM PDT 24
Finished Jul 07 05:07:52 PM PDT 24
Peak memory 208620 kb
Host smart-9f350f28-ee8d-40d7-9441-a26884f4ecde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948874526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1948874526
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.4078025069
Short name T457
Test name
Test status
Simulation time 2780024044 ps
CPU time 19.2 seconds
Started Jul 07 05:07:48 PM PDT 24
Finished Jul 07 05:08:08 PM PDT 24
Peak memory 208228 kb
Host smart-7fc8237b-3751-4e67-a1ee-71eb82cd8cbd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078025069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.4078025069
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2924083351
Short name T435
Test name
Test status
Simulation time 148633790 ps
CPU time 2.41 seconds
Started Jul 07 05:07:47 PM PDT 24
Finished Jul 07 05:07:50 PM PDT 24
Peak memory 208540 kb
Host smart-a53eecd8-09f7-4701-9c83-4a2d7d639329
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924083351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2924083351
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3500996704
Short name T85
Test name
Test status
Simulation time 252956434 ps
CPU time 3.53 seconds
Started Jul 07 05:07:48 PM PDT 24
Finished Jul 07 05:07:52 PM PDT 24
Peak memory 208560 kb
Host smart-344dc281-efc8-44b6-a6c9-bf4c94d3984f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500996704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3500996704
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.4192302480
Short name T824
Test name
Test status
Simulation time 289764783 ps
CPU time 6.47 seconds
Started Jul 07 05:07:54 PM PDT 24
Finished Jul 07 05:08:00 PM PDT 24
Peak memory 210204 kb
Host smart-2d97c045-a8ba-4052-b64d-74f35e9df18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192302480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.4192302480
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1041409263
Short name T455
Test name
Test status
Simulation time 196984064 ps
CPU time 2.76 seconds
Started Jul 07 05:07:48 PM PDT 24
Finished Jul 07 05:07:51 PM PDT 24
Peak memory 208384 kb
Host smart-c876e9c1-de3e-41ea-8245-3475d829fec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041409263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1041409263
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1771409410
Short name T268
Test name
Test status
Simulation time 1873842906 ps
CPU time 28.77 seconds
Started Jul 07 05:07:51 PM PDT 24
Finished Jul 07 05:08:20 PM PDT 24
Peak memory 222728 kb
Host smart-114d2b89-3a85-4bce-8c67-41022f2e8544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771409410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1771409410
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1130692928
Short name T831
Test name
Test status
Simulation time 292607043 ps
CPU time 3.98 seconds
Started Jul 07 05:07:52 PM PDT 24
Finished Jul 07 05:07:56 PM PDT 24
Peak memory 214248 kb
Host smart-b45a4595-0787-47cb-9c96-9f2bbb0072c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130692928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1130692928
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2094028108
Short name T611
Test name
Test status
Simulation time 118677896 ps
CPU time 2.62 seconds
Started Jul 07 05:07:54 PM PDT 24
Finished Jul 07 05:07:57 PM PDT 24
Peak memory 210828 kb
Host smart-319b9fc1-fef5-44ea-84b9-0308fdf73225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094028108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2094028108
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.121084461
Short name T910
Test name
Test status
Simulation time 45913569 ps
CPU time 0.84 seconds
Started Jul 07 05:07:56 PM PDT 24
Finished Jul 07 05:07:57 PM PDT 24
Peak memory 205968 kb
Host smart-e1d69ab1-e564-44df-aff2-dbf1a1cc9e38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121084461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.121084461
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2530215444
Short name T513
Test name
Test status
Simulation time 103172861 ps
CPU time 5.14 seconds
Started Jul 07 05:08:03 PM PDT 24
Finished Jul 07 05:08:09 PM PDT 24
Peak memory 209872 kb
Host smart-781418dd-9c50-4420-810e-7b41bf1f89fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530215444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2530215444
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1974546416
Short name T893
Test name
Test status
Simulation time 80664106 ps
CPU time 1.78 seconds
Started Jul 07 05:07:53 PM PDT 24
Finished Jul 07 05:07:55 PM PDT 24
Peak memory 209768 kb
Host smart-dd4baf64-9de1-4722-a211-74298e9b105a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974546416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1974546416
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.760844319
Short name T258
Test name
Test status
Simulation time 114823193 ps
CPU time 2.55 seconds
Started Jul 07 05:07:52 PM PDT 24
Finished Jul 07 05:07:54 PM PDT 24
Peak memory 214640 kb
Host smart-5acf9a89-dfb9-4a65-b8ac-ff7387485b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760844319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.760844319
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.547970530
Short name T854
Test name
Test status
Simulation time 269981202 ps
CPU time 3.54 seconds
Started Jul 07 05:07:53 PM PDT 24
Finished Jul 07 05:07:57 PM PDT 24
Peak memory 214528 kb
Host smart-40ebe1ae-4892-4569-ade0-6c9cc3de81c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547970530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.547970530
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1551944638
Short name T884
Test name
Test status
Simulation time 435104872 ps
CPU time 3.93 seconds
Started Jul 07 05:07:53 PM PDT 24
Finished Jul 07 05:07:57 PM PDT 24
Peak memory 220380 kb
Host smart-a55bc0c9-d2d0-42f5-93c5-9e677afa09dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551944638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1551944638
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3633401457
Short name T619
Test name
Test status
Simulation time 878482607 ps
CPU time 6.54 seconds
Started Jul 07 05:07:52 PM PDT 24
Finished Jul 07 05:07:59 PM PDT 24
Peak memory 209216 kb
Host smart-66cc8e18-1d6c-4350-8012-2503a3c7eb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633401457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3633401457
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3419823774
Short name T675
Test name
Test status
Simulation time 203615733 ps
CPU time 2.88 seconds
Started Jul 07 05:07:54 PM PDT 24
Finished Jul 07 05:07:58 PM PDT 24
Peak memory 208684 kb
Host smart-fb42beae-b53a-4f87-ad7d-3d248e48e4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419823774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3419823774
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3900041768
Short name T423
Test name
Test status
Simulation time 1906919407 ps
CPU time 24.13 seconds
Started Jul 07 05:07:52 PM PDT 24
Finished Jul 07 05:08:17 PM PDT 24
Peak memory 208652 kb
Host smart-eaa4080a-271d-4944-ae2a-4791f30dc435
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900041768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3900041768
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3512625049
Short name T389
Test name
Test status
Simulation time 821287290 ps
CPU time 6.31 seconds
Started Jul 07 05:07:54 PM PDT 24
Finished Jul 07 05:08:01 PM PDT 24
Peak memory 208436 kb
Host smart-fde0fed5-d344-41bc-b2e6-122da25c2caa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512625049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3512625049
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1661133142
Short name T594
Test name
Test status
Simulation time 219817470 ps
CPU time 2.52 seconds
Started Jul 07 05:07:56 PM PDT 24
Finished Jul 07 05:07:59 PM PDT 24
Peak memory 215236 kb
Host smart-df1a59a1-2d5e-4915-be81-5d3fdbe4e47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661133142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1661133142
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3511476002
Short name T907
Test name
Test status
Simulation time 77114987 ps
CPU time 3.39 seconds
Started Jul 07 05:07:58 PM PDT 24
Finished Jul 07 05:08:02 PM PDT 24
Peak memory 208288 kb
Host smart-8801c0fd-fad5-4f94-b773-c0b93db78c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511476002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3511476002
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2124994195
Short name T155
Test name
Test status
Simulation time 1796602745 ps
CPU time 14.4 seconds
Started Jul 07 05:07:56 PM PDT 24
Finished Jul 07 05:08:10 PM PDT 24
Peak memory 220116 kb
Host smart-3cdb8853-8158-42d4-80e4-16c8fdfdca66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124994195 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2124994195
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.4277524673
Short name T387
Test name
Test status
Simulation time 47520440 ps
CPU time 3.37 seconds
Started Jul 07 05:07:53 PM PDT 24
Finished Jul 07 05:07:56 PM PDT 24
Peak memory 210136 kb
Host smart-9a81ccca-ef0f-4b33-9191-497fe8f40f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277524673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.4277524673
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1959460536
Short name T379
Test name
Test status
Simulation time 56092186 ps
CPU time 2.75 seconds
Started Jul 07 05:07:56 PM PDT 24
Finished Jul 07 05:07:59 PM PDT 24
Peak memory 210124 kb
Host smart-cdb74cf8-8456-4ea1-8ceb-e5480ec01dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959460536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1959460536
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2983390243
Short name T468
Test name
Test status
Simulation time 14813425 ps
CPU time 1.08 seconds
Started Jul 07 05:08:02 PM PDT 24
Finished Jul 07 05:08:03 PM PDT 24
Peak memory 206112 kb
Host smart-51c30bb4-12d3-421b-8542-07d9f17a487d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983390243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2983390243
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2464765527
Short name T75
Test name
Test status
Simulation time 236166612 ps
CPU time 3.74 seconds
Started Jul 07 05:07:54 PM PDT 24
Finished Jul 07 05:07:58 PM PDT 24
Peak memory 214252 kb
Host smart-9687f2c6-b5f2-4dfe-8e63-aa4f402d0fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464765527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2464765527
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3188378981
Short name T472
Test name
Test status
Simulation time 57146786 ps
CPU time 2.94 seconds
Started Jul 07 05:07:56 PM PDT 24
Finished Jul 07 05:08:00 PM PDT 24
Peak memory 209452 kb
Host smart-272d282e-6f00-4e31-b1f0-9f22f20497f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188378981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3188378981
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.4293940455
Short name T99
Test name
Test status
Simulation time 100939562 ps
CPU time 3.56 seconds
Started Jul 07 05:07:56 PM PDT 24
Finished Jul 07 05:08:00 PM PDT 24
Peak memory 214320 kb
Host smart-0d579ed5-bf92-49cd-b2de-5a802e92b94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293940455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4293940455
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2879238948
Short name T908
Test name
Test status
Simulation time 131023137 ps
CPU time 3.35 seconds
Started Jul 07 05:07:55 PM PDT 24
Finished Jul 07 05:07:59 PM PDT 24
Peak memory 214272 kb
Host smart-a9a53cfd-a31a-4a02-bc73-53474e3a5213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879238948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2879238948
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1793545808
Short name T32
Test name
Test status
Simulation time 73693408 ps
CPU time 3.73 seconds
Started Jul 07 05:07:56 PM PDT 24
Finished Jul 07 05:08:00 PM PDT 24
Peak memory 214380 kb
Host smart-a1f3d3f0-a74f-46b0-bb7c-6dc43b6a3136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793545808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1793545808
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.462273181
Short name T564
Test name
Test status
Simulation time 579154593 ps
CPU time 8.37 seconds
Started Jul 07 05:07:56 PM PDT 24
Finished Jul 07 05:08:05 PM PDT 24
Peak memory 214324 kb
Host smart-5d40e3aa-7629-488e-9273-98525e392aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462273181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.462273181
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.141305294
Short name T799
Test name
Test status
Simulation time 56776675 ps
CPU time 3.01 seconds
Started Jul 07 05:07:56 PM PDT 24
Finished Jul 07 05:07:59 PM PDT 24
Peak memory 207576 kb
Host smart-7d024f77-3328-4e86-8a2a-6d925eaeabb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141305294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.141305294
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1325842034
Short name T710
Test name
Test status
Simulation time 7119867926 ps
CPU time 65.23 seconds
Started Jul 07 05:07:55 PM PDT 24
Finished Jul 07 05:09:01 PM PDT 24
Peak memory 208260 kb
Host smart-52b91ff4-21b6-47fc-9c5c-5b70a1edaf37
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325842034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1325842034
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2423988317
Short name T514
Test name
Test status
Simulation time 217024214 ps
CPU time 2.11 seconds
Started Jul 07 05:07:59 PM PDT 24
Finished Jul 07 05:08:02 PM PDT 24
Peak memory 208772 kb
Host smart-7bf636be-9330-489f-a8e0-2b5e941b1717
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423988317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2423988317
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.666780354
Short name T591
Test name
Test status
Simulation time 71872890 ps
CPU time 2.97 seconds
Started Jul 07 05:07:55 PM PDT 24
Finished Jul 07 05:07:59 PM PDT 24
Peak memory 206792 kb
Host smart-f9c6d808-d95f-4c68-b56c-233faba8ca04
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666780354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.666780354
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1166225244
Short name T162
Test name
Test status
Simulation time 98471384 ps
CPU time 4.36 seconds
Started Jul 07 05:08:05 PM PDT 24
Finished Jul 07 05:08:09 PM PDT 24
Peak memory 210032 kb
Host smart-b55c7539-bafc-465e-9793-dc6b98e3d358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166225244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1166225244
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1166826577
Short name T858
Test name
Test status
Simulation time 165861752 ps
CPU time 2.43 seconds
Started Jul 07 05:07:57 PM PDT 24
Finished Jul 07 05:08:00 PM PDT 24
Peak memory 207372 kb
Host smart-8a6a6fa9-d8cf-45f9-9a6d-041c11c7d6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166826577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1166826577
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1879468875
Short name T223
Test name
Test status
Simulation time 24205305056 ps
CPU time 107.09 seconds
Started Jul 07 05:08:03 PM PDT 24
Finished Jul 07 05:09:50 PM PDT 24
Peak memory 217544 kb
Host smart-72dcfeb0-d7eb-4aa1-a104-3a429e41a3a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879468875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1879468875
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.105493875
Short name T749
Test name
Test status
Simulation time 507632754 ps
CPU time 5.12 seconds
Started Jul 07 05:07:56 PM PDT 24
Finished Jul 07 05:08:02 PM PDT 24
Peak memory 209524 kb
Host smart-c1658d06-199a-4952-8066-3313b5a6067e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105493875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.105493875
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2751962916
Short name T194
Test name
Test status
Simulation time 21628441 ps
CPU time 1.43 seconds
Started Jul 07 05:07:59 PM PDT 24
Finished Jul 07 05:08:01 PM PDT 24
Peak memory 209864 kb
Host smart-f727cf75-8421-4ac4-a5fc-f9fa99d3038e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751962916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2751962916
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3809817094
Short name T486
Test name
Test status
Simulation time 13178410 ps
CPU time 0.87 seconds
Started Jul 07 05:08:03 PM PDT 24
Finished Jul 07 05:08:05 PM PDT 24
Peak memory 205988 kb
Host smart-5ffa447f-e624-4c9a-be0b-4534466a4755
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809817094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3809817094
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3709143725
Short name T117
Test name
Test status
Simulation time 1440925374 ps
CPU time 13.75 seconds
Started Jul 07 05:08:01 PM PDT 24
Finished Jul 07 05:08:15 PM PDT 24
Peak memory 214328 kb
Host smart-f948f0d5-33c8-4a3a-9a9e-afbbab3bcaa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3709143725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3709143725
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.4239604363
Short name T686
Test name
Test status
Simulation time 592938925 ps
CPU time 4.97 seconds
Started Jul 07 05:07:59 PM PDT 24
Finished Jul 07 05:08:04 PM PDT 24
Peak memory 209424 kb
Host smart-3a116fce-99eb-4c26-80db-34cfbe46e2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239604363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.4239604363
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3342177890
Short name T597
Test name
Test status
Simulation time 185047217 ps
CPU time 2.66 seconds
Started Jul 07 05:08:00 PM PDT 24
Finished Jul 07 05:08:03 PM PDT 24
Peak memory 210112 kb
Host smart-9ee86f80-85a7-4c52-a724-e1c509f68b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342177890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3342177890
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2020596643
Short name T794
Test name
Test status
Simulation time 82481340 ps
CPU time 2.42 seconds
Started Jul 07 05:08:01 PM PDT 24
Finished Jul 07 05:08:04 PM PDT 24
Peak memory 215564 kb
Host smart-0519f17f-1edf-4bf4-ac9e-9fee70cb1fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020596643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2020596643
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2894853888
Short name T840
Test name
Test status
Simulation time 59263369 ps
CPU time 2.19 seconds
Started Jul 07 05:08:00 PM PDT 24
Finished Jul 07 05:08:02 PM PDT 24
Peak memory 214184 kb
Host smart-b55bc228-f2f4-4bc6-a69d-127c18e3ff45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894853888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2894853888
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2054532060
Short name T214
Test name
Test status
Simulation time 160878224 ps
CPU time 3.55 seconds
Started Jul 07 05:08:01 PM PDT 24
Finished Jul 07 05:08:05 PM PDT 24
Peak memory 208928 kb
Host smart-d9a29578-7e76-4541-b9d5-0a8d2bbdfbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054532060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2054532060
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1815482255
Short name T256
Test name
Test status
Simulation time 845840869 ps
CPU time 19.03 seconds
Started Jul 07 05:08:02 PM PDT 24
Finished Jul 07 05:08:21 PM PDT 24
Peak memory 209316 kb
Host smart-3d469254-4f28-4abf-ba6a-4856b65fca97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815482255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1815482255
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1340580375
Short name T160
Test name
Test status
Simulation time 255013464 ps
CPU time 2.25 seconds
Started Jul 07 05:08:02 PM PDT 24
Finished Jul 07 05:08:04 PM PDT 24
Peak memory 206732 kb
Host smart-15fc15b8-b294-4368-a047-333354cff0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340580375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1340580375
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2188424233
Short name T498
Test name
Test status
Simulation time 48595054 ps
CPU time 2.81 seconds
Started Jul 07 05:08:01 PM PDT 24
Finished Jul 07 05:08:04 PM PDT 24
Peak memory 208780 kb
Host smart-e7c1a5a3-275a-40e8-aa24-05b384c81566
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188424233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2188424233
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1927407554
Short name T384
Test name
Test status
Simulation time 1660902851 ps
CPU time 35.07 seconds
Started Jul 07 05:08:00 PM PDT 24
Finished Jul 07 05:08:35 PM PDT 24
Peak memory 208212 kb
Host smart-d9fb5822-6d50-40e1-8b34-5e49043b0037
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927407554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1927407554
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1364387986
Short name T360
Test name
Test status
Simulation time 102089905 ps
CPU time 2.03 seconds
Started Jul 07 05:08:03 PM PDT 24
Finished Jul 07 05:08:05 PM PDT 24
Peak memory 218144 kb
Host smart-4901b2ff-7d1e-4a0e-a3b4-7f77cf3580bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364387986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1364387986
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1824669937
Short name T534
Test name
Test status
Simulation time 113342643 ps
CPU time 2.57 seconds
Started Jul 07 05:08:01 PM PDT 24
Finished Jul 07 05:08:04 PM PDT 24
Peak memory 208216 kb
Host smart-9e6b0184-3806-4da4-8ef8-dfe453bcfede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824669937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1824669937
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1929856724
Short name T477
Test name
Test status
Simulation time 545973119 ps
CPU time 7.35 seconds
Started Jul 07 05:08:05 PM PDT 24
Finished Jul 07 05:08:13 PM PDT 24
Peak memory 222548 kb
Host smart-90cb469e-3501-4cb9-8558-6e80e4dea064
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929856724 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1929856724
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1984822216
Short name T753
Test name
Test status
Simulation time 158079579 ps
CPU time 6.9 seconds
Started Jul 07 05:08:14 PM PDT 24
Finished Jul 07 05:08:21 PM PDT 24
Peak memory 210384 kb
Host smart-bde13c64-b10a-48f6-94b2-d14bcd0db112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984822216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1984822216
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1130334191
Short name T609
Test name
Test status
Simulation time 30215259 ps
CPU time 1.18 seconds
Started Jul 07 05:08:09 PM PDT 24
Finished Jul 07 05:08:11 PM PDT 24
Peak memory 206028 kb
Host smart-5cd7b1d0-f711-4aa8-b3de-6afc9e6c096e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130334191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1130334191
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3825888840
Short name T661
Test name
Test status
Simulation time 56404727 ps
CPU time 2.78 seconds
Started Jul 07 05:08:05 PM PDT 24
Finished Jul 07 05:08:08 PM PDT 24
Peak memory 221496 kb
Host smart-e48a2273-04e9-4c43-a5ef-f69cf726b984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825888840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3825888840
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3290980356
Short name T773
Test name
Test status
Simulation time 37447211 ps
CPU time 2.49 seconds
Started Jul 07 05:08:05 PM PDT 24
Finished Jul 07 05:08:07 PM PDT 24
Peak memory 207500 kb
Host smart-efc30338-20a4-49c2-b9d3-a44367925495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290980356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3290980356
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2949181867
Short name T270
Test name
Test status
Simulation time 38997017 ps
CPU time 1.85 seconds
Started Jul 07 05:08:04 PM PDT 24
Finished Jul 07 05:08:07 PM PDT 24
Peak memory 214224 kb
Host smart-d3c5f5b4-ac0f-4c1e-b793-80fd7e667411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949181867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2949181867
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1541434344
Short name T912
Test name
Test status
Simulation time 190723255 ps
CPU time 3.06 seconds
Started Jul 07 05:08:05 PM PDT 24
Finished Jul 07 05:08:09 PM PDT 24
Peak memory 222348 kb
Host smart-b9a30afd-1af6-4aea-b0bf-99ef305d0662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541434344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1541434344
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.4185914098
Short name T905
Test name
Test status
Simulation time 167754059 ps
CPU time 3.08 seconds
Started Jul 07 05:08:12 PM PDT 24
Finished Jul 07 05:08:15 PM PDT 24
Peak memory 214332 kb
Host smart-249ff83b-5f69-4cfa-89c3-1da622515d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185914098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.4185914098
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2186207955
Short name T198
Test name
Test status
Simulation time 86617451 ps
CPU time 4.11 seconds
Started Jul 07 05:08:09 PM PDT 24
Finished Jul 07 05:08:14 PM PDT 24
Peak memory 209996 kb
Host smart-828d88e4-7a01-4cdb-b9ca-84bfa8d92707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186207955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2186207955
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.500903532
Short name T767
Test name
Test status
Simulation time 54635329 ps
CPU time 3.09 seconds
Started Jul 07 05:08:04 PM PDT 24
Finished Jul 07 05:08:07 PM PDT 24
Peak memory 206824 kb
Host smart-248b51ca-d7b3-4c83-b4c4-0f66dbf267e1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500903532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.500903532
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2537249693
Short name T419
Test name
Test status
Simulation time 122182622 ps
CPU time 2.47 seconds
Started Jul 07 05:08:04 PM PDT 24
Finished Jul 07 05:08:07 PM PDT 24
Peak memory 209084 kb
Host smart-8d9316bd-ce17-48a7-85ff-ff983cea7725
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537249693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2537249693
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.4025098110
Short name T646
Test name
Test status
Simulation time 189180540 ps
CPU time 6.92 seconds
Started Jul 07 05:08:03 PM PDT 24
Finished Jul 07 05:08:10 PM PDT 24
Peak memory 208940 kb
Host smart-c7604ca4-59a6-452a-89eb-a8503b268eb6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025098110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.4025098110
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1148708003
Short name T394
Test name
Test status
Simulation time 43786272 ps
CPU time 2.32 seconds
Started Jul 07 05:08:05 PM PDT 24
Finished Jul 07 05:08:08 PM PDT 24
Peak memory 209068 kb
Host smart-d30af244-9bd5-4fb0-b237-dbf55b30dd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148708003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1148708003
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3463960902
Short name T703
Test name
Test status
Simulation time 89611775 ps
CPU time 2.31 seconds
Started Jul 07 05:08:11 PM PDT 24
Finished Jul 07 05:08:14 PM PDT 24
Peak memory 206912 kb
Host smart-dc163f76-63b1-4514-b8da-cb45b3f06bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463960902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3463960902
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1465081475
Short name T632
Test name
Test status
Simulation time 124255962 ps
CPU time 3.45 seconds
Started Jul 07 05:08:03 PM PDT 24
Finished Jul 07 05:08:07 PM PDT 24
Peak memory 218284 kb
Host smart-a97f61f9-4dcb-478d-aa3f-c1b2bd635c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465081475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1465081475
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2759517861
Short name T471
Test name
Test status
Simulation time 150971287 ps
CPU time 2.65 seconds
Started Jul 07 05:08:04 PM PDT 24
Finished Jul 07 05:08:07 PM PDT 24
Peak memory 210468 kb
Host smart-14b1ed06-1fe4-49d9-badd-490f1c9f297a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759517861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2759517861
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.104803965
Short name T110
Test name
Test status
Simulation time 11892247 ps
CPU time 0.91 seconds
Started Jul 07 05:08:12 PM PDT 24
Finished Jul 07 05:08:13 PM PDT 24
Peak memory 205992 kb
Host smart-ca55cf22-b47b-4474-9792-9e828ebd8cff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104803965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.104803965
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1289047825
Short name T555
Test name
Test status
Simulation time 451658701 ps
CPU time 4.58 seconds
Started Jul 07 05:08:08 PM PDT 24
Finished Jul 07 05:08:14 PM PDT 24
Peak memory 220304 kb
Host smart-15b66d15-2293-405d-a1c8-e2701b394c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289047825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1289047825
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3571413480
Short name T70
Test name
Test status
Simulation time 199106786 ps
CPU time 2.31 seconds
Started Jul 07 05:08:09 PM PDT 24
Finished Jul 07 05:08:12 PM PDT 24
Peak memory 208780 kb
Host smart-d495fb6e-b42d-4c22-bf78-2f6e5a4981d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571413480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3571413480
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3803488124
Short name T356
Test name
Test status
Simulation time 736928939 ps
CPU time 7.04 seconds
Started Jul 07 05:08:10 PM PDT 24
Finished Jul 07 05:08:17 PM PDT 24
Peak memory 222484 kb
Host smart-75bb4d68-2958-4a2a-9bb0-fff945c4eb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803488124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3803488124
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1416756581
Short name T801
Test name
Test status
Simulation time 190983092 ps
CPU time 1.95 seconds
Started Jul 07 05:08:14 PM PDT 24
Finished Jul 07 05:08:16 PM PDT 24
Peak memory 220504 kb
Host smart-20106091-7e0e-4313-a95a-6def9479244d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416756581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1416756581
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_random.3192598981
Short name T545
Test name
Test status
Simulation time 10372284808 ps
CPU time 30.85 seconds
Started Jul 07 05:08:11 PM PDT 24
Finished Jul 07 05:08:42 PM PDT 24
Peak memory 209372 kb
Host smart-d4a500da-672c-4f3d-b4f0-fd7f16acaed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192598981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3192598981
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1262529702
Short name T336
Test name
Test status
Simulation time 111721727 ps
CPU time 3.25 seconds
Started Jul 07 05:08:08 PM PDT 24
Finished Jul 07 05:08:11 PM PDT 24
Peak memory 208580 kb
Host smart-66312ed0-6133-4345-9f7d-88e78d618671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262529702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1262529702
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1617122360
Short name T602
Test name
Test status
Simulation time 313957087 ps
CPU time 2.63 seconds
Started Jul 07 05:08:09 PM PDT 24
Finished Jul 07 05:08:12 PM PDT 24
Peak memory 207012 kb
Host smart-ec3f7249-30b7-4d2c-aaf2-984d7c58c3c8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617122360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1617122360
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1449797164
Short name T392
Test name
Test status
Simulation time 129289976 ps
CPU time 2.35 seconds
Started Jul 07 05:08:11 PM PDT 24
Finished Jul 07 05:08:14 PM PDT 24
Peak memory 206972 kb
Host smart-76a9a591-cd86-43bb-826d-2eb4e3ae6cab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449797164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1449797164
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3310956429
Short name T422
Test name
Test status
Simulation time 148041040 ps
CPU time 3.76 seconds
Started Jul 07 05:08:07 PM PDT 24
Finished Jul 07 05:08:11 PM PDT 24
Peak memory 206892 kb
Host smart-b54d18a6-7eff-4b77-bd38-d64e3b7dcd1c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310956429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3310956429
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1618829444
Short name T744
Test name
Test status
Simulation time 72583830 ps
CPU time 3.83 seconds
Started Jul 07 05:08:08 PM PDT 24
Finished Jul 07 05:08:12 PM PDT 24
Peak memory 209312 kb
Host smart-1f469045-4a56-4a12-86b0-23f130d2566e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618829444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1618829444
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2190801019
Short name T437
Test name
Test status
Simulation time 19943403 ps
CPU time 1.8 seconds
Started Jul 07 05:08:09 PM PDT 24
Finished Jul 07 05:08:12 PM PDT 24
Peak memory 206728 kb
Host smart-86dad82a-d24a-4d54-83d4-245899a9c97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190801019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2190801019
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.2846466198
Short name T806
Test name
Test status
Simulation time 1543042082 ps
CPU time 8.85 seconds
Started Jul 07 05:08:15 PM PDT 24
Finished Jul 07 05:08:24 PM PDT 24
Peak memory 219280 kb
Host smart-c69c1015-b344-47b6-a04e-ceb36d5031bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846466198 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.2846466198
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3946557438
Short name T887
Test name
Test status
Simulation time 72450526 ps
CPU time 3.91 seconds
Started Jul 07 05:08:08 PM PDT 24
Finished Jul 07 05:08:12 PM PDT 24
Peak memory 208536 kb
Host smart-bd15b7fa-71e8-432a-9e1a-9be91976b2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946557438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3946557438
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.4010420383
Short name T37
Test name
Test status
Simulation time 1385081032 ps
CPU time 6.89 seconds
Started Jul 07 05:08:08 PM PDT 24
Finished Jul 07 05:08:16 PM PDT 24
Peak memory 211436 kb
Host smart-d72c8808-d205-433f-aade-aae63ec73662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010420383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.4010420383
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2725052484
Short name T111
Test name
Test status
Simulation time 39903825 ps
CPU time 0.87 seconds
Started Jul 07 05:08:17 PM PDT 24
Finished Jul 07 05:08:19 PM PDT 24
Peak memory 205872 kb
Host smart-a592eb7b-34a4-4569-aa32-82c6c39197b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725052484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2725052484
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1330936449
Short name T593
Test name
Test status
Simulation time 101768488 ps
CPU time 4.3 seconds
Started Jul 07 05:08:13 PM PDT 24
Finished Jul 07 05:08:18 PM PDT 24
Peak memory 222840 kb
Host smart-acc58ae6-3423-46cb-ac99-e313583f5fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330936449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1330936449
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.185238490
Short name T473
Test name
Test status
Simulation time 48243838 ps
CPU time 1.92 seconds
Started Jul 07 05:08:16 PM PDT 24
Finished Jul 07 05:08:19 PM PDT 24
Peak memory 214332 kb
Host smart-aa6c9ca8-3172-42d5-b63c-85db59639dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185238490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.185238490
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2838914124
Short name T843
Test name
Test status
Simulation time 64870568 ps
CPU time 3.05 seconds
Started Jul 07 05:08:13 PM PDT 24
Finished Jul 07 05:08:17 PM PDT 24
Peak memory 214252 kb
Host smart-c914287e-36ae-40ca-bf25-08b18161312f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838914124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2838914124
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1764051190
Short name T8
Test name
Test status
Simulation time 491791719 ps
CPU time 3.85 seconds
Started Jul 07 05:08:11 PM PDT 24
Finished Jul 07 05:08:16 PM PDT 24
Peak memory 210164 kb
Host smart-5f07d3f8-0001-4381-9c36-3a9d0ebbbd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764051190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1764051190
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.872297501
Short name T426
Test name
Test status
Simulation time 30152465 ps
CPU time 2.28 seconds
Started Jul 07 05:08:18 PM PDT 24
Finished Jul 07 05:08:21 PM PDT 24
Peak memory 209464 kb
Host smart-26e91aca-cdd6-4811-8975-f32042dd1208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872297501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.872297501
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1712185667
Short name T43
Test name
Test status
Simulation time 6545898631 ps
CPU time 33.79 seconds
Started Jul 07 05:08:18 PM PDT 24
Finished Jul 07 05:08:52 PM PDT 24
Peak memory 207892 kb
Host smart-3c9a70af-8fd4-4b72-a52b-a2a07e86f386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712185667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1712185667
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.432634945
Short name T509
Test name
Test status
Simulation time 6752866234 ps
CPU time 32.97 seconds
Started Jul 07 05:08:16 PM PDT 24
Finished Jul 07 05:08:50 PM PDT 24
Peak memory 209004 kb
Host smart-6c2e3e55-26ed-4af9-bf00-5dc4b863be23
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432634945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.432634945
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3991520018
Short name T834
Test name
Test status
Simulation time 506448965 ps
CPU time 2.68 seconds
Started Jul 07 05:08:12 PM PDT 24
Finished Jul 07 05:08:15 PM PDT 24
Peak memory 206980 kb
Host smart-48a4316b-e48b-4c49-b0ac-f5c34b27340f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991520018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3991520018
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3004186583
Short name T897
Test name
Test status
Simulation time 242818121 ps
CPU time 3.76 seconds
Started Jul 07 05:08:12 PM PDT 24
Finished Jul 07 05:08:16 PM PDT 24
Peak memory 208500 kb
Host smart-cded54c9-137b-4519-b6a3-4ccf38fc371a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004186583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3004186583
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3135337213
Short name T314
Test name
Test status
Simulation time 424812839 ps
CPU time 2.63 seconds
Started Jul 07 05:08:11 PM PDT 24
Finished Jul 07 05:08:15 PM PDT 24
Peak memory 218268 kb
Host smart-caeef123-85d3-4033-9105-123a8986319a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135337213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3135337213
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.98102912
Short name T784
Test name
Test status
Simulation time 123023588 ps
CPU time 3.92 seconds
Started Jul 07 05:08:12 PM PDT 24
Finished Jul 07 05:08:16 PM PDT 24
Peak memory 208568 kb
Host smart-54f3e90f-c04d-43ef-862e-ce51456b5a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98102912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.98102912
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.851051923
Short name T832
Test name
Test status
Simulation time 2534966358 ps
CPU time 16.78 seconds
Started Jul 07 05:08:14 PM PDT 24
Finished Jul 07 05:08:31 PM PDT 24
Peak memory 222672 kb
Host smart-19dff29c-7621-43ce-873c-5de6a60f34ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851051923 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.851051923
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1865223274
Short name T197
Test name
Test status
Simulation time 806046227 ps
CPU time 6.24 seconds
Started Jul 07 05:08:16 PM PDT 24
Finished Jul 07 05:08:23 PM PDT 24
Peak memory 209300 kb
Host smart-44707e14-3073-4915-851a-f43dc65a4d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865223274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1865223274
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3832494804
Short name T170
Test name
Test status
Simulation time 174805333 ps
CPU time 2.34 seconds
Started Jul 07 05:08:18 PM PDT 24
Finished Jul 07 05:08:21 PM PDT 24
Peak memory 209932 kb
Host smart-0c64119e-a1e8-49a3-93ae-1c9f9e009034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832494804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3832494804
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1057127684
Short name T610
Test name
Test status
Simulation time 18258290 ps
CPU time 0.75 seconds
Started Jul 07 05:08:17 PM PDT 24
Finished Jul 07 05:08:19 PM PDT 24
Peak memory 206252 kb
Host smart-a01a3110-61f3-4443-8bc4-24cd596a51a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057127684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1057127684
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3873086322
Short name T596
Test name
Test status
Simulation time 349372163 ps
CPU time 4.96 seconds
Started Jul 07 05:08:16 PM PDT 24
Finished Jul 07 05:08:22 PM PDT 24
Peak memory 209700 kb
Host smart-3a538932-4934-4989-abb9-c7fdd47a1a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873086322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3873086322
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.791349716
Short name T762
Test name
Test status
Simulation time 148622663 ps
CPU time 5.12 seconds
Started Jul 07 05:08:17 PM PDT 24
Finished Jul 07 05:08:23 PM PDT 24
Peak memory 214320 kb
Host smart-fb155d62-73cb-4b9c-bf79-1eebe8908069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791349716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.791349716
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.866728490
Short name T898
Test name
Test status
Simulation time 921136554 ps
CPU time 4.78 seconds
Started Jul 07 05:08:21 PM PDT 24
Finished Jul 07 05:08:26 PM PDT 24
Peak memory 208216 kb
Host smart-cc195105-c491-488b-a199-03ec123909dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866728490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.866728490
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2487762446
Short name T864
Test name
Test status
Simulation time 69108477 ps
CPU time 2.99 seconds
Started Jul 07 05:08:19 PM PDT 24
Finished Jul 07 05:08:23 PM PDT 24
Peak memory 220404 kb
Host smart-f69b273a-1866-4046-8a7f-4e8575b4aaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487762446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2487762446
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3834555585
Short name T717
Test name
Test status
Simulation time 123355370 ps
CPU time 5.25 seconds
Started Jul 07 05:08:21 PM PDT 24
Finished Jul 07 05:08:27 PM PDT 24
Peak memory 209468 kb
Host smart-7ad58358-f1c5-4e60-b29c-be73561203d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834555585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3834555585
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3511334091
Short name T743
Test name
Test status
Simulation time 807586730 ps
CPU time 6.67 seconds
Started Jul 07 05:08:18 PM PDT 24
Finished Jul 07 05:08:25 PM PDT 24
Peak memory 208420 kb
Host smart-618d64dc-8e8f-418d-b997-e99cd9d84116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511334091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3511334091
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3616803492
Short name T202
Test name
Test status
Simulation time 59473315 ps
CPU time 3.12 seconds
Started Jul 07 05:08:15 PM PDT 24
Finished Jul 07 05:08:19 PM PDT 24
Peak memory 208552 kb
Host smart-c616a631-192b-49ff-9481-c1b185976b16
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616803492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3616803492
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2606125525
Short name T255
Test name
Test status
Simulation time 2290061714 ps
CPU time 7.06 seconds
Started Jul 07 05:08:19 PM PDT 24
Finished Jul 07 05:08:27 PM PDT 24
Peak memory 207872 kb
Host smart-ccd5c4c8-efb4-4475-ad81-4dc97b5faf08
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606125525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2606125525
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3238601956
Short name T873
Test name
Test status
Simulation time 37631505 ps
CPU time 2.52 seconds
Started Jul 07 05:08:20 PM PDT 24
Finished Jul 07 05:08:23 PM PDT 24
Peak memory 207048 kb
Host smart-f36b28ae-ff44-45f9-b787-7e4ac46a3b0b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238601956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3238601956
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1859476724
Short name T627
Test name
Test status
Simulation time 54533428 ps
CPU time 2.8 seconds
Started Jul 07 05:08:19 PM PDT 24
Finished Jul 07 05:08:23 PM PDT 24
Peak memory 209316 kb
Host smart-1cdcf686-73fc-451b-bdd4-f6df16be6d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859476724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1859476724
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1261487967
Short name T750
Test name
Test status
Simulation time 56797575 ps
CPU time 2.89 seconds
Started Jul 07 05:08:12 PM PDT 24
Finished Jul 07 05:08:15 PM PDT 24
Peak memory 208560 kb
Host smart-b0a09b3c-042c-48f0-9bd4-14ce7240e281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261487967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1261487967
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3329556679
Short name T215
Test name
Test status
Simulation time 1882397236 ps
CPU time 19.52 seconds
Started Jul 07 05:08:17 PM PDT 24
Finished Jul 07 05:08:38 PM PDT 24
Peak memory 222372 kb
Host smart-a24e3ada-6eea-4cc1-85b3-052a2fa0aeac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329556679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3329556679
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2500713716
Short name T865
Test name
Test status
Simulation time 365991146 ps
CPU time 3.43 seconds
Started Jul 07 05:08:16 PM PDT 24
Finished Jul 07 05:08:21 PM PDT 24
Peak memory 208036 kb
Host smart-c0737ba5-c662-4cdb-b8f2-aa4cb0298923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500713716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2500713716
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1558259394
Short name T64
Test name
Test status
Simulation time 386786088 ps
CPU time 4 seconds
Started Jul 07 05:08:17 PM PDT 24
Finished Jul 07 05:08:22 PM PDT 24
Peak memory 210400 kb
Host smart-b21c088c-2f0f-494d-8b2b-eb3a8757171e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558259394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1558259394
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2170263826
Short name T805
Test name
Test status
Simulation time 54436738 ps
CPU time 0.95 seconds
Started Jul 07 05:08:23 PM PDT 24
Finished Jul 07 05:08:25 PM PDT 24
Peak memory 206104 kb
Host smart-85a984cb-898e-495f-8a3f-efb9c1f111d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170263826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2170263826
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1143639331
Short name T411
Test name
Test status
Simulation time 940116398 ps
CPU time 12.1 seconds
Started Jul 07 05:08:26 PM PDT 24
Finished Jul 07 05:08:39 PM PDT 24
Peak memory 214240 kb
Host smart-adb30a8f-803d-4865-84af-7d21e8e991ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1143639331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1143639331
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3406066433
Short name T804
Test name
Test status
Simulation time 199051402 ps
CPU time 5.66 seconds
Started Jul 07 05:08:27 PM PDT 24
Finished Jul 07 05:08:33 PM PDT 24
Peak memory 220020 kb
Host smart-e276546d-4275-4911-b1fd-295d3c51b817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406066433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3406066433
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1749228985
Short name T84
Test name
Test status
Simulation time 49899061 ps
CPU time 2.42 seconds
Started Jul 07 05:08:22 PM PDT 24
Finished Jul 07 05:08:25 PM PDT 24
Peak memory 208276 kb
Host smart-ba81625b-e569-4f57-b9ca-0be601a29700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749228985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1749228985
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1651691933
Short name T352
Test name
Test status
Simulation time 713168623 ps
CPU time 3.6 seconds
Started Jul 07 05:08:24 PM PDT 24
Finished Jul 07 05:08:28 PM PDT 24
Peak memory 214336 kb
Host smart-f7e041f8-7f6e-485f-926c-a4b18202fb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651691933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1651691933
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1161222889
Short name T95
Test name
Test status
Simulation time 131190342 ps
CPU time 2.15 seconds
Started Jul 07 05:08:22 PM PDT 24
Finished Jul 07 05:08:24 PM PDT 24
Peak memory 214272 kb
Host smart-6c99992d-b26c-4d81-9288-77e7a415961d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161222889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1161222889
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1113821174
Short name T740
Test name
Test status
Simulation time 1409706262 ps
CPU time 3.68 seconds
Started Jul 07 05:08:23 PM PDT 24
Finished Jul 07 05:08:28 PM PDT 24
Peak memory 214248 kb
Host smart-829bc12b-a00e-4b6a-a724-dddf1ae1f540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113821174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1113821174
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.628027660
Short name T906
Test name
Test status
Simulation time 41636242 ps
CPU time 3.01 seconds
Started Jul 07 05:08:25 PM PDT 24
Finished Jul 07 05:08:29 PM PDT 24
Peak memory 218468 kb
Host smart-9a99ef39-4792-4413-86c7-8111bc7d743c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628027660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.628027660
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2455500568
Short name T91
Test name
Test status
Simulation time 4748931006 ps
CPU time 51.82 seconds
Started Jul 07 05:08:20 PM PDT 24
Finished Jul 07 05:09:12 PM PDT 24
Peak memory 208608 kb
Host smart-914b6e01-2dc6-4d20-ab98-d1cff1fd2552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455500568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2455500568
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3551775582
Short name T783
Test name
Test status
Simulation time 370112651 ps
CPU time 2.45 seconds
Started Jul 07 05:08:19 PM PDT 24
Finished Jul 07 05:08:22 PM PDT 24
Peak memory 206816 kb
Host smart-08d82f59-9cc6-4476-9344-94ed9292c476
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551775582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3551775582
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1471335150
Short name T203
Test name
Test status
Simulation time 164543716 ps
CPU time 6.55 seconds
Started Jul 07 05:08:16 PM PDT 24
Finished Jul 07 05:08:24 PM PDT 24
Peak memory 208896 kb
Host smart-f3c1295a-f0de-4186-aaca-490594d0acb5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471335150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1471335150
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.693806493
Short name T881
Test name
Test status
Simulation time 263211233 ps
CPU time 7.68 seconds
Started Jul 07 05:08:26 PM PDT 24
Finished Jul 07 05:08:35 PM PDT 24
Peak memory 207940 kb
Host smart-8d88365f-e349-4f03-bb7e-d851a299b23a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693806493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.693806493
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.4092467125
Short name T252
Test name
Test status
Simulation time 187820723 ps
CPU time 4.15 seconds
Started Jul 07 05:08:20 PM PDT 24
Finished Jul 07 05:08:24 PM PDT 24
Peak memory 209320 kb
Host smart-531e535e-dfc3-4e2f-bba9-dbab11c0afe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092467125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.4092467125
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3032802933
Short name T862
Test name
Test status
Simulation time 169195034 ps
CPU time 3.61 seconds
Started Jul 07 05:08:16 PM PDT 24
Finished Jul 07 05:08:21 PM PDT 24
Peak memory 208224 kb
Host smart-66a83695-7ea1-4d08-a113-4297f0c31b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032802933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3032802933
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2112159702
Short name T154
Test name
Test status
Simulation time 678157716 ps
CPU time 15.6 seconds
Started Jul 07 05:08:23 PM PDT 24
Finished Jul 07 05:08:39 PM PDT 24
Peak memory 222484 kb
Host smart-e7a16ea3-b052-4388-aa1f-f74ee8a49745
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112159702 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2112159702
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3409852933
Short name T628
Test name
Test status
Simulation time 323764338 ps
CPU time 4.29 seconds
Started Jul 07 05:08:22 PM PDT 24
Finished Jul 07 05:08:26 PM PDT 24
Peak memory 207452 kb
Host smart-f5c839c3-24df-4407-92d4-9f0b9b6af062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409852933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3409852933
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.855314122
Short name T734
Test name
Test status
Simulation time 38843385 ps
CPU time 0.82 seconds
Started Jul 07 05:06:31 PM PDT 24
Finished Jul 07 05:06:32 PM PDT 24
Peak memory 205920 kb
Host smart-08ec3bcf-3905-46fc-9944-daa39b495b60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855314122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.855314122
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2409344618
Short name T237
Test name
Test status
Simulation time 1025090884 ps
CPU time 4.51 seconds
Started Jul 07 05:06:28 PM PDT 24
Finished Jul 07 05:06:33 PM PDT 24
Peak memory 214340 kb
Host smart-cd562e07-3119-4ae1-ba5b-d4c5599128c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2409344618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2409344618
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.705451042
Short name T18
Test name
Test status
Simulation time 350458781 ps
CPU time 2.53 seconds
Started Jul 07 05:06:28 PM PDT 24
Finished Jul 07 05:06:31 PM PDT 24
Peak memory 221492 kb
Host smart-a19aa3bd-fef0-41d9-bd2f-9c31d3b17e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705451042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.705451042
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1616891691
Short name T812
Test name
Test status
Simulation time 146947216 ps
CPU time 2.83 seconds
Started Jul 07 05:06:27 PM PDT 24
Finished Jul 07 05:06:31 PM PDT 24
Peak memory 214344 kb
Host smart-a9d60596-7eed-446b-b024-2b2421c8b70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616891691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1616891691
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.896255155
Short name T106
Test name
Test status
Simulation time 610620983 ps
CPU time 5.68 seconds
Started Jul 07 05:06:26 PM PDT 24
Finished Jul 07 05:06:32 PM PDT 24
Peak memory 222696 kb
Host smart-91803c24-97c6-4870-8d7e-627f8a841553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896255155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.896255155
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2306446592
Short name T260
Test name
Test status
Simulation time 39342059 ps
CPU time 2.25 seconds
Started Jul 07 05:06:27 PM PDT 24
Finished Jul 07 05:06:30 PM PDT 24
Peak memory 214252 kb
Host smart-9abd12fc-050e-4ab3-8c62-1814b1c8167a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306446592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2306446592
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_random.2379899982
Short name T280
Test name
Test status
Simulation time 88808108 ps
CPU time 4.88 seconds
Started Jul 07 05:06:25 PM PDT 24
Finished Jul 07 05:06:30 PM PDT 24
Peak memory 207892 kb
Host smart-6cfe90e9-b5d3-4fe0-aa74-8ac9dfb133a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379899982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2379899982
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.178088366
Short name T886
Test name
Test status
Simulation time 334189992 ps
CPU time 2.42 seconds
Started Jul 07 05:06:25 PM PDT 24
Finished Jul 07 05:06:27 PM PDT 24
Peak memory 206776 kb
Host smart-b223d89e-6cd5-4f25-bdfc-86953cc47dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178088366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.178088366
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3092355412
Short name T570
Test name
Test status
Simulation time 286173100 ps
CPU time 3.34 seconds
Started Jul 07 05:06:27 PM PDT 24
Finished Jul 07 05:06:31 PM PDT 24
Peak memory 207820 kb
Host smart-00153d18-eba8-4269-be7b-97b38a813d11
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092355412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3092355412
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2856631477
Short name T870
Test name
Test status
Simulation time 21700344 ps
CPU time 1.82 seconds
Started Jul 07 05:06:26 PM PDT 24
Finished Jul 07 05:06:29 PM PDT 24
Peak memory 206744 kb
Host smart-94122b47-01fa-4207-8ac6-470fb379edc2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856631477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2856631477
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1619994349
Short name T370
Test name
Test status
Simulation time 298233744 ps
CPU time 3.22 seconds
Started Jul 07 05:06:25 PM PDT 24
Finished Jul 07 05:06:29 PM PDT 24
Peak memory 206792 kb
Host smart-9a94016b-4155-48b8-8495-144e2aafef2e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619994349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1619994349
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3358423366
Short name T319
Test name
Test status
Simulation time 102898377 ps
CPU time 2.32 seconds
Started Jul 07 05:06:27 PM PDT 24
Finished Jul 07 05:06:30 PM PDT 24
Peak memory 209244 kb
Host smart-a567f3e3-1e6f-4c5a-9afd-4388bf3353b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358423366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3358423366
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3030089947
Short name T549
Test name
Test status
Simulation time 1126694822 ps
CPU time 4.2 seconds
Started Jul 07 05:06:26 PM PDT 24
Finished Jul 07 05:06:30 PM PDT 24
Peak memory 207712 kb
Host smart-cd060959-a243-4c95-b967-f57c852dd166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030089947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3030089947
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3614237635
Short name T815
Test name
Test status
Simulation time 292166323 ps
CPU time 6.59 seconds
Started Jul 07 05:06:27 PM PDT 24
Finished Jul 07 05:06:34 PM PDT 24
Peak memory 207564 kb
Host smart-a6d9997d-f8fe-4e64-9b3b-59b05f3d95dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614237635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3614237635
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3931835744
Short name T179
Test name
Test status
Simulation time 173686302 ps
CPU time 2.1 seconds
Started Jul 07 05:06:30 PM PDT 24
Finished Jul 07 05:06:33 PM PDT 24
Peak memory 210460 kb
Host smart-d5f572c1-9c09-4a01-b5a4-35e3fa0622fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931835744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3931835744
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3219568649
Short name T440
Test name
Test status
Simulation time 40613801 ps
CPU time 0.71 seconds
Started Jul 07 05:08:26 PM PDT 24
Finished Jul 07 05:08:28 PM PDT 24
Peak memory 205972 kb
Host smart-5cb25635-714f-4490-8efa-04c74758d9b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219568649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3219568649
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.4046636381
Short name T6
Test name
Test status
Simulation time 57971616 ps
CPU time 3.05 seconds
Started Jul 07 05:08:21 PM PDT 24
Finished Jul 07 05:08:25 PM PDT 24
Peak memory 210488 kb
Host smart-a79c47c7-34c8-4927-a721-4f9d5edb51e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046636381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.4046636381
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2230852871
Short name T329
Test name
Test status
Simulation time 28901309 ps
CPU time 2.23 seconds
Started Jul 07 05:08:21 PM PDT 24
Finished Jul 07 05:08:24 PM PDT 24
Peak memory 218420 kb
Host smart-1e2cdbbb-267f-469f-82f1-c775ea2922af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230852871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2230852871
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.925337400
Short name T890
Test name
Test status
Simulation time 65778188 ps
CPU time 1.6 seconds
Started Jul 07 05:08:21 PM PDT 24
Finished Jul 07 05:08:23 PM PDT 24
Peak memory 214320 kb
Host smart-e065351b-950b-4c9e-9b3d-943938fd0f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925337400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.925337400
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3047003752
Short name T678
Test name
Test status
Simulation time 102321264 ps
CPU time 2.47 seconds
Started Jul 07 05:08:26 PM PDT 24
Finished Jul 07 05:08:29 PM PDT 24
Peak memory 215460 kb
Host smart-59f05eff-6ee0-48f5-a938-557db7ea4256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047003752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3047003752
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1568651597
Short name T901
Test name
Test status
Simulation time 329998309 ps
CPU time 10.03 seconds
Started Jul 07 05:08:23 PM PDT 24
Finished Jul 07 05:08:34 PM PDT 24
Peak memory 214320 kb
Host smart-55d5a232-d487-4caf-996b-a8d84e4b316d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568651597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1568651597
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3956103145
Short name T264
Test name
Test status
Simulation time 1057173829 ps
CPU time 3.62 seconds
Started Jul 07 05:08:22 PM PDT 24
Finished Jul 07 05:08:26 PM PDT 24
Peak memory 208512 kb
Host smart-04ea868c-1500-4a49-905e-7206caf50811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956103145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3956103145
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1630850222
Short name T558
Test name
Test status
Simulation time 99189616 ps
CPU time 4.49 seconds
Started Jul 07 05:08:21 PM PDT 24
Finished Jul 07 05:08:26 PM PDT 24
Peak memory 208568 kb
Host smart-98fce2ac-2d32-4976-ada1-06a7a47e47fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630850222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1630850222
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1515646650
Short name T657
Test name
Test status
Simulation time 411497392 ps
CPU time 5.32 seconds
Started Jul 07 05:08:24 PM PDT 24
Finished Jul 07 05:08:30 PM PDT 24
Peak memory 208192 kb
Host smart-8f722288-6e47-48df-bee4-66bc5a221a80
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515646650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1515646650
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1862498477
Short name T429
Test name
Test status
Simulation time 236486730 ps
CPU time 5.95 seconds
Started Jul 07 05:08:21 PM PDT 24
Finished Jul 07 05:08:28 PM PDT 24
Peak memory 208704 kb
Host smart-02455f46-fa1c-4d9c-9cf7-9940611989ac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862498477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1862498477
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.629264391
Short name T363
Test name
Test status
Simulation time 207887888 ps
CPU time 5.09 seconds
Started Jul 07 05:08:26 PM PDT 24
Finished Jul 07 05:08:32 PM PDT 24
Peak memory 208740 kb
Host smart-a4613d4f-c0b6-4f6e-80bd-7671c6fab070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629264391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.629264391
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3366234282
Short name T751
Test name
Test status
Simulation time 81432945 ps
CPU time 1.76 seconds
Started Jul 07 05:08:23 PM PDT 24
Finished Jul 07 05:08:25 PM PDT 24
Peak memory 206708 kb
Host smart-3768c345-097c-4cc0-a68b-03ac7ab9f93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366234282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3366234282
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2508350449
Short name T25
Test name
Test status
Simulation time 182441434 ps
CPU time 5.84 seconds
Started Jul 07 05:08:20 PM PDT 24
Finished Jul 07 05:08:26 PM PDT 24
Peak memory 214568 kb
Host smart-194f4904-3f2a-4c48-9b57-def6f92cc510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508350449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2508350449
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2177886000
Short name T731
Test name
Test status
Simulation time 51985381 ps
CPU time 2.7 seconds
Started Jul 07 05:08:21 PM PDT 24
Finished Jul 07 05:08:24 PM PDT 24
Peak memory 210248 kb
Host smart-ef442748-f4f4-492f-8463-8182bd5cc215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177886000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2177886000
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.18877847
Short name T670
Test name
Test status
Simulation time 38420644 ps
CPU time 0.74 seconds
Started Jul 07 05:08:25 PM PDT 24
Finished Jul 07 05:08:27 PM PDT 24
Peak memory 205864 kb
Host smart-1c514a15-7bd5-4fed-8e25-8ff5a1a3f66f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18877847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.18877847
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3662064184
Short name T829
Test name
Test status
Simulation time 93923071 ps
CPU time 3.64 seconds
Started Jul 07 05:08:26 PM PDT 24
Finished Jul 07 05:08:31 PM PDT 24
Peak memory 221660 kb
Host smart-d606eeeb-1d20-4634-8cbc-42bc1f390c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662064184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3662064184
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.911595267
Short name T521
Test name
Test status
Simulation time 182418639 ps
CPU time 2.69 seconds
Started Jul 07 05:08:26 PM PDT 24
Finished Jul 07 05:08:29 PM PDT 24
Peak memory 207388 kb
Host smart-5d8631b1-7d29-42ae-bb54-9973fa455d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911595267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.911595267
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1757930780
Short name T867
Test name
Test status
Simulation time 134156211 ps
CPU time 2.28 seconds
Started Jul 07 05:08:26 PM PDT 24
Finished Jul 07 05:08:30 PM PDT 24
Peak memory 214236 kb
Host smart-b7ff8f62-ce69-4525-9dff-192acc48b274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757930780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1757930780
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1081827837
Short name T747
Test name
Test status
Simulation time 546534867 ps
CPU time 4.2 seconds
Started Jul 07 05:08:29 PM PDT 24
Finished Jul 07 05:08:34 PM PDT 24
Peak memory 214252 kb
Host smart-df7df72e-c220-4cb9-9954-07806ff67e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081827837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1081827837
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1220321488
Short name T45
Test name
Test status
Simulation time 216289092 ps
CPU time 4.11 seconds
Started Jul 07 05:08:26 PM PDT 24
Finished Jul 07 05:08:31 PM PDT 24
Peak memory 219964 kb
Host smart-d3028417-db72-435b-9847-f334f8b4b501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220321488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1220321488
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.442321129
Short name T158
Test name
Test status
Simulation time 4575822979 ps
CPU time 48.21 seconds
Started Jul 07 05:08:30 PM PDT 24
Finished Jul 07 05:09:18 PM PDT 24
Peak memory 219700 kb
Host smart-2f4bc591-91c8-412c-be15-d9437f393618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442321129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.442321129
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.4117986196
Short name T476
Test name
Test status
Simulation time 50346170 ps
CPU time 2.7 seconds
Started Jul 07 05:08:26 PM PDT 24
Finished Jul 07 05:08:30 PM PDT 24
Peak memory 206912 kb
Host smart-e0688a9c-1af1-497b-b2f2-f972cf5d204b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117986196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.4117986196
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.27782559
Short name T894
Test name
Test status
Simulation time 154110155 ps
CPU time 2.22 seconds
Started Jul 07 05:08:28 PM PDT 24
Finished Jul 07 05:08:30 PM PDT 24
Peak memory 206824 kb
Host smart-a0a94f90-bc6c-4a19-a6a1-6414ea288e29
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27782559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.27782559
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3248312376
Short name T837
Test name
Test status
Simulation time 304567681 ps
CPU time 3.06 seconds
Started Jul 07 05:08:26 PM PDT 24
Finished Jul 07 05:08:29 PM PDT 24
Peak memory 206880 kb
Host smart-7c238958-414d-4a22-a43c-69d2b048aa9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248312376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3248312376
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1405191454
Short name T827
Test name
Test status
Simulation time 44857445 ps
CPU time 2.57 seconds
Started Jul 07 05:08:30 PM PDT 24
Finished Jul 07 05:08:33 PM PDT 24
Peak memory 206860 kb
Host smart-6b9360c3-d12b-4a0c-a4ed-6398d5ef41fd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405191454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1405191454
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.828684971
Short name T692
Test name
Test status
Simulation time 295319301 ps
CPU time 3.58 seconds
Started Jul 07 05:08:24 PM PDT 24
Finished Jul 07 05:08:28 PM PDT 24
Peak memory 218232 kb
Host smart-15227dd8-8b66-4ab6-9fce-7f2379455bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828684971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.828684971
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2866488151
Short name T427
Test name
Test status
Simulation time 504361531 ps
CPU time 2.57 seconds
Started Jul 07 05:08:27 PM PDT 24
Finished Jul 07 05:08:30 PM PDT 24
Peak memory 208340 kb
Host smart-64fc46c2-8fc8-4d19-8cf8-6afc63df2ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866488151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2866488151
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.522849941
Short name T332
Test name
Test status
Simulation time 807931509 ps
CPU time 9.8 seconds
Started Jul 07 05:08:25 PM PDT 24
Finished Jul 07 05:08:36 PM PDT 24
Peak memory 214216 kb
Host smart-29e41e6b-f920-4d71-95a5-6dbdd010b557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522849941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.522849941
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3010766866
Short name T381
Test name
Test status
Simulation time 68085063 ps
CPU time 2 seconds
Started Jul 07 05:08:30 PM PDT 24
Finished Jul 07 05:08:32 PM PDT 24
Peak memory 210044 kb
Host smart-fd9cf001-33ce-48c1-b920-ff6e3173e973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010766866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3010766866
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1700431304
Short name T787
Test name
Test status
Simulation time 200894791 ps
CPU time 0.84 seconds
Started Jul 07 05:08:34 PM PDT 24
Finished Jul 07 05:08:35 PM PDT 24
Peak memory 205980 kb
Host smart-236e1026-fd6f-469b-b947-e5655efe18fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700431304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1700431304
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3265508346
Short name T242
Test name
Test status
Simulation time 1094676465 ps
CPU time 14.1 seconds
Started Jul 07 05:08:31 PM PDT 24
Finished Jul 07 05:08:46 PM PDT 24
Peak memory 214504 kb
Host smart-46df5063-a841-4648-922d-9e19988b40d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265508346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3265508346
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1358518237
Short name T793
Test name
Test status
Simulation time 118415580 ps
CPU time 3.15 seconds
Started Jul 07 05:08:31 PM PDT 24
Finished Jul 07 05:08:34 PM PDT 24
Peak memory 214608 kb
Host smart-92cf9a47-afd7-43af-a023-055f70d9099d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358518237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1358518237
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.386589307
Short name T524
Test name
Test status
Simulation time 373804190 ps
CPU time 4 seconds
Started Jul 07 05:08:30 PM PDT 24
Finished Jul 07 05:08:34 PM PDT 24
Peak memory 218284 kb
Host smart-915af460-6c9d-486b-85ed-3652986624a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386589307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.386589307
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2371290223
Short name T561
Test name
Test status
Simulation time 26772657 ps
CPU time 2.09 seconds
Started Jul 07 05:08:29 PM PDT 24
Finished Jul 07 05:08:31 PM PDT 24
Peak memory 214300 kb
Host smart-328f0a3b-bc18-4a2e-bf4a-6cf87fe4fc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371290223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2371290223
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2882017178
Short name T623
Test name
Test status
Simulation time 43228145 ps
CPU time 2.5 seconds
Started Jul 07 05:08:29 PM PDT 24
Finished Jul 07 05:08:31 PM PDT 24
Peak memory 214248 kb
Host smart-694495d4-ebd1-4650-aeaa-9545b64dd938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882017178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2882017178
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.47884253
Short name T679
Test name
Test status
Simulation time 171182364 ps
CPU time 3.65 seconds
Started Jul 07 05:08:30 PM PDT 24
Finished Jul 07 05:08:34 PM PDT 24
Peak memory 214296 kb
Host smart-da323072-d358-4de5-8d1d-37a29e5c593b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47884253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.47884253
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.680274824
Short name T566
Test name
Test status
Simulation time 599089666 ps
CPU time 6.33 seconds
Started Jul 07 05:08:38 PM PDT 24
Finished Jul 07 05:08:44 PM PDT 24
Peak memory 214424 kb
Host smart-3711713b-f3fe-42e2-82fa-006eaa0d03d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680274824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.680274824
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2347275696
Short name T416
Test name
Test status
Simulation time 1269734048 ps
CPU time 33.9 seconds
Started Jul 07 05:08:30 PM PDT 24
Finished Jul 07 05:09:05 PM PDT 24
Peak memory 208216 kb
Host smart-93bb40b0-dd00-4d1d-ac63-72080c1c9050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347275696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2347275696
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2249993980
Short name T630
Test name
Test status
Simulation time 394014582 ps
CPU time 6.5 seconds
Started Jul 07 05:08:30 PM PDT 24
Finished Jul 07 05:08:37 PM PDT 24
Peak memory 208128 kb
Host smart-6c191962-1d46-4ab5-aa42-03e4c3affc09
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249993980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2249993980
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3858159271
Short name T573
Test name
Test status
Simulation time 87262348 ps
CPU time 2.18 seconds
Started Jul 07 05:08:34 PM PDT 24
Finished Jul 07 05:08:37 PM PDT 24
Peak memory 208536 kb
Host smart-2f374fa6-20dd-4543-ae10-a1551c511ae5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858159271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3858159271
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2818668831
Short name T885
Test name
Test status
Simulation time 306763413 ps
CPU time 4.62 seconds
Started Jul 07 05:08:32 PM PDT 24
Finished Jul 07 05:08:36 PM PDT 24
Peak memory 208064 kb
Host smart-dbce4f19-892a-4bc9-b17d-609bec5d62b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818668831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2818668831
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2181874459
Short name T671
Test name
Test status
Simulation time 79699229 ps
CPU time 3.5 seconds
Started Jul 07 05:08:30 PM PDT 24
Finished Jul 07 05:08:34 PM PDT 24
Peak memory 222424 kb
Host smart-3660f1b7-ec1c-4b20-80e7-3c1bb3052984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181874459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2181874459
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1137440582
Short name T431
Test name
Test status
Simulation time 364804411 ps
CPU time 3.14 seconds
Started Jul 07 05:08:31 PM PDT 24
Finished Jul 07 05:08:34 PM PDT 24
Peak memory 208476 kb
Host smart-92c843ac-bb6d-4760-bfa3-5824898347c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137440582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1137440582
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2610681424
Short name T366
Test name
Test status
Simulation time 3649040055 ps
CPU time 75.96 seconds
Started Jul 07 05:08:31 PM PDT 24
Finished Jul 07 05:09:47 PM PDT 24
Peak memory 222564 kb
Host smart-1252457d-4f2c-42f5-a943-707d995860a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610681424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2610681424
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.4167924203
Short name T449
Test name
Test status
Simulation time 556006482 ps
CPU time 9.62 seconds
Started Jul 07 05:08:33 PM PDT 24
Finished Jul 07 05:08:43 PM PDT 24
Peak memory 222548 kb
Host smart-6cb77191-2910-4b6e-bb9e-fc166e1d0235
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167924203 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.4167924203
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1349400447
Short name T532
Test name
Test status
Simulation time 3397627211 ps
CPU time 42.32 seconds
Started Jul 07 05:08:30 PM PDT 24
Finished Jul 07 05:09:13 PM PDT 24
Peak memory 209612 kb
Host smart-55b67c86-ab08-4245-bcb3-fc11fa956dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349400447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1349400447
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1049447300
Short name T55
Test name
Test status
Simulation time 611808777 ps
CPU time 2.61 seconds
Started Jul 07 05:08:34 PM PDT 24
Finished Jul 07 05:08:38 PM PDT 24
Peak memory 209928 kb
Host smart-d386067f-d687-4eb8-ada8-0ffe18f5c1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049447300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1049447300
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.996948956
Short name T529
Test name
Test status
Simulation time 42998280 ps
CPU time 0.76 seconds
Started Jul 07 05:08:36 PM PDT 24
Finished Jul 07 05:08:37 PM PDT 24
Peak memory 205992 kb
Host smart-f812c1a6-6441-44e2-ad14-3a21f9540dd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996948956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.996948956
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.206907155
Short name T151
Test name
Test status
Simulation time 75141481 ps
CPU time 3.38 seconds
Started Jul 07 05:08:35 PM PDT 24
Finished Jul 07 05:08:39 PM PDT 24
Peak memory 217884 kb
Host smart-8bdd4842-62c1-47f3-b1cf-fbe88cb1b89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206907155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.206907155
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1143640053
Short name T652
Test name
Test status
Simulation time 81586629 ps
CPU time 3.08 seconds
Started Jul 07 05:08:35 PM PDT 24
Finished Jul 07 05:08:39 PM PDT 24
Peak memory 208536 kb
Host smart-a2b20a69-50ca-427d-8980-d7fccbc4e527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143640053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1143640053
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.732663378
Short name T89
Test name
Test status
Simulation time 82716882 ps
CPU time 1.94 seconds
Started Jul 07 05:08:35 PM PDT 24
Finished Jul 07 05:08:38 PM PDT 24
Peak memory 214396 kb
Host smart-70bff937-4e47-4074-b6b3-9109b96b0c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732663378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.732663378
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3555756480
Short name T856
Test name
Test status
Simulation time 66917835 ps
CPU time 2.22 seconds
Started Jul 07 05:08:35 PM PDT 24
Finished Jul 07 05:08:38 PM PDT 24
Peak memory 214160 kb
Host smart-4e962530-3db4-4dce-b066-82db49053b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555756480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3555756480
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.221537232
Short name T53
Test name
Test status
Simulation time 297036517 ps
CPU time 3.92 seconds
Started Jul 07 05:08:32 PM PDT 24
Finished Jul 07 05:08:36 PM PDT 24
Peak memory 218560 kb
Host smart-7d3453b1-c2b7-4f35-85a4-605a17d8d77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221537232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.221537232
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1219790655
Short name T592
Test name
Test status
Simulation time 36899981 ps
CPU time 2.88 seconds
Started Jul 07 05:08:35 PM PDT 24
Finished Jul 07 05:08:38 PM PDT 24
Peak memory 214312 kb
Host smart-304732d2-109d-495a-b0a2-2c2944ab9d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219790655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1219790655
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.426598134
Short name T641
Test name
Test status
Simulation time 3159040335 ps
CPU time 5.31 seconds
Started Jul 07 05:08:34 PM PDT 24
Finished Jul 07 05:08:41 PM PDT 24
Peak memory 207060 kb
Host smart-c3d60b3b-5b6a-486f-bae0-2d5fb24b6ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426598134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.426598134
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3213067211
Short name T246
Test name
Test status
Simulation time 231487110 ps
CPU time 6.41 seconds
Started Jul 07 05:08:35 PM PDT 24
Finished Jul 07 05:08:42 PM PDT 24
Peak memory 208788 kb
Host smart-9c525303-d1ca-431a-b115-28d677a146f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213067211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3213067211
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2154011292
Short name T481
Test name
Test status
Simulation time 124276289 ps
CPU time 4.16 seconds
Started Jul 07 05:08:34 PM PDT 24
Finished Jul 07 05:08:38 PM PDT 24
Peak memory 206996 kb
Host smart-fb86ab40-7e85-448c-8c3d-e1cea30294b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154011292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2154011292
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3790914664
Short name T530
Test name
Test status
Simulation time 354651403 ps
CPU time 3.97 seconds
Started Jul 07 05:08:40 PM PDT 24
Finished Jul 07 05:08:45 PM PDT 24
Peak memory 208736 kb
Host smart-bb339dd6-60a5-41ac-9892-a12c5bc7ef1e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790914664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3790914664
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2282460742
Short name T687
Test name
Test status
Simulation time 165351856 ps
CPU time 2.87 seconds
Started Jul 07 05:08:35 PM PDT 24
Finished Jul 07 05:08:38 PM PDT 24
Peak memory 215924 kb
Host smart-6a47447a-1128-4471-8d47-0a05adebabbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282460742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2282460742
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.468668041
Short name T655
Test name
Test status
Simulation time 28944858 ps
CPU time 2.11 seconds
Started Jul 07 05:08:36 PM PDT 24
Finished Jul 07 05:08:39 PM PDT 24
Peak memory 208548 kb
Host smart-691c4431-ce2b-4339-99cb-193fc95fe56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468668041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.468668041
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.172204629
Short name T709
Test name
Test status
Simulation time 6227184523 ps
CPU time 24.85 seconds
Started Jul 07 05:08:35 PM PDT 24
Finished Jul 07 05:09:01 PM PDT 24
Peak memory 222536 kb
Host smart-bfb5ff8c-ae6e-46a9-9983-8cc9e4497063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172204629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.172204629
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.64116614
Short name T559
Test name
Test status
Simulation time 424305691 ps
CPU time 11.83 seconds
Started Jul 07 05:08:41 PM PDT 24
Finished Jul 07 05:08:54 PM PDT 24
Peak memory 222720 kb
Host smart-6f7058c5-2d28-421d-b64f-73bb1f2256ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64116614 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.64116614
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1638141984
Short name T456
Test name
Test status
Simulation time 350268059 ps
CPU time 8.9 seconds
Started Jul 07 05:08:35 PM PDT 24
Finished Jul 07 05:08:45 PM PDT 24
Peak memory 218204 kb
Host smart-4519e40a-d143-462f-b188-b799d3fc243d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638141984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1638141984
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3011283284
Short name T616
Test name
Test status
Simulation time 48620300 ps
CPU time 2.23 seconds
Started Jul 07 05:08:34 PM PDT 24
Finished Jul 07 05:08:37 PM PDT 24
Peak memory 209976 kb
Host smart-059d3582-ca14-4a83-8e25-fb609fee8dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011283284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3011283284
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.885844670
Short name T163
Test name
Test status
Simulation time 9956771 ps
CPU time 0.74 seconds
Started Jul 07 05:08:39 PM PDT 24
Finished Jul 07 05:08:40 PM PDT 24
Peak memory 205928 kb
Host smart-5c52b7ae-7ab9-4d41-b3a6-0b5988ebe098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885844670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.885844670
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3864935501
Short name T902
Test name
Test status
Simulation time 40622727 ps
CPU time 2.5 seconds
Started Jul 07 05:08:41 PM PDT 24
Finished Jul 07 05:08:44 PM PDT 24
Peak memory 215104 kb
Host smart-6df3ec48-571f-42e2-a616-b83e6593d7c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864935501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3864935501
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2912688052
Short name T866
Test name
Test status
Simulation time 39295771 ps
CPU time 2.34 seconds
Started Jul 07 05:08:36 PM PDT 24
Finished Jul 07 05:08:39 PM PDT 24
Peak memory 207784 kb
Host smart-7813104b-7620-4dc8-a59a-005f22745428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912688052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2912688052
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3739323631
Short name T642
Test name
Test status
Simulation time 1788022280 ps
CPU time 7.07 seconds
Started Jul 07 05:08:38 PM PDT 24
Finished Jul 07 05:08:45 PM PDT 24
Peak memory 221008 kb
Host smart-31371054-db57-4de1-ac86-89c18f0d5a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739323631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3739323631
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2830867584
Short name T585
Test name
Test status
Simulation time 50579740 ps
CPU time 3 seconds
Started Jul 07 05:08:38 PM PDT 24
Finished Jul 07 05:08:41 PM PDT 24
Peak memory 220152 kb
Host smart-350f6f86-49aa-4063-85f4-09ece78f47c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830867584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2830867584
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2777974279
Short name T131
Test name
Test status
Simulation time 510200701 ps
CPU time 7.92 seconds
Started Jul 07 05:08:35 PM PDT 24
Finished Jul 07 05:08:44 PM PDT 24
Peak memory 214352 kb
Host smart-1aa0082d-a666-4472-8e8b-f7db59606e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777974279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2777974279
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3171805827
Short name T490
Test name
Test status
Simulation time 1176267705 ps
CPU time 20.7 seconds
Started Jul 07 05:08:34 PM PDT 24
Finished Jul 07 05:08:55 PM PDT 24
Peak memory 207820 kb
Host smart-1b043b2a-fee4-4d71-b648-7c34caac0a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171805827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3171805827
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1528534392
Short name T702
Test name
Test status
Simulation time 47819654 ps
CPU time 2.15 seconds
Started Jul 07 05:08:40 PM PDT 24
Finished Jul 07 05:08:43 PM PDT 24
Peak memory 208800 kb
Host smart-8db4cc6b-60c6-4a73-a3a4-b26d01a829dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528534392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1528534392
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2936744583
Short name T418
Test name
Test status
Simulation time 385776112 ps
CPU time 3.83 seconds
Started Jul 07 05:08:35 PM PDT 24
Finished Jul 07 05:08:40 PM PDT 24
Peak memory 206920 kb
Host smart-6516d003-21b0-430a-b029-f677d0cec19d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936744583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2936744583
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3581895449
Short name T444
Test name
Test status
Simulation time 37955361 ps
CPU time 2.5 seconds
Started Jul 07 05:08:33 PM PDT 24
Finished Jul 07 05:08:36 PM PDT 24
Peak memory 206940 kb
Host smart-4503429b-b990-47b9-b7fe-bc4f4881bac3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581895449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3581895449
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1881874210
Short name T746
Test name
Test status
Simulation time 362824492 ps
CPU time 5.81 seconds
Started Jul 07 05:08:40 PM PDT 24
Finished Jul 07 05:08:47 PM PDT 24
Peak memory 218140 kb
Host smart-07865ac3-4e60-4595-b663-5c1894bc80f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881874210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1881874210
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.742113274
Short name T792
Test name
Test status
Simulation time 273167275 ps
CPU time 5.31 seconds
Started Jul 07 05:08:35 PM PDT 24
Finished Jul 07 05:08:41 PM PDT 24
Peak memory 208216 kb
Host smart-d6b26a41-0506-4e55-aa6f-a46ad1c93235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742113274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.742113274
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.819664088
Short name T335
Test name
Test status
Simulation time 2268216653 ps
CPU time 52.34 seconds
Started Jul 07 05:08:38 PM PDT 24
Finished Jul 07 05:09:31 PM PDT 24
Peak memory 220508 kb
Host smart-f7e2d861-20b1-4770-965a-2d16063d114e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819664088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.819664088
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3399392078
Short name T284
Test name
Test status
Simulation time 251508217 ps
CPU time 3.82 seconds
Started Jul 07 05:08:40 PM PDT 24
Finished Jul 07 05:08:45 PM PDT 24
Peak memory 207636 kb
Host smart-c00d8988-949d-4c47-8c7d-cb4ee167cb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399392078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3399392078
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1279980650
Short name T694
Test name
Test status
Simulation time 196495770 ps
CPU time 2.48 seconds
Started Jul 07 05:08:42 PM PDT 24
Finished Jul 07 05:08:45 PM PDT 24
Peak memory 214376 kb
Host smart-6188e931-2f02-4a74-89d6-99a3c0599b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279980650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1279980650
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2912168250
Short name T695
Test name
Test status
Simulation time 40283059 ps
CPU time 0.8 seconds
Started Jul 07 05:08:45 PM PDT 24
Finished Jul 07 05:08:47 PM PDT 24
Peak memory 205980 kb
Host smart-61e47d96-3d1d-449b-ad2f-f66f9393d23c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912168250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2912168250
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2753764406
Short name T398
Test name
Test status
Simulation time 94361888 ps
CPU time 3.51 seconds
Started Jul 07 05:08:39 PM PDT 24
Finished Jul 07 05:08:43 PM PDT 24
Peak memory 214352 kb
Host smart-04b12861-e65a-4a3d-b690-b5316e47a765
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2753764406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2753764406
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.849637789
Short name T17
Test name
Test status
Simulation time 244314982 ps
CPU time 2.48 seconds
Started Jul 07 05:08:39 PM PDT 24
Finished Jul 07 05:08:42 PM PDT 24
Peak memory 219536 kb
Host smart-87ce6056-daa3-4657-86eb-cf9b12c82881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849637789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.849637789
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2547506415
Short name T883
Test name
Test status
Simulation time 69245812 ps
CPU time 1.73 seconds
Started Jul 07 05:08:39 PM PDT 24
Finished Jul 07 05:08:42 PM PDT 24
Peak memory 208072 kb
Host smart-7b2a1d58-b3eb-4dd4-8054-fa57ed6a66fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547506415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2547506415
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1122354081
Short name T613
Test name
Test status
Simulation time 51694928 ps
CPU time 1.92 seconds
Started Jul 07 05:08:41 PM PDT 24
Finished Jul 07 05:08:43 PM PDT 24
Peak memory 214296 kb
Host smart-48454116-2175-466a-a443-0baf9840e31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122354081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1122354081
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3823425062
Short name T289
Test name
Test status
Simulation time 73446977 ps
CPU time 3.2 seconds
Started Jul 07 05:08:39 PM PDT 24
Finished Jul 07 05:08:42 PM PDT 24
Peak memory 214148 kb
Host smart-46d810aa-8c95-4c34-beb4-f4ccf2cd88a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823425062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3823425062
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3936718004
Short name T676
Test name
Test status
Simulation time 125872526 ps
CPU time 4.24 seconds
Started Jul 07 05:08:41 PM PDT 24
Finished Jul 07 05:08:45 PM PDT 24
Peak memory 209084 kb
Host smart-7bfe2ee6-75be-4eb6-b8b8-40cb86616db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936718004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3936718004
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.570454263
Short name T896
Test name
Test status
Simulation time 89679518 ps
CPU time 4.09 seconds
Started Jul 07 05:08:40 PM PDT 24
Finished Jul 07 05:08:44 PM PDT 24
Peak memory 214328 kb
Host smart-64037353-0d28-4ce3-8533-ca6ff26585a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570454263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.570454263
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3266189190
Short name T527
Test name
Test status
Simulation time 437138635 ps
CPU time 6.25 seconds
Started Jul 07 05:08:39 PM PDT 24
Finished Jul 07 05:08:46 PM PDT 24
Peak memory 208056 kb
Host smart-ab4715d4-aa53-455e-87d8-23c5d72623d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266189190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3266189190
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.4245722261
Short name T813
Test name
Test status
Simulation time 34806030 ps
CPU time 2.37 seconds
Started Jul 07 05:08:41 PM PDT 24
Finished Jul 07 05:08:44 PM PDT 24
Peak memory 207264 kb
Host smart-a993373b-0271-4ece-b028-8258749a65c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245722261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.4245722261
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3244648156
Short name T738
Test name
Test status
Simulation time 95470574 ps
CPU time 2.61 seconds
Started Jul 07 05:08:40 PM PDT 24
Finished Jul 07 05:08:43 PM PDT 24
Peak memory 206844 kb
Host smart-ba12adc2-cddd-478a-92fb-8e6f005adc57
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244648156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3244648156
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.225533895
Short name T882
Test name
Test status
Simulation time 71068881 ps
CPU time 3.24 seconds
Started Jul 07 05:08:38 PM PDT 24
Finished Jul 07 05:08:42 PM PDT 24
Peak memory 208264 kb
Host smart-6651b3ae-d094-474e-bc32-4e0af1e0590c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225533895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.225533895
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.389366290
Short name T821
Test name
Test status
Simulation time 35570530 ps
CPU time 2.01 seconds
Started Jul 07 05:08:48 PM PDT 24
Finished Jul 07 05:08:50 PM PDT 24
Peak memory 215696 kb
Host smart-7bca46f2-40f9-4945-9cdd-f8522188e7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389366290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.389366290
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.862198082
Short name T12
Test name
Test status
Simulation time 66161482 ps
CPU time 2.51 seconds
Started Jul 07 05:08:41 PM PDT 24
Finished Jul 07 05:08:44 PM PDT 24
Peak memory 206676 kb
Host smart-1581ee97-ff20-44bd-97ab-257391c73a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862198082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.862198082
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.680675055
Short name T239
Test name
Test status
Simulation time 125886645 ps
CPU time 5.02 seconds
Started Jul 07 05:08:40 PM PDT 24
Finished Jul 07 05:08:45 PM PDT 24
Peak memory 209528 kb
Host smart-f2d8b27a-3022-4330-b518-4572586b6089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680675055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.680675055
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3821662881
Short name T869
Test name
Test status
Simulation time 165035779 ps
CPU time 0.87 seconds
Started Jul 07 05:08:47 PM PDT 24
Finished Jul 07 05:08:48 PM PDT 24
Peak memory 205976 kb
Host smart-e0ee8925-29da-40c9-9cde-a6e38ad60862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821662881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3821662881
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2232687476
Short name T346
Test name
Test status
Simulation time 217497950 ps
CPU time 4.13 seconds
Started Jul 07 05:08:43 PM PDT 24
Finished Jul 07 05:08:48 PM PDT 24
Peak memory 215120 kb
Host smart-e5645a73-a7d3-42c9-88c8-879b50b927e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2232687476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2232687476
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1718360221
Short name T761
Test name
Test status
Simulation time 135667156 ps
CPU time 3.11 seconds
Started Jul 07 05:08:43 PM PDT 24
Finished Jul 07 05:08:46 PM PDT 24
Peak memory 209204 kb
Host smart-85c51769-fd0a-4885-b01d-8ddff5539ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718360221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1718360221
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3172490641
Short name T103
Test name
Test status
Simulation time 1204667452 ps
CPU time 12.21 seconds
Started Jul 07 05:08:44 PM PDT 24
Finished Jul 07 05:08:57 PM PDT 24
Peak memory 214308 kb
Host smart-53bc531b-e7f0-452b-b5e5-f975f9d3893e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172490641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3172490641
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1310564598
Short name T735
Test name
Test status
Simulation time 427793284 ps
CPU time 6.5 seconds
Started Jul 07 05:08:48 PM PDT 24
Finished Jul 07 05:08:54 PM PDT 24
Peak memory 206972 kb
Host smart-d65e4127-fb2a-4569-86e0-3078125aeb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310564598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1310564598
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_random.762208030
Short name T286
Test name
Test status
Simulation time 76756372 ps
CPU time 3.67 seconds
Started Jul 07 05:08:44 PM PDT 24
Finished Jul 07 05:08:48 PM PDT 24
Peak memory 208692 kb
Host smart-4bffe4ef-f292-455a-be12-98092774245d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762208030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.762208030
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1967083363
Short name T460
Test name
Test status
Simulation time 2037539441 ps
CPU time 5.42 seconds
Started Jul 07 05:08:44 PM PDT 24
Finished Jul 07 05:08:50 PM PDT 24
Peak memory 206808 kb
Host smart-b53c5f6c-9371-44f7-8b65-36dfc56370e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967083363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1967083363
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2017544678
Short name T763
Test name
Test status
Simulation time 73686050 ps
CPU time 3.45 seconds
Started Jul 07 05:08:43 PM PDT 24
Finished Jul 07 05:08:47 PM PDT 24
Peak memory 208892 kb
Host smart-77396475-9173-48bc-8c92-29fb6dae4071
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017544678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2017544678
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.624149737
Short name T633
Test name
Test status
Simulation time 6389319400 ps
CPU time 43.52 seconds
Started Jul 07 05:08:43 PM PDT 24
Finished Jul 07 05:09:26 PM PDT 24
Peak memory 207896 kb
Host smart-8657a285-13dc-4bb7-9f14-eb0e88c6820a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624149737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.624149737
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3159481226
Short name T590
Test name
Test status
Simulation time 106824358 ps
CPU time 3.97 seconds
Started Jul 07 05:08:45 PM PDT 24
Finished Jul 07 05:08:50 PM PDT 24
Peak memory 208600 kb
Host smart-5937a796-323f-4b86-8a4a-d4828e8cb41e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159481226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3159481226
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3232493752
Short name T759
Test name
Test status
Simulation time 267631747 ps
CPU time 3.18 seconds
Started Jul 07 05:08:48 PM PDT 24
Finished Jul 07 05:08:52 PM PDT 24
Peak memory 214412 kb
Host smart-557d1e18-095a-4db7-aa3d-97418fe6436f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232493752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3232493752
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1274712525
Short name T838
Test name
Test status
Simulation time 414817634 ps
CPU time 2.71 seconds
Started Jul 07 05:08:43 PM PDT 24
Finished Jul 07 05:08:47 PM PDT 24
Peak memory 208432 kb
Host smart-3d78680b-ea21-48c7-bb98-88b2f100310f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274712525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1274712525
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1806743075
Short name T778
Test name
Test status
Simulation time 107257095 ps
CPU time 2.12 seconds
Started Jul 07 05:08:52 PM PDT 24
Finished Jul 07 05:08:55 PM PDT 24
Peak memory 208720 kb
Host smart-cf96073b-5637-474b-b6af-641642fa2bef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806743075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1806743075
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3692855984
Short name T451
Test name
Test status
Simulation time 805990825 ps
CPU time 6.99 seconds
Started Jul 07 05:08:47 PM PDT 24
Finished Jul 07 05:08:54 PM PDT 24
Peak memory 214272 kb
Host smart-7bd81d25-101b-4707-86ae-c81df59a4b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692855984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3692855984
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.4258913393
Short name T446
Test name
Test status
Simulation time 49981986 ps
CPU time 1.72 seconds
Started Jul 07 05:08:48 PM PDT 24
Finished Jul 07 05:08:50 PM PDT 24
Peak memory 209952 kb
Host smart-2ac191a8-765f-48cb-ab76-c7d208d02617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258913393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.4258913393
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1926573770
Short name T659
Test name
Test status
Simulation time 69707940 ps
CPU time 0.82 seconds
Started Jul 07 05:08:52 PM PDT 24
Finished Jul 07 05:08:53 PM PDT 24
Peak memory 205888 kb
Host smart-c97d4f9f-a857-44f1-b7e5-05c6169475e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926573770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1926573770
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.4098191771
Short name T307
Test name
Test status
Simulation time 120578570 ps
CPU time 4.2 seconds
Started Jul 07 05:08:50 PM PDT 24
Finished Jul 07 05:08:54 PM PDT 24
Peak memory 215468 kb
Host smart-6072501c-64dd-4d8a-a237-98fe26c88ac0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098191771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.4098191771
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.815321870
Short name T388
Test name
Test status
Simulation time 142448040 ps
CPU time 4.35 seconds
Started Jul 07 05:08:48 PM PDT 24
Finished Jul 07 05:08:53 PM PDT 24
Peak memory 207640 kb
Host smart-901d058d-aa03-46cf-95cd-0107c6ae4b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815321870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.815321870
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1268217809
Short name T98
Test name
Test status
Simulation time 72605112 ps
CPU time 2.48 seconds
Started Jul 07 05:08:46 PM PDT 24
Finished Jul 07 05:08:49 PM PDT 24
Peak memory 214256 kb
Host smart-56fe99d3-3573-486f-b338-4aab940a2507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268217809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1268217809
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2729221258
Short name T528
Test name
Test status
Simulation time 1030863995 ps
CPU time 7.01 seconds
Started Jul 07 05:08:48 PM PDT 24
Finished Jul 07 05:08:55 PM PDT 24
Peak memory 222444 kb
Host smart-ef290b36-0c85-4e6e-a074-28dc96d821d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729221258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2729221258
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1327123694
Short name T720
Test name
Test status
Simulation time 89465272 ps
CPU time 2.91 seconds
Started Jul 07 05:08:47 PM PDT 24
Finished Jul 07 05:08:50 PM PDT 24
Peak memory 215060 kb
Host smart-8e2df00d-9b1a-4b35-9fb5-21289d5e7a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327123694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1327123694
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.308700259
Short name T406
Test name
Test status
Simulation time 39739603 ps
CPU time 2.82 seconds
Started Jul 07 05:08:50 PM PDT 24
Finished Jul 07 05:08:53 PM PDT 24
Peak memory 209408 kb
Host smart-108ab686-f82f-487f-9dbb-2a9cb6bccb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308700259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.308700259
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3601565689
Short name T634
Test name
Test status
Simulation time 934081225 ps
CPU time 6.39 seconds
Started Jul 07 05:08:47 PM PDT 24
Finished Jul 07 05:08:54 PM PDT 24
Peak memory 207824 kb
Host smart-e0a8aedf-e0f5-4f5e-a156-45a9762e1634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601565689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3601565689
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2060455523
Short name T639
Test name
Test status
Simulation time 112424115 ps
CPU time 4.82 seconds
Started Jul 07 05:08:47 PM PDT 24
Finished Jul 07 05:08:52 PM PDT 24
Peak memory 209156 kb
Host smart-8ab98d2c-f114-48c3-bc86-12f4735132be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060455523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2060455523
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3386869366
Short name T587
Test name
Test status
Simulation time 107423179 ps
CPU time 3.72 seconds
Started Jul 07 05:08:47 PM PDT 24
Finished Jul 07 05:08:51 PM PDT 24
Peak memory 208740 kb
Host smart-78d2815c-58af-4eb3-a38a-bdf4eeada61c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386869366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3386869366
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.4066470091
Short name T365
Test name
Test status
Simulation time 20894219 ps
CPU time 1.78 seconds
Started Jul 07 05:08:46 PM PDT 24
Finished Jul 07 05:08:48 PM PDT 24
Peak memory 206784 kb
Host smart-205264a9-5551-40cc-98dd-89aa180cea3d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066470091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.4066470091
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2420835556
Short name T44
Test name
Test status
Simulation time 35228344 ps
CPU time 1.75 seconds
Started Jul 07 05:08:52 PM PDT 24
Finished Jul 07 05:08:54 PM PDT 24
Peak memory 208328 kb
Host smart-c51fd6a2-f57d-4407-a760-05d6f4cd3eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420835556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2420835556
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3038344488
Short name T588
Test name
Test status
Simulation time 37982003 ps
CPU time 1.78 seconds
Started Jul 07 05:08:47 PM PDT 24
Finished Jul 07 05:08:49 PM PDT 24
Peak memory 207444 kb
Host smart-9f111674-1ed3-4904-a32e-0cb7138ef79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038344488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3038344488
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3780955267
Short name T769
Test name
Test status
Simulation time 884317789 ps
CPU time 13.77 seconds
Started Jul 07 05:08:51 PM PDT 24
Finished Jul 07 05:09:05 PM PDT 24
Peak memory 222620 kb
Host smart-a58e16b9-6920-4d15-889c-6b1577c29d53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780955267 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3780955267
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3403370510
Short name T506
Test name
Test status
Simulation time 2175292937 ps
CPU time 76.82 seconds
Started Jul 07 05:08:51 PM PDT 24
Finished Jul 07 05:10:08 PM PDT 24
Peak memory 208300 kb
Host smart-f2da6c41-6fc0-497d-b9b2-f3683281e01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403370510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3403370510
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.4204958184
Short name T811
Test name
Test status
Simulation time 60693567 ps
CPU time 2.29 seconds
Started Jul 07 05:08:51 PM PDT 24
Finished Jul 07 05:08:54 PM PDT 24
Peak memory 210348 kb
Host smart-6d18293d-9d69-4309-98ed-560ce4e1608a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204958184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.4204958184
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1068430425
Short name T442
Test name
Test status
Simulation time 177912308 ps
CPU time 0.9 seconds
Started Jul 07 05:08:56 PM PDT 24
Finished Jul 07 05:08:57 PM PDT 24
Peak memory 206252 kb
Host smart-4efe8134-368a-4c79-9069-b6f1eef22d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068430425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1068430425
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1271392613
Short name T405
Test name
Test status
Simulation time 790946611 ps
CPU time 10.22 seconds
Started Jul 07 05:08:50 PM PDT 24
Finished Jul 07 05:09:01 PM PDT 24
Peak memory 214548 kb
Host smart-8e7f769c-4e32-4a0e-9ef1-48c4f46a1997
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271392613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1271392613
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1260233734
Short name T34
Test name
Test status
Simulation time 91813269 ps
CPU time 4.1 seconds
Started Jul 07 05:08:53 PM PDT 24
Finished Jul 07 05:08:57 PM PDT 24
Peak memory 218496 kb
Host smart-ce77beed-fe28-400b-b758-1804ee8afd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260233734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1260233734
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1723030874
Short name T80
Test name
Test status
Simulation time 1587365492 ps
CPU time 15.85 seconds
Started Jul 07 05:08:53 PM PDT 24
Finished Jul 07 05:09:09 PM PDT 24
Peak memory 214320 kb
Host smart-1d9cb157-bd51-40bb-9bce-ecf7f42aefaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723030874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1723030874
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3187375932
Short name T104
Test name
Test status
Simulation time 45277633 ps
CPU time 3.14 seconds
Started Jul 07 05:08:50 PM PDT 24
Finished Jul 07 05:08:54 PM PDT 24
Peak memory 214416 kb
Host smart-f12999fe-6669-49bb-92e8-ad1b00dd34d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187375932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3187375932
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1708309488
Short name T372
Test name
Test status
Simulation time 429796695 ps
CPU time 6.44 seconds
Started Jul 07 05:08:53 PM PDT 24
Finished Jul 07 05:09:00 PM PDT 24
Peak memory 222344 kb
Host smart-7a408c31-8a7f-4ab2-86c7-f8fd93f932cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708309488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1708309488
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.4239134395
Short name T851
Test name
Test status
Simulation time 92995535 ps
CPU time 4.45 seconds
Started Jul 07 05:08:50 PM PDT 24
Finished Jul 07 05:08:55 PM PDT 24
Peak memory 214496 kb
Host smart-11c9879c-7b58-4504-a5f2-bdf64a1764c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239134395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.4239134395
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.391187224
Short name T249
Test name
Test status
Simulation time 193143850 ps
CPU time 6.94 seconds
Started Jul 07 05:08:52 PM PDT 24
Finished Jul 07 05:08:59 PM PDT 24
Peak memory 218816 kb
Host smart-1b4fc5d5-a653-4400-8c56-91e00624a4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391187224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.391187224
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.573982563
Short name T483
Test name
Test status
Simulation time 145958690 ps
CPU time 5.76 seconds
Started Jul 07 05:08:50 PM PDT 24
Finished Jul 07 05:08:56 PM PDT 24
Peak memory 209036 kb
Host smart-f8a618a2-541a-4ec2-8e16-3898d54db3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573982563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.573982563
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.927297493
Short name T689
Test name
Test status
Simulation time 133967364 ps
CPU time 3.28 seconds
Started Jul 07 05:08:51 PM PDT 24
Finished Jul 07 05:08:55 PM PDT 24
Peak memory 208744 kb
Host smart-9192a89e-bb9a-4e45-8200-b38a611018af
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927297493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.927297493
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2053466007
Short name T872
Test name
Test status
Simulation time 1647376329 ps
CPU time 8.28 seconds
Started Jul 07 05:08:50 PM PDT 24
Finished Jul 07 05:08:58 PM PDT 24
Peak memory 208588 kb
Host smart-ea87a9a6-8c32-4493-8f6c-4fd48eb43df4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053466007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2053466007
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3853208692
Short name T361
Test name
Test status
Simulation time 2653001858 ps
CPU time 17.89 seconds
Started Jul 07 05:08:52 PM PDT 24
Finished Jul 07 05:09:11 PM PDT 24
Peak memory 208016 kb
Host smart-34ef41c7-4767-428d-a1b9-56a0a8a29bd5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853208692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3853208692
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.577334639
Short name T501
Test name
Test status
Simulation time 69185241 ps
CPU time 2.13 seconds
Started Jul 07 05:08:54 PM PDT 24
Finished Jul 07 05:08:56 PM PDT 24
Peak memory 208224 kb
Host smart-561fd9b0-fa41-446c-a2b5-7fd619c167db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577334639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.577334639
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2606474178
Short name T904
Test name
Test status
Simulation time 221123163 ps
CPU time 2.69 seconds
Started Jul 07 05:08:52 PM PDT 24
Finished Jul 07 05:08:55 PM PDT 24
Peak memory 208788 kb
Host smart-f895d216-48d2-4eee-9a91-e099ff2858a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606474178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2606474178
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2163360876
Short name T367
Test name
Test status
Simulation time 270202576 ps
CPU time 10.8 seconds
Started Jul 07 05:08:58 PM PDT 24
Finished Jul 07 05:09:09 PM PDT 24
Peak memory 215948 kb
Host smart-a958bb51-de3f-4db6-b073-1de2ddc4771c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163360876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2163360876
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.438297015
Short name T722
Test name
Test status
Simulation time 363272107 ps
CPU time 17.24 seconds
Started Jul 07 05:08:57 PM PDT 24
Finished Jul 07 05:09:14 PM PDT 24
Peak memory 220812 kb
Host smart-ee71c87f-e7e9-4342-9496-29cdc6789235
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438297015 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.438297015
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3694811021
Short name T636
Test name
Test status
Simulation time 280990980 ps
CPU time 3.87 seconds
Started Jul 07 05:08:53 PM PDT 24
Finished Jul 07 05:08:57 PM PDT 24
Peak memory 208828 kb
Host smart-78b1fb5b-d099-4aeb-b935-bfcda167b24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694811021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3694811021
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3419739402
Short name T541
Test name
Test status
Simulation time 166697491 ps
CPU time 2.22 seconds
Started Jul 07 05:08:57 PM PDT 24
Finished Jul 07 05:08:59 PM PDT 24
Peak memory 210516 kb
Host smart-3faf5892-278c-41ef-8c9a-fcc2d61a6ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419739402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3419739402
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1696246686
Short name T817
Test name
Test status
Simulation time 11851427 ps
CPU time 0.79 seconds
Started Jul 07 05:09:02 PM PDT 24
Finished Jul 07 05:09:03 PM PDT 24
Peak memory 205980 kb
Host smart-a7da36a8-dd95-42af-8d0b-13bd8d3cc082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696246686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1696246686
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2889076296
Short name T135
Test name
Test status
Simulation time 105401131 ps
CPU time 2.31 seconds
Started Jul 07 05:08:57 PM PDT 24
Finished Jul 07 05:09:00 PM PDT 24
Peak memory 214996 kb
Host smart-75a9d2fd-9b36-483e-887d-81fb61eb8198
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2889076296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2889076296
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1813399993
Short name T143
Test name
Test status
Simulation time 271680791 ps
CPU time 4.26 seconds
Started Jul 07 05:08:58 PM PDT 24
Finished Jul 07 05:09:03 PM PDT 24
Peak memory 218012 kb
Host smart-b1483672-4f54-4d21-9570-bfcc109b0c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813399993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1813399993
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.957296691
Short name T845
Test name
Test status
Simulation time 150156760 ps
CPU time 5.46 seconds
Started Jul 07 05:08:58 PM PDT 24
Finished Jul 07 05:09:04 PM PDT 24
Peak memory 214308 kb
Host smart-11a486db-7f64-4de5-a32d-feaf2fc80af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957296691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.957296691
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1735880623
Short name T101
Test name
Test status
Simulation time 326808643 ps
CPU time 10.49 seconds
Started Jul 07 05:08:57 PM PDT 24
Finished Jul 07 05:09:08 PM PDT 24
Peak memory 214308 kb
Host smart-23503bb4-7675-40c2-8c73-e282fb6eba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735880623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1735880623
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.4287027110
Short name T739
Test name
Test status
Simulation time 78745177 ps
CPU time 2.19 seconds
Started Jul 07 05:08:54 PM PDT 24
Finished Jul 07 05:08:56 PM PDT 24
Peak memory 218420 kb
Host smart-bb8b6b9d-08ce-4fbe-ba1c-82b27176e7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287027110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.4287027110
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3878092471
Short name T511
Test name
Test status
Simulation time 270939066 ps
CPU time 3.71 seconds
Started Jul 07 05:08:58 PM PDT 24
Finished Jul 07 05:09:02 PM PDT 24
Peak memory 214324 kb
Host smart-dca7692d-f790-4ffb-826c-ffc0f2f6b17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878092471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3878092471
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2596155314
Short name T323
Test name
Test status
Simulation time 44683248 ps
CPU time 3.22 seconds
Started Jul 07 05:08:54 PM PDT 24
Finished Jul 07 05:08:58 PM PDT 24
Peak memory 219348 kb
Host smart-663a266d-cb79-4eaa-9959-668c40819a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596155314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2596155314
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1435224987
Short name T488
Test name
Test status
Simulation time 135713005 ps
CPU time 3.87 seconds
Started Jul 07 05:08:58 PM PDT 24
Finished Jul 07 05:09:02 PM PDT 24
Peak memory 208680 kb
Host smart-ab0aa8c7-798d-4fca-9341-74b403fc2e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435224987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1435224987
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3510970307
Short name T343
Test name
Test status
Simulation time 41408243 ps
CPU time 2.49 seconds
Started Jul 07 05:08:56 PM PDT 24
Finished Jul 07 05:08:59 PM PDT 24
Peak memory 206784 kb
Host smart-b8803236-174e-49d3-99cd-dd49e459fd9a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510970307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3510970307
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2465639978
Short name T204
Test name
Test status
Simulation time 578282140 ps
CPU time 4.74 seconds
Started Jul 07 05:08:56 PM PDT 24
Finished Jul 07 05:09:01 PM PDT 24
Peak memory 207012 kb
Host smart-8f84d780-8946-4aa6-92e1-6e260d8187a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465639978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2465639978
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3766141138
Short name T462
Test name
Test status
Simulation time 32014788 ps
CPU time 2.34 seconds
Started Jul 07 05:09:32 PM PDT 24
Finished Jul 07 05:09:35 PM PDT 24
Peak memory 207320 kb
Host smart-7074397a-8960-4495-ad11-0bce88d0cab1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766141138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3766141138
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2897067041
Short name T489
Test name
Test status
Simulation time 671516413 ps
CPU time 12 seconds
Started Jul 07 05:08:56 PM PDT 24
Finished Jul 07 05:09:08 PM PDT 24
Peak memory 208184 kb
Host smart-95c7e0ca-d6a5-4a3c-920b-208718b6092b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897067041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2897067041
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3164313854
Short name T200
Test name
Test status
Simulation time 6779143550 ps
CPU time 59.76 seconds
Started Jul 07 05:08:55 PM PDT 24
Finished Jul 07 05:09:55 PM PDT 24
Peak memory 209252 kb
Host smart-a03c0520-a5af-4c65-959b-0ee367711cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164313854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3164313854
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.423050963
Short name T586
Test name
Test status
Simulation time 68751465 ps
CPU time 2.3 seconds
Started Jul 07 05:08:58 PM PDT 24
Finished Jul 07 05:09:01 PM PDT 24
Peak memory 209812 kb
Host smart-a5f45e7f-ae8d-49a3-a88a-e5edcc8c8276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423050963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.423050963
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2941413838
Short name T669
Test name
Test status
Simulation time 14883201 ps
CPU time 0.93 seconds
Started Jul 07 05:06:40 PM PDT 24
Finished Jul 07 05:06:41 PM PDT 24
Peak memory 206144 kb
Host smart-37ba364a-fe3d-4803-810a-ae06377b2173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941413838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2941413838
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2492469016
Short name T404
Test name
Test status
Simulation time 433146402 ps
CPU time 6.6 seconds
Started Jul 07 05:06:33 PM PDT 24
Finished Jul 07 05:06:40 PM PDT 24
Peak memory 214320 kb
Host smart-4bdb4618-9390-4495-b6c4-cbd4a5114e0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2492469016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2492469016
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3291282218
Short name T712
Test name
Test status
Simulation time 262993481 ps
CPU time 3.03 seconds
Started Jul 07 05:06:35 PM PDT 24
Finished Jul 07 05:06:38 PM PDT 24
Peak memory 220140 kb
Host smart-e270b083-a7d6-472f-924b-1f8565473943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291282218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3291282218
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.651184084
Short name T73
Test name
Test status
Simulation time 198124051 ps
CPU time 2.1 seconds
Started Jul 07 05:06:35 PM PDT 24
Finished Jul 07 05:06:37 PM PDT 24
Peak memory 207556 kb
Host smart-d0717142-9799-4f5b-9b33-481f9e02de70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651184084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.651184084
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1083913980
Short name T879
Test name
Test status
Simulation time 134955007 ps
CPU time 2.1 seconds
Started Jul 07 05:06:34 PM PDT 24
Finished Jul 07 05:06:36 PM PDT 24
Peak memory 214264 kb
Host smart-2fcf04c4-86d7-46a6-9d85-17f8f27b6703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083913980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1083913980
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2390763665
Short name T658
Test name
Test status
Simulation time 70139709 ps
CPU time 3.71 seconds
Started Jul 07 05:06:33 PM PDT 24
Finished Jul 07 05:06:37 PM PDT 24
Peak memory 210728 kb
Host smart-6b780433-38f9-40d8-b789-a5dd52cb7139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390763665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2390763665
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.4208743134
Short name T572
Test name
Test status
Simulation time 196617345 ps
CPU time 2.95 seconds
Started Jul 07 05:06:35 PM PDT 24
Finished Jul 07 05:06:38 PM PDT 24
Peak memory 207728 kb
Host smart-18e36089-274c-4ab0-8108-b078890412e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208743134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.4208743134
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2678372496
Short name T39
Test name
Test status
Simulation time 3854692424 ps
CPU time 17.81 seconds
Started Jul 07 05:06:39 PM PDT 24
Finished Jul 07 05:06:57 PM PDT 24
Peak memory 232688 kb
Host smart-aeb43c58-84c4-4c6f-928c-3b77c4f208b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678372496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2678372496
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1783278337
Short name T727
Test name
Test status
Simulation time 1993976105 ps
CPU time 7.94 seconds
Started Jul 07 05:06:30 PM PDT 24
Finished Jul 07 05:06:38 PM PDT 24
Peak memory 208072 kb
Host smart-cfc71a28-5fdd-45c8-ac2f-b2314fc75a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783278337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1783278337
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2317921097
Short name T495
Test name
Test status
Simulation time 183573504 ps
CPU time 2.89 seconds
Started Jul 07 05:06:30 PM PDT 24
Finished Jul 07 05:06:33 PM PDT 24
Peak memory 209060 kb
Host smart-634c5534-ac2a-45b5-afbe-06363d9a6114
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317921097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2317921097
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.4252867199
Short name T4
Test name
Test status
Simulation time 36011568 ps
CPU time 2.58 seconds
Started Jul 07 05:06:30 PM PDT 24
Finished Jul 07 05:06:33 PM PDT 24
Peak memory 208496 kb
Host smart-fc085212-9933-4bc2-9812-2b87874e5463
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252867199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4252867199
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2938484885
Short name T690
Test name
Test status
Simulation time 651321933 ps
CPU time 5.03 seconds
Started Jul 07 05:06:36 PM PDT 24
Finished Jul 07 05:06:41 PM PDT 24
Peak memory 208692 kb
Host smart-b7fc5742-81c8-4514-a4b2-41370c237fce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938484885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2938484885
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_smoke.4154961161
Short name T620
Test name
Test status
Simulation time 1847087367 ps
CPU time 11.36 seconds
Started Jul 07 05:06:32 PM PDT 24
Finished Jul 07 05:06:44 PM PDT 24
Peak memory 207820 kb
Host smart-1ef59228-644f-4149-908f-bfc458d5ce2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154961161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.4154961161
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.481701260
Short name T324
Test name
Test status
Simulation time 1508976954 ps
CPU time 15.09 seconds
Started Jul 07 05:06:40 PM PDT 24
Finished Jul 07 05:06:56 PM PDT 24
Peak memory 220348 kb
Host smart-d25fcf43-0309-4b42-9fdc-44f7bb6e7de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481701260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.481701260
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1361467712
Short name T79
Test name
Test status
Simulation time 500239198 ps
CPU time 15.07 seconds
Started Jul 07 05:06:36 PM PDT 24
Finished Jul 07 05:06:51 PM PDT 24
Peak memory 222536 kb
Host smart-273b0977-f1c4-4631-945f-8562714f51d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361467712 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1361467712
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2845789962
Short name T454
Test name
Test status
Simulation time 300209499 ps
CPU time 4.06 seconds
Started Jul 07 05:06:38 PM PDT 24
Finished Jul 07 05:06:42 PM PDT 24
Peak memory 215216 kb
Host smart-88838d90-c0b0-4d00-863a-b7a98463b887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845789962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2845789962
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1786748261
Short name T612
Test name
Test status
Simulation time 193746252 ps
CPU time 2.4 seconds
Started Jul 07 05:06:34 PM PDT 24
Finished Jul 07 05:06:37 PM PDT 24
Peak memory 209888 kb
Host smart-00c9ef02-6bf4-4389-8579-e3afffa7301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786748261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1786748261
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3158177528
Short name T546
Test name
Test status
Simulation time 44933115 ps
CPU time 0.75 seconds
Started Jul 07 05:08:59 PM PDT 24
Finished Jul 07 05:09:00 PM PDT 24
Peak memory 205968 kb
Host smart-ab6f26e9-c1be-4beb-8312-82bfb2f17259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158177528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3158177528
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.667116927
Short name T327
Test name
Test status
Simulation time 218276212 ps
CPU time 3.68 seconds
Started Jul 07 05:09:02 PM PDT 24
Finished Jul 07 05:09:06 PM PDT 24
Peak memory 214324 kb
Host smart-44f2488a-ece4-4769-a8ea-2432e1bc6d9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=667116927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.667116927
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.152867018
Short name T579
Test name
Test status
Simulation time 888442488 ps
CPU time 33.99 seconds
Started Jul 07 05:09:04 PM PDT 24
Finished Jul 07 05:09:38 PM PDT 24
Peak memory 214244 kb
Host smart-49daddf8-f98d-4595-840e-2e7ede5a2df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152867018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.152867018
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.465792753
Short name T470
Test name
Test status
Simulation time 32005746 ps
CPU time 2.22 seconds
Started Jul 07 05:09:00 PM PDT 24
Finished Jul 07 05:09:03 PM PDT 24
Peak memory 207832 kb
Host smart-ce00089a-8b87-4aa2-9af5-64dd4b612b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465792753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.465792753
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.726605638
Short name T660
Test name
Test status
Simulation time 110849318 ps
CPU time 3.3 seconds
Started Jul 07 05:08:58 PM PDT 24
Finished Jul 07 05:09:02 PM PDT 24
Peak memory 214424 kb
Host smart-54aa4971-44d5-4105-948b-c7174bfaa7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726605638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.726605638
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2893940363
Short name T823
Test name
Test status
Simulation time 256432276 ps
CPU time 4 seconds
Started Jul 07 05:08:59 PM PDT 24
Finished Jul 07 05:09:03 PM PDT 24
Peak memory 214164 kb
Host smart-e2fcc2c9-c321-4abb-b233-01843b884771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893940363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2893940363
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3034555590
Short name T568
Test name
Test status
Simulation time 335841238 ps
CPU time 3.83 seconds
Started Jul 07 05:08:59 PM PDT 24
Finished Jul 07 05:09:03 PM PDT 24
Peak memory 215400 kb
Host smart-b35ef83b-439f-4c2d-ace4-08fef53dd405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034555590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3034555590
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.953203000
Short name T523
Test name
Test status
Simulation time 547628069 ps
CPU time 3.91 seconds
Started Jul 07 05:09:04 PM PDT 24
Finished Jul 07 05:09:08 PM PDT 24
Peak memory 207452 kb
Host smart-0733cb7d-d01e-4c7f-8f54-6939dd042155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953203000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.953203000
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1705189253
Short name T548
Test name
Test status
Simulation time 232055485 ps
CPU time 3.26 seconds
Started Jul 07 05:08:59 PM PDT 24
Finished Jul 07 05:09:03 PM PDT 24
Peak memory 208648 kb
Host smart-631886cf-e7d8-4088-8555-1292511e490e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705189253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1705189253
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2804662299
Short name T466
Test name
Test status
Simulation time 219505808 ps
CPU time 6.06 seconds
Started Jul 07 05:09:00 PM PDT 24
Finished Jul 07 05:09:06 PM PDT 24
Peak memory 208148 kb
Host smart-849da82f-05e8-42ad-8c5f-27f917bf0e29
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804662299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2804662299
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2782701611
Short name T857
Test name
Test status
Simulation time 759230580 ps
CPU time 5.65 seconds
Started Jul 07 05:09:07 PM PDT 24
Finished Jul 07 05:09:14 PM PDT 24
Peak memory 208792 kb
Host smart-375fa54a-783c-45fd-91e0-6c42c6e2cfdc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782701611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2782701611
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.426084055
Short name T554
Test name
Test status
Simulation time 178370935 ps
CPU time 2.6 seconds
Started Jul 07 05:09:08 PM PDT 24
Finished Jul 07 05:09:11 PM PDT 24
Peak memory 207452 kb
Host smart-b7cb02eb-23d6-4d8e-ba8f-443f2f70ddd7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426084055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.426084055
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1695644982
Short name T705
Test name
Test status
Simulation time 554521051 ps
CPU time 16.52 seconds
Started Jul 07 05:09:03 PM PDT 24
Finished Jul 07 05:09:20 PM PDT 24
Peak memory 208832 kb
Host smart-835939c9-1a45-40e8-ad9e-8f8990a58a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695644982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1695644982
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.681662315
Short name T601
Test name
Test status
Simulation time 29058784 ps
CPU time 2.12 seconds
Started Jul 07 05:08:59 PM PDT 24
Finished Jul 07 05:09:01 PM PDT 24
Peak memory 206972 kb
Host smart-9ff4fb5f-96e4-4371-85cc-5f50dac4b710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681662315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.681662315
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.475276800
Short name T226
Test name
Test status
Simulation time 5473951538 ps
CPU time 91.66 seconds
Started Jul 07 05:08:59 PM PDT 24
Finished Jul 07 05:10:31 PM PDT 24
Peak memory 215784 kb
Host smart-01821657-8e08-48a9-83c2-04330c7083d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475276800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.475276800
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2930965121
Short name T531
Test name
Test status
Simulation time 213751799 ps
CPU time 8.41 seconds
Started Jul 07 05:09:00 PM PDT 24
Finished Jul 07 05:09:09 PM PDT 24
Peak memory 210508 kb
Host smart-8158763f-8c33-44bb-8dee-c7670e105381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930965121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2930965121
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1330086685
Short name T820
Test name
Test status
Simulation time 120392817 ps
CPU time 2.47 seconds
Started Jul 07 05:09:03 PM PDT 24
Finished Jul 07 05:09:06 PM PDT 24
Peak memory 209948 kb
Host smart-6739913d-6885-4255-bbf1-73953e8be95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330086685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1330086685
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1208259350
Short name T802
Test name
Test status
Simulation time 215037762 ps
CPU time 0.78 seconds
Started Jul 07 05:09:03 PM PDT 24
Finished Jul 07 05:09:04 PM PDT 24
Peak memory 206240 kb
Host smart-3d47a470-668f-4dc4-8a96-9a43771c57bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208259350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1208259350
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1225765306
Short name T407
Test name
Test status
Simulation time 209645557 ps
CPU time 3.72 seconds
Started Jul 07 05:09:04 PM PDT 24
Finished Jul 07 05:09:09 PM PDT 24
Peak memory 215520 kb
Host smart-a598b99e-ee2a-4d67-b14e-6528d0515279
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225765306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1225765306
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.720808310
Short name T23
Test name
Test status
Simulation time 46599675 ps
CPU time 2.45 seconds
Started Jul 07 05:09:03 PM PDT 24
Finished Jul 07 05:09:06 PM PDT 24
Peak memory 216708 kb
Host smart-bed23c31-36e3-4740-8834-2699884b8b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720808310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.720808310
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.541145387
Short name T807
Test name
Test status
Simulation time 28286119 ps
CPU time 1.67 seconds
Started Jul 07 05:09:07 PM PDT 24
Finished Jul 07 05:09:09 PM PDT 24
Peak memory 206748 kb
Host smart-9d59f192-70bc-47ae-acbe-1612d375acdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541145387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.541145387
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1679023202
Short name T464
Test name
Test status
Simulation time 1954807522 ps
CPU time 29.17 seconds
Started Jul 07 05:09:07 PM PDT 24
Finished Jul 07 05:09:37 PM PDT 24
Peak memory 209632 kb
Host smart-ba5d2438-518e-4a2c-b22f-5e969f339c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679023202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1679023202
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3073315395
Short name T770
Test name
Test status
Simulation time 144698881 ps
CPU time 4.12 seconds
Started Jul 07 05:08:59 PM PDT 24
Finished Jul 07 05:09:04 PM PDT 24
Peak memory 214188 kb
Host smart-2c99b9f0-1bab-48d2-9139-d823cb76b51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073315395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3073315395
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3271568197
Short name T56
Test name
Test status
Simulation time 970495676 ps
CPU time 5.31 seconds
Started Jul 07 05:08:58 PM PDT 24
Finished Jul 07 05:09:04 PM PDT 24
Peak memory 222380 kb
Host smart-8e54d52e-6892-426c-ada8-2c74556035ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271568197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3271568197
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.159656811
Short name T576
Test name
Test status
Simulation time 455018562 ps
CPU time 5.05 seconds
Started Jul 07 05:09:04 PM PDT 24
Finished Jul 07 05:09:10 PM PDT 24
Peak memory 208240 kb
Host smart-6abc2f72-84c6-482d-958e-342324b82ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159656811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.159656811
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2416320731
Short name T563
Test name
Test status
Simulation time 321723007 ps
CPU time 5.27 seconds
Started Jul 07 05:09:03 PM PDT 24
Finished Jul 07 05:09:08 PM PDT 24
Peak memory 208492 kb
Host smart-06d0db22-1309-440c-8305-7137c3272ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416320731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2416320731
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1949132351
Short name T349
Test name
Test status
Simulation time 1606033331 ps
CPU time 22.97 seconds
Started Jul 07 05:09:03 PM PDT 24
Finished Jul 07 05:09:26 PM PDT 24
Peak memory 208024 kb
Host smart-44e1ca84-f323-41a3-ba25-7e43840d48d3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949132351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1949132351
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.149315930
Short name T718
Test name
Test status
Simulation time 116827364 ps
CPU time 2.44 seconds
Started Jul 07 05:08:59 PM PDT 24
Finished Jul 07 05:09:02 PM PDT 24
Peak memory 208980 kb
Host smart-2e477fe3-d55f-4bf1-a52f-48531c781ca6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149315930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.149315930
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.120108183
Short name T650
Test name
Test status
Simulation time 111805007 ps
CPU time 3.09 seconds
Started Jul 07 05:09:00 PM PDT 24
Finished Jul 07 05:09:04 PM PDT 24
Peak memory 208636 kb
Host smart-329e9a68-e9d2-45d5-a29b-3a995ee349e7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120108183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.120108183
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3529886934
Short name T479
Test name
Test status
Simulation time 1566125385 ps
CPU time 17.25 seconds
Started Jul 07 05:09:04 PM PDT 24
Finished Jul 07 05:09:21 PM PDT 24
Peak memory 214312 kb
Host smart-97028e07-e501-4c09-bb10-d9ffc92d9b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529886934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3529886934
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.571604048
Short name T575
Test name
Test status
Simulation time 2759936704 ps
CPU time 29.7 seconds
Started Jul 07 05:08:59 PM PDT 24
Finished Jul 07 05:09:29 PM PDT 24
Peak memory 208864 kb
Host smart-3241898f-1c01-4ad9-8712-79ff87cef821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571604048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.571604048
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1128832774
Short name T233
Test name
Test status
Simulation time 669812417 ps
CPU time 26.65 seconds
Started Jul 07 05:09:03 PM PDT 24
Finished Jul 07 05:09:30 PM PDT 24
Peak memory 216092 kb
Host smart-142c5535-3c59-4459-925e-c4257e49c00b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128832774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1128832774
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.946089233
Short name T696
Test name
Test status
Simulation time 4916176810 ps
CPU time 40.73 seconds
Started Jul 07 05:09:08 PM PDT 24
Finished Jul 07 05:09:50 PM PDT 24
Peak memory 209000 kb
Host smart-5cfee885-3f7b-41db-a075-063fbb22547e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946089233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.946089233
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3148068898
Short name T169
Test name
Test status
Simulation time 62475931 ps
CPU time 2.6 seconds
Started Jul 07 05:09:04 PM PDT 24
Finished Jul 07 05:09:07 PM PDT 24
Peak memory 210008 kb
Host smart-26ec2410-bc72-4f7b-a275-d1af3bb89907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148068898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3148068898
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3029959831
Short name T861
Test name
Test status
Simulation time 42641344 ps
CPU time 0.8 seconds
Started Jul 07 05:09:08 PM PDT 24
Finished Jul 07 05:09:10 PM PDT 24
Peak memory 205872 kb
Host smart-51f2b995-17cf-4af5-aae5-d558cd205268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029959831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3029959831
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2156097733
Short name T816
Test name
Test status
Simulation time 138159913 ps
CPU time 3.45 seconds
Started Jul 07 05:09:03 PM PDT 24
Finished Jul 07 05:09:07 PM PDT 24
Peak memory 214720 kb
Host smart-49f86c73-c4b5-40e0-b4ea-7c45572b78e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156097733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2156097733
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1842635255
Short name T257
Test name
Test status
Simulation time 40758458 ps
CPU time 2.86 seconds
Started Jul 07 05:09:02 PM PDT 24
Finished Jul 07 05:09:05 PM PDT 24
Peak memory 208008 kb
Host smart-2142e603-d0a8-4722-9f67-28fd01368c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842635255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1842635255
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.4026978604
Short name T373
Test name
Test status
Simulation time 61998602 ps
CPU time 2.49 seconds
Started Jul 07 05:09:03 PM PDT 24
Finished Jul 07 05:09:06 PM PDT 24
Peak memory 214296 kb
Host smart-16864f96-4e14-4164-9c57-9253e5c89996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026978604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.4026978604
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.998089116
Short name T261
Test name
Test status
Simulation time 122142460 ps
CPU time 2.07 seconds
Started Jul 07 05:09:05 PM PDT 24
Finished Jul 07 05:09:07 PM PDT 24
Peak memory 214184 kb
Host smart-f87d11a5-e5ad-4133-aedc-4fef55d1882d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998089116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.998089116
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1035336587
Short name T224
Test name
Test status
Simulation time 346647660 ps
CPU time 3.04 seconds
Started Jul 07 05:09:06 PM PDT 24
Finished Jul 07 05:09:09 PM PDT 24
Peak memory 220184 kb
Host smart-5b0a0a17-67d6-441f-85a9-f2efe134bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035336587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1035336587
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2458528622
Short name T543
Test name
Test status
Simulation time 668132186 ps
CPU time 10.39 seconds
Started Jul 07 05:09:03 PM PDT 24
Finished Jul 07 05:09:14 PM PDT 24
Peak memory 219904 kb
Host smart-c58b7a0f-1284-4d6e-ae36-1a00e35db4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458528622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2458528622
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2469177049
Short name T475
Test name
Test status
Simulation time 112298656 ps
CPU time 2.72 seconds
Started Jul 07 05:09:05 PM PDT 24
Finished Jul 07 05:09:08 PM PDT 24
Peak memory 206928 kb
Host smart-3831d98b-53b4-4696-b274-bfa0af11c3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469177049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2469177049
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1711869699
Short name T615
Test name
Test status
Simulation time 332107159 ps
CPU time 3.98 seconds
Started Jul 07 05:09:05 PM PDT 24
Finished Jul 07 05:09:09 PM PDT 24
Peak memory 208572 kb
Host smart-2d6e43ea-678e-4abf-b191-46dcb2352a30
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711869699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1711869699
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3482000619
Short name T768
Test name
Test status
Simulation time 1308432029 ps
CPU time 29.54 seconds
Started Jul 07 05:09:06 PM PDT 24
Finished Jul 07 05:09:35 PM PDT 24
Peak memory 208020 kb
Host smart-e18b30cf-396d-48c2-b312-0d7c7af1a931
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482000619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3482000619
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3984428968
Short name T624
Test name
Test status
Simulation time 523344609 ps
CPU time 6.3 seconds
Started Jul 07 05:09:05 PM PDT 24
Finished Jul 07 05:09:12 PM PDT 24
Peak memory 208188 kb
Host smart-e69a10db-8496-464d-aa5e-bb7d054248bf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984428968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3984428968
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2951693134
Short name T348
Test name
Test status
Simulation time 577312974 ps
CPU time 2.68 seconds
Started Jul 07 05:09:06 PM PDT 24
Finished Jul 07 05:09:09 PM PDT 24
Peak memory 208184 kb
Host smart-7fbcd29a-9583-4bbf-80ee-79c811002352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951693134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2951693134
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3643825313
Short name T714
Test name
Test status
Simulation time 155264060 ps
CPU time 3.37 seconds
Started Jul 07 05:09:04 PM PDT 24
Finished Jul 07 05:09:08 PM PDT 24
Peak memory 208636 kb
Host smart-026c7c47-ae55-4a89-b4c0-9c168dddf813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643825313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3643825313
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1466659951
Short name T176
Test name
Test status
Simulation time 324141891 ps
CPU time 19 seconds
Started Jul 07 05:09:04 PM PDT 24
Finished Jul 07 05:09:23 PM PDT 24
Peak memory 222700 kb
Host smart-b647a2c3-7e36-442d-8979-6365ddb40b4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466659951 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1466659951
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2947420677
Short name T706
Test name
Test status
Simulation time 127623349 ps
CPU time 4.71 seconds
Started Jul 07 05:09:05 PM PDT 24
Finished Jul 07 05:09:10 PM PDT 24
Peak memory 210048 kb
Host smart-b5880b6e-34bc-4b03-955e-c01efb44da47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947420677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2947420677
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.879516844
Short name T810
Test name
Test status
Simulation time 77960546 ps
CPU time 2.28 seconds
Started Jul 07 05:09:06 PM PDT 24
Finished Jul 07 05:09:09 PM PDT 24
Peak memory 210052 kb
Host smart-ef664091-303d-42dd-8a2a-09fa3fe6f8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879516844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.879516844
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.4006837227
Short name T713
Test name
Test status
Simulation time 41571996 ps
CPU time 0.89 seconds
Started Jul 07 05:09:10 PM PDT 24
Finished Jul 07 05:09:11 PM PDT 24
Peak memory 205952 kb
Host smart-719140d9-ee39-47b8-9ee1-c064a2276506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006837227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.4006837227
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.585349925
Short name T382
Test name
Test status
Simulation time 52248442 ps
CPU time 3.58 seconds
Started Jul 07 05:09:11 PM PDT 24
Finished Jul 07 05:09:15 PM PDT 24
Peak memory 214332 kb
Host smart-c5d8edff-45fa-41b5-9b95-ce590e6adbdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585349925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.585349925
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.357364865
Short name T728
Test name
Test status
Simulation time 569493362 ps
CPU time 7.55 seconds
Started Jul 07 05:09:08 PM PDT 24
Finished Jul 07 05:09:16 PM PDT 24
Peak memory 209232 kb
Host smart-0baad84d-7ff2-4952-adc6-0a95b38f15b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357364865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.357364865
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3213121099
Short name T375
Test name
Test status
Simulation time 368853152 ps
CPU time 5.41 seconds
Started Jul 07 05:09:09 PM PDT 24
Finished Jul 07 05:09:15 PM PDT 24
Peak memory 221300 kb
Host smart-6df83cec-46a7-4032-9b9a-292d80755193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213121099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3213121099
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3710210739
Short name T212
Test name
Test status
Simulation time 292460689 ps
CPU time 3.21 seconds
Started Jul 07 05:09:08 PM PDT 24
Finished Jul 07 05:09:12 PM PDT 24
Peak memory 219736 kb
Host smart-03195129-a5db-415a-88c0-247ce4e27ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710210739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3710210739
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.149651134
Short name T691
Test name
Test status
Simulation time 75035469 ps
CPU time 2.87 seconds
Started Jul 07 05:09:08 PM PDT 24
Finished Jul 07 05:09:12 PM PDT 24
Peak memory 214360 kb
Host smart-31227b0c-83c3-440c-84d1-a92aada11cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149651134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.149651134
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2975354667
Short name T161
Test name
Test status
Simulation time 2439272553 ps
CPU time 16.97 seconds
Started Jul 07 05:09:08 PM PDT 24
Finished Jul 07 05:09:26 PM PDT 24
Peak memory 208048 kb
Host smart-625e7997-60a1-4c17-b95b-34f6a7105174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975354667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2975354667
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2627774908
Short name T836
Test name
Test status
Simulation time 950394618 ps
CPU time 3.4 seconds
Started Jul 07 05:09:08 PM PDT 24
Finished Jul 07 05:09:12 PM PDT 24
Peak memory 206984 kb
Host smart-dbc78130-0b98-4f0a-9cc4-26dafa893697
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627774908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2627774908
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3617797047
Short name T726
Test name
Test status
Simulation time 1407796428 ps
CPU time 27.08 seconds
Started Jul 07 05:09:09 PM PDT 24
Finished Jul 07 05:09:37 PM PDT 24
Peak memory 208812 kb
Host smart-58c85955-4069-43ab-bf9b-b8a02963a390
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617797047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3617797047
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2940595777
Short name T393
Test name
Test status
Simulation time 158442374 ps
CPU time 4.13 seconds
Started Jul 07 05:09:07 PM PDT 24
Finished Jul 07 05:09:11 PM PDT 24
Peak memory 206896 kb
Host smart-ad8db9f2-2e49-4254-a416-1204cfa4fbbd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940595777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2940595777
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.386768528
Short name T390
Test name
Test status
Simulation time 193027646 ps
CPU time 3.73 seconds
Started Jul 07 05:09:07 PM PDT 24
Finished Jul 07 05:09:11 PM PDT 24
Peak memory 208352 kb
Host smart-efdd2f62-8312-4989-89df-e41a2947a855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386768528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.386768528
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1122356628
Short name T665
Test name
Test status
Simulation time 1334654102 ps
CPU time 20.82 seconds
Started Jul 07 05:09:08 PM PDT 24
Finished Jul 07 05:09:29 PM PDT 24
Peak memory 207840 kb
Host smart-4a7e7810-a604-40f4-8573-aaf86995b620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122356628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1122356628
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.848657250
Short name T645
Test name
Test status
Simulation time 22090582287 ps
CPU time 389.76 seconds
Started Jul 07 05:09:09 PM PDT 24
Finished Jul 07 05:15:39 PM PDT 24
Peak memory 222164 kb
Host smart-973e497b-e515-4cb3-bce1-35071ceffffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848657250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.848657250
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.3230243162
Short name T112
Test name
Test status
Simulation time 436131032 ps
CPU time 10.14 seconds
Started Jul 07 05:09:07 PM PDT 24
Finished Jul 07 05:09:18 PM PDT 24
Peak memory 222624 kb
Host smart-e3aab6f1-21d5-41d3-b216-ad372ced2cd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230243162 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.3230243162
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2526145304
Short name T294
Test name
Test status
Simulation time 268250802 ps
CPU time 6.09 seconds
Started Jul 07 05:09:08 PM PDT 24
Finished Jul 07 05:09:15 PM PDT 24
Peak memory 218372 kb
Host smart-b927b942-501f-446f-b3a4-6dd378c435b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526145304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2526145304
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2089521728
Short name T395
Test name
Test status
Simulation time 240051924 ps
CPU time 2.71 seconds
Started Jul 07 05:09:09 PM PDT 24
Finished Jul 07 05:09:12 PM PDT 24
Peak memory 209904 kb
Host smart-d021987e-a18f-48cd-bb2c-4f5b818bb71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089521728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2089521728
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.777989719
Short name T415
Test name
Test status
Simulation time 20299681 ps
CPU time 0.78 seconds
Started Jul 07 05:09:11 PM PDT 24
Finished Jul 07 05:09:12 PM PDT 24
Peak memory 205892 kb
Host smart-8c68440c-e964-42ca-9cad-3e604b5d208c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777989719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.777989719
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.749167852
Short name T402
Test name
Test status
Simulation time 90718302 ps
CPU time 2.14 seconds
Started Jul 07 05:09:12 PM PDT 24
Finished Jul 07 05:09:14 PM PDT 24
Peak memory 214224 kb
Host smart-2fdcc7a9-ff06-468b-93ad-2733b12299f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=749167852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.749167852
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1121697382
Short name T65
Test name
Test status
Simulation time 173967296 ps
CPU time 4.92 seconds
Started Jul 07 05:09:10 PM PDT 24
Finished Jul 07 05:09:15 PM PDT 24
Peak memory 208212 kb
Host smart-2fb6ffa2-905f-4c6c-98c8-bfa17dc0a52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121697382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1121697382
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.628939568
Short name T351
Test name
Test status
Simulation time 47102548 ps
CPU time 1.73 seconds
Started Jul 07 05:09:11 PM PDT 24
Finished Jul 07 05:09:13 PM PDT 24
Peak memory 214192 kb
Host smart-ff86ae6c-eaeb-4db1-a2ac-e637b72a4b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628939568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.628939568
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1738433145
Short name T878
Test name
Test status
Simulation time 160336576 ps
CPU time 4.4 seconds
Started Jul 07 05:09:12 PM PDT 24
Finished Jul 07 05:09:17 PM PDT 24
Peak memory 222412 kb
Host smart-fb6c7853-e11d-4094-8565-a5b80012e86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738433145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1738433145
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2137914944
Short name T742
Test name
Test status
Simulation time 423490725 ps
CPU time 4.81 seconds
Started Jul 07 05:09:15 PM PDT 24
Finished Jul 07 05:09:20 PM PDT 24
Peak memory 210316 kb
Host smart-a981abc0-25a7-40a4-8eb1-da0b4dc8f7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137914944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2137914944
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2249839356
Short name T321
Test name
Test status
Simulation time 332385550 ps
CPU time 7.76 seconds
Started Jul 07 05:09:13 PM PDT 24
Finished Jul 07 05:09:21 PM PDT 24
Peak memory 214288 kb
Host smart-93901b21-c29a-4ea7-8a4d-17d0a2b21bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249839356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2249839356
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3122824945
Short name T491
Test name
Test status
Simulation time 115651411 ps
CPU time 1.78 seconds
Started Jul 07 05:09:14 PM PDT 24
Finished Jul 07 05:09:16 PM PDT 24
Peak memory 206800 kb
Host smart-37936573-e44e-4eff-b56d-112d3d851228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122824945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3122824945
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.4290590480
Short name T461
Test name
Test status
Simulation time 37173400 ps
CPU time 1.76 seconds
Started Jul 07 05:09:13 PM PDT 24
Finished Jul 07 05:09:15 PM PDT 24
Peak memory 206852 kb
Host smart-966bae49-6dc5-4f0a-880a-4f0fa6efe29e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290590480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.4290590480
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2845847899
Short name T362
Test name
Test status
Simulation time 51358995 ps
CPU time 2.74 seconds
Started Jul 07 05:09:14 PM PDT 24
Finished Jul 07 05:09:17 PM PDT 24
Peak memory 208396 kb
Host smart-bfccc01b-1e4c-471c-bd4f-ba2f726a1315
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845847899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2845847899
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1314996744
Short name T115
Test name
Test status
Simulation time 74961326 ps
CPU time 3.33 seconds
Started Jul 07 05:09:13 PM PDT 24
Finished Jul 07 05:09:17 PM PDT 24
Peak memory 208532 kb
Host smart-55812c1d-64b4-451a-a1b6-b4ccb92cf64f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314996744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1314996744
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2426985410
Short name T547
Test name
Test status
Simulation time 82435681 ps
CPU time 2.45 seconds
Started Jul 07 05:09:12 PM PDT 24
Finished Jul 07 05:09:15 PM PDT 24
Peak memory 208564 kb
Host smart-577c5787-43bf-4fb8-a872-9bffe0eddad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426985410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2426985410
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1055869462
Short name T500
Test name
Test status
Simulation time 110060191 ps
CPU time 2.91 seconds
Started Jul 07 05:09:12 PM PDT 24
Finished Jul 07 05:09:15 PM PDT 24
Peak memory 206720 kb
Host smart-916232ac-542f-496e-ad2f-12ab3c5275e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055869462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1055869462
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1631307341
Short name T544
Test name
Test status
Simulation time 777953119 ps
CPU time 15.61 seconds
Started Jul 07 05:09:13 PM PDT 24
Finished Jul 07 05:09:29 PM PDT 24
Peak memory 222608 kb
Host smart-412f6c7b-4833-41df-82d0-535286cf45b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631307341 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1631307341
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2415998583
Short name T771
Test name
Test status
Simulation time 84345855 ps
CPU time 4.65 seconds
Started Jul 07 05:09:13 PM PDT 24
Finished Jul 07 05:09:18 PM PDT 24
Peak memory 214216 kb
Host smart-17042763-0152-4e9d-bfea-cea32847feb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415998583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2415998583
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2393384493
Short name T171
Test name
Test status
Simulation time 72756749 ps
CPU time 2.36 seconds
Started Jul 07 05:09:11 PM PDT 24
Finished Jul 07 05:09:13 PM PDT 24
Peak memory 210136 kb
Host smart-db85485d-c5e8-4c0c-9286-4a3b603c166a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393384493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2393384493
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.4236645240
Short name T538
Test name
Test status
Simulation time 32331115 ps
CPU time 0.74 seconds
Started Jul 07 05:09:19 PM PDT 24
Finished Jul 07 05:09:20 PM PDT 24
Peak memory 205988 kb
Host smart-40f67eb6-a121-4146-ac1f-fa49fc47a5a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236645240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.4236645240
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3717940561
Short name T721
Test name
Test status
Simulation time 74607081 ps
CPU time 3.54 seconds
Started Jul 07 05:09:17 PM PDT 24
Finished Jul 07 05:09:21 PM PDT 24
Peak memory 209872 kb
Host smart-9c27297a-8cfd-4891-a278-a74a9b1e85c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717940561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3717940561
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1775833858
Short name T848
Test name
Test status
Simulation time 58313689 ps
CPU time 1.81 seconds
Started Jul 07 05:09:24 PM PDT 24
Finished Jul 07 05:09:27 PM PDT 24
Peak memory 209660 kb
Host smart-d358a791-307f-4768-b901-eff262745311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775833858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1775833858
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.4046412028
Short name T244
Test name
Test status
Simulation time 50183994 ps
CPU time 1.74 seconds
Started Jul 07 05:09:24 PM PDT 24
Finished Jul 07 05:09:27 PM PDT 24
Peak memory 214176 kb
Host smart-683da605-0d77-4a13-a861-e8a1823ebf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046412028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.4046412028
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2320146852
Short name T888
Test name
Test status
Simulation time 147475753 ps
CPU time 3.53 seconds
Started Jul 07 05:09:24 PM PDT 24
Finished Jul 07 05:09:29 PM PDT 24
Peak memory 213796 kb
Host smart-1af07fd2-2b74-4d20-9835-b175c1a6ea79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320146852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2320146852
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3514932956
Short name T525
Test name
Test status
Simulation time 91106632 ps
CPU time 2.98 seconds
Started Jul 07 05:09:24 PM PDT 24
Finished Jul 07 05:09:28 PM PDT 24
Peak memory 214368 kb
Host smart-ed1a9b40-f3e3-4aa6-97f6-3ae08559c325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514932956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3514932956
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2508886449
Short name T40
Test name
Test status
Simulation time 36059580 ps
CPU time 2.72 seconds
Started Jul 07 05:09:17 PM PDT 24
Finished Jul 07 05:09:21 PM PDT 24
Peak memory 207328 kb
Host smart-f1c76d11-cb90-478b-9ac8-25a0f1b2a1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508886449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2508886449
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2180066644
Short name T850
Test name
Test status
Simulation time 121519595 ps
CPU time 3.93 seconds
Started Jul 07 05:09:19 PM PDT 24
Finished Jul 07 05:09:23 PM PDT 24
Peak memory 208456 kb
Host smart-8d1a823e-57df-4ea1-8d80-a19911a48597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180066644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2180066644
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1491614011
Short name T467
Test name
Test status
Simulation time 245836786 ps
CPU time 7.09 seconds
Started Jul 07 05:09:17 PM PDT 24
Finished Jul 07 05:09:25 PM PDT 24
Peak memory 207808 kb
Host smart-3d4cdb9d-3407-48b1-ab70-a6ea33f798d1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491614011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1491614011
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.75792010
Short name T863
Test name
Test status
Simulation time 165464835 ps
CPU time 2.41 seconds
Started Jul 07 05:09:16 PM PDT 24
Finished Jul 07 05:09:19 PM PDT 24
Peak memory 207160 kb
Host smart-a8a4bf91-fe12-468a-8aab-ad11487d0d50
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75792010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.75792010
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3294226728
Short name T791
Test name
Test status
Simulation time 133812021 ps
CPU time 2.54 seconds
Started Jul 07 05:09:15 PM PDT 24
Finished Jul 07 05:09:18 PM PDT 24
Peak memory 206856 kb
Host smart-39e63c02-0b78-42bd-a00b-8344d0451d15
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294226728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3294226728
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2264773135
Short name T334
Test name
Test status
Simulation time 66242345 ps
CPU time 2.19 seconds
Started Jul 07 05:09:14 PM PDT 24
Finished Jul 07 05:09:17 PM PDT 24
Peak memory 218344 kb
Host smart-37262772-97fa-44a6-bb8a-939e96c3e776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264773135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2264773135
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.657100332
Short name T651
Test name
Test status
Simulation time 51770667 ps
CPU time 2.06 seconds
Started Jul 07 05:09:12 PM PDT 24
Finished Jul 07 05:09:14 PM PDT 24
Peak memory 206832 kb
Host smart-1276c233-91ac-4040-b8f3-21bfbb3e3190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657100332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.657100332
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3403839774
Short name T760
Test name
Test status
Simulation time 858347060 ps
CPU time 12.02 seconds
Started Jul 07 05:09:18 PM PDT 24
Finished Jul 07 05:09:30 PM PDT 24
Peak memory 220508 kb
Host smart-df95518a-cf72-4503-81e2-0b87cec0c7c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403839774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3403839774
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3805172562
Short name T353
Test name
Test status
Simulation time 193538758 ps
CPU time 14.04 seconds
Started Jul 07 05:09:16 PM PDT 24
Finished Jul 07 05:09:30 PM PDT 24
Peak memory 222580 kb
Host smart-ce622ab9-be15-457f-b111-bd0d2fda0efb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805172562 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3805172562
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.213481644
Short name T241
Test name
Test status
Simulation time 151077239 ps
CPU time 5.66 seconds
Started Jul 07 05:09:24 PM PDT 24
Finished Jul 07 05:09:31 PM PDT 24
Peak memory 208592 kb
Host smart-106687ed-3ad3-40ef-9384-85e4a0c41762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213481644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.213481644
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2286159114
Short name T754
Test name
Test status
Simulation time 293221551 ps
CPU time 3.15 seconds
Started Jul 07 05:09:24 PM PDT 24
Finished Jul 07 05:09:27 PM PDT 24
Peak memory 210596 kb
Host smart-0b22d8a0-cce2-4229-bd8d-9ed57bb4f08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286159114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2286159114
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.4046852537
Short name T496
Test name
Test status
Simulation time 11639659 ps
CPU time 0.91 seconds
Started Jul 07 05:09:20 PM PDT 24
Finished Jul 07 05:09:21 PM PDT 24
Peak memory 206004 kb
Host smart-9a47d893-aa92-4fe1-9524-860d1c9ab4e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046852537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.4046852537
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3349204607
Short name T302
Test name
Test status
Simulation time 246120514 ps
CPU time 4.65 seconds
Started Jul 07 05:09:19 PM PDT 24
Finished Jul 07 05:09:24 PM PDT 24
Peak memory 214944 kb
Host smart-24e88660-e3ae-4a17-9834-5f464f6da98d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349204607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3349204607
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1599346767
Short name T31
Test name
Test status
Simulation time 136834627 ps
CPU time 2.13 seconds
Started Jul 07 05:09:23 PM PDT 24
Finished Jul 07 05:09:25 PM PDT 24
Peak memory 221548 kb
Host smart-6c40fbc6-7f35-4409-8db7-764e469fea01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599346767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1599346767
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3008399551
Short name T682
Test name
Test status
Simulation time 441138105 ps
CPU time 6.39 seconds
Started Jul 07 05:09:21 PM PDT 24
Finished Jul 07 05:09:28 PM PDT 24
Peak memory 208920 kb
Host smart-c49093b2-224e-400c-874b-daca0281a812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008399551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3008399551
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1194591827
Short name T20
Test name
Test status
Simulation time 1711897576 ps
CPU time 5.15 seconds
Started Jul 07 05:09:21 PM PDT 24
Finished Jul 07 05:09:27 PM PDT 24
Peak memory 214392 kb
Host smart-c0af8f09-2974-4b0d-b6dc-26d8608b5550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194591827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1194591827
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.779294675
Short name T822
Test name
Test status
Simulation time 254581047 ps
CPU time 3.93 seconds
Started Jul 07 05:09:19 PM PDT 24
Finished Jul 07 05:09:24 PM PDT 24
Peak memory 217040 kb
Host smart-fcf07b85-4a79-4d9b-aa58-44fd25987ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779294675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.779294675
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.495502491
Short name T756
Test name
Test status
Simulation time 155236610 ps
CPU time 1.78 seconds
Started Jul 07 05:09:21 PM PDT 24
Finished Jul 07 05:09:23 PM PDT 24
Peak memory 214320 kb
Host smart-3f3c95ee-2b84-4f48-a525-3ad8dde06278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495502491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.495502491
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3467674340
Short name T295
Test name
Test status
Simulation time 225368607 ps
CPU time 6.54 seconds
Started Jul 07 05:09:17 PM PDT 24
Finished Jul 07 05:09:24 PM PDT 24
Peak memory 214196 kb
Host smart-879ea46c-aa77-413c-af29-61cdffde855b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467674340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3467674340
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2757317093
Short name T891
Test name
Test status
Simulation time 642670333 ps
CPU time 6.18 seconds
Started Jul 07 05:09:16 PM PDT 24
Finished Jul 07 05:09:22 PM PDT 24
Peak memory 208476 kb
Host smart-7e00ef8c-9b34-4d26-bef5-c7d329724347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757317093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2757317093
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2577200703
Short name T552
Test name
Test status
Simulation time 28990141 ps
CPU time 2.24 seconds
Started Jul 07 05:09:17 PM PDT 24
Finished Jul 07 05:09:20 PM PDT 24
Peak memory 208520 kb
Host smart-903b9f18-ad01-4519-a56b-ddf4792a69a0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577200703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2577200703
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2166987244
Short name T432
Test name
Test status
Simulation time 126760338 ps
CPU time 3.09 seconds
Started Jul 07 05:09:24 PM PDT 24
Finished Jul 07 05:09:28 PM PDT 24
Peak memory 206516 kb
Host smart-076fb8d6-ef93-46fb-9262-43c7a93672c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166987244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2166987244
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.563314096
Short name T279
Test name
Test status
Simulation time 1851329136 ps
CPU time 57.48 seconds
Started Jul 07 05:09:14 PM PDT 24
Finished Jul 07 05:10:12 PM PDT 24
Peak memory 209236 kb
Host smart-bffd189a-ef35-4e8b-a549-a956857d4c1b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563314096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.563314096
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3829081097
Short name T251
Test name
Test status
Simulation time 394924792 ps
CPU time 8.29 seconds
Started Jul 07 05:09:22 PM PDT 24
Finished Jul 07 05:09:31 PM PDT 24
Peak memory 208636 kb
Host smart-2dcfac16-619a-4b5f-8556-cd789c3a8310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829081097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3829081097
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.495072710
Short name T663
Test name
Test status
Simulation time 2763804375 ps
CPU time 3.8 seconds
Started Jul 07 05:09:24 PM PDT 24
Finished Jul 07 05:09:28 PM PDT 24
Peak memory 208216 kb
Host smart-af85ba00-0d94-49c4-8405-5782a5bf70d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495072710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.495072710
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.473909605
Short name T814
Test name
Test status
Simulation time 1325988919 ps
CPU time 25.63 seconds
Started Jul 07 05:09:22 PM PDT 24
Finished Jul 07 05:09:48 PM PDT 24
Peak memory 215380 kb
Host smart-4c1e6f60-e334-4f81-956e-0f023fc02c08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473909605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.473909605
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3138522446
Short name T877
Test name
Test status
Simulation time 2499323324 ps
CPU time 27.93 seconds
Started Jul 07 05:09:22 PM PDT 24
Finished Jul 07 05:09:50 PM PDT 24
Peak memory 219800 kb
Host smart-ba5bfb1e-cd46-4d0b-ad27-041f8c044cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138522446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3138522446
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1087160115
Short name T699
Test name
Test status
Simulation time 879078467 ps
CPU time 20.01 seconds
Started Jul 07 05:09:21 PM PDT 24
Finished Jul 07 05:09:42 PM PDT 24
Peak memory 211156 kb
Host smart-a0d198eb-2344-4dd2-8d87-887cd6b93f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087160115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1087160115
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1945593798
Short name T748
Test name
Test status
Simulation time 33987038 ps
CPU time 0.7 seconds
Started Jul 07 05:09:22 PM PDT 24
Finished Jul 07 05:09:23 PM PDT 24
Peak memory 205984 kb
Host smart-9f6d7b12-7f44-4fe1-8314-9bbf3e337ba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945593798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1945593798
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1362218174
Short name T819
Test name
Test status
Simulation time 155162789 ps
CPU time 3.76 seconds
Started Jul 07 05:09:24 PM PDT 24
Finished Jul 07 05:09:28 PM PDT 24
Peak memory 218212 kb
Host smart-4fba5d74-694d-4d71-aa38-1cbd25006784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362218174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1362218174
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.727427621
Short name T745
Test name
Test status
Simulation time 885039625 ps
CPU time 3.63 seconds
Started Jul 07 05:09:21 PM PDT 24
Finished Jul 07 05:09:25 PM PDT 24
Peak memory 214324 kb
Host smart-91d62d80-5065-4e29-97a1-4f9a1a57ca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727427621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.727427621
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3620752802
Short name T818
Test name
Test status
Simulation time 516579941 ps
CPU time 2.95 seconds
Started Jul 07 05:09:24 PM PDT 24
Finished Jul 07 05:09:29 PM PDT 24
Peak memory 214288 kb
Host smart-b2764e70-76a0-4769-bca7-0d5106caa605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620752802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3620752802
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2296239916
Short name T855
Test name
Test status
Simulation time 393856332 ps
CPU time 3.97 seconds
Started Jul 07 05:09:22 PM PDT 24
Finished Jul 07 05:09:27 PM PDT 24
Peak memory 208680 kb
Host smart-6585d12e-426a-46ec-8bf8-1fe803174284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296239916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2296239916
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1347074676
Short name T90
Test name
Test status
Simulation time 180485278 ps
CPU time 4.48 seconds
Started Jul 07 05:09:21 PM PDT 24
Finished Jul 07 05:09:25 PM PDT 24
Peak memory 208256 kb
Host smart-fe7b137b-3238-49ee-87da-3e87ab16ff0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347074676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1347074676
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1881913300
Short name T654
Test name
Test status
Simulation time 431371021 ps
CPU time 5.4 seconds
Started Jul 07 05:09:21 PM PDT 24
Finished Jul 07 05:09:27 PM PDT 24
Peak memory 208544 kb
Host smart-7d3de719-3807-492f-88ec-ffa444d56a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881913300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1881913300
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1903074967
Short name T571
Test name
Test status
Simulation time 288848157 ps
CPU time 3.19 seconds
Started Jul 07 05:09:19 PM PDT 24
Finished Jul 07 05:09:23 PM PDT 24
Peak memory 208468 kb
Host smart-eac2dac1-3b49-4b31-85b4-e0beda8ef181
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903074967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1903074967
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2801945747
Short name T685
Test name
Test status
Simulation time 139074040 ps
CPU time 5.03 seconds
Started Jul 07 05:09:21 PM PDT 24
Finished Jul 07 05:09:26 PM PDT 24
Peak memory 208644 kb
Host smart-3417545a-987a-4dd7-bef4-e87501e2888a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801945747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2801945747
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2263832961
Short name T736
Test name
Test status
Simulation time 30530112 ps
CPU time 2.17 seconds
Started Jul 07 05:09:23 PM PDT 24
Finished Jul 07 05:09:26 PM PDT 24
Peak memory 208624 kb
Host smart-3716b5e7-90f9-49aa-b38f-7877ba040ad8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263832961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2263832961
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.202861946
Short name T640
Test name
Test status
Simulation time 23538246 ps
CPU time 1.93 seconds
Started Jul 07 05:09:20 PM PDT 24
Finished Jul 07 05:09:22 PM PDT 24
Peak memory 208372 kb
Host smart-27dc3993-bd22-48f9-b64d-374d48bc7acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202861946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.202861946
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.528775700
Short name T786
Test name
Test status
Simulation time 571005149 ps
CPU time 2.6 seconds
Started Jul 07 05:09:18 PM PDT 24
Finished Jul 07 05:09:21 PM PDT 24
Peak memory 206936 kb
Host smart-82c65e6a-4017-48d6-9012-2d19ef676bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528775700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.528775700
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.811075663
Short name T580
Test name
Test status
Simulation time 530809255 ps
CPU time 5.63 seconds
Started Jul 07 05:09:25 PM PDT 24
Finished Jul 07 05:09:32 PM PDT 24
Peak memory 214236 kb
Host smart-d56a42b0-c559-4fa2-852e-a026d967b67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811075663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.811075663
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.241617012
Short name T493
Test name
Test status
Simulation time 135128966 ps
CPU time 2.27 seconds
Started Jul 07 05:09:22 PM PDT 24
Finished Jul 07 05:09:25 PM PDT 24
Peak memory 210528 kb
Host smart-21543a41-a628-4f86-8976-48752d47969d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241617012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.241617012
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2212883280
Short name T480
Test name
Test status
Simulation time 18851697 ps
CPU time 0.75 seconds
Started Jul 07 05:09:25 PM PDT 24
Finished Jul 07 05:09:27 PM PDT 24
Peak memory 205976 kb
Host smart-1c4ab66a-f994-4e71-9a10-3ec5020c1e0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212883280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2212883280
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1611694260
Short name T397
Test name
Test status
Simulation time 140140355 ps
CPU time 7.63 seconds
Started Jul 07 05:09:26 PM PDT 24
Finished Jul 07 05:09:35 PM PDT 24
Peak memory 215752 kb
Host smart-5e48fea8-4dfd-4b83-b11f-b945e43c4b61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611694260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1611694260
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1376170879
Short name T26
Test name
Test status
Simulation time 181717013 ps
CPU time 4.96 seconds
Started Jul 07 05:09:25 PM PDT 24
Finished Jul 07 05:09:31 PM PDT 24
Peak memory 214684 kb
Host smart-a32e101f-6796-4159-bf59-730ec71dcb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376170879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1376170879
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2916653655
Short name T533
Test name
Test status
Simulation time 437140597 ps
CPU time 12.18 seconds
Started Jul 07 05:09:24 PM PDT 24
Finished Jul 07 05:09:38 PM PDT 24
Peak memory 214576 kb
Host smart-7d644b47-92e4-4dfc-b783-975d461bdf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916653655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2916653655
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.693535535
Short name T102
Test name
Test status
Simulation time 241839938 ps
CPU time 4.34 seconds
Started Jul 07 05:09:26 PM PDT 24
Finished Jul 07 05:09:31 PM PDT 24
Peak memory 214284 kb
Host smart-4dc69dc7-f267-49d0-832b-dcc56449b0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693535535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.693535535
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.53657357
Short name T350
Test name
Test status
Simulation time 39420744 ps
CPU time 2.62 seconds
Started Jul 07 05:09:27 PM PDT 24
Finished Jul 07 05:09:30 PM PDT 24
Peak memory 214268 kb
Host smart-ca904539-a944-4f40-9a6d-527fbd5d5a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53657357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.53657357
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_random.2611607655
Short name T159
Test name
Test status
Simulation time 171862759 ps
CPU time 4.26 seconds
Started Jul 07 05:09:26 PM PDT 24
Finished Jul 07 05:09:31 PM PDT 24
Peak memory 208220 kb
Host smart-6c416bdc-aaa6-41cf-9c3b-650ad9b42640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611607655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2611607655
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2124954361
Short name T775
Test name
Test status
Simulation time 84898207 ps
CPU time 2.45 seconds
Started Jul 07 05:09:19 PM PDT 24
Finished Jul 07 05:09:22 PM PDT 24
Peak memory 208664 kb
Host smart-d9d34745-718e-45e7-8ff2-cc92c8f77b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124954361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2124954361
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1690642060
Short name T338
Test name
Test status
Simulation time 964843417 ps
CPU time 6.88 seconds
Started Jul 07 05:09:25 PM PDT 24
Finished Jul 07 05:09:33 PM PDT 24
Peak memory 208404 kb
Host smart-2f0c03fa-0e51-4a10-9432-408723ae0ca2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690642060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1690642060
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1040851339
Short name T474
Test name
Test status
Simulation time 63032326 ps
CPU time 3.16 seconds
Started Jul 07 05:09:21 PM PDT 24
Finished Jul 07 05:09:25 PM PDT 24
Peak memory 206956 kb
Host smart-5f84a776-660d-40e2-a9e0-9bee0cb9f013
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040851339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1040851339
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3961446348
Short name T522
Test name
Test status
Simulation time 102952178 ps
CPU time 3.77 seconds
Started Jul 07 05:09:24 PM PDT 24
Finished Jul 07 05:09:29 PM PDT 24
Peak memory 206928 kb
Host smart-ac6a5fa6-57d3-49a1-85fc-0dfe6fdc8dd4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961446348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3961446348
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.324866970
Short name T757
Test name
Test status
Simulation time 65678663 ps
CPU time 2.78 seconds
Started Jul 07 05:09:27 PM PDT 24
Finished Jul 07 05:09:30 PM PDT 24
Peak memory 218172 kb
Host smart-fa980d85-e018-4bdb-8e24-6e4dfc9129f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324866970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.324866970
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.882470284
Short name T453
Test name
Test status
Simulation time 1167523843 ps
CPU time 19.53 seconds
Started Jul 07 05:09:20 PM PDT 24
Finished Jul 07 05:09:40 PM PDT 24
Peak memory 208052 kb
Host smart-0fea6989-c4d0-462c-af77-ad6607018f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882470284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.882470284
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2563289221
Short name T166
Test name
Test status
Simulation time 1040946566 ps
CPU time 25.72 seconds
Started Jul 07 05:09:26 PM PDT 24
Finished Jul 07 05:09:53 PM PDT 24
Peak memory 216056 kb
Host smart-add7ef29-7343-4628-a486-fb9797d29d85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563289221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2563289221
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3666076412
Short name T844
Test name
Test status
Simulation time 537784465 ps
CPU time 10.1 seconds
Started Jul 07 05:09:25 PM PDT 24
Finished Jul 07 05:09:36 PM PDT 24
Peak memory 222608 kb
Host smart-03ab467e-57cd-4164-89e9-2f800bc488c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666076412 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3666076412
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3801618504
Short name T341
Test name
Test status
Simulation time 668806867 ps
CPU time 8.51 seconds
Started Jul 07 05:09:25 PM PDT 24
Finished Jul 07 05:09:35 PM PDT 24
Peak memory 214408 kb
Host smart-5e9d4df0-b260-4543-b858-73679c96cdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801618504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3801618504
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3396339765
Short name T376
Test name
Test status
Simulation time 120686485 ps
CPU time 3 seconds
Started Jul 07 05:09:27 PM PDT 24
Finished Jul 07 05:09:31 PM PDT 24
Peak memory 210680 kb
Host smart-b6b3d7cd-b2cf-44b5-8553-5f16f5d6c692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396339765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3396339765
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2747253783
Short name T421
Test name
Test status
Simulation time 17388805 ps
CPU time 0.75 seconds
Started Jul 07 05:09:30 PM PDT 24
Finished Jul 07 05:09:32 PM PDT 24
Peak memory 205992 kb
Host smart-334de8b3-244e-449c-a60b-630467fbeaf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747253783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2747253783
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1749454556
Short name T399
Test name
Test status
Simulation time 4167665711 ps
CPU time 58.76 seconds
Started Jul 07 05:09:25 PM PDT 24
Finished Jul 07 05:10:25 PM PDT 24
Peak memory 214620 kb
Host smart-d12dc302-ccfa-4da8-ac28-49749b0b9f48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1749454556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1749454556
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.498992943
Short name T551
Test name
Test status
Simulation time 80368394 ps
CPU time 3.56 seconds
Started Jul 07 05:09:29 PM PDT 24
Finished Jul 07 05:09:33 PM PDT 24
Peak memory 209064 kb
Host smart-20e268b7-f7f9-4f2a-92c2-f364e24ca7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498992943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.498992943
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1604885291
Short name T643
Test name
Test status
Simulation time 97292300 ps
CPU time 2.26 seconds
Started Jul 07 05:09:29 PM PDT 24
Finished Jul 07 05:09:31 PM PDT 24
Peak memory 214320 kb
Host smart-5c53a096-5f19-42b2-a248-ffaeef300831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604885291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1604885291
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.372549308
Short name T715
Test name
Test status
Simulation time 407262948 ps
CPU time 4.43 seconds
Started Jul 07 05:09:30 PM PDT 24
Finished Jul 07 05:09:35 PM PDT 24
Peak memory 222412 kb
Host smart-782e724d-6fd3-4781-b1d7-cdfc149f736d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372549308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.372549308
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3047957888
Short name T516
Test name
Test status
Simulation time 842874892 ps
CPU time 3.57 seconds
Started Jul 07 05:09:28 PM PDT 24
Finished Jul 07 05:09:32 PM PDT 24
Peak memory 214196 kb
Host smart-f2175146-1cdb-4c2a-ab30-f3d3e21f1264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047957888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3047957888
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2142451141
Short name T326
Test name
Test status
Simulation time 181093557 ps
CPU time 3.22 seconds
Started Jul 07 05:09:25 PM PDT 24
Finished Jul 07 05:09:30 PM PDT 24
Peak memory 207692 kb
Host smart-9324ff47-6eef-46ae-9b07-7a3ae55e5347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142451141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2142451141
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1185201684
Short name T369
Test name
Test status
Simulation time 33869236 ps
CPU time 2.51 seconds
Started Jul 07 05:09:25 PM PDT 24
Finished Jul 07 05:09:29 PM PDT 24
Peak memory 208604 kb
Host smart-238c4007-c462-411f-ac23-39a1b171977f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185201684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1185201684
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2753090915
Short name T693
Test name
Test status
Simulation time 6368003596 ps
CPU time 51.86 seconds
Started Jul 07 05:09:25 PM PDT 24
Finished Jul 07 05:10:18 PM PDT 24
Peak memory 209232 kb
Host smart-0843853e-034c-46a1-ba68-188c744e2be2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753090915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2753090915
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1059580100
Short name T578
Test name
Test status
Simulation time 155377248 ps
CPU time 4.52 seconds
Started Jul 07 05:09:25 PM PDT 24
Finished Jul 07 05:09:31 PM PDT 24
Peak memory 208788 kb
Host smart-4e51deca-3de5-4bcf-8aea-241e3386ff32
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059580100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1059580100
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3876859423
Short name T895
Test name
Test status
Simulation time 64031802 ps
CPU time 3.31 seconds
Started Jul 07 05:09:24 PM PDT 24
Finished Jul 07 05:09:29 PM PDT 24
Peak memory 208820 kb
Host smart-cea790ad-c44a-429c-8ce0-21d8713d4c7a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876859423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3876859423
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.4010709909
Short name T355
Test name
Test status
Simulation time 102063335 ps
CPU time 4.34 seconds
Started Jul 07 05:09:27 PM PDT 24
Finished Jul 07 05:09:32 PM PDT 24
Peak memory 209512 kb
Host smart-8699c100-ed3f-4648-8bcf-da5bdba3bbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010709909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.4010709909
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1350684349
Short name T733
Test name
Test status
Simulation time 180473348 ps
CPU time 2.84 seconds
Started Jul 07 05:09:26 PM PDT 24
Finished Jul 07 05:09:30 PM PDT 24
Peak memory 208364 kb
Host smart-a4833194-13b9-471c-8444-f207f03ab213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350684349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1350684349
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1242059360
Short name T216
Test name
Test status
Simulation time 1586219542 ps
CPU time 34.83 seconds
Started Jul 07 05:09:29 PM PDT 24
Finished Jul 07 05:10:04 PM PDT 24
Peak memory 216848 kb
Host smart-22c79a3c-4483-4d61-9aa9-dd9ba1898e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242059360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1242059360
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2788169625
Short name T380
Test name
Test status
Simulation time 165392529 ps
CPU time 1.19 seconds
Started Jul 07 05:09:30 PM PDT 24
Finished Jul 07 05:09:32 PM PDT 24
Peak memory 209768 kb
Host smart-0a2a6678-b3ec-4ae6-b281-27fede3785c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788169625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2788169625
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.112777669
Short name T537
Test name
Test status
Simulation time 19499599 ps
CPU time 0.89 seconds
Started Jul 07 05:06:46 PM PDT 24
Finished Jul 07 05:06:47 PM PDT 24
Peak memory 205972 kb
Host smart-ef15f945-1939-4784-8e2a-d7eb1b56318e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112777669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.112777669
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3372493454
Short name T253
Test name
Test status
Simulation time 118848152 ps
CPU time 2.43 seconds
Started Jul 07 05:06:40 PM PDT 24
Finished Jul 07 05:06:42 PM PDT 24
Peak memory 214220 kb
Host smart-6738a4ed-1028-45ec-b65b-e0f69d808bb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3372493454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3372493454
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1710179084
Short name T82
Test name
Test status
Simulation time 155690300 ps
CPU time 2.07 seconds
Started Jul 07 05:06:39 PM PDT 24
Finished Jul 07 05:06:41 PM PDT 24
Peak memory 214212 kb
Host smart-c84b205c-84ee-45e0-9bf1-b0c7df7ed403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710179084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1710179084
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2342000110
Short name T359
Test name
Test status
Simulation time 961616648 ps
CPU time 8.27 seconds
Started Jul 07 05:06:44 PM PDT 24
Finished Jul 07 05:06:52 PM PDT 24
Peak memory 209660 kb
Host smart-bd5956b3-bb32-4bc2-9e7b-77becad7b77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342000110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2342000110
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.84674353
Short name T430
Test name
Test status
Simulation time 82352053 ps
CPU time 2.76 seconds
Started Jul 07 05:06:43 PM PDT 24
Finished Jul 07 05:06:45 PM PDT 24
Peak memory 220160 kb
Host smart-559c8f9c-2041-4135-a4b3-6f2987a6e2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84674353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.84674353
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3452421786
Short name T859
Test name
Test status
Simulation time 206088795 ps
CPU time 6.72 seconds
Started Jul 07 05:06:39 PM PDT 24
Finished Jul 07 05:06:46 PM PDT 24
Peak memory 217824 kb
Host smart-a4c04b75-dcfd-49d1-ac67-18fe604762ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452421786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3452421786
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.216754369
Short name T766
Test name
Test status
Simulation time 495837864 ps
CPU time 3.36 seconds
Started Jul 07 05:06:38 PM PDT 24
Finished Jul 07 05:06:42 PM PDT 24
Peak memory 206760 kb
Host smart-4c80db72-2163-44e0-9329-4f47ff53ff03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216754369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.216754369
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3867902549
Short name T201
Test name
Test status
Simulation time 976083478 ps
CPU time 7.55 seconds
Started Jul 07 05:06:38 PM PDT 24
Finished Jul 07 05:06:46 PM PDT 24
Peak memory 208284 kb
Host smart-9628edc5-522a-43d5-ad7a-5a5a7d760341
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867902549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3867902549
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2422266454
Short name T673
Test name
Test status
Simulation time 190768100 ps
CPU time 2.71 seconds
Started Jul 07 05:06:40 PM PDT 24
Finished Jul 07 05:06:43 PM PDT 24
Peak memory 206912 kb
Host smart-75240fdc-d037-4364-aef6-18c61c26aefc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422266454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2422266454
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2864136933
Short name T600
Test name
Test status
Simulation time 435838903 ps
CPU time 5.41 seconds
Started Jul 07 05:06:40 PM PDT 24
Finished Jul 07 05:06:46 PM PDT 24
Peak memory 208508 kb
Host smart-0c7cc211-5505-4c0f-bda6-ccf03b2d2a9b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864136933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2864136933
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.4235408437
Short name T542
Test name
Test status
Simulation time 190248809 ps
CPU time 2.91 seconds
Started Jul 07 05:06:46 PM PDT 24
Finished Jul 07 05:06:49 PM PDT 24
Peak memory 215684 kb
Host smart-dddc9aac-62a5-4f53-a173-4047cedf3953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235408437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.4235408437
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.294136127
Short name T438
Test name
Test status
Simulation time 408020596 ps
CPU time 4.25 seconds
Started Jul 07 05:06:38 PM PDT 24
Finished Jul 07 05:06:43 PM PDT 24
Peak memory 208648 kb
Host smart-31c5316c-1b80-4fbd-9533-6d5d332494e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294136127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.294136127
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3594908353
Short name T235
Test name
Test status
Simulation time 1827124321 ps
CPU time 14.47 seconds
Started Jul 07 05:06:45 PM PDT 24
Finished Jul 07 05:07:00 PM PDT 24
Peak memory 216144 kb
Host smart-ab931df2-acbf-4bb0-9f9b-8a73dab08882
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594908353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3594908353
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2503745380
Short name T315
Test name
Test status
Simulation time 694162978 ps
CPU time 5.88 seconds
Started Jul 07 05:06:44 PM PDT 24
Finished Jul 07 05:06:51 PM PDT 24
Peak memory 218636 kb
Host smart-4fc1ed77-3407-4df5-ab41-190fba8bcb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503745380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2503745380
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3199862815
Short name T502
Test name
Test status
Simulation time 201209306 ps
CPU time 3.81 seconds
Started Jul 07 05:06:44 PM PDT 24
Finished Jul 07 05:06:49 PM PDT 24
Peak memory 210652 kb
Host smart-4ec372f6-8fc6-4967-80f7-298f9d96755e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199862815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3199862815
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2649848740
Short name T434
Test name
Test status
Simulation time 19743902 ps
CPU time 0.97 seconds
Started Jul 07 05:06:49 PM PDT 24
Finished Jul 07 05:06:51 PM PDT 24
Peak memory 206120 kb
Host smart-030b3373-7929-4e8d-a4d0-4903d2c7fd62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649848740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2649848740
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1114110811
Short name T400
Test name
Test status
Simulation time 174878165 ps
CPU time 9.73 seconds
Started Jul 07 05:06:52 PM PDT 24
Finished Jul 07 05:07:03 PM PDT 24
Peak memory 214888 kb
Host smart-33fa3083-489a-4d8c-8773-0a7a2e941d29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1114110811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1114110811
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1333376807
Short name T505
Test name
Test status
Simulation time 423383081 ps
CPU time 6.09 seconds
Started Jul 07 05:06:54 PM PDT 24
Finished Jul 07 05:07:00 PM PDT 24
Peak memory 219896 kb
Host smart-16ead3fc-ab34-4a45-98a1-49e7980e5d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333376807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1333376807
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1087610160
Short name T556
Test name
Test status
Simulation time 142190870 ps
CPU time 1.68 seconds
Started Jul 07 05:06:54 PM PDT 24
Finished Jul 07 05:06:56 PM PDT 24
Peak memory 208408 kb
Host smart-79cda142-d9dc-4131-9db4-c69e3be850c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087610160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1087610160
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1079220749
Short name T50
Test name
Test status
Simulation time 323255862 ps
CPU time 2.95 seconds
Started Jul 07 05:06:48 PM PDT 24
Finished Jul 07 05:06:51 PM PDT 24
Peak memory 214344 kb
Host smart-8e882bf3-fe96-4fb9-a705-ec9a813a3ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079220749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1079220749
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3462237402
Short name T209
Test name
Test status
Simulation time 108840994 ps
CPU time 4.93 seconds
Started Jul 07 05:06:49 PM PDT 24
Finished Jul 07 05:06:55 PM PDT 24
Peak memory 222420 kb
Host smart-cd010da0-c337-42f8-96c4-4c4386067069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462237402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3462237402
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.377379415
Short name T732
Test name
Test status
Simulation time 163175958 ps
CPU time 2.47 seconds
Started Jul 07 05:06:52 PM PDT 24
Finished Jul 07 05:06:54 PM PDT 24
Peak memory 222328 kb
Host smart-aa5d2aee-c845-4297-893e-782719d1a909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377379415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.377379415
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2192248294
Short name T238
Test name
Test status
Simulation time 92216738 ps
CPU time 4.04 seconds
Started Jul 07 05:06:50 PM PDT 24
Finished Jul 07 05:06:54 PM PDT 24
Peak memory 207892 kb
Host smart-e367c5f0-b46c-44d6-83e5-fb9283478cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192248294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2192248294
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.576901694
Short name T504
Test name
Test status
Simulation time 613410984 ps
CPU time 14.32 seconds
Started Jul 07 05:07:16 PM PDT 24
Finished Jul 07 05:07:30 PM PDT 24
Peak memory 207872 kb
Host smart-dd3b9887-a5ea-40e3-a919-8df44c7eb124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576901694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.576901694
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.419444922
Short name T664
Test name
Test status
Simulation time 364277666 ps
CPU time 3.69 seconds
Started Jul 07 05:06:44 PM PDT 24
Finished Jul 07 05:06:48 PM PDT 24
Peak memory 206944 kb
Host smart-5c40eb3a-5f80-4ab9-9d01-4214b2d8780b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419444922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.419444922
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1207778566
Short name T680
Test name
Test status
Simulation time 47760839 ps
CPU time 2.85 seconds
Started Jul 07 05:06:43 PM PDT 24
Finished Jul 07 05:06:46 PM PDT 24
Peak memory 208708 kb
Host smart-40fc6740-5dae-4bf2-9371-ee43958cf7ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207778566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1207778566
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.4224596722
Short name T210
Test name
Test status
Simulation time 279492385 ps
CPU time 4.43 seconds
Started Jul 07 05:06:45 PM PDT 24
Finished Jul 07 05:06:49 PM PDT 24
Peak memory 208688 kb
Host smart-e44fc2bf-1704-460e-bb7b-eac4f34c0d45
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224596722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.4224596722
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3305831942
Short name T339
Test name
Test status
Simulation time 203460625 ps
CPU time 3.04 seconds
Started Jul 07 05:06:48 PM PDT 24
Finished Jul 07 05:06:51 PM PDT 24
Peak memory 215848 kb
Host smart-8895097b-22c8-478c-a512-89a446544946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305831942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3305831942
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2511710793
Short name T494
Test name
Test status
Simulation time 1556539881 ps
CPU time 3.51 seconds
Started Jul 07 05:06:45 PM PDT 24
Finished Jul 07 05:06:49 PM PDT 24
Peak memory 208332 kb
Host smart-744d66c9-17a6-4566-ad11-9f163909a250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511710793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2511710793
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3106641079
Short name T199
Test name
Test status
Simulation time 12341100017 ps
CPU time 39.15 seconds
Started Jul 07 05:06:49 PM PDT 24
Finished Jul 07 05:07:29 PM PDT 24
Peak memory 208152 kb
Host smart-d3bf4c56-e2eb-4a5a-96d7-f105539e5ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106641079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3106641079
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1161700697
Short name T635
Test name
Test status
Simulation time 302572748 ps
CPU time 3.4 seconds
Started Jul 07 05:06:49 PM PDT 24
Finished Jul 07 05:06:52 PM PDT 24
Peak memory 209848 kb
Host smart-dcb2c4b2-153f-4296-9067-455c093b3e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161700697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1161700697
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3497404449
Short name T808
Test name
Test status
Simulation time 8280535 ps
CPU time 0.84 seconds
Started Jul 07 05:06:54 PM PDT 24
Finished Jul 07 05:06:55 PM PDT 24
Peak memory 205968 kb
Host smart-d23ec4d8-ec29-45c0-9ecc-4eacd6b9f4ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497404449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3497404449
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1901743993
Short name T386
Test name
Test status
Simulation time 188931394 ps
CPU time 2.17 seconds
Started Jul 07 05:06:47 PM PDT 24
Finished Jul 07 05:06:50 PM PDT 24
Peak memory 209580 kb
Host smart-99588e70-0c57-47af-81cd-9834f7fc0857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901743993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1901743993
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.4116533588
Short name T108
Test name
Test status
Simulation time 771209039 ps
CPU time 22.54 seconds
Started Jul 07 05:07:01 PM PDT 24
Finished Jul 07 05:07:24 PM PDT 24
Peak memory 220844 kb
Host smart-709205be-ce82-4f17-9093-57bb92df0d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116533588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.4116533588
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.4281214724
Short name T463
Test name
Test status
Simulation time 91852946 ps
CPU time 3.08 seconds
Started Jul 07 05:07:02 PM PDT 24
Finished Jul 07 05:07:06 PM PDT 24
Peak memory 214248 kb
Host smart-bbb85a18-59bd-4b05-b368-3ea0c902ce3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281214724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.4281214724
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.574261201
Short name T225
Test name
Test status
Simulation time 72880742 ps
CPU time 3.02 seconds
Started Jul 07 05:06:55 PM PDT 24
Finished Jul 07 05:06:58 PM PDT 24
Peak memory 220284 kb
Host smart-54e313d2-acf6-4d9d-bee7-0e9b164ba4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574261201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.574261201
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.597209459
Short name T842
Test name
Test status
Simulation time 4754509788 ps
CPU time 41 seconds
Started Jul 07 05:06:49 PM PDT 24
Finished Jul 07 05:07:31 PM PDT 24
Peak memory 209440 kb
Host smart-b979cdb4-65a5-4b6c-8d6e-e48a8aefec28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597209459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.597209459
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3325090648
Short name T741
Test name
Test status
Simulation time 665637604 ps
CPU time 15.68 seconds
Started Jul 07 05:06:54 PM PDT 24
Finished Jul 07 05:07:10 PM PDT 24
Peak memory 208244 kb
Host smart-3e322d5e-512a-4ddc-a410-3560fb80dc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325090648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3325090648
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.4242543189
Short name T443
Test name
Test status
Simulation time 113730009 ps
CPU time 2.9 seconds
Started Jul 07 05:06:51 PM PDT 24
Finished Jul 07 05:06:54 PM PDT 24
Peak memory 208344 kb
Host smart-c732dc59-aa1b-47aa-adeb-027aca241fa2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242543189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.4242543189
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2009867448
Short name T617
Test name
Test status
Simulation time 261517050 ps
CPU time 4.24 seconds
Started Jul 07 05:06:51 PM PDT 24
Finished Jul 07 05:06:55 PM PDT 24
Peak memory 206736 kb
Host smart-d2b1b80d-d362-48ab-ae58-e241f7e85183
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009867448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2009867448
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3148315743
Short name T344
Test name
Test status
Simulation time 55985190 ps
CPU time 2.84 seconds
Started Jul 07 05:06:50 PM PDT 24
Finished Jul 07 05:06:53 PM PDT 24
Peak memory 206832 kb
Host smart-0e35ec7c-6d04-4040-a187-f4648f8b6a71
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148315743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3148315743
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1650243781
Short name T774
Test name
Test status
Simulation time 128203631 ps
CPU time 1.83 seconds
Started Jul 07 05:07:02 PM PDT 24
Finished Jul 07 05:07:05 PM PDT 24
Peak memory 214328 kb
Host smart-685eb4ca-a1af-42ae-ad5c-adeb4cf29e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650243781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1650243781
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2820970318
Short name T853
Test name
Test status
Simulation time 52691163 ps
CPU time 2.66 seconds
Started Jul 07 05:06:52 PM PDT 24
Finished Jul 07 05:06:55 PM PDT 24
Peak memory 206860 kb
Host smart-9023108f-f0cd-4908-843c-6e4d42070d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820970318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2820970318
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.626301159
Short name T313
Test name
Test status
Simulation time 65721340 ps
CPU time 3.08 seconds
Started Jul 07 05:07:02 PM PDT 24
Finished Jul 07 05:07:06 PM PDT 24
Peak memory 208860 kb
Host smart-e9362cb1-8d2b-4792-af23-8fa162e1e578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626301159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.626301159
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.4158974051
Short name T621
Test name
Test status
Simulation time 32813210 ps
CPU time 2.32 seconds
Started Jul 07 05:06:54 PM PDT 24
Finished Jul 07 05:06:56 PM PDT 24
Peak memory 207232 kb
Host smart-f597d560-ab5e-4120-a098-5652eb1a063b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158974051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.4158974051
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2486644965
Short name T730
Test name
Test status
Simulation time 252056419 ps
CPU time 2.78 seconds
Started Jul 07 05:07:01 PM PDT 24
Finished Jul 07 05:07:04 PM PDT 24
Peak memory 210160 kb
Host smart-9bd79a11-e5b7-45bf-bf09-ba87e6595b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486644965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2486644965
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1002762712
Short name T535
Test name
Test status
Simulation time 14326286 ps
CPU time 0.97 seconds
Started Jul 07 05:07:02 PM PDT 24
Finished Jul 07 05:07:04 PM PDT 24
Peak memory 206004 kb
Host smart-a422c16b-134e-41a9-8ca5-76b59c97535a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002762712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1002762712
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.441317756
Short name T492
Test name
Test status
Simulation time 298851003 ps
CPU time 2.74 seconds
Started Jul 07 05:07:06 PM PDT 24
Finished Jul 07 05:07:09 PM PDT 24
Peak memory 210392 kb
Host smart-14d2e6c5-cbfe-40ea-ae7f-f1fa30019793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441317756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.441317756
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.153748129
Short name T638
Test name
Test status
Simulation time 306285224 ps
CPU time 11.22 seconds
Started Jul 07 05:06:53 PM PDT 24
Finished Jul 07 05:07:05 PM PDT 24
Peak memory 214304 kb
Host smart-38e2aca5-24fa-4687-a8d4-6cff7b50999f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153748129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.153748129
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3754583544
Short name T484
Test name
Test status
Simulation time 122826642 ps
CPU time 2.69 seconds
Started Jul 07 05:07:05 PM PDT 24
Finished Jul 07 05:07:09 PM PDT 24
Peak memory 214252 kb
Host smart-cc6b30e6-27a3-4931-9648-287136177e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754583544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3754583544
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.595482133
Short name T637
Test name
Test status
Simulation time 90277689 ps
CPU time 2.69 seconds
Started Jul 07 05:07:05 PM PDT 24
Finished Jul 07 05:07:08 PM PDT 24
Peak memory 214248 kb
Host smart-9cd76282-decd-4ba8-8d14-067ddbad07c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595482133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.595482133
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1726814402
Short name T222
Test name
Test status
Simulation time 324883002 ps
CPU time 4.03 seconds
Started Jul 07 05:06:53 PM PDT 24
Finished Jul 07 05:06:57 PM PDT 24
Peak memory 215088 kb
Host smart-710a0830-7c5d-4458-bfa8-2ac2b14365bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726814402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1726814402
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1500853100
Short name T526
Test name
Test status
Simulation time 5368044160 ps
CPU time 10.76 seconds
Started Jul 07 05:07:05 PM PDT 24
Finished Jul 07 05:07:17 PM PDT 24
Peak memory 208052 kb
Host smart-b83d6bce-251e-4786-bf0e-426049fa3ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500853100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1500853100
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.4090371339
Short name T582
Test name
Test status
Simulation time 34165492 ps
CPU time 2.32 seconds
Started Jul 07 05:07:03 PM PDT 24
Finished Jul 07 05:07:06 PM PDT 24
Peak memory 208512 kb
Host smart-2d1d9c22-b61d-48d4-994c-5e71568fd063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090371339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.4090371339
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.459577050
Short name T269
Test name
Test status
Simulation time 587906066 ps
CPU time 4.59 seconds
Started Jul 07 05:06:53 PM PDT 24
Finished Jul 07 05:06:58 PM PDT 24
Peak memory 208004 kb
Host smart-6e07ee9e-2abe-451e-9499-7043332bb583
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459577050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.459577050
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.619168853
Short name T452
Test name
Test status
Simulation time 2015693390 ps
CPU time 22.79 seconds
Started Jul 07 05:06:53 PM PDT 24
Finished Jul 07 05:07:16 PM PDT 24
Peak memory 208444 kb
Host smart-f6eb623d-06a5-4384-92af-e14dd3b42f24
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619168853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.619168853
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3707031115
Short name T508
Test name
Test status
Simulation time 89194308 ps
CPU time 3.86 seconds
Started Jul 07 05:06:53 PM PDT 24
Finished Jul 07 05:06:57 PM PDT 24
Peak memory 208912 kb
Host smart-5026c343-3e12-4395-9e5a-d3ef0c0b1db3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707031115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3707031115
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.4113097292
Short name T603
Test name
Test status
Simulation time 659860677 ps
CPU time 3.26 seconds
Started Jul 07 05:07:02 PM PDT 24
Finished Jul 07 05:07:05 PM PDT 24
Peak memory 208920 kb
Host smart-068e1d6b-55c3-44dd-8395-b8a233b2fcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113097292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.4113097292
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2775932941
Short name T439
Test name
Test status
Simulation time 1318920967 ps
CPU time 3.44 seconds
Started Jul 07 05:07:02 PM PDT 24
Finished Jul 07 05:07:06 PM PDT 24
Peak memory 206644 kb
Host smart-ac5f3008-56d8-4170-bf56-9a8b43180bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775932941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2775932941
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2079983652
Short name T567
Test name
Test status
Simulation time 154466650 ps
CPU time 6.15 seconds
Started Jul 07 05:06:56 PM PDT 24
Finished Jul 07 05:07:02 PM PDT 24
Peak memory 218776 kb
Host smart-7fdfdccd-084b-42ea-9d69-a02bd55b28e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079983652 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2079983652
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.714724847
Short name T282
Test name
Test status
Simulation time 504867957 ps
CPU time 6.41 seconds
Started Jul 07 05:07:02 PM PDT 24
Finished Jul 07 05:07:09 PM PDT 24
Peak memory 218520 kb
Host smart-722ebcdf-67ab-4ed3-86ab-2d65a14349fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714724847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.714724847
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1342845281
Short name T378
Test name
Test status
Simulation time 319172480 ps
CPU time 2.34 seconds
Started Jul 07 05:07:02 PM PDT 24
Finished Jul 07 05:07:05 PM PDT 24
Peak memory 210932 kb
Host smart-88b3cac1-0bc3-40d4-9ec3-f8948435345e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342845281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1342845281
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.940746282
Short name T540
Test name
Test status
Simulation time 35547635 ps
CPU time 0.92 seconds
Started Jul 07 05:07:00 PM PDT 24
Finished Jul 07 05:07:02 PM PDT 24
Peak memory 205980 kb
Host smart-33e748de-2024-43a6-a6b5-555789433d34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940746282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.940746282
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.4041999248
Short name T317
Test name
Test status
Simulation time 243878241 ps
CPU time 3.71 seconds
Started Jul 07 05:07:05 PM PDT 24
Finished Jul 07 05:07:10 PM PDT 24
Peak memory 214220 kb
Host smart-874c1f34-1d60-474e-9e35-1c25e234b288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4041999248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.4041999248
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3043079628
Short name T28
Test name
Test status
Simulation time 1040625900 ps
CPU time 3.21 seconds
Started Jul 07 05:07:05 PM PDT 24
Finished Jul 07 05:07:10 PM PDT 24
Peak memory 214324 kb
Host smart-67aa2a2e-6933-44c6-aa36-1467f41a574f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043079628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3043079628
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2972295639
Short name T539
Test name
Test status
Simulation time 396946192 ps
CPU time 4.81 seconds
Started Jul 07 05:07:03 PM PDT 24
Finished Jul 07 05:07:08 PM PDT 24
Peak memory 214408 kb
Host smart-19de1ebb-46a9-4af6-a48f-66304e4eb2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972295639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2972295639
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2842991263
Short name T107
Test name
Test status
Simulation time 223356568 ps
CPU time 8.13 seconds
Started Jul 07 05:07:03 PM PDT 24
Finished Jul 07 05:07:12 PM PDT 24
Peak memory 222480 kb
Host smart-6d17ade0-1440-4d49-80b9-7ed8ae302762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842991263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2842991263
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.454096928
Short name T340
Test name
Test status
Simulation time 730497454 ps
CPU time 4.05 seconds
Started Jul 07 05:07:03 PM PDT 24
Finished Jul 07 05:07:07 PM PDT 24
Peak memory 220996 kb
Host smart-c11905b2-745f-4c86-bfc9-d534ce320d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454096928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.454096928
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.4219776485
Short name T213
Test name
Test status
Simulation time 1013725279 ps
CPU time 12.15 seconds
Started Jul 07 05:07:01 PM PDT 24
Finished Jul 07 05:07:13 PM PDT 24
Peak memory 222460 kb
Host smart-3802b08d-d0e6-4765-94c5-7bc5e6e61911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219776485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.4219776485
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1768253186
Short name T674
Test name
Test status
Simulation time 38059659938 ps
CPU time 93.36 seconds
Started Jul 07 05:07:01 PM PDT 24
Finished Jul 07 05:08:35 PM PDT 24
Peak memory 208912 kb
Host smart-e824ac01-e18f-423e-a2bf-d9feb3f4c365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768253186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1768253186
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.416565577
Short name T789
Test name
Test status
Simulation time 84931697 ps
CPU time 4.06 seconds
Started Jul 07 05:07:01 PM PDT 24
Finished Jul 07 05:07:06 PM PDT 24
Peak memory 208748 kb
Host smart-54678491-1837-40d6-88a4-e1405f4db82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416565577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.416565577
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3748171945
Short name T595
Test name
Test status
Simulation time 84314438 ps
CPU time 1.95 seconds
Started Jul 07 05:07:03 PM PDT 24
Finished Jul 07 05:07:05 PM PDT 24
Peak memory 208748 kb
Host smart-e9ab708a-2907-4dc9-9707-5c79d047dbd4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748171945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3748171945
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1575904993
Short name T517
Test name
Test status
Simulation time 151737496 ps
CPU time 2.65 seconds
Started Jul 07 05:07:03 PM PDT 24
Finished Jul 07 05:07:06 PM PDT 24
Peak memory 207388 kb
Host smart-5f5b62c4-b9b6-4bab-bbf4-873f148f32eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575904993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1575904993
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3204674448
Short name T292
Test name
Test status
Simulation time 225132113 ps
CPU time 3.52 seconds
Started Jul 07 05:07:03 PM PDT 24
Finished Jul 07 05:07:07 PM PDT 24
Peak memory 208688 kb
Host smart-74911503-608f-45f8-bc40-f997836dfb46
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204674448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3204674448
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1712303451
Short name T604
Test name
Test status
Simulation time 54079649 ps
CPU time 2.18 seconds
Started Jul 07 05:07:02 PM PDT 24
Finished Jul 07 05:07:05 PM PDT 24
Peak memory 207512 kb
Host smart-799cf240-a1bf-476f-9c9a-9575820c5e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712303451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1712303451
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1634892705
Short name T725
Test name
Test status
Simulation time 699594236 ps
CPU time 7.37 seconds
Started Jul 07 05:07:05 PM PDT 24
Finished Jul 07 05:07:13 PM PDT 24
Peak memory 208472 kb
Host smart-7eb2da00-0684-470e-983f-3ed23a4081a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634892705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1634892705
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1931156220
Short name T220
Test name
Test status
Simulation time 3758446220 ps
CPU time 17.97 seconds
Started Jul 07 05:07:02 PM PDT 24
Finished Jul 07 05:07:20 PM PDT 24
Peak memory 220368 kb
Host smart-ef219119-31c6-48fe-87f1-f043419ff11e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931156220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1931156220
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2753590612
Short name T299
Test name
Test status
Simulation time 1284065905 ps
CPU time 8.79 seconds
Started Jul 07 05:06:56 PM PDT 24
Finished Jul 07 05:07:05 PM PDT 24
Peak memory 209324 kb
Host smart-f9378352-5e8d-4a54-be62-1fbfb11a7efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753590612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2753590612
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.375326600
Short name T860
Test name
Test status
Simulation time 31951934 ps
CPU time 1.32 seconds
Started Jul 07 05:07:05 PM PDT 24
Finished Jul 07 05:07:07 PM PDT 24
Peak memory 209432 kb
Host smart-04dc0ffa-fef2-4cf1-87d8-f64f5f3d7081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375326600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.375326600
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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