Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
55885 |
1 |
|
|
T2 |
33 |
|
T3 |
25 |
|
T4 |
15 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
32591 |
1 |
|
|
T3 |
25 |
|
T4 |
15 |
|
T14 |
85 |
auto[1] |
23294 |
1 |
|
|
T2 |
33 |
|
T5 |
33 |
|
T15 |
15 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
27816 |
1 |
|
|
T2 |
17 |
|
T3 |
1 |
|
T4 |
1 |
auto[1] |
28069 |
1 |
|
|
T2 |
16 |
|
T3 |
24 |
|
T4 |
14 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
16111 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T14 |
43 |
all_values[0] |
auto[0] |
auto[1] |
16480 |
1 |
|
|
T3 |
24 |
|
T4 |
14 |
|
T14 |
42 |
all_values[0] |
auto[1] |
auto[0] |
11705 |
1 |
|
|
T2 |
17 |
|
T5 |
17 |
|
T15 |
8 |
all_values[0] |
auto[1] |
auto[1] |
11589 |
1 |
|
|
T2 |
16 |
|
T5 |
16 |
|
T15 |
7 |