Group : keymgr_env_pkg::keymgr_env_cov::reseed_interval_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : keymgr_env_pkg::keymgr_env_cov::reseed_interval_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv



Summary for Group keymgr_env_pkg::keymgr_env_cov::reseed_interval_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 37 0 37 100.00


Variables for Group keymgr_env_pkg::keymgr_env_cov::reseed_interval_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
reseed_interval_cp 37 0 37 100.00 100 1 1 0


Summary for Variable reseed_interval_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 37 0 37 100.00


User Defined Bins for reseed_interval_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
large_values[0] 1799 1 T2 1 T3 2 T4 1
large_values[1] 20 1 T35 1 T123 1 T106 1
large_values[2] 22 1 T37 1 T144 1 T74 1
large_values[3] 14 1 T405 1 T134 1 T104 1
large_values[4] 20 1 T38 1 T74 1 T212 1
large_values[5] 14 1 T256 1 T213 1 T48 1
large_values[6] 13 1 T209 1 T249 1 T212 1
large_values[7] 18 1 T75 1 T123 1 T406 1
large_values[8] 18 1 T33 1 T52 1 T64 1
large_values[9] 12 1 T75 1 T65 1 T266 1
large_values[10] 9 1 T17 1 T248 1 T335 1
large_values[11] 18 1 T246 1 T252 1 T407 1
large_values[12] 11 1 T36 1 T50 1 T258 1
large_values[13] 9 1 T65 1 T347 1 T408 2
large_values[14] 9 1 T208 1 T409 1 T365 1
large_values[15] 13 1 T336 1 T410 1 T353 1
large_values[16] 21 1 T32 1 T411 1 T412 1
large_values[17] 18 1 T151 1 T123 1 T291 1
large_values[18] 18 1 T207 1 T162 1 T42 1
large_values[19] 22 1 T4 1 T53 1 T253 1
large_values[20] 13 1 T203 1 T65 1 T413 1
large_values[21] 16 1 T53 1 T123 1 T105 1
large_values[22] 15 1 T74 1 T206 1 T386 1
large_values[23] 10 1 T34 1 T330 1 T80 1
large_values[24] 12 1 T115 1 T60 1 T292 1
large_values[25] 21 1 T53 1 T75 1 T305 1
large_values[26] 18 1 T142 1 T64 1 T49 1
large_values[27] 15 1 T7 1 T119 1 T121 1
large_values[28] 18 1 T75 1 T135 1 T283 1
large_values[29] 18 1 T15 1 T45 1 T116 1
large_values[30] 14 1 T2 1 T73 1 T293 1
large_values[31] 12 1 T150 1 T137 1 T414 1
small_values[0] 95 1 T62 1 T74 1 T53 2
small_values[1] 92 1 T5 1 T35 1 T97 1
small_values[2] 81 1 T74 1 T40 1 T160 1
small_values[3] 81 1 T147 1 T39 1 T74 1
small_values[4] 99 1 T81 1 T74 1 T256 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%