Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4674

1

T2

8

T3

5

T14

3

auto[1]

558

1

T17

1

T47

1

T116

3

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4674

1

T2

8

T3

5

T14

3

auto[1]

558

1

T17

1

T47

1

T116

3

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4695

1

T2

4

T3

5

T14

3

auto[1]

537

1

T2

4

T17

1

T43

6

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4695

1

T2

4

T3

5

T14

3

auto[1]

537

1

T2

4

T17

1

T43

6

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	401	1			T3	1		T32	1		T45	7
auto[OpGenId]	1135	1			T3	1		T14	1		T17	4
auto[OpGenSwOut]	1153	1			T3	2		T17	1		T45	9
auto[OpGenHwOut]	2485	1			T2	8		T3	1		T14	2
auto[OpDisable]	58	1			T53	2		T59	1		T78	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	401	1			T3	1		T32	1		T45	7
auto[OpGenId]	1135	1			T3	1		T14	1		T17	4
auto[OpGenSwOut]	1153	1			T3	2		T17	1		T45	9
auto[OpGenHwOut]	2485	1			T2	8		T3	1		T14	2
auto[OpDisable]	58	1			T53	2		T59	1		T78	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4670

1

T2

8

T3

5

T14

3

auto[1]

562

1

T45

5

T97

2

T23

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4670

1

T2

8

T3

5

T14

3

auto[1]

562

1

T45

5

T97

2

T23

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4967

1

T2

8

T3

5

T14

3

auto[1]

265

1

T45

21

T128

7

T160

7

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1793	1			T2	3		T3	2		T14	1
auto[1]	676	1			T2	1		T3	1		T14	1
auto[2]	714	1			T3	1		T16	1		T43	1
auto[3]	678	1			T2	1		T17	1		T43	5
auto[4]	352	1			T2	1		T97	1		T98	1
auto[5]	339	1			T2	1		T35	1		T97	3
auto[6]	345	1			T2	1		T32	1		T45	2
auto[7]	335	1			T3	1		T14	1		T16	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1371	1			T2	3		T3	1		T14	1
clear_one[1]	676	1			T2	1		T3	1		T14	1
clear_one[2]	714	1			T3	1		T16	1		T43	1
clear_one[3]	678	1			T2	1		T17	1		T43	5
clear_none	1793	1			T2	3		T3	2		T14	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	935	1			T14	1		T16	2		T17	3
auto[StInit]	644	1			T2	1		T3	5		T14	1
auto[StCreatorRootKey]	575	1			T2	1		T14	1		T16	1
auto[StOwnerIntKey]	535	1			T2	1		T17	1		T43	1
auto[StOwnerKey]	461	1			T2	1		T17	1		T43	1
auto[StDisabled]	1826	1			T2	4		T43	4		T45	8
auto[StInvalid]	256	1			T35	2		T37	4		T38	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	935	1			T14	1		T16	2		T17	3
auto[StInit]	644	1			T2	1		T3	5		T14	1
auto[StCreatorRootKey]	575	1			T2	1		T14	1		T16	1
auto[StOwnerIntKey]	535	1			T2	1		T17	1		T43	1
auto[StOwnerKey]	461	1			T2	1		T17	1		T43	1
auto[StDisabled]	1826	1			T2	4		T43	4		T45	8
auto[StInvalid]	256	1			T35	2		T37	4		T38	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4] - auto[5]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[4] - auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StCreatorRootKey]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T244	1		T245	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	161	1			T17	2		T52	1		T115	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	153	1			T34	1		T61	1		T115	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	240	1			T14	1		T16	1		T43	2
auto[0]	auto[StInit]	auto[OpAdvance]	43	1			T32	1		T204	1		T203	1
auto[0]	auto[StInit]	auto[OpGenId]	98	1			T17	1		T144	1		T211	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	99	1			T3	2		T45	6		T128	2
auto[0]	auto[StInit]	auto[OpGenHwOut]	166	1			T2	1		T116	1		T214	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	24	1			T98	1		T151	1		T50	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	44	1			T74	1		T53	1		T64	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	56	1			T23	1		T143	1		T53	2
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	87	1			T43	1		T74	1		T210	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	17	1			T151	1		T246	1		T247	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	43	1			T74	1		T248	1		T249	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	29	1			T53	1		T150	3		T64	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	46	1			T98	1		T147	1		T250	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T45	3		T51	1		T87	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	20	1			T53	1		T251	1		T252	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	24	1			T73	1		T203	1		T64	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T2	1		T43	1		T47	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	24	1			T45	4		T75	1		T65	1
auto[0]	auto[StDisabled]	auto[OpGenId]	63	1			T45	2		T143	1		T73	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	50	1			T128	2		T212	1		T106	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	167	1			T2	1		T45	2		T97	1
auto[0]	auto[StDisabled]	auto[OpDisable]	16	1			T53	1		T59	1		T69	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	8	1			T253	1		T101	1		T254	2
auto[0]	auto[StInvalid]	auto[OpGenId]	37	1			T35	1		T37	1		T54	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T37	1		T255	1		T100	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T256	1		T257	1		T258	1
auto[1]	auto[StReset]	auto[OpGenId]	25	1			T37	1		T21	1		T123	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	23	1			T49	1		T259	2		T260	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	35	1			T116	1		T78	1		T261	1
auto[1]	auto[StInit]	auto[OpAdvance]	4	1			T3	1		T262	1		T263	1
auto[1]	auto[StInit]	auto[OpGenId]	14	1			T14	1		T79	1		T264	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	15	1			T21	1		T213	1		T123	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	12	1			T16	1		T250	1		T265	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T266	1		T154	1		T234	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T75	1		T267	1		T137	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T36	1		T64	1		T268	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T215	1		T53	1		T269	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T266	1		T270	1		T271	2
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T45	3		T123	1		T272	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T45	3		T264	1		T273	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T2	1		T116	1		T216	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T212	1		T152	1		T274	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	11	1			T144	1		T275	1		T135	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	22	1			T65	1		T137	1		T138	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T249	1		T276	1		T49	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	24	1			T150	2		T277	1		T50	1
auto[1]	auto[StDisabled]	auto[OpGenId]	37	1			T53	2		T75	1		T99	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T53	1		T150	1		T213	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	159	1			T43	1		T23	1		T214	1
auto[1]	auto[StDisabled]	auto[OpDisable]	10	1			T51	2		T234	1		T87	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	10	1			T255	1		T100	1		T278	1
auto[1]	auto[StInvalid]	auto[OpGenId]	8	1			T279	1		T278	1		T103	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T54	1		T279	1		T280	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T38	2		T281	1		T280	2
auto[2]	auto[StReset]	auto[OpGenId]	8	1			T61	1		T53	1		T282	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	17	1			T78	1		T79	1		T212	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	47	1			T16	1		T116	1		T34	1
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T283	1		T241	1		T284	1
auto[2]	auto[StInit]	auto[OpGenId]	10	1			T3	1		T207	1		T285	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	13	1			T115	1		T268	1		T85	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	18	1			T286	1		T261	1		T65	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T68	1		T287	1		T270	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T288	1		T50	1		T111	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T53	1		T289	1		T290	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T214	1		T206	1		T265	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T160	1		T266	1		T234	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	21	1			T75	1		T50	2		T259	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	19	1			T115	1		T65	1		T49	2
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	38	1			T97	1		T215	1		T128	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T291	2		T260	1		T292	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	11	1			T128	3		T160	1		T53	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T206	1		T213	1		T212	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T250	1		T150	1		T265	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	18	1			T161	1		T266	1		T111	1
auto[2]	auto[StDisabled]	auto[OpGenId]	67	1			T98	1		T53	3		T251	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	66	1			T115	1		T144	1		T128	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T43	1		T214	1		T215	1
auto[2]	auto[StDisabled]	auto[OpDisable]	11	1			T293	1		T294	1		T295	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	6	1			T278	1		T296	1		T297	1
auto[2]	auto[StInvalid]	auto[OpGenId]	7	1			T256	1		T280	1		T298	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T104	1		T255	1		T299	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T256	2		T104	1		T257	1
auto[3]	auto[StReset]	auto[OpGenId]	19	1			T38	1		T142	1		T209	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	14	1			T52	1		T58	1		T207	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	30	1			T43	1		T97	1		T116	1
auto[3]	auto[StInit]	auto[OpAdvance]	6	1			T62	1		T105	1		T300	1
auto[3]	auto[StInit]	auto[OpGenId]	14	1			T21	1		T75	1		T301	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	10	1			T38	1		T302	1		T65	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	22	1			T43	1		T97	1		T276	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T128	1		T303	1		T266	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T134	1		T50	1		T304	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T34	1		T305	1		T294	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	33	1			T2	1		T216	1		T250	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T210	1		T306	1		T307	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	20	1			T74	1		T211	1		T160	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T21	1		T53	1		T302	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T17	1		T43	1		T142	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T161	1		T212	1		T93	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	10	1			T53	1		T212	1		T266	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T161	1		T285	1		T300	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T97	1		T53	1		T216	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	19	1			T161	1		T308	3		T292	1
auto[3]	auto[StDisabled]	auto[OpGenId]	60	1			T64	1		T151	1		T275	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T64	3		T75	2		T123	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	167	1			T43	2		T116	1		T215	1
auto[3]	auto[StDisabled]	auto[OpDisable]	8	1			T53	1		T50	1		T309	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	7	1			T310	1		T311	1		T312	2
auto[3]	auto[StInvalid]	auto[OpGenId]	4	1			T313	1		T314	1		T315	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T37	1		T310	1		T316	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	17	1			T38	1		T54	1		T104	1
auto[4]	auto[StReset]	auto[OpAdvance]	1	1			T154	1		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	10	1			T115	1		T160	1		T53	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	11	1			T53	1		T229	1		T317	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	18	1			T318	1		T319	1		T122	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T320	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	4	1			T321	1		T266	1		T294	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	3	1			T22	1		T51	1		T322	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	12	1			T49	1		T122	1		T323	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T321	1		T24	1		T291	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T160	2		T247	1		T93	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T115	1		T53	1		T324	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T116	1		T74	1		T160	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T325	1		T326	1		T327	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T53	1		T328	1		T329	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T49	1		T234	1		T148	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T64	1		T330	1		T90	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T303	1		T234	1		T227	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	8	1			T53	1		T266	1		T85	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T291	1		T270	1		T331	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T115	1		T269	1		T50	2
auto[4]	auto[StDisabled]	auto[OpAdvance]	11	1			T332	1		T51	1		T306	2
auto[4]	auto[StDisabled]	auto[OpGenId]	26	1			T75	1		T212	1		T65	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T98	1		T160	1		T53	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	84	1			T2	1		T97	1		T116	1
auto[4]	auto[StDisabled]	auto[OpDisable]	1	1			T50	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpAdvance]	4	1			T258	2		T333	1		T334	1
auto[4]	auto[StInvalid]	auto[OpGenId]	4	1			T256	1		T279	1		T335	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T37	1		T54	1		T310	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T54	1		T336	1		T337	1
auto[5]	auto[StReset]	auto[OpAdvance]	1	1			T308	1		-	-		-	-
auto[5]	auto[StReset]	auto[OpGenId]	9	1			T53	2		T289	1		T338	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	7	1			T206	1		T80	1		T317	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	19	1			T97	1		T52	1		T53	1
auto[5]	auto[StInit]	auto[OpAdvance]	3	1			T241	1		T339	1		T231	1
auto[5]	auto[StInit]	auto[OpGenId]	5	1			T140	1		T234	1		T340	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	7	1			T341	1		T212	1		T152	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	10	1			T210	1		T318	1		T319	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T327	1		T342	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T7	1		T75	1		T343	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T112	1		T344	1		T345	4
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T346	1		T347	1		T220	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T217	1		T348	1		T345	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T317	1		T152	1		T227	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T287	1		T304	1		T266	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T214	1		T269	1		T286	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T139	1		T349	1		T234	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	5	1			T349	1		T350	1		T351	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T308	1		T217	1		T320	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T116	1		T286	1		T318	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	7	1			T150	1		T134	1		T154	1
auto[5]	auto[StDisabled]	auto[OpGenId]	23	1			T212	1		T121	1		T352	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	38	1			T53	1		T64	1		T246	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	75	1			T2	1		T97	2		T98	1
auto[5]	auto[StDisabled]	auto[OpDisable]	3	1			T78	1		T353	1		T89	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T257	1		T354	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	2	1			T35	1		T355	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T311	1		T356	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T278	1		T101	1		T296	1
auto[6]	auto[StReset]	auto[OpAdvance]	1	1			T357	1		-	-		-	-
auto[6]	auto[StReset]	auto[OpGenId]	14	1			T270	1		T358	1		T306	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	12	1			T302	1		T65	1		T314	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	14	1			T359	1		T360	1		T347	1
auto[6]	auto[StInit]	auto[OpAdvance]	4	1			T134	1		T139	1		T361	1
auto[6]	auto[StInit]	auto[OpGenId]	1	1			T227	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenSwOut]	5	1			T115	1		T99	1		T362	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	9	1			T330	1		T227	1		T363	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T45	2		T144	1		T301	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T203	1		T364	1		T89	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	30	1			T32	1		T97	1		T285	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T365	1		T366	1		T231	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T275	1		T285	1		T367	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T343	1		T368	1		T369	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T370	1		T70	1		T371	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T372	1		-	-		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	7	1			T75	1		T50	1		T373	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T374	1		T85	1		T329	2
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T261	1		T95	1		T375	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	11	1			T128	3		T152	2		T376	1
auto[6]	auto[StDisabled]	auto[OpGenId]	31	1			T115	1		T277	1		T212	3
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T53	1		T213	1		T275	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T2	1		T53	1		T250	1
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T289	1		T227	1		T377	1
auto[6]	auto[StInvalid]	auto[OpGenId]	5	1			T38	1		T314	1		T311	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T253	1		T313	1		T297	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T257	2		T335	1		T378	1
auto[7]	auto[StReset]	auto[OpGenId]	15	1			T212	2		T301	1		T367	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	12	1			T17	1		T268	1		T140	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	17	1			T43	1		T97	1		T53	2
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T226	1		T239	1		T231	1
auto[7]	auto[StInit]	auto[OpGenId]	6	1			T49	1		T241	1		T198	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	8	1			T160	2		T71	1		T379	2
auto[7]	auto[StInit]	auto[OpGenHwOut]	14	1			T3	1		T160	2		T380	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T374	1		T71	1		T381	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T50	1		T108	1		T231	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T204	1		T293	1		T212	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T14	1		T16	1		T370	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T50	1		T112	1		T382	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T65	1		T383	1		T384	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T206	1		T305	1		T212	2
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T341	1		T385	1		T386	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T365	1		T270	1		T382	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	6	1			T17	1		T98	1		T50	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T64	1		T387	1		T388	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	14	1			T215	1		T389	1		T246	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	11	1			T160	1		T390	1		T137	1
auto[7]	auto[StDisabled]	auto[OpGenId]	28	1			T74	1		T64	2		T275	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	22	1			T203	1		T53	1		T75	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	74	1			T214	1		T215	1		T144	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T82	1		T88	1		T384	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	2	1			T391	1		T392	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	7	1			T281	1		T296	1		T337	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T333	1		T310	1		T316	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T299	1		T393	1		T337	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1371

1

T2

3

T3

1

T14

1

clear_one[1]

auto[0]

auto[0]

auto[0]

385

1

T3

1

T14

1

T16

1

clear_one[1]

auto[0]

auto[0]

auto[1]

135

1

T215

1

T36

1

T216

1

clear_one[1]

auto[0]

auto[1]

auto[0]

117

1

T2

1

T43

1

T269

1

clear_one[1]

auto[0]

auto[1]

auto[1]

39

1

T23

1

T75

1

T249

1

clear_one[2]

auto[0]

auto[0]

auto[0]

412

1

T3

1

T16

1

T43

1

clear_one[2]

auto[0]

auto[0]

auto[1]

123

1

T97

1

T215

2

T128

1

clear_one[2]

auto[1]

auto[0]

auto[0]

122

1

T214

2

T128

3

T206

1

clear_one[2]

auto[1]

auto[0]

auto[1]

57

1

T161

2

T277

1

T91

1

clear_one[3]

auto[0]

auto[0]

auto[0]

366

1

T43

2

T97

3

T116

1

clear_one[3]

auto[0]

auto[1]

auto[0]

141

1

T2

1

T43

3

T34

1

clear_one[3]

auto[1]

auto[0]

auto[0]

123

1

T116

1

T211

1

T389

2

clear_one[3]

auto[1]

auto[1]

auto[0]

48

1

T17

1

T210

1

T53

1

clear_none

auto[0]

auto[0]

auto[0]

1307

1

T2

1

T3

2

T14

1

clear_none

auto[0]

auto[0]

auto[1]

133

1

T45

1

T97

1

T128

2

clear_none

auto[0]

auto[1]

auto[0]

122

1

T2

2

T43

2

T98

1

clear_none

auto[0]

auto[1]

auto[1]

23

1

T45

4

T53

1

T289

1

clear_none

auto[1]

auto[0]

auto[0]

128

1

T116

2

T214

1

T74

1

clear_none

auto[1]

auto[0]

auto[1]

33

1

T211

1

T75

1

T212

1

clear_none

auto[1]

auto[1]

auto[0]

28

1

T47

1

T248

1

T93

1

clear_none

auto[1]

auto[1]

auto[1]

19

1

T73

2

T210

1

T387

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1308	1			T2	3		T3	1		T14	1
clear_all	auto[1]	63	1			T45	1		T128	2		T160	5
clear_one[1]	auto[0]	640	1			T2	1		T3	1		T14	1
clear_one[1]	auto[1]	36	1			T45	5		T160	1		T150	2
clear_one[2]	auto[0]	660	1			T3	1		T16	1		T43	1
clear_one[2]	auto[1]	54	1			T128	3		T160	1		T161	1
clear_one[3]	auto[0]	637	1			T2	1		T17	1		T43	5
clear_one[3]	auto[1]	41	1			T150	2		T161	3		T151	1
clear_none	auto[0]	1722	1			T2	3		T3	2		T14	1
clear_none	auto[1]	71	1			T45	15		T128	2		T150	4