Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10833

1

T2

3

T3

9

T4

10

auto[Attestation]

7322

1

T2

5

T3

7

T4

2

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2586	1			T3	3		T4	2		T5	1
auto[Aes]	3273	1			T3	2		T4	3		T5	2
auto[Kmac]	3183	1			T2	8		T3	3		T4	2
auto[Otbn]	3310	1			T3	4		T4	2		T5	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7503	1			T2	8		T3	8		T4	2
auto[OpGenId]	5803	1			T3	4		T4	3		T5	4
auto[OpGenSwOut]	5654	1			T3	7		T4	7		T5	4
auto[OpGenHwOut]	6698	1			T2	8		T3	5		T4	2
auto[OpDisable]	121	1			T15	1		T52	1		T53	3

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10249

1

T2

8

T3

1

T4

2

auto[OpDoneFail]

15530

1

T2

8

T3

23

T4

12

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6243	1			T2	1		T3	1		T4	10
auto[StInit]	3693	1			T2	2		T3	23		T4	4
auto[StCreatorRootKey]	3017	1			T2	2		T5	2		T14	6
auto[StOwnerIntKey]	2723	1			T2	2		T5	2		T14	6
auto[StOwnerKey]	2386	1			T2	2		T5	2		T14	2
auto[StDisabled]	7717	1			T2	7		T5	7		T14	16

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	316	1			T4	1		T16	3		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	103	1			T4	1		T128	1		T21	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	73	1			T33	1		T36	1		T203	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	62	1			T14	1		T128	1		T161	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	67	1			T45	1		T204	1		T21	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	193	1			T15	1		T74	3		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	327	1			T4	2		T96	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	98	1			T3	1		T115	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	87	1			T17	1		T34	1		T204	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	71	1			T14	1		T34	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	65	1			T33	1		T21	1		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	209	1			T115	1		T74	1		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	323	1			T4	2		T14	2		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	107	1			T3	1		T33	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	93	1			T62	1		T38	1		T209	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	66	1			T53	1		T75	2		T123	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	58	1			T33	1		T23	1		T142	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	210	1			T96	1		T98	1		T210	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	315	1			T4	1		T52	1		T115	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	102	1			T3	1		T74	3		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	77	1			T17	1		T115	2		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	75	1			T98	1		T7	1		T115	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	56	1			T17	1		T21	1		T75	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	216	1			T5	1		T96	1		T98	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	66	1			T38	1		T53	5		T75	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	89	1			T3	1		T38	1		T143	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	91	1			T15	1		T147	1		T142	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	74	1			T23	1		T144	1		T205	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	57	1			T211	1		T203	1		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	203	1			T5	1		T14	1		T142	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	58	1			T53	1		T75	3		T212	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	98	1			T3	1		T21	1		T205	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	69	1			T32	1		T23	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	69	1			T5	1		T16	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	58	1			T34	1		T204	1		T203	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	217	1			T5	1		T14	2		T98	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	78	1			T53	4		T212	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	97	1			T3	1		T45	1		T98	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	76	1			T33	1		T206	1		T64	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	67	1			T96	1		T36	1		T203	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	54	1			T23	1		T74	2		T213	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	193	1			T98	1		T23	1		T142	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	62	1			T53	1		T212	1		T65	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	112	1			T3	1		T38	1		T142	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	75	1			T61	2		T52	1		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	77	1			T47	1		T204	1		T143	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	51	1			T33	1		T47	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	194	1			T96	2		T115	2		T142	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	270	1			T16	2		T17	2		T34	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	76	1			T3	1		T17	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	74	1			T14	1		T34	1		T204	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	53	1			T147	1		T7	1		T204	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	55	1			T17	1		T45	1		T115	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	200	1			T14	1		T142	1		T143	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	432	1			T4	1		T16	1		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	102	1			T23	1		T39	1		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	96	1			T116	1		T214	1		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	117	1			T16	2		T17	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	96	1			T17	1		T33	1		T98	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	291	1			T14	1		T116	2		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	392	1			T14	1		T16	1		T43	8
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	111	1			T43	1		T36	1		T115	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	87	1			T32	1		T43	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	85	1			T16	1		T33	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	96	1			T43	1		T47	1		T206	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	261	1			T2	3		T43	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	456	1			T14	1		T16	1		T97	10
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	115	1			T3	2		T15	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	111	1			T14	1		T33	1		T97	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	94	1			T14	1		T34	1		T147	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	83	1			T17	1		T97	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	305	1			T97	2		T23	2		T215	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	71	1			T53	7		T75	3		T65	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	88	1			T3	1		T16	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	72	1			T14	1		T32	1		T61	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	54	1			T98	1		T128	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	37	1			T23	1		T210	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	142	1			T14	1		T210	1		T53	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	57	1			T53	4		T212	1		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	117	1			T116	1		T147	1		T214	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	99	1			T14	1		T32	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	95	1			T16	1		T34	1		T147	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	86	1			T47	2		T214	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	259	1			T14	1		T98	1		T116	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	46	1			T53	8		T65	1		T135	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	119	1			T2	1		T3	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	107	1			T2	1		T33	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	93	1			T2	1		T17	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	82	1			T2	1		T17	1		T98	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	282	1			T2	1		T43	3		T74	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	51	1			T53	2		T123	1		T212	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	123	1			T4	1		T97	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	111	1			T16	1		T215	1		T209	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	86	1			T97	1		T53	1		T216	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	75	1			T142	1		T74	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	288	1			T45	1		T97	2		T215	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	183	1			T14	1		T45	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	631	1			T4	2		T15	1		T16	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	203	1			T14	1		T17	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	654	1			T3	1		T4	2		T96	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	200	1			T33	1		T23	1		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	657	1			T3	1		T4	2		T14	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	184	1			T17	2		T98	1		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	657	1			T3	1		T4	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	204	1			T15	1		T147	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	376	1			T3	1		T5	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	176	1			T5	1		T16	1		T32	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	393	1			T3	1		T5	1		T14	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	181	1			T96	1		T33	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	384	1			T3	1		T45	1		T98	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	184	1			T33	1		T47	2		T61	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	387	1			T3	1		T96	2		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	158	1			T14	1		T17	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	570	1			T3	1		T14	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	292	1			T16	2		T17	2		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	842	1			T4	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	247	1			T16	1		T32	1		T43	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	785	1			T2	3		T14	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	273	1			T14	1		T17	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	891	1			T3	2		T14	2		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	152	1			T14	1		T32	1		T98	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	312	1			T3	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	265	1			T14	1		T16	1		T32	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	448	1			T14	1		T98	1		T116	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	270	1			T2	3		T17	2		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	459	1			T2	2		T3	1		T43	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	260	1			T16	1		T97	1		T215	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	474	1			T4	1		T45	1		T97	3