Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31666

1

T2

20

T3

28

T4

15

auto[1]

307

1

T45

17

T128

6

T160

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31676	1			T2	20		T3	28		T4	15
auto[134217728:268435455]	7	1			T151	1		T154	1		T415	1
auto[268435456:402653183]	5	1			T45	1		T379	1		T416	1
auto[402653184:536870911]	7	1			T45	1		T308	1		T403	1
auto[536870912:671088639]	9	1			T93	1		T379	1		T366	1
auto[671088640:805306367]	5	1			T417	1		T418	1		T403	1
auto[805306368:939524095]	14	1			T45	1		T160	1		T161	1
auto[939524096:1073741823]	8	1			T128	1		T400	1		T307	1
auto[1073741824:1207959551]	6	1			T128	1		T366	1		T419	1
auto[1207959552:1342177279]	9	1			T128	2		T93	1		T416	2
auto[1342177280:1476395007]	14	1			T93	1		T291	1		T349	2
auto[1476395008:1610612735]	7	1			T150	1		T244	1		T403	1
auto[1610612736:1744830463]	11	1			T45	1		T366	1		T400	1
auto[1744830464:1879048191]	6	1			T45	1		T161	1		T379	1
auto[1879048192:2013265919]	14	1			T93	1		T379	1		T244	1
auto[2013265920:2147483647]	9	1			T45	1		T379	1		T349	1
auto[2147483648:2281701375]	12	1			T45	2		T160	1		T150	1
auto[2281701376:2415919103]	12	1			T45	3		T244	1		T152	1
auto[2415919104:2550136831]	12	1			T45	1		T160	1		T151	1
auto[2550136832:2684354559]	15	1			T45	1		T128	2		T291	1
auto[2684354560:2818572287]	6	1			T45	1		T160	2		T308	1
auto[2818572288:2952790015]	9	1			T45	1		T150	1		T379	1
auto[2952790016:3087007743]	12	1			T244	1		T152	1		T416	1
auto[3087007744:3221225471]	9	1			T308	1		T349	1		T152	1
auto[3221225472:3355443199]	9	1			T45	1		T93	1		T379	3
auto[3355443200:3489660927]	14	1			T150	1		T379	1		T244	1
auto[3489660928:3623878655]	6	1			T150	1		T93	1		T416	1
auto[3623878656:3758096383]	9	1			T291	1		T416	1		T417	1
auto[3758096384:3892314111]	6	1			T45	1		T152	1		T404	1
auto[3892314112:4026531839]	7	1			T150	1		T379	1		T404	1
auto[4026531840:4160749567]	14	1			T308	2		T291	2		T244	1
auto[4160749568:4294967295]	14	1			T150	1		T161	1		T291	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31666	1			T2	20		T3	28		T4	15
auto[0:134217727]	auto[1]	10	1			T150	1		T349	1		T154	1
auto[134217728:268435455]	auto[1]	7	1			T151	1		T154	1		T415	1
auto[268435456:402653183]	auto[1]	5	1			T45	1		T379	1		T416	1
auto[402653184:536870911]	auto[1]	7	1			T45	1		T308	1		T403	1
auto[536870912:671088639]	auto[1]	9	1			T93	1		T379	1		T366	1
auto[671088640:805306367]	auto[1]	5	1			T417	1		T418	1		T403	1
auto[805306368:939524095]	auto[1]	14	1			T45	1		T160	1		T161	1
auto[939524096:1073741823]	auto[1]	8	1			T128	1		T400	1		T307	1
auto[1073741824:1207959551]	auto[1]	6	1			T128	1		T366	1		T419	1
auto[1207959552:1342177279]	auto[1]	9	1			T128	2		T93	1		T416	2
auto[1342177280:1476395007]	auto[1]	14	1			T93	1		T291	1		T349	2
auto[1476395008:1610612735]	auto[1]	7	1			T150	1		T244	1		T403	1
auto[1610612736:1744830463]	auto[1]	11	1			T45	1		T366	1		T400	1
auto[1744830464:1879048191]	auto[1]	6	1			T45	1		T161	1		T379	1
auto[1879048192:2013265919]	auto[1]	14	1			T93	1		T379	1		T244	1
auto[2013265920:2147483647]	auto[1]	9	1			T45	1		T379	1		T349	1
auto[2147483648:2281701375]	auto[1]	12	1			T45	2		T160	1		T150	1
auto[2281701376:2415919103]	auto[1]	12	1			T45	3		T244	1		T152	1
auto[2415919104:2550136831]	auto[1]	12	1			T45	1		T160	1		T151	1
auto[2550136832:2684354559]	auto[1]	15	1			T45	1		T128	2		T291	1
auto[2684354560:2818572287]	auto[1]	6	1			T45	1		T160	2		T308	1
auto[2818572288:2952790015]	auto[1]	9	1			T45	1		T150	1		T379	1
auto[2952790016:3087007743]	auto[1]	12	1			T244	1		T152	1		T416	1
auto[3087007744:3221225471]	auto[1]	9	1			T308	1		T349	1		T152	1
auto[3221225472:3355443199]	auto[1]	9	1			T45	1		T93	1		T379	3
auto[3355443200:3489660927]	auto[1]	14	1			T150	1		T379	1		T244	1
auto[3489660928:3623878655]	auto[1]	6	1			T150	1		T93	1		T416	1
auto[3623878656:3758096383]	auto[1]	9	1			T291	1		T416	1		T417	1
auto[3758096384:3892314111]	auto[1]	6	1			T45	1		T152	1		T404	1
auto[3892314112:4026531839]	auto[1]	7	1			T150	1		T379	1		T404	1
auto[4026531840:4160749567]	auto[1]	14	1			T308	2		T291	2		T244	1
auto[4160749568:4294967295]	auto[1]	14	1			T150	1		T161	1		T291	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1625

1

T3

1

T4

4

T14

2

auto[1]

1652

1

T3

1

T4

2

T14

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T3	1		T4	1		T14	1
auto[134217728:268435455]	108	1			T37	1		T58	1		T206	1
auto[268435456:402653183]	99	1			T14	1		T6	1		T36	1
auto[402653184:536870911]	103	1			T4	1		T17	1		T34	1
auto[536870912:671088639]	101	1			T61	1		T52	1		T36	1
auto[671088640:805306367]	89	1			T45	1		T98	3		T74	1
auto[805306368:939524095]	93	1			T61	2		T63	1		T21	1
auto[939524096:1073741823]	96	1			T4	1		T6	1		T32	1
auto[1073741824:1207959551]	113	1			T45	1		T74	1		T210	1
auto[1207959552:1342177279]	108	1			T16	1		T204	1		T38	1
auto[1342177280:1476395007]	111	1			T35	1		T34	1		T61	1
auto[1476395008:1610612735]	89	1			T14	1		T52	2		T209	1
auto[1610612736:1744830463]	106	1			T16	1		T17	2		T61	1
auto[1744830464:1879048191]	93	1			T36	1		T63	1		T74	1
auto[1879048192:2013265919]	99	1			T142	1		T64	1		T161	1
auto[2013265920:2147483647]	120	1			T6	1		T45	1		T37	2
auto[2147483648:2281701375]	100	1			T32	1		T73	1		T53	1
auto[2281701376:2415919103]	105	1			T142	1		T73	1		T150	1
auto[2415919104:2550136831]	94	1			T204	1		T21	1		T248	1
auto[2550136832:2684354559]	92	1			T14	1		T34	1		T37	1
auto[2684354560:2818572287]	99	1			T15	1		T35	1		T147	1
auto[2818572288:2952790015]	104	1			T3	1		T4	1		T34	1
auto[2952790016:3087007743]	107	1			T35	1		T23	1		T62	1
auto[3087007744:3221225471]	106	1			T6	1		T204	1		T128	1
auto[3221225472:3355443199]	108	1			T45	1		T7	1		T211	1
auto[3355443200:3489660927]	122	1			T4	1		T14	1		T7	1
auto[3489660928:3623878655]	107	1			T45	1		T47	1		T37	1
auto[3623878656:3758096383]	97	1			T38	1		T73	1		T40	1
auto[3758096384:3892314111]	103	1			T204	1		T38	1		T63	1
auto[3892314112:4026531839]	85	1			T35	1		T34	1		T62	1
auto[4026531840:4160749567]	101	1			T4	1		T15	1		T74	1
auto[4160749568:4294967295]	114	1			T16	1		T45	1		T62	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T4	1		T21	1		T75	1
auto[0:134217727]	auto[1]	57	1			T3	1		T14	1		T47	1
auto[134217728:268435455]	auto[0]	48	1			T37	1		T58	1		T75	1
auto[134217728:268435455]	auto[1]	60	1			T206	1		T53	1		T123	1
auto[268435456:402653183]	auto[0]	44	1			T6	1		T37	2		T142	1
auto[268435456:402653183]	auto[1]	55	1			T14	1		T36	1		T37	1
auto[402653184:536870911]	auto[0]	52	1			T34	1		T209	1		T63	1
auto[402653184:536870911]	auto[1]	51	1			T4	1		T17	1		T37	1
auto[536870912:671088639]	auto[0]	44	1			T52	1		T62	1		T58	2
auto[536870912:671088639]	auto[1]	57	1			T61	1		T36	1		T21	1
auto[671088640:805306367]	auto[0]	43	1			T53	1		T48	1		T49	1
auto[671088640:805306367]	auto[1]	46	1			T45	1		T98	3		T74	1
auto[805306368:939524095]	auto[0]	52	1			T61	2		T21	1		T277	1
auto[805306368:939524095]	auto[1]	41	1			T63	1		T246	1		T321	1
auto[939524096:1073741823]	auto[0]	46	1			T115	1		T209	1		T99	1
auto[939524096:1073741823]	auto[1]	50	1			T4	1		T6	1		T32	1
auto[1073741824:1207959551]	auto[0]	58	1			T45	1		T160	1		T75	1
auto[1073741824:1207959551]	auto[1]	55	1			T74	1		T210	1		T211	1
auto[1207959552:1342177279]	auto[0]	56	1			T16	1		T204	1		T38	1
auto[1207959552:1342177279]	auto[1]	52	1			T58	1		T75	1		T246	1
auto[1342177280:1476395007]	auto[0]	57	1			T34	1		T62	1		T64	3
auto[1342177280:1476395007]	auto[1]	54	1			T35	1		T61	1		T115	1
auto[1476395008:1610612735]	auto[0]	44	1			T14	1		T52	1		T74	1
auto[1476395008:1610612735]	auto[1]	45	1			T52	1		T209	1		T203	1
auto[1610612736:1744830463]	auto[0]	50	1			T16	1		T17	1		T38	1
auto[1610612736:1744830463]	auto[1]	56	1			T17	1		T61	1		T7	1
auto[1744830464:1879048191]	auto[0]	42	1			T210	1		T253	1		T48	1
auto[1744830464:1879048191]	auto[1]	51	1			T36	1		T63	1		T74	1
auto[1879048192:2013265919]	auto[0]	47	1			T142	1		T64	1		T161	1
auto[1879048192:2013265919]	auto[1]	52	1			T275	1		T246	1		T212	3
auto[2013265920:2147483647]	auto[0]	56	1			T6	1		T45	1		T37	2
auto[2013265920:2147483647]	auto[1]	64	1			T203	1		T206	1		T53	1
auto[2147483648:2281701375]	auto[0]	50	1			T32	1		T134	1		T119	1
auto[2147483648:2281701375]	auto[1]	50	1			T73	1		T53	1		T64	2
auto[2281701376:2415919103]	auto[0]	48	1			T142	1		T73	1		T253	1
auto[2281701376:2415919103]	auto[1]	57	1			T150	1		T213	2		T212	3
auto[2415919104:2550136831]	auto[0]	50	1			T204	1		T21	1		T64	1
auto[2415919104:2550136831]	auto[1]	44	1			T248	1		T405	1		T302	1
auto[2550136832:2684354559]	auto[0]	41	1			T34	1		T37	1		T21	1
auto[2550136832:2684354559]	auto[1]	51	1			T14	1		T74	1		T64	1
auto[2684354560:2818572287]	auto[0]	55	1			T35	1		T147	1		T21	1
auto[2684354560:2818572287]	auto[1]	44	1			T15	1		T7	1		T115	1
auto[2818572288:2952790015]	auto[0]	56	1			T3	1		T4	1		T34	1
auto[2818572288:2952790015]	auto[1]	48	1			T204	1		T211	1		T58	1
auto[2952790016:3087007743]	auto[0]	56	1			T35	1		T62	1		T99	1
auto[2952790016:3087007743]	auto[1]	51	1			T23	1		T203	1		T420	1
auto[3087007744:3221225471]	auto[0]	55	1			T6	1		T128	1		T302	1
auto[3087007744:3221225471]	auto[1]	51	1			T204	1		T53	1		T64	1
auto[3221225472:3355443199]	auto[0]	56	1			T45	1		T421	1		T212	1
auto[3221225472:3355443199]	auto[1]	52	1			T7	1		T211	1		T53	1
auto[3355443200:3489660927]	auto[0]	65	1			T4	1		T14	1		T7	1
auto[3355443200:3489660927]	auto[1]	57	1			T128	1		T210	1		T321	1
auto[3489660928:3623878655]	auto[0]	56	1			T45	1		T37	1		T142	1
auto[3489660928:3623878655]	auto[1]	51	1			T47	1		T74	1		T210	1
auto[3623878656:3758096383]	auto[0]	43	1			T38	1		T40	1		T160	1
auto[3623878656:3758096383]	auto[1]	54	1			T73	1		T75	1		T151	1
auto[3758096384:3892314111]	auto[0]	52	1			T38	1		T63	1		T161	1
auto[3758096384:3892314111]	auto[1]	51	1			T204	1		T151	1		T275	2
auto[3892314112:4026531839]	auto[0]	42	1			T35	1		T62	1		T38	1
auto[3892314112:4026531839]	auto[1]	43	1			T34	1		T63	1		T74	1
auto[4026531840:4160749567]	auto[0]	47	1			T4	1		T285	1		T212	1
auto[4026531840:4160749567]	auto[1]	54	1			T15	1		T74	1		T206	1
auto[4160749568:4294967295]	auto[0]	66	1			T62	2		T73	1		T21	1
auto[4160749568:4294967295]	auto[1]	48	1			T16	1		T45	1		T73	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1593

1

T3

1

T4

3

T14

1

auto[1]

1685

1

T3

1

T4

3

T14

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T14	1		T7	1		T37	2
auto[134217728:268435455]	116	1			T36	1		T74	1		T53	2
auto[268435456:402653183]	93	1			T3	1		T4	1		T35	1
auto[402653184:536870911]	101	1			T45	1		T7	1		T115	1
auto[536870912:671088639]	96	1			T4	1		T17	1		T35	1
auto[671088640:805306367]	106	1			T17	1		T98	1		T142	1
auto[805306368:939524095]	116	1			T32	1		T62	2		T38	1
auto[939524096:1073741823]	111	1			T17	1		T45	1		T52	1
auto[1073741824:1207959551]	108	1			T37	1		T62	1		T74	1
auto[1207959552:1342177279]	111	1			T4	1		T14	1		T34	1
auto[1342177280:1476395007]	106	1			T15	1		T204	2		T37	1
auto[1476395008:1610612735]	97	1			T35	1		T61	1		T62	1
auto[1610612736:1744830463]	107	1			T61	1		T115	1		T38	1
auto[1744830464:1879048191]	105	1			T34	1		T36	1		T128	1
auto[1879048192:2013265919]	99	1			T45	1		T61	1		T37	1
auto[2013265920:2147483647]	82	1			T3	1		T7	1		T37	1
auto[2147483648:2281701375]	109	1			T45	1		T204	1		T74	1
auto[2281701376:2415919103]	94	1			T4	1		T34	1		T147	1
auto[2415919104:2550136831]	90	1			T4	1		T14	1		T16	1
auto[2550136832:2684354559]	105	1			T15	1		T45	1		T62	1
auto[2684354560:2818572287]	98	1			T34	1		T37	1		T209	1
auto[2818572288:2952790015]	103	1			T14	1		T6	1		T115	1
auto[2952790016:3087007743]	102	1			T16	1		T203	1		T75	1
auto[3087007744:3221225471]	121	1			T61	1		T23	1		T128	1
auto[3221225472:3355443199]	100	1			T6	1		T98	1		T61	1
auto[3355443200:3489660927]	97	1			T4	1		T14	1		T38	1
auto[3489660928:3623878655]	98	1			T47	1		T37	1		T62	1
auto[3623878656:3758096383]	102	1			T16	1		T52	1		T211	1
auto[3758096384:3892314111]	102	1			T6	1		T35	1		T7	1
auto[3892314112:4026531839]	111	1			T34	1		T73	1		T21	1
auto[4026531840:4160749567]	89	1			T6	1		T32	1		T38	1
auto[4160749568:4294967295]	91	1			T204	1		T123	1		T277	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T14	1		T37	2		T62	3
auto[0:134217727]	auto[1]	59	1			T7	1		T211	1		T64	1
auto[134217728:268435455]	auto[0]	50	1			T53	1		T75	1		T249	1
auto[134217728:268435455]	auto[1]	66	1			T36	1		T74	1		T53	1
auto[268435456:402653183]	auto[0]	44	1			T35	1		T142	1		T21	1
auto[268435456:402653183]	auto[1]	49	1			T3	1		T4	1		T47	1
auto[402653184:536870911]	auto[0]	48	1			T45	1		T7	1		T63	1
auto[402653184:536870911]	auto[1]	53	1			T115	1		T38	1		T128	1
auto[536870912:671088639]	auto[0]	36	1			T4	1		T37	1		T212	1
auto[536870912:671088639]	auto[1]	60	1			T17	1		T35	1		T204	1
auto[671088640:805306367]	auto[0]	48	1			T142	1		T21	1		T79	1
auto[671088640:805306367]	auto[1]	58	1			T17	1		T98	1		T74	1
auto[805306368:939524095]	auto[0]	43	1			T62	2		T142	1		T160	1
auto[805306368:939524095]	auto[1]	73	1			T32	1		T38	1		T73	1
auto[939524096:1073741823]	auto[0]	59	1			T45	1		T52	1		T37	1
auto[939524096:1073741823]	auto[1]	52	1			T17	1		T36	1		T37	1
auto[1073741824:1207959551]	auto[0]	54	1			T62	1		T203	1		T53	1
auto[1073741824:1207959551]	auto[1]	54	1			T37	1		T74	1		T210	1
auto[1207959552:1342177279]	auto[0]	65	1			T4	1		T34	1		T142	1
auto[1207959552:1342177279]	auto[1]	46	1			T14	1		T74	1		T203	1
auto[1342177280:1476395007]	auto[0]	57	1			T15	1		T204	2		T37	1
auto[1342177280:1476395007]	auto[1]	49	1			T63	1		T21	1		T69	1
auto[1476395008:1610612735]	auto[0]	53	1			T35	1		T62	1		T53	1
auto[1476395008:1610612735]	auto[1]	44	1			T61	1		T74	1		T210	1
auto[1610612736:1744830463]	auto[0]	63	1			T61	1		T115	1		T38	1
auto[1610612736:1744830463]	auto[1]	44	1			T63	2		T211	1		T161	1
auto[1744830464:1879048191]	auto[0]	46	1			T34	1		T36	1		T128	1
auto[1744830464:1879048191]	auto[1]	59	1			T74	1		T211	1		T302	1
auto[1879048192:2013265919]	auto[0]	50	1			T45	1		T37	1		T209	1
auto[1879048192:2013265919]	auto[1]	49	1			T61	1		T54	1		T405	1
auto[2013265920:2147483647]	auto[0]	37	1			T3	1		T37	1		T70	1
auto[2013265920:2147483647]	auto[1]	45	1			T7	1		T210	1		T422	1
auto[2147483648:2281701375]	auto[0]	49	1			T45	1		T151	1		T49	1
auto[2147483648:2281701375]	auto[1]	60	1			T204	1		T74	1		T40	1
auto[2281701376:2415919103]	auto[0]	54	1			T34	1		T147	1		T63	1
auto[2281701376:2415919103]	auto[1]	40	1			T4	1		T248	1		T65	1
auto[2415919104:2550136831]	auto[0]	38	1			T4	1		T209	1		T74	1
auto[2415919104:2550136831]	auto[1]	52	1			T14	1		T16	1		T45	1
auto[2550136832:2684354559]	auto[0]	45	1			T15	1		T62	1		T75	1
auto[2550136832:2684354559]	auto[1]	60	1			T45	1		T64	2		T246	1
auto[2684354560:2818572287]	auto[0]	43	1			T34	1		T37	1		T21	1
auto[2684354560:2818572287]	auto[1]	55	1			T209	1		T206	1		T75	1
auto[2818572288:2952790015]	auto[0]	54	1			T6	1		T38	1		T75	1
auto[2818572288:2952790015]	auto[1]	49	1			T14	1		T115	1		T206	1
auto[2952790016:3087007743]	auto[0]	56	1			T16	1		T75	1		T48	1
auto[2952790016:3087007743]	auto[1]	46	1			T203	1		T341	1		T212	1
auto[3087007744:3221225471]	auto[0]	64	1			T160	1		T64	1		T65	1
auto[3087007744:3221225471]	auto[1]	57	1			T61	1		T23	1		T128	1
auto[3221225472:3355443199]	auto[0]	39	1			T6	1		T61	1		T151	1
auto[3221225472:3355443199]	auto[1]	61	1			T98	1		T74	1		T160	1
auto[3355443200:3489660927]	auto[0]	55	1			T247	1		T387	1		T68	1
auto[3355443200:3489660927]	auto[1]	42	1			T4	1		T14	1		T38	1
auto[3489660928:3623878655]	auto[0]	50	1			T37	1		T62	1		T209	1
auto[3489660928:3623878655]	auto[1]	48	1			T47	1		T123	1		T275	1
auto[3623878656:3758096383]	auto[0]	46	1			T16	1		T64	1		T212	2
auto[3623878656:3758096383]	auto[1]	56	1			T52	1		T211	1		T248	1
auto[3758096384:3892314111]	auto[0]	53	1			T6	1		T35	1		T209	1
auto[3758096384:3892314111]	auto[1]	49	1			T7	1		T73	1		T252	1
auto[3892314112:4026531839]	auto[0]	52	1			T34	1		T73	1		T210	1
auto[3892314112:4026531839]	auto[1]	59	1			T21	1		T203	1		T405	1
auto[4026531840:4160749567]	auto[0]	48	1			T32	1		T38	1		T63	1
auto[4026531840:4160749567]	auto[1]	41	1			T6	1		T63	1		T74	1
auto[4160749568:4294967295]	auto[0]	41	1			T277	1		T212	1		T308	1
auto[4160749568:4294967295]	auto[1]	50	1			T204	1		T123	1		T212	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1581

1

T3

1

T4

4

T14

2

auto[1]

1695

1

T3

1

T4

2

T14

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	118	1			T3	1		T4	1		T36	1
auto[134217728:268435455]	97	1			T16	1		T98	1		T74	2
auto[268435456:402653183]	87	1			T62	1		T53	1		T64	1
auto[402653184:536870911]	118	1			T14	1		T61	1		T63	1
auto[536870912:671088639]	113	1			T14	1		T16	1		T7	1
auto[671088640:805306367]	93	1			T74	1		T160	1		T248	1
auto[805306368:939524095]	106	1			T14	1		T36	1		T37	2
auto[939524096:1073741823]	125	1			T4	1		T6	2		T45	1
auto[1073741824:1207959551]	102	1			T4	1		T14	1		T17	1
auto[1207959552:1342177279]	94	1			T45	1		T54	1		T206	1
auto[1342177280:1476395007]	116	1			T14	1		T98	1		T34	1
auto[1476395008:1610612735]	113	1			T4	1		T35	1		T62	1
auto[1610612736:1744830463]	104	1			T16	1		T32	1		T147	1
auto[1744830464:1879048191]	108	1			T4	1		T61	1		T23	1
auto[1879048192:2013265919]	95	1			T45	1		T47	1		T52	1
auto[2013265920:2147483647]	101	1			T61	1		T204	1		T62	1
auto[2147483648:2281701375]	104	1			T6	1		T45	1		T34	1
auto[2281701376:2415919103]	102	1			T142	1		T209	1		T63	1
auto[2415919104:2550136831]	112	1			T6	1		T62	1		T73	1
auto[2550136832:2684354559]	101	1			T61	1		T142	1		T209	1
auto[2684354560:2818572287]	104	1			T15	2		T47	1		T34	1
auto[2818572288:2952790015]	98	1			T17	1		T7	1		T115	1
auto[2952790016:3087007743]	110	1			T21	1		T422	1		T75	1
auto[3087007744:3221225471]	100	1			T61	1		T7	1		T37	1
auto[3221225472:3355443199]	107	1			T21	1		T53	1		T64	2
auto[3355443200:3489660927]	80	1			T36	1		T115	1		T62	1
auto[3489660928:3623878655]	105	1			T32	1		T37	1		T38	1
auto[3623878656:3758096383]	81	1			T35	1		T98	1		T34	1
auto[3758096384:3892314111]	92	1			T4	1		T35	1		T38	1
auto[3892314112:4026531839]	97	1			T3	1		T52	1		T21	1
auto[4026531840:4160749567]	105	1			T17	1		T35	1		T62	1
auto[4160749568:4294967295]	88	1			T37	1		T210	1		T211	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	59	1			T3	1		T160	1		T64	1
auto[0:134217727]	auto[1]	59	1			T4	1		T36	1		T74	1
auto[134217728:268435455]	auto[0]	45	1			T16	1		T53	1		T119	1
auto[134217728:268435455]	auto[1]	52	1			T98	1		T74	2		T203	1
auto[268435456:402653183]	auto[0]	55	1			T62	1		T123	1		T79	1
auto[268435456:402653183]	auto[1]	32	1			T53	1		T64	1		T75	1
auto[402653184:536870911]	auto[0]	56	1			T63	1		T21	1		T74	1
auto[402653184:536870911]	auto[1]	62	1			T14	1		T61	1		T210	1
auto[536870912:671088639]	auto[0]	57	1			T37	1		T128	1		T53	1
auto[536870912:671088639]	auto[1]	56	1			T14	1		T16	1		T7	1
auto[671088640:805306367]	auto[0]	41	1			T160	1		T104	1		T22	1
auto[671088640:805306367]	auto[1]	52	1			T74	1		T248	1		T134	1
auto[805306368:939524095]	auto[0]	54	1			T14	1		T36	1		T37	1
auto[805306368:939524095]	auto[1]	52	1			T37	1		T63	1		T211	1
auto[939524096:1073741823]	auto[0]	68	1			T4	1		T6	2		T45	1
auto[939524096:1073741823]	auto[1]	57	1			T37	1		T73	1		T74	1
auto[1073741824:1207959551]	auto[0]	46	1			T45	1		T34	1		T37	1
auto[1073741824:1207959551]	auto[1]	56	1			T4	1		T14	1		T17	1
auto[1207959552:1342177279]	auto[0]	51	1			T45	1		T64	1		T253	1
auto[1207959552:1342177279]	auto[1]	43	1			T54	1		T206	1		T53	1
auto[1342177280:1476395007]	auto[0]	50	1			T14	1		T34	1		T21	1
auto[1342177280:1476395007]	auto[1]	66	1			T98	1		T128	2		T151	1
auto[1476395008:1610612735]	auto[0]	53	1			T4	1		T35	1		T62	1
auto[1476395008:1610612735]	auto[1]	60	1			T203	1		T53	1		T64	1
auto[1610612736:1744830463]	auto[0]	47	1			T16	1		T32	1		T38	1
auto[1610612736:1744830463]	auto[1]	57	1			T147	1		T38	1		T142	1
auto[1744830464:1879048191]	auto[0]	45	1			T4	1		T58	1		T422	1
auto[1744830464:1879048191]	auto[1]	63	1			T61	1		T23	1		T204	1
auto[1879048192:2013265919]	auto[0]	46	1			T52	1		T62	1		T21	1
auto[1879048192:2013265919]	auto[1]	49	1			T45	1		T47	1		T63	1
auto[2013265920:2147483647]	auto[0]	45	1			T61	1		T204	1		T305	1
auto[2013265920:2147483647]	auto[1]	56	1			T62	1		T73	1		T53	1
auto[2147483648:2281701375]	auto[0]	49	1			T6	1		T45	1		T34	1
auto[2147483648:2281701375]	auto[1]	55	1			T7	1		T204	1		T58	1
auto[2281701376:2415919103]	auto[0]	51	1			T142	1		T209	1		T21	1
auto[2281701376:2415919103]	auto[1]	51	1			T63	1		T203	1		T53	1
auto[2415919104:2550136831]	auto[0]	65	1			T62	1		T73	1		T70	1
auto[2415919104:2550136831]	auto[1]	47	1			T6	1		T69	1		T75	1
auto[2550136832:2684354559]	auto[0]	46	1			T61	1		T142	1		T64	1
auto[2550136832:2684354559]	auto[1]	55	1			T209	1		T248	1		T150	1
auto[2684354560:2818572287]	auto[0]	48	1			T15	1		T47	1		T34	1
auto[2684354560:2818572287]	auto[1]	56	1			T15	1		T275	1		T302	1
auto[2818572288:2952790015]	auto[0]	51	1			T421	1		T390	1		T105	1
auto[2818572288:2952790015]	auto[1]	47	1			T17	1		T7	1		T115	1
auto[2952790016:3087007743]	auto[0]	47	1			T21	1		T75	1		T253	1
auto[2952790016:3087007743]	auto[1]	63	1			T422	1		T123	1		T302	1
auto[3087007744:3221225471]	auto[0]	53	1			T7	1		T37	1		T62	1
auto[3087007744:3221225471]	auto[1]	47	1			T61	1		T63	1		T213	1
auto[3221225472:3355443199]	auto[0]	48	1			T75	1		T253	1		T277	1
auto[3221225472:3355443199]	auto[1]	59	1			T21	1		T53	1		T64	2
auto[3355443200:3489660927]	auto[0]	42	1			T115	1		T142	1		T74	1
auto[3355443200:3489660927]	auto[1]	38	1			T36	1		T62	1		T211	1
auto[3489660928:3623878655]	auto[0]	47	1			T32	1		T37	1		T38	1
auto[3489660928:3623878655]	auto[1]	58	1			T73	1		T75	1		T246	1
auto[3623878656:3758096383]	auto[0]	38	1			T35	1		T34	1		T37	1
auto[3623878656:3758096383]	auto[1]	43	1			T98	1		T61	1		T74	1
auto[3758096384:3892314111]	auto[0]	42	1			T4	1		T38	1		T73	1
auto[3758096384:3892314111]	auto[1]	50	1			T35	1		T53	1		T106	1
auto[3892314112:4026531839]	auto[0]	43	1			T64	1		T70	1		T212	1
auto[3892314112:4026531839]	auto[1]	54	1			T3	1		T52	1		T21	1
auto[4026531840:4160749567]	auto[0]	53	1			T35	1		T62	1		T142	1
auto[4026531840:4160749567]	auto[1]	52	1			T17	1		T74	1		T69	1
auto[4160749568:4294967295]	auto[0]	40	1			T37	1		T53	1		T48	1
auto[4160749568:4294967295]	auto[1]	48	1			T210	1		T211	1		T203	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1603

1

T3

1

T4

4

T14

1

auto[1]

1675

1

T3

1

T4

2

T14

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T38	1		T210	1		T160	2
auto[134217728:268435455]	104	1			T142	1		T63	1		T210	1
auto[268435456:402653183]	104	1			T98	1		T61	1		T204	1
auto[402653184:536870911]	102	1			T74	1		T213	1		T253	1
auto[536870912:671088639]	90	1			T64	1		T123	1		T420	1
auto[671088640:805306367]	100	1			T7	1		T73	1		T210	1
auto[805306368:939524095]	108	1			T45	1		T23	1		T63	1
auto[939524096:1073741823]	121	1			T4	1		T45	1		T36	1
auto[1073741824:1207959551]	93	1			T17	1		T36	1		T37	1
auto[1207959552:1342177279]	108	1			T98	1		T7	1		T204	1
auto[1342177280:1476395007]	87	1			T61	1		T37	2		T211	1
auto[1476395008:1610612735]	99	1			T35	1		T36	1		T37	1
auto[1610612736:1744830463]	88	1			T4	1		T62	2		T74	2
auto[1744830464:1879048191]	114	1			T4	1		T15	1		T6	1
auto[1879048192:2013265919]	102	1			T3	1		T4	1		T6	1
auto[2013265920:2147483647]	100	1			T6	1		T16	1		T47	1
auto[2147483648:2281701375]	104	1			T61	1		T37	1		T209	1
auto[2281701376:2415919103]	85	1			T14	1		T32	1		T34	1
auto[2415919104:2550136831]	123	1			T32	1		T52	1		T62	1
auto[2550136832:2684354559]	89	1			T14	1		T15	1		T45	1
auto[2684354560:2818572287]	97	1			T4	1		T61	1		T74	1
auto[2818572288:2952790015]	107	1			T61	1		T204	1		T115	2
auto[2952790016:3087007743]	104	1			T3	1		T16	1		T52	1
auto[3087007744:3221225471]	111	1			T17	1		T98	1		T34	1
auto[3221225472:3355443199]	104	1			T35	1		T45	1		T37	1
auto[3355443200:3489660927]	99	1			T14	1		T37	1		T62	1
auto[3489660928:3623878655]	97	1			T74	1		T206	1		T78	1
auto[3623878656:3758096383]	106	1			T45	1		T63	1		T21	1
auto[3758096384:3892314111]	109	1			T4	1		T14	1		T34	1
auto[3892314112:4026531839]	95	1			T35	1		T45	1		T34	1
auto[4026531840:4160749567]	106	1			T6	1		T17	1		T128	1
auto[4160749568:4294967295]	122	1			T14	1		T16	1		T204	1