dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4338 1 T3 4 T4 10 T14 4
auto[1] 2218 1 T4 2 T14 6 T15 4



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 216 1 T17 2 T115 2 T63 2
auto[134217728:268435455] 206 1 T209 2 T63 2 T74 2
auto[268435456:402653183] 200 1 T210 2 T58 4 T150 2
auto[402653184:536870911] 186 1 T62 2 T209 2 T160 2
auto[536870912:671088639] 196 1 T4 2 T204 2 T142 2
auto[671088640:805306367] 212 1 T38 2 T128 2 T21 2
auto[805306368:939524095] 216 1 T61 2 T37 2 T54 2
auto[939524096:1073741823] 200 1 T14 4 T45 2 T61 2
auto[1073741824:1207959551] 228 1 T16 2 T35 2 T52 2
auto[1207959552:1342177279] 178 1 T6 2 T98 2 T34 2
auto[1342177280:1476395007] 172 1 T34 2 T37 2 T62 2
auto[1476395008:1610612735] 216 1 T52 2 T62 2 T128 2
auto[1610612736:1744830463] 196 1 T4 2 T35 2 T45 2
auto[1744830464:1879048191] 238 1 T4 4 T17 4 T7 2
auto[1879048192:2013265919] 190 1 T32 2 T142 2 T209 2
auto[2013265920:2147483647] 174 1 T16 2 T37 2 T38 2
auto[2147483648:2281701375] 168 1 T4 2 T47 2 T37 2
auto[2281701376:2415919103] 208 1 T14 2 T7 2 T37 2
auto[2415919104:2550136831] 204 1 T7 2 T62 2 T128 2
auto[2550136832:2684354559] 208 1 T14 2 T15 2 T61 2
auto[2684354560:2818572287] 208 1 T4 2 T45 2 T47 2
auto[2818572288:2952790015] 170 1 T3 2 T61 2 T204 2
auto[2952790016:3087007743] 254 1 T6 2 T35 2 T45 2
auto[3087007744:3221225471] 222 1 T15 2 T98 2 T36 2
auto[3221225472:3355443199] 230 1 T6 2 T32 2 T35 2
auto[3355443200:3489660927] 174 1 T16 2 T98 2 T204 2
auto[3489660928:3623878655] 212 1 T14 2 T45 2 T204 2
auto[3623878656:3758096383] 190 1 T34 2 T21 2 T74 2
auto[3758096384:3892314111] 252 1 T61 2 T204 2 T115 2
auto[3892314112:4026531839] 230 1 T3 2 T34 2 T73 2
auto[4026531840:4160749567] 182 1 T62 2 T74 4 T53 2
auto[4160749568:4294967295] 220 1 T6 2 T52 2 T38 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 138 1 T17 2 T78 2 T249 2
auto[0:134217727] auto[1] 78 1 T115 2 T63 2 T249 2
auto[134217728:268435455] auto[0] 136 1 T209 2 T63 2 T74 2
auto[134217728:268435455] auto[1] 70 1 T53 2 T25 2 T75 2
auto[268435456:402653183] auto[0] 144 1 T210 2 T58 4 T150 2
auto[268435456:402653183] auto[1] 56 1 T285 4 T82 2 T135 2
auto[402653184:536870911] auto[0] 122 1 T62 2 T209 2 T69 2
auto[402653184:536870911] auto[1] 64 1 T160 2 T106 4 T49 2
auto[536870912:671088639] auto[0] 126 1 T4 2 T209 2 T160 2
auto[536870912:671088639] auto[1] 70 1 T204 2 T142 2 T212 4
auto[671088640:805306367] auto[0] 142 1 T21 2 T210 2 T75 2
auto[671088640:805306367] auto[1] 70 1 T38 2 T128 2 T420 2
auto[805306368:939524095] auto[0] 136 1 T37 2 T75 2 T293 2
auto[805306368:939524095] auto[1] 80 1 T61 2 T54 2 T206 2
auto[939524096:1073741823] auto[0] 132 1 T14 2 T45 2 T63 2
auto[939524096:1073741823] auto[1] 68 1 T14 2 T61 2 T420 2
auto[1073741824:1207959551] auto[0] 136 1 T35 2 T52 2 T37 2
auto[1073741824:1207959551] auto[1] 92 1 T16 2 T64 2 T75 2
auto[1207959552:1342177279] auto[0] 112 1 T74 2 T212 4 T134 2
auto[1207959552:1342177279] auto[1] 66 1 T6 2 T98 2 T34 2
auto[1342177280:1476395007] auto[0] 106 1 T34 2 T37 2 T62 2
auto[1342177280:1476395007] auto[1] 66 1 T275 2 T104 2 T289 2
auto[1476395008:1610612735] auto[0] 160 1 T52 2 T62 2 T128 2
auto[1476395008:1610612735] auto[1] 56 1 T74 2 T75 2 T246 2
auto[1610612736:1744830463] auto[0] 132 1 T4 2 T45 2 T21 2
auto[1610612736:1744830463] auto[1] 64 1 T35 2 T36 2 T142 2
auto[1744830464:1879048191] auto[0] 170 1 T4 4 T17 2 T37 2
auto[1744830464:1879048191] auto[1] 68 1 T17 2 T7 2 T246 2
auto[1879048192:2013265919] auto[0] 124 1 T209 2 T73 2 T58 2
auto[1879048192:2013265919] auto[1] 66 1 T32 2 T142 2 T211 2
auto[2013265920:2147483647] auto[0] 114 1 T37 2 T38 2 T203 2
auto[2013265920:2147483647] auto[1] 60 1 T16 2 T405 2 T123 2
auto[2147483648:2281701375] auto[0] 110 1 T37 2 T160 2 T53 2
auto[2147483648:2281701375] auto[1] 58 1 T4 2 T47 2 T65 2
auto[2281701376:2415919103] auto[0] 128 1 T14 2 T7 2 T37 2
auto[2281701376:2415919103] auto[1] 80 1 T63 2 T211 2 T53 2
auto[2415919104:2550136831] auto[0] 154 1 T7 2 T62 2 T128 2
auto[2415919104:2550136831] auto[1] 50 1 T74 2 T246 2 T48 2
auto[2550136832:2684354559] auto[0] 128 1 T37 2 T73 2 T21 2
auto[2550136832:2684354559] auto[1] 80 1 T14 2 T15 2 T61 2
auto[2684354560:2818572287] auto[0] 148 1 T4 2 T7 2 T74 2
auto[2684354560:2818572287] auto[1] 60 1 T45 2 T47 2 T142 2
auto[2818572288:2952790015] auto[0] 110 1 T3 2 T62 4 T75 2
auto[2818572288:2952790015] auto[1] 60 1 T61 2 T204 2 T142 2
auto[2952790016:3087007743] auto[0] 168 1 T6 2 T45 2 T74 2
auto[2952790016:3087007743] auto[1] 86 1 T35 2 T34 2 T61 2
auto[3087007744:3221225471] auto[0] 144 1 T98 2 T62 2 T203 2
auto[3087007744:3221225471] auto[1] 78 1 T15 2 T36 2 T420 2
auto[3221225472:3355443199] auto[0] 170 1 T6 2 T32 2 T45 2
auto[3221225472:3355443199] auto[1] 60 1 T35 2 T74 2 T53 2
auto[3355443200:3489660927] auto[0] 106 1 T115 2 T37 2 T203 2
auto[3355443200:3489660927] auto[1] 68 1 T16 2 T98 2 T204 2
auto[3489660928:3623878655] auto[0] 122 1 T45 2 T37 2 T160 2
auto[3489660928:3623878655] auto[1] 90 1 T14 2 T204 2 T53 2
auto[3623878656:3758096383] auto[0] 132 1 T21 2 T275 2 T70 2
auto[3623878656:3758096383] auto[1] 58 1 T34 2 T74 2 T268 2
auto[3758096384:3892314111] auto[0] 158 1 T37 2 T21 2 T213 2
auto[3758096384:3892314111] auto[1] 94 1 T61 2 T204 2 T115 2
auto[3892314112:4026531839] auto[0] 152 1 T3 2 T34 2 T73 2
auto[3892314112:4026531839] auto[1] 78 1 T64 2 T78 2 T75 2
auto[4026531840:4160749567] auto[0] 122 1 T62 2 T74 2 T53 2
auto[4026531840:4160749567] auto[1] 60 1 T74 2 T293 2 T65 2
auto[4160749568:4294967295] auto[0] 156 1 T6 2 T52 2 T73 2
auto[4160749568:4294967295] auto[1] 64 1 T38 2 T211 2 T212 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%