Unified Coverage Report :: Group Instance : salt_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2840

1

T3

2

T4

5

T14

5

auto[1]

298

1

T45

12

T128

5

T160

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T14	1		T52	1		T21	1
auto[134217728:268435455]	96	1			T16	1		T17	1		T45	2
auto[268435456:402653183]	107	1			T17	1		T37	1		T62	1
auto[402653184:536870911]	110	1			T4	3		T204	1		T37	1
auto[536870912:671088639]	97	1			T37	1		T38	1		T142	2
auto[671088640:805306367]	91	1			T14	1		T45	1		T47	1
auto[805306368:939524095]	89	1			T45	1		T73	1		T74	2
auto[939524096:1073741823]	92	1			T3	1		T34	1		T209	1
auto[1073741824:1207959551]	95	1			T35	1		T45	1		T52	1
auto[1207959552:1342177279]	100	1			T7	1		T37	1		T38	1
auto[1342177280:1476395007]	102	1			T37	1		T38	1		T73	1
auto[1476395008:1610612735]	113	1			T14	1		T17	1		T45	2
auto[1610612736:1744830463]	100	1			T98	1		T36	1		T62	1
auto[1744830464:1879048191]	82	1			T3	1		T35	1		T204	1
auto[1879048192:2013265919]	89	1			T4	1		T45	1		T7	1
auto[2013265920:2147483647]	101	1			T47	1		T38	1		T211	1
auto[2147483648:2281701375]	98	1			T61	1		T115	1		T142	1
auto[2281701376:2415919103]	101	1			T34	1		T128	1		T210	1
auto[2415919104:2550136831]	93	1			T45	2		T204	1		T115	1
auto[2550136832:2684354559]	96	1			T14	1		T147	1		T128	1
auto[2684354560:2818572287]	124	1			T14	1		T35	1		T45	2
auto[2818572288:2952790015]	80	1			T16	1		T209	1		T21	1
auto[2952790016:3087007743]	83	1			T115	1		T37	1		T128	1
auto[3087007744:3221225471]	101	1			T45	1		T37	1		T160	1
auto[3221225472:3355443199]	87	1			T45	1		T21	2		T74	1
auto[3355443200:3489660927]	120	1			T7	1		T21	1		T203	1
auto[3489660928:3623878655]	88	1			T4	1		T15	1		T98	1
auto[3623878656:3758096383]	100	1			T128	1		T210	1		T213	1
auto[3758096384:3892314111]	93	1			T45	1		T34	1		T62	1
auto[3892314112:4026531839]	101	1			T15	1		T16	1		T34	1
auto[4026531840:4160749567]	96	1			T45	1		T37	2		T422	1
auto[4160749568:4294967295]	105	1			T35	1		T45	2		T37	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	100	1			T14	1		T52	1		T21	1
auto[0:134217727]	auto[1]	8	1			T160	1		T150	1		T379	1
auto[134217728:268435455]	auto[0]	87	1			T16	1		T17	1		T45	1
auto[134217728:268435455]	auto[1]	9	1			T45	1		T151	1		T308	1
auto[268435456:402653183]	auto[0]	95	1			T17	1		T37	1		T62	1
auto[268435456:402653183]	auto[1]	12	1			T291	2		T379	1		T349	1
auto[402653184:536870911]	auto[0]	94	1			T4	3		T204	1		T37	1
auto[402653184:536870911]	auto[1]	16	1			T93	1		T308	1		T291	1
auto[536870912:671088639]	auto[0]	94	1			T37	1		T38	1		T142	2
auto[536870912:671088639]	auto[1]	3	1			T415	1		T361	1		T428	1
auto[671088640:805306367]	auto[0]	87	1			T14	1		T45	1		T47	1
auto[671088640:805306367]	auto[1]	4	1			T244	1		T427	1		T429	1
auto[805306368:939524095]	auto[0]	82	1			T45	1		T73	1		T74	2
auto[805306368:939524095]	auto[1]	7	1			T93	4		T431	1		T263	1
auto[939524096:1073741823]	auto[0]	85	1			T3	1		T34	1		T209	1
auto[939524096:1073741823]	auto[1]	7	1			T161	1		T419	2		T263	1
auto[1073741824:1207959551]	auto[0]	89	1			T35	1		T52	1		T74	1
auto[1073741824:1207959551]	auto[1]	6	1			T45	1		T291	1		T379	1
auto[1207959552:1342177279]	auto[0]	99	1			T7	1		T37	1		T38	1
auto[1207959552:1342177279]	auto[1]	1	1			T150	1		-	-		-	-
auto[1342177280:1476395007]	auto[0]	91	1			T37	1		T38	1		T73	1
auto[1342177280:1476395007]	auto[1]	11	1			T160	1		T151	1		T93	1
auto[1476395008:1610612735]	auto[0]	102	1			T14	1		T17	1		T98	1
auto[1476395008:1610612735]	auto[1]	11	1			T45	2		T308	1		T291	1
auto[1610612736:1744830463]	auto[0]	90	1			T98	1		T36	1		T62	1
auto[1610612736:1744830463]	auto[1]	10	1			T291	1		T244	1		T417	1
auto[1744830464:1879048191]	auto[0]	79	1			T3	1		T35	1		T204	1
auto[1744830464:1879048191]	auto[1]	3	1			T419	1		T401	1		T357	1
auto[1879048192:2013265919]	auto[0]	83	1			T4	1		T45	1		T7	1
auto[1879048192:2013265919]	auto[1]	6	1			T365	1		T307	1		T345	1
auto[2013265920:2147483647]	auto[0]	89	1			T47	1		T38	1		T211	1
auto[2013265920:2147483647]	auto[1]	12	1			T160	2		T416	1		T418	1
auto[2147483648:2281701375]	auto[0]	88	1			T61	1		T115	1		T142	1
auto[2147483648:2281701375]	auto[1]	10	1			T150	1		T244	1		T419	1
auto[2281701376:2415919103]	auto[0]	88	1			T34	1		T210	1		T150	1
auto[2281701376:2415919103]	auto[1]	13	1			T128	1		T349	1		T244	1
auto[2415919104:2550136831]	auto[0]	81	1			T204	1		T115	1		T62	1
auto[2415919104:2550136831]	auto[1]	12	1			T45	2		T128	1		T160	1
auto[2550136832:2684354559]	auto[0]	81	1			T14	1		T147	1		T211	1
auto[2550136832:2684354559]	auto[1]	15	1			T128	1		T349	1		T366	2
auto[2684354560:2818572287]	auto[0]	113	1			T14	1		T35	1		T45	1
auto[2684354560:2818572287]	auto[1]	11	1			T45	1		T152	1		T366	1
auto[2818572288:2952790015]	auto[0]	71	1			T16	1		T209	1		T21	1
auto[2818572288:2952790015]	auto[1]	9	1			T150	2		T291	2		T379	1
auto[2952790016:3087007743]	auto[0]	77	1			T115	1		T37	1		T128	1
auto[2952790016:3087007743]	auto[1]	6	1			T291	1		T379	1		T366	1
auto[3087007744:3221225471]	auto[0]	92	1			T37	1		T160	1		T53	1
auto[3087007744:3221225471]	auto[1]	9	1			T45	1		T291	1		T152	1
auto[3221225472:3355443199]	auto[0]	79	1			T21	2		T74	1		T58	1
auto[3221225472:3355443199]	auto[1]	8	1			T45	1		T152	1		T417	1
auto[3355443200:3489660927]	auto[0]	107	1			T7	1		T21	1		T203	1
auto[3355443200:3489660927]	auto[1]	13	1			T379	1		T349	2		T152	2
auto[3489660928:3623878655]	auto[0]	81	1			T4	1		T15	1		T98	1
auto[3489660928:3623878655]	auto[1]	7	1			T128	1		T427	1		T418	1
auto[3623878656:3758096383]	auto[0]	89	1			T210	1		T213	1		T275	1
auto[3623878656:3758096383]	auto[1]	11	1			T128	1		T379	1		T349	1
auto[3758096384:3892314111]	auto[0]	78	1			T34	1		T62	1		T38	1
auto[3758096384:3892314111]	auto[1]	15	1			T45	1		T160	1		T150	1
auto[3892314112:4026531839]	auto[0]	89	1			T15	1		T16	1		T34	1
auto[3892314112:4026531839]	auto[1]	12	1			T160	1		T349	1		T366	1
auto[4026531840:4160749567]	auto[0]	84	1			T37	2		T422	1		T253	2
auto[4026531840:4160749567]	auto[1]	12	1			T45	1		T306	1		T404	1
auto[4160749568:4294967295]	auto[0]	96	1			T35	1		T45	1		T37	1
auto[4160749568:4294967295]	auto[1]	9	1			T45	1		T379	1		T416	1