Unified Coverage Report :: Group Instance : sealing_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1607

1

T3

1

T4

4

T14

2

auto[1]

1670

1

T3

1

T4

2

T14

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T47	1		T34	1		T53	1
auto[134217728:268435455]	105	1			T36	1		T204	1		T21	2
auto[268435456:402653183]	104	1			T16	2		T52	1		T115	1
auto[402653184:536870911]	102	1			T4	1		T61	1		T62	1
auto[536870912:671088639]	100	1			T45	1		T147	1		T37	1
auto[671088640:805306367]	104	1			T14	1		T6	1		T45	1
auto[805306368:939524095]	106	1			T15	1		T35	1		T45	1
auto[939524096:1073741823]	107	1			T4	1		T6	1		T35	1
auto[1073741824:1207959551]	101	1			T58	1		T53	1		T64	2
auto[1207959552:1342177279]	106	1			T34	1		T36	1		T142	1
auto[1342177280:1476395007]	95	1			T4	2		T98	1		T115	1
auto[1476395008:1610612735]	106	1			T3	1		T16	1		T7	1
auto[1610612736:1744830463]	99	1			T6	2		T61	2		T21	1
auto[1744830464:1879048191]	81	1			T15	1		T17	1		T45	1
auto[1879048192:2013265919]	111	1			T14	1		T37	1		T58	1
auto[2013265920:2147483647]	94	1			T47	1		T23	1		T62	1
auto[2147483648:2281701375]	95	1			T4	1		T32	1		T61	1
auto[2281701376:2415919103]	112	1			T45	1		T61	1		T7	1
auto[2415919104:2550136831]	106	1			T98	1		T7	1		T63	1
auto[2550136832:2684354559]	101	1			T3	1		T45	1		T74	2
auto[2684354560:2818572287]	108	1			T4	1		T17	1		T98	1
auto[2818572288:2952790015]	125	1			T14	1		T37	1		T209	1
auto[2952790016:3087007743]	116	1			T37	1		T62	1		T203	1
auto[3087007744:3221225471]	109	1			T211	1		T53	2		T422	1
auto[3221225472:3355443199]	98	1			T32	1		T35	2		T52	1
auto[3355443200:3489660927]	107	1			T14	1		T17	1		T128	1
auto[3489660928:3623878655]	97	1			T14	1		T52	1		T204	1
auto[3623878656:3758096383]	97	1			T37	1		T62	1		T142	1
auto[3758096384:3892314111]	92	1			T34	1		T62	1		T38	1
auto[3892314112:4026531839]	100	1			T62	1		T142	1		T73	1
auto[4026531840:4160749567]	90	1			T36	1		T204	1		T37	1
auto[4160749568:4294967295]	99	1			T37	1		T142	1		T128	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T34	1		T75	1		T94	1
auto[0:134217727]	auto[1]	61	1			T47	1		T53	1		T75	1
auto[134217728:268435455]	auto[0]	55	1			T21	2		T58	1		T64	1
auto[134217728:268435455]	auto[1]	50	1			T36	1		T204	1		T78	1
auto[268435456:402653183]	auto[0]	49	1			T16	1		T37	1		T160	1
auto[268435456:402653183]	auto[1]	55	1			T16	1		T52	1		T115	1
auto[402653184:536870911]	auto[0]	52	1			T4	1		T62	1		T142	1
auto[402653184:536870911]	auto[1]	50	1			T61	1		T73	1		T53	2
auto[536870912:671088639]	auto[0]	57	1			T147	1		T37	1		T38	1
auto[536870912:671088639]	auto[1]	43	1			T45	1		T59	1		T275	1
auto[671088640:805306367]	auto[0]	46	1			T6	1		T45	1		T34	1
auto[671088640:805306367]	auto[1]	58	1			T14	1		T74	1		T206	1
auto[805306368:939524095]	auto[0]	55	1			T35	1		T45	1		T204	1
auto[805306368:939524095]	auto[1]	51	1			T15	1		T63	1		T25	1
auto[939524096:1073741823]	auto[0]	61	1			T4	1		T6	1		T35	1
auto[939524096:1073741823]	auto[1]	46	1			T150	1		T75	1		T213	1
auto[1073741824:1207959551]	auto[0]	45	1			T58	1		T161	1		T123	1
auto[1073741824:1207959551]	auto[1]	56	1			T53	1		T64	2		T246	1
auto[1207959552:1342177279]	auto[0]	51	1			T34	1		T142	1		T73	1
auto[1207959552:1342177279]	auto[1]	55	1			T36	1		T161	1		T75	1
auto[1342177280:1476395007]	auto[0]	48	1			T4	1		T115	1		T74	1
auto[1342177280:1476395007]	auto[1]	47	1			T4	1		T98	1		T206	1
auto[1476395008:1610612735]	auto[0]	49	1			T16	1		T209	1		T160	1
auto[1476395008:1610612735]	auto[1]	57	1			T3	1		T7	1		T74	1
auto[1610612736:1744830463]	auto[0]	47	1			T61	1		T21	1		T53	1
auto[1610612736:1744830463]	auto[1]	52	1			T6	2		T61	1		T53	1
auto[1744830464:1879048191]	auto[0]	47	1			T15	1		T45	1		T61	1
auto[1744830464:1879048191]	auto[1]	34	1			T17	1		T203	1		T212	1
auto[1879048192:2013265919]	auto[0]	57	1			T14	1		T37	1		T75	1
auto[1879048192:2013265919]	auto[1]	54	1			T58	1		T151	1		T305	1
auto[2013265920:2147483647]	auto[0]	51	1			T62	1		T249	1		T91	1
auto[2013265920:2147483647]	auto[1]	43	1			T47	1		T23	1		T73	1
auto[2147483648:2281701375]	auto[0]	49	1			T4	1		T32	1		T62	1
auto[2147483648:2281701375]	auto[1]	46	1			T61	1		T206	1		T53	2
auto[2281701376:2415919103]	auto[0]	53	1			T21	1		T40	1		T248	1
auto[2281701376:2415919103]	auto[1]	59	1			T45	1		T61	1		T7	1
auto[2415919104:2550136831]	auto[0]	49	1			T160	1		T253	1		T134	1
auto[2415919104:2550136831]	auto[1]	57	1			T98	1		T7	1		T63	1
auto[2550136832:2684354559]	auto[0]	41	1			T3	1		T70	1		T212	2
auto[2550136832:2684354559]	auto[1]	60	1			T45	1		T74	2		T210	1
auto[2684354560:2818572287]	auto[0]	56	1			T17	1		T34	1		T7	1
auto[2684354560:2818572287]	auto[1]	52	1			T4	1		T98	1		T38	1
auto[2818572288:2952790015]	auto[0]	58	1			T14	1		T37	1		T209	1
auto[2818572288:2952790015]	auto[1]	67	1			T63	2		T74	2		T210	2
auto[2952790016:3087007743]	auto[0]	50	1			T62	1		T203	1		T135	1
auto[2952790016:3087007743]	auto[1]	66	1			T37	1		T53	1		T248	1
auto[3087007744:3221225471]	auto[0]	61	1			T53	1		T212	2		T48	1
auto[3087007744:3221225471]	auto[1]	48	1			T211	1		T53	1		T422	1
auto[3221225472:3355443199]	auto[0]	46	1			T35	1		T52	1		T37	1
auto[3221225472:3355443199]	auto[1]	52	1			T32	1		T35	1		T115	1
auto[3355443200:3489660927]	auto[0]	48	1			T128	1		T58	1		T160	1
auto[3355443200:3489660927]	auto[1]	59	1			T14	1		T17	1		T63	1
auto[3489660928:3623878655]	auto[0]	49	1			T64	1		T70	1		T212	1
auto[3489660928:3623878655]	auto[1]	48	1			T14	1		T52	1		T204	1
auto[3623878656:3758096383]	auto[0]	54	1			T62	1		T142	1		T21	1
auto[3623878656:3758096383]	auto[1]	43	1			T37	1		T209	1		T64	1
auto[3758096384:3892314111]	auto[0]	44	1			T34	1		T62	1		T38	1
auto[3758096384:3892314111]	auto[1]	48	1			T211	1		T64	2		T75	1
auto[3892314112:4026531839]	auto[0]	45	1			T62	1		T73	1		T212	1
auto[3892314112:4026531839]	auto[1]	55	1			T142	1		T74	2		T248	1
auto[4026531840:4160749567]	auto[0]	46	1			T204	1		T37	1		T209	1
auto[4026531840:4160749567]	auto[1]	44	1			T36	1		T58	1		T161	1
auto[4160749568:4294967295]	auto[0]	45	1			T37	1		T142	1		T21	1
auto[4160749568:4294967295]	auto[1]	54	1			T128	1		T203	1		T58	1