Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.04 97.99 98.42 100.00 99.02 98.41 91.19


Total test records in report: 1085
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T1005 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3467288757 Jul 09 06:54:44 PM PDT 24 Jul 09 06:54:51 PM PDT 24 490831274 ps
T1006 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.4268464855 Jul 09 06:54:35 PM PDT 24 Jul 09 06:54:37 PM PDT 24 102050165 ps
T1007 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3218812205 Jul 09 06:53:54 PM PDT 24 Jul 09 06:54:03 PM PDT 24 510827694 ps
T1008 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2784854052 Jul 09 06:54:32 PM PDT 24 Jul 09 06:54:33 PM PDT 24 28195440 ps
T1009 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2425929729 Jul 09 06:53:57 PM PDT 24 Jul 09 06:54:09 PM PDT 24 414007281 ps
T1010 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3671582813 Jul 09 06:54:17 PM PDT 24 Jul 09 06:54:21 PM PDT 24 139775594 ps
T1011 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2221386174 Jul 09 06:53:58 PM PDT 24 Jul 09 06:54:04 PM PDT 24 154681828 ps
T1012 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3597557616 Jul 09 06:54:38 PM PDT 24 Jul 09 06:54:40 PM PDT 24 35933831 ps
T1013 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2304487442 Jul 09 06:54:48 PM PDT 24 Jul 09 06:54:53 PM PDT 24 93506966 ps
T173 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.31702061 Jul 09 06:54:36 PM PDT 24 Jul 09 06:54:41 PM PDT 24 304088399 ps
T1014 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2894812307 Jul 09 06:54:21 PM PDT 24 Jul 09 06:54:24 PM PDT 24 91870461 ps
T1015 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3540558112 Jul 09 06:54:02 PM PDT 24 Jul 09 06:54:04 PM PDT 24 26900430 ps
T1016 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2243004158 Jul 09 06:54:03 PM PDT 24 Jul 09 06:54:09 PM PDT 24 190099823 ps
T1017 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3799763608 Jul 09 06:53:50 PM PDT 24 Jul 09 06:53:53 PM PDT 24 275309970 ps
T1018 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1087774711 Jul 09 06:54:46 PM PDT 24 Jul 09 06:54:49 PM PDT 24 43599226 ps
T1019 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.616008004 Jul 09 06:54:21 PM PDT 24 Jul 09 06:54:24 PM PDT 24 356518765 ps
T1020 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3384824955 Jul 09 06:54:47 PM PDT 24 Jul 09 06:54:49 PM PDT 24 18114185 ps
T1021 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3221574934 Jul 09 06:53:58 PM PDT 24 Jul 09 06:54:09 PM PDT 24 899743736 ps
T1022 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1872073678 Jul 09 06:54:08 PM PDT 24 Jul 09 06:54:11 PM PDT 24 293948882 ps
T1023 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.686259500 Jul 09 06:54:41 PM PDT 24 Jul 09 06:54:44 PM PDT 24 16860739 ps
T1024 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.571340531 Jul 09 06:54:41 PM PDT 24 Jul 09 06:54:46 PM PDT 24 452774315 ps
T1025 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2023273093 Jul 09 06:54:27 PM PDT 24 Jul 09 06:54:29 PM PDT 24 35196242 ps
T1026 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1531292365 Jul 09 06:54:42 PM PDT 24 Jul 09 06:54:46 PM PDT 24 18968961 ps
T169 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3924619236 Jul 09 06:54:02 PM PDT 24 Jul 09 06:54:11 PM PDT 24 394978703 ps
T1027 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3627822847 Jul 09 06:54:14 PM PDT 24 Jul 09 06:54:16 PM PDT 24 33413217 ps
T1028 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1705212958 Jul 09 06:54:20 PM PDT 24 Jul 09 06:54:24 PM PDT 24 49794378 ps
T1029 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1153032212 Jul 09 06:53:54 PM PDT 24 Jul 09 06:53:58 PM PDT 24 306890567 ps
T1030 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1324453670 Jul 09 06:54:14 PM PDT 24 Jul 09 06:54:16 PM PDT 24 46312844 ps
T1031 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1435943840 Jul 09 06:53:57 PM PDT 24 Jul 09 06:54:04 PM PDT 24 182283626 ps
T1032 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3776871249 Jul 09 06:54:09 PM PDT 24 Jul 09 06:54:11 PM PDT 24 19612260 ps
T1033 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1706658593 Jul 09 06:54:42 PM PDT 24 Jul 09 06:54:46 PM PDT 24 29234283 ps
T1034 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1052633594 Jul 09 06:54:36 PM PDT 24 Jul 09 06:54:39 PM PDT 24 81092773 ps
T1035 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3231029025 Jul 09 06:54:24 PM PDT 24 Jul 09 06:54:27 PM PDT 24 200179017 ps
T1036 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.782355410 Jul 09 06:54:28 PM PDT 24 Jul 09 06:54:33 PM PDT 24 116851992 ps
T1037 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2266204600 Jul 09 06:54:25 PM PDT 24 Jul 09 06:54:33 PM PDT 24 825436962 ps
T1038 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1246610012 Jul 09 06:54:11 PM PDT 24 Jul 09 06:54:15 PM PDT 24 363003563 ps
T1039 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.466920479 Jul 09 06:54:26 PM PDT 24 Jul 09 06:54:28 PM PDT 24 224062768 ps
T1040 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.240100688 Jul 09 06:54:09 PM PDT 24 Jul 09 06:54:17 PM PDT 24 132237864 ps
T1041 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.720053040 Jul 09 06:54:36 PM PDT 24 Jul 09 06:54:43 PM PDT 24 1823109467 ps
T1042 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3007685736 Jul 09 06:54:13 PM PDT 24 Jul 09 06:54:16 PM PDT 24 93956267 ps
T1043 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2920699175 Jul 09 06:54:02 PM PDT 24 Jul 09 06:54:04 PM PDT 24 128871826 ps
T1044 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.407513383 Jul 09 06:53:58 PM PDT 24 Jul 09 06:54:01 PM PDT 24 146869145 ps
T1045 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.705051200 Jul 09 06:54:38 PM PDT 24 Jul 09 06:54:45 PM PDT 24 151322046 ps
T1046 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2749337559 Jul 09 06:54:16 PM PDT 24 Jul 09 06:54:17 PM PDT 24 44502409 ps
T1047 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.4035937053 Jul 09 06:53:52 PM PDT 24 Jul 09 06:53:54 PM PDT 24 11529093 ps
T1048 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1621005436 Jul 09 06:54:09 PM PDT 24 Jul 09 06:54:23 PM PDT 24 445612377 ps
T1049 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.93677143 Jul 09 06:54:07 PM PDT 24 Jul 09 06:54:10 PM PDT 24 133075362 ps
T1050 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3201962582 Jul 09 06:54:01 PM PDT 24 Jul 09 06:54:05 PM PDT 24 181468370 ps
T1051 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.4098925754 Jul 09 06:54:36 PM PDT 24 Jul 09 06:54:40 PM PDT 24 336867255 ps
T1052 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.520831768 Jul 09 06:54:35 PM PDT 24 Jul 09 06:54:38 PM PDT 24 83967338 ps
T1053 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.833567229 Jul 09 06:54:24 PM PDT 24 Jul 09 06:54:30 PM PDT 24 653535492 ps
T1054 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1581070673 Jul 09 06:54:03 PM PDT 24 Jul 09 06:54:05 PM PDT 24 14909162 ps
T1055 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4177439430 Jul 09 06:54:46 PM PDT 24 Jul 09 06:54:49 PM PDT 24 31548686 ps
T1056 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3714998471 Jul 09 06:54:30 PM PDT 24 Jul 09 06:54:33 PM PDT 24 148767828 ps
T1057 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3620580506 Jul 09 06:54:33 PM PDT 24 Jul 09 06:54:36 PM PDT 24 80108739 ps
T1058 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2174730791 Jul 09 06:54:39 PM PDT 24 Jul 09 06:54:44 PM PDT 24 362036974 ps
T1059 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.616088915 Jul 09 06:54:13 PM PDT 24 Jul 09 06:54:14 PM PDT 24 19936463 ps
T1060 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.536257728 Jul 09 06:53:55 PM PDT 24 Jul 09 06:53:58 PM PDT 24 79176455 ps
T1061 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.677389254 Jul 09 06:54:26 PM PDT 24 Jul 09 06:54:30 PM PDT 24 72941078 ps
T1062 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3757882716 Jul 09 06:54:13 PM PDT 24 Jul 09 06:54:15 PM PDT 24 29934609 ps
T1063 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2090803724 Jul 09 06:54:03 PM PDT 24 Jul 09 06:54:20 PM PDT 24 4463023085 ps
T1064 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1851083920 Jul 09 06:54:22 PM PDT 24 Jul 09 06:54:31 PM PDT 24 544231250 ps
T174 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.301199632 Jul 09 06:54:30 PM PDT 24 Jul 09 06:54:34 PM PDT 24 52675740 ps
T1065 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.4173921459 Jul 09 06:54:10 PM PDT 24 Jul 09 06:54:11 PM PDT 24 40218803 ps
T182 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3930610807 Jul 09 06:54:05 PM PDT 24 Jul 09 06:54:11 PM PDT 24 288246750 ps
T1066 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1858259043 Jul 09 06:53:52 PM PDT 24 Jul 09 06:53:54 PM PDT 24 25468236 ps
T1067 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1358457588 Jul 09 06:54:42 PM PDT 24 Jul 09 06:54:47 PM PDT 24 23668717 ps
T1068 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3264860034 Jul 09 06:54:34 PM PDT 24 Jul 09 06:54:40 PM PDT 24 189254040 ps
T1069 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4205502769 Jul 09 06:54:14 PM PDT 24 Jul 09 06:54:17 PM PDT 24 149876641 ps
T1070 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.285309329 Jul 09 06:53:59 PM PDT 24 Jul 09 06:54:06 PM PDT 24 135467243 ps
T1071 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3471620748 Jul 09 06:54:18 PM PDT 24 Jul 09 06:54:21 PM PDT 24 16501139 ps
T1072 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3339302757 Jul 09 06:54:18 PM PDT 24 Jul 09 06:54:23 PM PDT 24 400966312 ps
T1073 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.346027640 Jul 09 06:53:52 PM PDT 24 Jul 09 06:54:02 PM PDT 24 474299464 ps
T1074 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.335680078 Jul 09 06:53:57 PM PDT 24 Jul 09 06:54:01 PM PDT 24 182824368 ps
T1075 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1441902613 Jul 09 06:53:53 PM PDT 24 Jul 09 06:53:55 PM PDT 24 9453346 ps
T1076 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2782443362 Jul 09 06:54:26 PM PDT 24 Jul 09 06:54:30 PM PDT 24 657136217 ps
T1077 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.887989726 Jul 09 06:54:14 PM PDT 24 Jul 09 06:54:16 PM PDT 24 23377244 ps
T1078 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3254167686 Jul 09 06:54:27 PM PDT 24 Jul 09 06:54:29 PM PDT 24 119309256 ps
T1079 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.246518385 Jul 09 06:54:39 PM PDT 24 Jul 09 06:54:41 PM PDT 24 24721675 ps
T1080 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.4051505376 Jul 09 06:54:40 PM PDT 24 Jul 09 06:54:42 PM PDT 24 12113220 ps
T1081 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.284158257 Jul 09 06:54:36 PM PDT 24 Jul 09 06:54:39 PM PDT 24 32501902 ps
T1082 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.708298604 Jul 09 06:54:28 PM PDT 24 Jul 09 06:54:31 PM PDT 24 219738269 ps
T1083 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1091283009 Jul 09 06:54:43 PM PDT 24 Jul 09 06:54:47 PM PDT 24 23501879 ps
T1084 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2277725182 Jul 09 06:54:08 PM PDT 24 Jul 09 06:54:13 PM PDT 24 274428623 ps
T1085 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2060896747 Jul 09 06:54:41 PM PDT 24 Jul 09 06:54:43 PM PDT 24 103713533 ps

Test location /workspace/coverage/default/39.keymgr_custom_cm.3499810541
Short name T4
Test name
Test status
Simulation time 199283130 ps
CPU time 4.94 seconds
Started Jul 09 07:01:44 PM PDT 24
Finished Jul 09 07:01:52 PM PDT 24
Peak memory 214736 kb
Host smart-18033e27-9ff2-490b-999b-7c4238a804f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499810541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3499810541
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.745218844
Short name T212
Test name
Test status
Simulation time 2725569552 ps
CPU time 68.64 seconds
Started Jul 09 07:01:34 PM PDT 24
Finished Jul 09 07:02:45 PM PDT 24
Peak memory 222456 kb
Host smart-9319ee7a-a681-4df7-a249-d106c501a244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745218844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.745218844
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.814341831
Short name T115
Test name
Test status
Simulation time 1757229588 ps
CPU time 12.2 seconds
Started Jul 09 07:02:11 PM PDT 24
Finished Jul 09 07:02:28 PM PDT 24
Peak memory 222672 kb
Host smart-449d417c-60e6-4236-9f7c-1cc25eeed125
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814341831 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.814341831
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.851547997
Short name T45
Test name
Test status
Simulation time 533682435 ps
CPU time 27.75 seconds
Started Jul 09 07:00:52 PM PDT 24
Finished Jul 09 07:01:21 PM PDT 24
Peak memory 214996 kb
Host smart-ce4efbb9-9d87-49d3-a86c-204fd4344ff9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=851547997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.851547997
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.501800100
Short name T11
Test name
Test status
Simulation time 1440586001 ps
CPU time 10.01 seconds
Started Jul 09 06:59:47 PM PDT 24
Finished Jul 09 06:59:58 PM PDT 24
Peak memory 229788 kb
Host smart-13ff303c-ad1b-44d1-83e1-3872eaa0f1de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501800100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.501800100
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2049644996
Short name T50
Test name
Test status
Simulation time 1222612762 ps
CPU time 33.38 seconds
Started Jul 09 07:00:27 PM PDT 24
Finished Jul 09 07:01:02 PM PDT 24
Peak memory 216052 kb
Host smart-dcd9620f-8344-40f2-8265-d013401a0a6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049644996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2049644996
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1707703364
Short name T74
Test name
Test status
Simulation time 509730231 ps
CPU time 17.84 seconds
Started Jul 09 07:01:49 PM PDT 24
Finished Jul 09 07:02:09 PM PDT 24
Peak memory 221212 kb
Host smart-f9322268-5f7b-466c-96d3-d01dfa779b41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707703364 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1707703364
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2188633772
Short name T6
Test name
Test status
Simulation time 101899011 ps
CPU time 2.97 seconds
Started Jul 09 07:01:52 PM PDT 24
Finished Jul 09 07:01:58 PM PDT 24
Peak memory 214752 kb
Host smart-11a6787b-c862-41b2-8e7f-c50ca134b32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188633772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2188633772
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.4211128230
Short name T37
Test name
Test status
Simulation time 56168505 ps
CPU time 3.23 seconds
Started Jul 09 07:00:14 PM PDT 24
Finished Jul 09 07:00:21 PM PDT 24
Peak memory 214372 kb
Host smart-7265c680-01b8-4708-85f1-24b46854912c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211128230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.4211128230
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.4255944249
Short name T65
Test name
Test status
Simulation time 1087023618 ps
CPU time 20.7 seconds
Started Jul 09 06:59:54 PM PDT 24
Finished Jul 09 07:00:16 PM PDT 24
Peak memory 222520 kb
Host smart-40dd8ef8-f351-41cf-9f45-17acc2e00426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255944249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.4255944249
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.4155337567
Short name T38
Test name
Test status
Simulation time 68459194 ps
CPU time 3.22 seconds
Started Jul 09 06:59:54 PM PDT 24
Finished Jul 09 06:59:58 PM PDT 24
Peak memory 222412 kb
Host smart-ce701e1c-3893-4fe7-a258-9e487d701c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155337567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.4155337567
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2159108990
Short name T125
Test name
Test status
Simulation time 781531183 ps
CPU time 5.37 seconds
Started Jul 09 06:54:15 PM PDT 24
Finished Jul 09 06:54:21 PM PDT 24
Peak memory 214112 kb
Host smart-b20d0da2-f488-449c-878e-52ecaa956aab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159108990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2159108990
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.244106865
Short name T9
Test name
Test status
Simulation time 613655468 ps
CPU time 3.9 seconds
Started Jul 09 07:00:59 PM PDT 24
Finished Jul 09 07:01:06 PM PDT 24
Peak memory 221256 kb
Host smart-a52741de-f195-4930-986f-a9ed46268159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244106865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.244106865
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3103395372
Short name T53
Test name
Test status
Simulation time 1095208506 ps
CPU time 25.91 seconds
Started Jul 09 07:01:40 PM PDT 24
Finished Jul 09 07:02:08 PM PDT 24
Peak memory 215916 kb
Host smart-dc9df574-2405-4a5c-8582-771c3a021c1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103395372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3103395372
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1928619910
Short name T379
Test name
Test status
Simulation time 5956197862 ps
CPU time 88.08 seconds
Started Jul 09 06:59:47 PM PDT 24
Finished Jul 09 07:01:16 PM PDT 24
Peak memory 215844 kb
Host smart-34d6efd1-7be3-41f5-9109-063f774dec45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1928619910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1928619910
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3084772758
Short name T21
Test name
Test status
Simulation time 829318451 ps
CPU time 7.57 seconds
Started Jul 09 07:02:12 PM PDT 24
Finished Jul 09 07:02:24 PM PDT 24
Peak memory 214356 kb
Host smart-b7f0e10d-6851-4627-8c81-bf8d35c060db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084772758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3084772758
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2253389903
Short name T361
Test name
Test status
Simulation time 853754821 ps
CPU time 43.69 seconds
Started Jul 09 06:59:42 PM PDT 24
Finished Jul 09 07:00:27 PM PDT 24
Peak memory 215384 kb
Host smart-87978701-2e03-4934-9aa0-9820cde6a1ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2253389903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2253389903
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2955478577
Short name T34
Test name
Test status
Simulation time 57313418 ps
CPU time 4.18 seconds
Started Jul 09 07:00:52 PM PDT 24
Finished Jul 09 07:00:58 PM PDT 24
Peak memory 222676 kb
Host smart-a1dafd96-fc38-4f2f-b3df-1db8931a87ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955478577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2955478577
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2018782557
Short name T93
Test name
Test status
Simulation time 233902236 ps
CPU time 4.09 seconds
Started Jul 09 07:01:53 PM PDT 24
Finished Jul 09 07:01:59 PM PDT 24
Peak memory 214352 kb
Host smart-e71f0da6-fff4-47ca-8943-aeb59cb41054
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2018782557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2018782557
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2031875604
Short name T75
Test name
Test status
Simulation time 6086019275 ps
CPU time 137.01 seconds
Started Jul 09 07:01:02 PM PDT 24
Finished Jul 09 07:03:22 PM PDT 24
Peak memory 222560 kb
Host smart-81f93edb-e776-4d03-8ed2-2a439dcf0344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031875604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2031875604
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.804069240
Short name T126
Test name
Test status
Simulation time 290154732 ps
CPU time 2.62 seconds
Started Jul 09 06:54:34 PM PDT 24
Finished Jul 09 06:54:37 PM PDT 24
Peak memory 214008 kb
Host smart-84dcd6ce-117d-4194-be71-c2e0ab9787a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804069240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.804069240
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2735095877
Short name T345
Test name
Test status
Simulation time 1057821824 ps
CPU time 16.65 seconds
Started Jul 09 07:00:34 PM PDT 24
Finished Jul 09 07:00:52 PM PDT 24
Peak memory 214728 kb
Host smart-7247ace2-6386-40c1-9dd6-8b71a30b18a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2735095877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2735095877
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2800376353
Short name T36
Test name
Test status
Simulation time 2011685956 ps
CPU time 6.85 seconds
Started Jul 09 07:01:21 PM PDT 24
Finished Jul 09 07:01:31 PM PDT 24
Peak memory 218508 kb
Host smart-b6447fe5-41a1-4d3c-9a26-2bada41d81c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800376353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2800376353
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2301350160
Short name T266
Test name
Test status
Simulation time 830941054 ps
CPU time 22.83 seconds
Started Jul 09 07:01:02 PM PDT 24
Finished Jul 09 07:01:28 PM PDT 24
Peak memory 221524 kb
Host smart-dfe4fdc5-7c12-4c95-9410-3c3bd7eed5d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301350160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2301350160
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2828762094
Short name T244
Test name
Test status
Simulation time 4331080471 ps
CPU time 53.97 seconds
Started Jul 09 07:02:16 PM PDT 24
Finished Jul 09 07:03:13 PM PDT 24
Peak memory 222512 kb
Host smart-ecee67c0-328c-4794-931b-5286af98d05b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2828762094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2828762094
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1138948398
Short name T64
Test name
Test status
Simulation time 5160317760 ps
CPU time 35.52 seconds
Started Jul 09 07:01:10 PM PDT 24
Finished Jul 09 07:01:50 PM PDT 24
Peak memory 217344 kb
Host smart-9d64cf9e-796e-44b9-ac92-80b29b1babce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138948398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1138948398
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3484799804
Short name T102
Test name
Test status
Simulation time 43359830 ps
CPU time 3.23 seconds
Started Jul 09 06:59:37 PM PDT 24
Finished Jul 09 06:59:43 PM PDT 24
Peak memory 214340 kb
Host smart-9869fa0b-8765-43b7-a470-62c4e14d258a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484799804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3484799804
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3159514004
Short name T18
Test name
Test status
Simulation time 55552905 ps
CPU time 1.58 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:04 PM PDT 24
Peak memory 222804 kb
Host smart-7ee0d525-2b1d-4ad8-816b-372fe61d17aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159514004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3159514004
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2966496475
Short name T227
Test name
Test status
Simulation time 3072864653 ps
CPU time 54.62 seconds
Started Jul 09 07:01:37 PM PDT 24
Finished Jul 09 07:02:33 PM PDT 24
Peak memory 222444 kb
Host smart-8c969712-98fa-42e8-9d5e-c3acc4c64265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966496475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2966496475
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.4292258456
Short name T357
Test name
Test status
Simulation time 602672142 ps
CPU time 8.77 seconds
Started Jul 09 07:01:43 PM PDT 24
Finished Jul 09 07:01:55 PM PDT 24
Peak memory 215340 kb
Host smart-9599218e-d71b-4742-a92d-705ba8150166
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4292258456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.4292258456
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2388686651
Short name T3
Test name
Test status
Simulation time 386328424 ps
CPU time 4.06 seconds
Started Jul 09 07:01:03 PM PDT 24
Finished Jul 09 07:01:11 PM PDT 24
Peak memory 208824 kb
Host smart-9fb3d909-0939-40bc-94d3-f3837eee0d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388686651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2388686651
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3018604828
Short name T366
Test name
Test status
Simulation time 753457306 ps
CPU time 35.42 seconds
Started Jul 09 06:59:42 PM PDT 24
Finished Jul 09 07:00:19 PM PDT 24
Peak memory 214528 kb
Host smart-2b8243a6-d855-40da-a9d6-e48f75b25fee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3018604828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3018604828
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3502053129
Short name T672
Test name
Test status
Simulation time 368238426 ps
CPU time 1.98 seconds
Started Jul 09 07:00:22 PM PDT 24
Finished Jul 09 07:00:27 PM PDT 24
Peak memory 206140 kb
Host smart-9ac70986-c481-4dd1-b637-aa70e4385fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502053129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3502053129
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.717571689
Short name T33
Test name
Test status
Simulation time 8811106048 ps
CPU time 30.31 seconds
Started Jul 09 07:02:00 PM PDT 24
Finished Jul 09 07:02:33 PM PDT 24
Peak memory 211896 kb
Host smart-a1d725f0-2019-46e7-a4cc-0cc010ab18bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717571689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.717571689
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2612749908
Short name T49
Test name
Test status
Simulation time 19695627973 ps
CPU time 185.39 seconds
Started Jul 09 07:00:59 PM PDT 24
Finished Jul 09 07:04:08 PM PDT 24
Peak memory 222632 kb
Host smart-5cfd041c-c702-49a7-83a8-8ead280af544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612749908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2612749908
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1859708193
Short name T171
Test name
Test status
Simulation time 393456553 ps
CPU time 5.27 seconds
Started Jul 09 06:53:52 PM PDT 24
Finished Jul 09 06:53:58 PM PDT 24
Peak memory 205628 kb
Host smart-3fee1ef3-8400-41f5-9486-9d2866f5504e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859708193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1859708193
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2885840743
Short name T445
Test name
Test status
Simulation time 12767554 ps
CPU time 0.71 seconds
Started Jul 09 06:59:52 PM PDT 24
Finished Jul 09 06:59:54 PM PDT 24
Peak memory 206004 kb
Host smart-f4b88bb4-5f63-4bbd-a973-c906bf42a900
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885840743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2885840743
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1011660612
Short name T138
Test name
Test status
Simulation time 2279448210 ps
CPU time 26.23 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:29 PM PDT 24
Peak memory 223116 kb
Host smart-68912619-72ae-4f6d-82fd-bb119e930377
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011660612 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1011660612
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3429508604
Short name T51
Test name
Test status
Simulation time 80658580153 ps
CPU time 276.42 seconds
Started Jul 09 07:02:03 PM PDT 24
Finished Jul 09 07:06:41 PM PDT 24
Peak memory 216956 kb
Host smart-b5d6ea54-0f6d-4093-aa24-1317f2386237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429508604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3429508604
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_random.2261997219
Short name T210
Test name
Test status
Simulation time 3486658555 ps
CPU time 20.54 seconds
Started Jul 09 07:03:32 PM PDT 24
Finished Jul 09 07:03:55 PM PDT 24
Peak memory 209924 kb
Host smart-ca794ec1-124e-4d96-85a7-119cded1da0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261997219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2261997219
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2086392246
Short name T88
Test name
Test status
Simulation time 15753625022 ps
CPU time 93.3 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:01:41 PM PDT 24
Peak memory 216292 kb
Host smart-72091543-2716-4976-ae74-e49204427d72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086392246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2086392246
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1150950216
Short name T57
Test name
Test status
Simulation time 1137619944 ps
CPU time 20.2 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:32 PM PDT 24
Peak memory 222620 kb
Host smart-9fc6f406-ac9e-449d-8501-3748941526ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150950216 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1150950216
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.896255916
Short name T256
Test name
Test status
Simulation time 102616236 ps
CPU time 1.98 seconds
Started Jul 09 07:00:49 PM PDT 24
Finished Jul 09 07:00:53 PM PDT 24
Peak memory 214288 kb
Host smart-6f33e55d-5f5e-4902-97f0-724e8ac256a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896255916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.896255916
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1077853940
Short name T369
Test name
Test status
Simulation time 527384098 ps
CPU time 24.36 seconds
Started Jul 09 07:01:21 PM PDT 24
Finished Jul 09 07:01:48 PM PDT 24
Peak memory 215092 kb
Host smart-ffb3849b-fdc8-4c60-8e22-ab20c3a6711c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077853940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1077853940
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2620111209
Short name T308
Test name
Test status
Simulation time 78260668 ps
CPU time 4.67 seconds
Started Jul 09 07:02:03 PM PDT 24
Finished Jul 09 07:02:11 PM PDT 24
Peak memory 222508 kb
Host smart-8b4f616f-c88f-404d-a838-dfff2a012196
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2620111209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2620111209
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3510987113
Short name T334
Test name
Test status
Simulation time 428279286 ps
CPU time 4.9 seconds
Started Jul 09 07:00:51 PM PDT 24
Finished Jul 09 07:00:58 PM PDT 24
Peak memory 214392 kb
Host smart-98075d8c-ccfd-4c59-8837-9a8b33bc5299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510987113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3510987113
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.128316100
Short name T382
Test name
Test status
Simulation time 1415818666 ps
CPU time 38.75 seconds
Started Jul 09 07:01:59 PM PDT 24
Finished Jul 09 07:02:39 PM PDT 24
Peak memory 214328 kb
Host smart-7c065e5a-aebf-4613-977a-33201bb5d173
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=128316100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.128316100
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.530570506
Short name T392
Test name
Test status
Simulation time 69248498 ps
CPU time 2.24 seconds
Started Jul 09 07:02:06 PM PDT 24
Finished Jul 09 07:02:13 PM PDT 24
Peak memory 214292 kb
Host smart-d04c109d-68ff-47bb-bb57-769be9f20574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530570506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.530570506
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2685411312
Short name T165
Test name
Test status
Simulation time 146507829 ps
CPU time 4.56 seconds
Started Jul 09 06:54:25 PM PDT 24
Finished Jul 09 06:54:30 PM PDT 24
Peak memory 213756 kb
Host smart-327475bd-1285-49a8-aa12-970d0a457650
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685411312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2685411312
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.341274766
Short name T162
Test name
Test status
Simulation time 70059410 ps
CPU time 2.78 seconds
Started Jul 09 07:01:17 PM PDT 24
Finished Jul 09 07:01:23 PM PDT 24
Peak memory 210452 kb
Host smart-7dec9b94-4320-402f-8637-c07422100c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341274766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.341274766
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2391888251
Short name T166
Test name
Test status
Simulation time 179603894 ps
CPU time 3.79 seconds
Started Jul 09 06:54:36 PM PDT 24
Finished Jul 09 06:54:40 PM PDT 24
Peak memory 213764 kb
Host smart-22bcecfc-168f-4dde-a8d9-908eaa0b44c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391888251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2391888251
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2580813309
Short name T177
Test name
Test status
Simulation time 304381632 ps
CPU time 7.34 seconds
Started Jul 09 06:54:36 PM PDT 24
Finished Jul 09 06:54:45 PM PDT 24
Peak memory 205500 kb
Host smart-64488bf7-d703-4151-804c-79d6086bff10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580813309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2580813309
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2010704900
Short name T190
Test name
Test status
Simulation time 252210664 ps
CPU time 2.9 seconds
Started Jul 09 07:01:25 PM PDT 24
Finished Jul 09 07:01:29 PM PDT 24
Peak memory 222684 kb
Host smart-e2b48d99-e34a-4d70-a576-f38d0cea75da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010704900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2010704900
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2414889951
Short name T291
Test name
Test status
Simulation time 214392983 ps
CPU time 11.03 seconds
Started Jul 09 07:00:21 PM PDT 24
Finished Jul 09 07:00:35 PM PDT 24
Peak memory 222556 kb
Host smart-4f6a0fe1-0a65-4f54-b539-f7da74ea94fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414889951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2414889951
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3460967038
Short name T206
Test name
Test status
Simulation time 72005417 ps
CPU time 3.74 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:15 PM PDT 24
Peak memory 209928 kb
Host smart-03a00331-f398-48bc-8822-02d044f24712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460967038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3460967038
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1962849445
Short name T347
Test name
Test status
Simulation time 127617374 ps
CPU time 2.47 seconds
Started Jul 09 07:02:09 PM PDT 24
Finished Jul 09 07:02:17 PM PDT 24
Peak memory 207224 kb
Host smart-1cff7fcf-0867-4851-a599-3d9a3886c685
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962849445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1962849445
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1571397744
Short name T81
Test name
Test status
Simulation time 480067258 ps
CPU time 2.87 seconds
Started Jul 09 07:01:42 PM PDT 24
Finished Jul 09 07:01:48 PM PDT 24
Peak memory 213216 kb
Host smart-2dfddebf-ab55-415c-9f91-5063454a2403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571397744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1571397744
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1128094557
Short name T62
Test name
Test status
Simulation time 609302948 ps
CPU time 3.54 seconds
Started Jul 09 07:00:18 PM PDT 24
Finished Jul 09 07:00:26 PM PDT 24
Peak memory 210224 kb
Host smart-360b213d-3e58-4b70-b46a-cbaa5d675320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128094557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1128094557
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1475511902
Short name T243
Test name
Test status
Simulation time 334011288 ps
CPU time 11.54 seconds
Started Jul 09 07:00:18 PM PDT 24
Finished Jul 09 07:00:34 PM PDT 24
Peak memory 208516 kb
Host smart-6e94fed4-bfe2-4659-a787-0e09151600b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475511902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1475511902
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.577135455
Short name T106
Test name
Test status
Simulation time 1056343077 ps
CPU time 5.24 seconds
Started Jul 09 06:59:54 PM PDT 24
Finished Jul 09 07:00:00 PM PDT 24
Peak memory 214304 kb
Host smart-69a5823c-66ac-4d30-94bd-d4d17f9b5353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577135455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.577135455
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.4196949353
Short name T979
Test name
Test status
Simulation time 542584143 ps
CPU time 3.63 seconds
Started Jul 09 06:53:53 PM PDT 24
Finished Jul 09 06:53:58 PM PDT 24
Peak memory 214072 kb
Host smart-72a8481c-bf3a-4055-b9af-35a79356648e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196949353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.4196949353
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3007736085
Short name T178
Test name
Test status
Simulation time 249784240 ps
CPU time 9.68 seconds
Started Jul 09 06:54:24 PM PDT 24
Finished Jul 09 06:54:34 PM PDT 24
Peak memory 215040 kb
Host smart-dde03efd-8a37-44ce-b17d-62fedc2655ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007736085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3007736085
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3648388342
Short name T20
Test name
Test status
Simulation time 207502245 ps
CPU time 2.71 seconds
Started Jul 09 07:01:12 PM PDT 24
Finished Jul 09 07:01:18 PM PDT 24
Peak memory 216464 kb
Host smart-f263bae4-9159-4c50-ade8-382ed3ecf4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648388342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3648388342
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3241047959
Short name T189
Test name
Test status
Simulation time 923007910 ps
CPU time 16.56 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:24 PM PDT 24
Peak memory 222792 kb
Host smart-8e07773f-97b7-4360-ac01-b6847043743e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241047959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3241047959
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3961491586
Short name T239
Test name
Test status
Simulation time 78872718 ps
CPU time 1.7 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:00:20 PM PDT 24
Peak memory 209652 kb
Host smart-277788a3-2d95-4732-8c25-5506a629a87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961491586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3961491586
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2128640553
Short name T152
Test name
Test status
Simulation time 176345869 ps
CPU time 5.43 seconds
Started Jul 09 07:01:06 PM PDT 24
Finished Jul 09 07:01:16 PM PDT 24
Peak memory 215140 kb
Host smart-2af7668d-e4b1-4eef-a453-b58393b75e1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128640553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2128640553
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2145859277
Short name T160
Test name
Test status
Simulation time 396083275 ps
CPU time 11.29 seconds
Started Jul 09 07:02:14 PM PDT 24
Finished Jul 09 07:02:29 PM PDT 24
Peak memory 214980 kb
Host smart-ffe6a1a5-0fda-4875-b60e-cb515b39d949
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145859277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2145859277
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3704138795
Short name T85
Test name
Test status
Simulation time 8723466728 ps
CPU time 108.84 seconds
Started Jul 09 07:02:12 PM PDT 24
Finished Jul 09 07:04:05 PM PDT 24
Peak memory 216952 kb
Host smart-ec6a91a3-2914-4592-9ba1-653e34ed1ab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704138795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3704138795
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3924619236
Short name T169
Test name
Test status
Simulation time 394978703 ps
CPU time 8.7 seconds
Started Jul 09 06:54:02 PM PDT 24
Finished Jul 09 06:54:11 PM PDT 24
Peak memory 205560 kb
Host smart-77964df3-4509-4ae7-bd5f-4cd0f1d01b4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924619236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3924619236
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1522243551
Short name T66
Test name
Test status
Simulation time 97049648 ps
CPU time 3.47 seconds
Started Jul 09 06:59:44 PM PDT 24
Finished Jul 09 06:59:49 PM PDT 24
Peak memory 210332 kb
Host smart-93d2f874-9df7-4ff4-80e4-3257122d34d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522243551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1522243551
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.643484905
Short name T187
Test name
Test status
Simulation time 405581405 ps
CPU time 3.42 seconds
Started Jul 09 07:00:56 PM PDT 24
Finished Jul 09 07:01:03 PM PDT 24
Peak memory 217956 kb
Host smart-0151fa05-78e5-4c19-b546-36011ce3ad2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643484905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.643484905
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.75964592
Short name T188
Test name
Test status
Simulation time 374923788 ps
CPU time 4.78 seconds
Started Jul 09 07:02:08 PM PDT 24
Finished Jul 09 07:02:19 PM PDT 24
Peak memory 218652 kb
Host smart-5d930c4e-3743-41e7-8b00-0c5b2b0379f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75964592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.75964592
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2759786623
Short name T231
Test name
Test status
Simulation time 942046288 ps
CPU time 33.83 seconds
Started Jul 09 07:00:17 PM PDT 24
Finished Jul 09 07:00:55 PM PDT 24
Peak memory 215644 kb
Host smart-33dc9bed-1709-4856-aae9-87df1b2aefaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759786623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2759786623
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.4131787878
Short name T278
Test name
Test status
Simulation time 258800867 ps
CPU time 3.58 seconds
Started Jul 09 07:00:21 PM PDT 24
Finished Jul 09 07:00:28 PM PDT 24
Peak memory 214240 kb
Host smart-d7b8b119-9157-419f-bfcb-18fa7e383ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131787878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.4131787878
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1144412637
Short name T364
Test name
Test status
Simulation time 354149617 ps
CPU time 4.38 seconds
Started Jul 09 07:00:33 PM PDT 24
Finished Jul 09 07:00:38 PM PDT 24
Peak memory 210176 kb
Host smart-fbfe59a1-8e7d-43df-bb54-0f5a143c7eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144412637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1144412637
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3204577923
Short name T864
Test name
Test status
Simulation time 173621274 ps
CPU time 3.23 seconds
Started Jul 09 07:00:47 PM PDT 24
Finished Jul 09 07:00:52 PM PDT 24
Peak memory 214368 kb
Host smart-d26ecc68-432c-4e45-9ace-acdca6e1fc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204577923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3204577923
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.401216114
Short name T320
Test name
Test status
Simulation time 2109488162 ps
CPU time 17.06 seconds
Started Jul 09 07:00:56 PM PDT 24
Finished Jul 09 07:01:16 PM PDT 24
Peak memory 215984 kb
Host smart-fad145b1-ff1b-4c78-93c0-7a85fc510f26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401216114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.401216114
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1428850020
Short name T236
Test name
Test status
Simulation time 729305967 ps
CPU time 9.75 seconds
Started Jul 09 07:02:22 PM PDT 24
Finished Jul 09 07:02:33 PM PDT 24
Peak memory 222420 kb
Host smart-c946ce21-a038-4fb7-bb36-0ca9b33b8c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428850020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1428850020
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2028668995
Short name T310
Test name
Test status
Simulation time 1823410687 ps
CPU time 6.01 seconds
Started Jul 09 07:02:19 PM PDT 24
Finished Jul 09 07:02:27 PM PDT 24
Peak memory 222516 kb
Host smart-a0efd1d2-3030-4791-83d7-469ee33c958a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028668995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2028668995
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3934229334
Short name T327
Test name
Test status
Simulation time 599203313 ps
CPU time 5.64 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:07 PM PDT 24
Peak memory 218496 kb
Host smart-04585834-319f-4b9f-8645-9c3e0b9765f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934229334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3934229334
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.4253094739
Short name T185
Test name
Test status
Simulation time 249373332 ps
CPU time 3.95 seconds
Started Jul 09 06:53:52 PM PDT 24
Finished Jul 09 06:53:58 PM PDT 24
Peak memory 213656 kb
Host smart-aa0dd60c-9fb3-4b2b-9f01-cb31d3f39752
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253094739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.4253094739
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.301199632
Short name T174
Test name
Test status
Simulation time 52675740 ps
CPU time 2.98 seconds
Started Jul 09 06:54:30 PM PDT 24
Finished Jul 09 06:54:34 PM PDT 24
Peak memory 205632 kb
Host smart-9fd86a71-c658-41dd-bb51-1aeb7377346c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301199632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.301199632
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2898215029
Short name T815
Test name
Test status
Simulation time 39830563 ps
CPU time 2.37 seconds
Started Jul 09 06:59:36 PM PDT 24
Finished Jul 09 06:59:41 PM PDT 24
Peak memory 221008 kb
Host smart-8cc98de3-eef6-462e-86b1-664e7c09efa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898215029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2898215029
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1901069395
Short name T226
Test name
Test status
Simulation time 1265812970 ps
CPU time 3.62 seconds
Started Jul 09 06:59:39 PM PDT 24
Finished Jul 09 06:59:44 PM PDT 24
Peak memory 219880 kb
Host smart-f61e1fab-62f2-401a-ac0a-372967541212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901069395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1901069395
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.4268324038
Short name T381
Test name
Test status
Simulation time 2183272350 ps
CPU time 43.15 seconds
Started Jul 09 06:59:46 PM PDT 24
Finished Jul 09 07:00:31 PM PDT 24
Peak memory 215132 kb
Host smart-5e5fc67c-863a-4861-b752-9d048e3b54f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268324038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.4268324038
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3765374665
Short name T498
Test name
Test status
Simulation time 111950558 ps
CPU time 4.57 seconds
Started Jul 09 06:59:44 PM PDT 24
Finished Jul 09 06:59:50 PM PDT 24
Peak memory 206952 kb
Host smart-01bcfd81-a530-4655-9da2-d13627cd3f39
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765374665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3765374665
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.367724300
Short name T301
Test name
Test status
Simulation time 5542102072 ps
CPU time 39.29 seconds
Started Jul 09 07:00:22 PM PDT 24
Finished Jul 09 07:01:04 PM PDT 24
Peak memory 214504 kb
Host smart-175f38ff-0e6d-4eeb-b456-e81c5a3676b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367724300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.367724300
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.996998319
Short name T235
Test name
Test status
Simulation time 1168976612 ps
CPU time 17.26 seconds
Started Jul 09 07:00:31 PM PDT 24
Finished Jul 09 07:00:50 PM PDT 24
Peak memory 214424 kb
Host smart-47491540-d47b-426e-8bb5-8b8cc5e95455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996998319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.996998319
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3596213954
Short name T311
Test name
Test status
Simulation time 1924902952 ps
CPU time 6.34 seconds
Started Jul 09 07:00:42 PM PDT 24
Finished Jul 09 07:00:50 PM PDT 24
Peak memory 214236 kb
Host smart-cb362a0b-5d75-49bb-9241-eb03a0af5ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596213954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3596213954
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3247906287
Short name T217
Test name
Test status
Simulation time 26136272010 ps
CPU time 167.07 seconds
Started Jul 09 06:59:51 PM PDT 24
Finished Jul 09 07:02:40 PM PDT 24
Peak memory 216800 kb
Host smart-b8d71c1c-5719-4ffe-809e-9bcbb575fb9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247906287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3247906287
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3560621247
Short name T78
Test name
Test status
Simulation time 271814493 ps
CPU time 2.45 seconds
Started Jul 09 07:00:51 PM PDT 24
Finished Jul 09 07:00:56 PM PDT 24
Peak memory 214340 kb
Host smart-a95f8ae2-62d7-424e-ae94-15c5a3dd49f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560621247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3560621247
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.559385516
Short name T427
Test name
Test status
Simulation time 178072417 ps
CPU time 3.37 seconds
Started Jul 09 07:00:59 PM PDT 24
Finished Jul 09 07:01:06 PM PDT 24
Peak memory 214316 kb
Host smart-7da70470-cafd-4055-a4d3-76d1c9b70319
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=559385516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.559385516
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.470895284
Short name T40
Test name
Test status
Simulation time 473749288 ps
CPU time 11.27 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:22 PM PDT 24
Peak memory 214272 kb
Host smart-a2153147-f66f-4e6d-92f5-d1522d35d3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470895284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.470895284
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2697030262
Short name T355
Test name
Test status
Simulation time 433319931 ps
CPU time 3.52 seconds
Started Jul 09 07:01:12 PM PDT 24
Finished Jul 09 07:01:19 PM PDT 24
Peak memory 214252 kb
Host smart-67c5ba9d-a5d5-4d11-acfd-d34255939f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697030262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2697030262
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2160579801
Short name T257
Test name
Test status
Simulation time 77798397 ps
CPU time 2.31 seconds
Started Jul 09 07:01:22 PM PDT 24
Finished Jul 09 07:01:27 PM PDT 24
Peak memory 214268 kb
Host smart-2ceb1011-e4fc-4e48-908f-ebda2824e4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160579801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2160579801
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2464108043
Short name T154
Test name
Test status
Simulation time 81662328 ps
CPU time 4.86 seconds
Started Jul 09 07:01:47 PM PDT 24
Finished Jul 09 07:01:54 PM PDT 24
Peak memory 215332 kb
Host smart-5ce2a3fd-50ae-485d-b527-2f1ae03aaef5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464108043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2464108043
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3598742548
Short name T372
Test name
Test status
Simulation time 109339007 ps
CPU time 3.47 seconds
Started Jul 09 07:01:48 PM PDT 24
Finished Jul 09 07:01:54 PM PDT 24
Peak memory 222496 kb
Host smart-0225250a-f6db-44b0-bfad-854ce9792fcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3598742548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3598742548
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2048563876
Short name T8
Test name
Test status
Simulation time 117881234 ps
CPU time 4.34 seconds
Started Jul 09 07:02:00 PM PDT 24
Finished Jul 09 07:02:07 PM PDT 24
Peak memory 210072 kb
Host smart-6adef921-4a2a-4294-9320-712b1f60ce34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048563876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2048563876
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2817905865
Short name T150
Test name
Test status
Simulation time 4025053260 ps
CPU time 51.88 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:01:10 PM PDT 24
Peak memory 214856 kb
Host smart-ba6d292d-22d5-48dc-a640-960261a3631b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2817905865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2817905865
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.4091346132
Short name T186
Test name
Test status
Simulation time 144596353 ps
CPU time 3.33 seconds
Started Jul 09 07:01:56 PM PDT 24
Finished Jul 09 07:02:01 PM PDT 24
Peak memory 222728 kb
Host smart-5b539528-b2c5-4ce9-859d-2c725689b8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091346132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.4091346132
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1326630176
Short name T199
Test name
Test status
Simulation time 3503585399 ps
CPU time 6.27 seconds
Started Jul 09 06:53:53 PM PDT 24
Finished Jul 09 06:54:01 PM PDT 24
Peak memory 205644 kb
Host smart-8551bd7a-fca4-4c84-8f9a-f2c88e34b292
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326630176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
326630176
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3218812205
Short name T1007
Test name
Test status
Simulation time 510827694 ps
CPU time 7.89 seconds
Started Jul 09 06:53:54 PM PDT 24
Finished Jul 09 06:54:03 PM PDT 24
Peak memory 205544 kb
Host smart-c51e7970-251b-4f8e-b8f8-b702cca6acbf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218812205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
218812205
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1526343659
Short name T932
Test name
Test status
Simulation time 28908385 ps
CPU time 1.24 seconds
Started Jul 09 06:53:52 PM PDT 24
Finished Jul 09 06:53:55 PM PDT 24
Peak memory 205568 kb
Host smart-30a432d0-bcec-4fa0-80b8-d71c0a9162c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526343659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
526343659
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1858259043
Short name T1066
Test name
Test status
Simulation time 25468236 ps
CPU time 1.4 seconds
Started Jul 09 06:53:52 PM PDT 24
Finished Jul 09 06:53:54 PM PDT 24
Peak memory 205780 kb
Host smart-b2ddbeaa-4051-4fa3-b4be-41626ec41dd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858259043 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1858259043
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.253294432
Short name T933
Test name
Test status
Simulation time 8790104 ps
CPU time 0.92 seconds
Started Jul 09 06:53:52 PM PDT 24
Finished Jul 09 06:53:54 PM PDT 24
Peak memory 205448 kb
Host smart-e8fe1630-3249-45fd-a26a-c898ef5e55fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253294432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.253294432
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.4035937053
Short name T1047
Test name
Test status
Simulation time 11529093 ps
CPU time 0.74 seconds
Started Jul 09 06:53:52 PM PDT 24
Finished Jul 09 06:53:54 PM PDT 24
Peak memory 205352 kb
Host smart-64138485-22b1-4e1d-98cd-29f362f0e47a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035937053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.4035937053
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2187076247
Short name T988
Test name
Test status
Simulation time 41249240 ps
CPU time 1.48 seconds
Started Jul 09 06:53:52 PM PDT 24
Finished Jul 09 06:53:55 PM PDT 24
Peak memory 205564 kb
Host smart-e7375012-3074-4423-ad49-49a26dea285d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187076247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2187076247
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.346027640
Short name T1073
Test name
Test status
Simulation time 474299464 ps
CPU time 8.11 seconds
Started Jul 09 06:53:52 PM PDT 24
Finished Jul 09 06:54:02 PM PDT 24
Peak memory 213980 kb
Host smart-f64aa3bf-d373-4706-bb0c-8877834467f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346027640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.346027640
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2084837211
Short name T970
Test name
Test status
Simulation time 190507765 ps
CPU time 1.71 seconds
Started Jul 09 06:53:52 PM PDT 24
Finished Jul 09 06:53:56 PM PDT 24
Peak memory 213884 kb
Host smart-4a214169-74a8-493f-ac64-b0f6bcca0ae0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084837211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2084837211
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3009558486
Short name T939
Test name
Test status
Simulation time 725514795 ps
CPU time 10.3 seconds
Started Jul 09 06:53:55 PM PDT 24
Finished Jul 09 06:54:07 PM PDT 24
Peak memory 205592 kb
Host smart-5ac52188-d7d7-4a34-8c0c-02cdbb7da99a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009558486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
009558486
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.285309329
Short name T1070
Test name
Test status
Simulation time 135467243 ps
CPU time 6.36 seconds
Started Jul 09 06:53:59 PM PDT 24
Finished Jul 09 06:54:06 PM PDT 24
Peak memory 205408 kb
Host smart-4cc041ea-b0f9-41a3-acb2-75082be9618b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285309329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.285309329
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2635042229
Short name T934
Test name
Test status
Simulation time 253811907 ps
CPU time 1.45 seconds
Started Jul 09 06:53:52 PM PDT 24
Finished Jul 09 06:53:55 PM PDT 24
Peak memory 205536 kb
Host smart-bd3c0c8f-62c3-45a5-982d-98fbc2726bfa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635042229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
635042229
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.407513383
Short name T1044
Test name
Test status
Simulation time 146869145 ps
CPU time 2.02 seconds
Started Jul 09 06:53:58 PM PDT 24
Finished Jul 09 06:54:01 PM PDT 24
Peak memory 213844 kb
Host smart-6033eabf-7e47-46e4-ac4f-3cacbb0878ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407513383 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.407513383
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1910812085
Short name T158
Test name
Test status
Simulation time 29636638 ps
CPU time 1.28 seconds
Started Jul 09 06:53:58 PM PDT 24
Finished Jul 09 06:54:01 PM PDT 24
Peak memory 205476 kb
Host smart-0bcf47ca-46b1-4ea3-ae0b-328fce5cf30f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910812085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1910812085
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1441902613
Short name T1075
Test name
Test status
Simulation time 9453346 ps
CPU time 0.79 seconds
Started Jul 09 06:53:53 PM PDT 24
Finished Jul 09 06:53:55 PM PDT 24
Peak memory 205404 kb
Host smart-93a7bdc2-fc50-4e20-898b-3716640b2e19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441902613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1441902613
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3300022833
Short name T156
Test name
Test status
Simulation time 184244237 ps
CPU time 2.87 seconds
Started Jul 09 06:53:56 PM PDT 24
Finished Jul 09 06:54:01 PM PDT 24
Peak memory 205552 kb
Host smart-da1467c4-2001-4cf9-b032-75528f6c1a9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300022833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3300022833
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3799763608
Short name T1017
Test name
Test status
Simulation time 275309970 ps
CPU time 1.94 seconds
Started Jul 09 06:53:50 PM PDT 24
Finished Jul 09 06:53:53 PM PDT 24
Peak memory 213952 kb
Host smart-5f1235c3-3619-40d6-829e-99d58c293075
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799763608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3799763608
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.916865834
Short name T992
Test name
Test status
Simulation time 163717359 ps
CPU time 4.42 seconds
Started Jul 09 06:53:53 PM PDT 24
Finished Jul 09 06:53:59 PM PDT 24
Peak memory 214060 kb
Host smart-3e1b8f50-99d1-4093-8b6b-78a104e9a2db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916865834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.916865834
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1153032212
Short name T1029
Test name
Test status
Simulation time 306890567 ps
CPU time 3.1 seconds
Started Jul 09 06:53:54 PM PDT 24
Finished Jul 09 06:53:58 PM PDT 24
Peak memory 213720 kb
Host smart-1865dd4e-81e5-4476-84ae-aa3377404fa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153032212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1153032212
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3254167686
Short name T1078
Test name
Test status
Simulation time 119309256 ps
CPU time 1.44 seconds
Started Jul 09 06:54:27 PM PDT 24
Finished Jul 09 06:54:29 PM PDT 24
Peak memory 205624 kb
Host smart-bae29778-6464-40ac-ba3d-6c576104d383
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254167686 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3254167686
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2900438505
Short name T947
Test name
Test status
Simulation time 36643377 ps
CPU time 1.01 seconds
Started Jul 09 06:54:27 PM PDT 24
Finished Jul 09 06:54:29 PM PDT 24
Peak memory 205540 kb
Host smart-1f9ea9be-cd25-4baf-9b31-a897098a4533
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900438505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2900438505
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.4166173676
Short name T980
Test name
Test status
Simulation time 10742113 ps
CPU time 0.83 seconds
Started Jul 09 06:54:27 PM PDT 24
Finished Jul 09 06:54:29 PM PDT 24
Peak memory 205360 kb
Host smart-38d76566-0c2f-4d6b-a153-1821fb80c125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166173676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.4166173676
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.782355410
Short name T1036
Test name
Test status
Simulation time 116851992 ps
CPU time 3.92 seconds
Started Jul 09 06:54:28 PM PDT 24
Finished Jul 09 06:54:33 PM PDT 24
Peak memory 205588 kb
Host smart-62ce2594-34cc-4c1f-8abe-71f891e361f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782355410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.782355410
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.833567229
Short name T1053
Test name
Test status
Simulation time 653535492 ps
CPU time 5.21 seconds
Started Jul 09 06:54:24 PM PDT 24
Finished Jul 09 06:54:30 PM PDT 24
Peak memory 214052 kb
Host smart-ad2df412-296d-4a24-83dc-9ebc3095ec06
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833567229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.833567229
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1205187225
Short name T954
Test name
Test status
Simulation time 2087103997 ps
CPU time 8.31 seconds
Started Jul 09 06:54:26 PM PDT 24
Finished Jul 09 06:54:35 PM PDT 24
Peak memory 214072 kb
Host smart-68479d0d-cced-459d-a066-d8e446b4f318
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205187225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1205187225
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2230394609
Short name T918
Test name
Test status
Simulation time 195561567 ps
CPU time 4.02 seconds
Started Jul 09 06:54:25 PM PDT 24
Finished Jul 09 06:54:29 PM PDT 24
Peak memory 213780 kb
Host smart-6e6b9ca6-bf23-4c20-8c19-698f7c509f9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230394609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2230394609
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2266204600
Short name T1037
Test name
Test status
Simulation time 825436962 ps
CPU time 6.86 seconds
Started Jul 09 06:54:25 PM PDT 24
Finished Jul 09 06:54:33 PM PDT 24
Peak memory 213800 kb
Host smart-428b56aa-cc91-4c20-b12f-6cf307885004
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266204600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2266204600
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3231029025
Short name T1035
Test name
Test status
Simulation time 200179017 ps
CPU time 2.17 seconds
Started Jul 09 06:54:24 PM PDT 24
Finished Jul 09 06:54:27 PM PDT 24
Peak memory 213852 kb
Host smart-d243b3bf-54ca-42d6-abbf-12d6d1b325c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231029025 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3231029025
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3567395877
Short name T953
Test name
Test status
Simulation time 27095361 ps
CPU time 1.16 seconds
Started Jul 09 06:54:29 PM PDT 24
Finished Jul 09 06:54:31 PM PDT 24
Peak memory 205524 kb
Host smart-8b9b916c-7c94-4367-9bfd-99cf51a098db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567395877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3567395877
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1336856467
Short name T935
Test name
Test status
Simulation time 46591114 ps
CPU time 0.72 seconds
Started Jul 09 06:54:26 PM PDT 24
Finished Jul 09 06:54:28 PM PDT 24
Peak memory 205344 kb
Host smart-4d45ab7c-315c-428d-8f6a-95bc2ee12966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336856467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1336856467
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.466920479
Short name T1039
Test name
Test status
Simulation time 224062768 ps
CPU time 2.26 seconds
Started Jul 09 06:54:26 PM PDT 24
Finished Jul 09 06:54:28 PM PDT 24
Peak memory 205516 kb
Host smart-c056b0bf-b60e-4439-b4d3-45ab8b6c9ae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466920479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.466920479
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1830286763
Short name T978
Test name
Test status
Simulation time 536983766 ps
CPU time 4.15 seconds
Started Jul 09 06:54:29 PM PDT 24
Finished Jul 09 06:54:35 PM PDT 24
Peak memory 214052 kb
Host smart-6d8a708d-fedd-4acf-8f93-376ea138d98a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830286763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1830286763
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2607376091
Short name T129
Test name
Test status
Simulation time 79656906 ps
CPU time 3.65 seconds
Started Jul 09 06:54:25 PM PDT 24
Finished Jul 09 06:54:29 PM PDT 24
Peak memory 214140 kb
Host smart-7281bbcf-a398-4b2b-b9c5-e94de118e429
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607376091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2607376091
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.677389254
Short name T1061
Test name
Test status
Simulation time 72941078 ps
CPU time 2.86 seconds
Started Jul 09 06:54:26 PM PDT 24
Finished Jul 09 06:54:30 PM PDT 24
Peak memory 216880 kb
Host smart-2703b4f1-9ebf-4d45-acfd-8963664f02ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677389254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.677389254
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3620580506
Short name T1057
Test name
Test status
Simulation time 80108739 ps
CPU time 1.67 seconds
Started Jul 09 06:54:33 PM PDT 24
Finished Jul 09 06:54:36 PM PDT 24
Peak memory 213876 kb
Host smart-0493d516-1107-44e7-bfa3-bc1059fda567
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620580506 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3620580506
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2069985282
Short name T994
Test name
Test status
Simulation time 102163800 ps
CPU time 1.35 seconds
Started Jul 09 06:54:28 PM PDT 24
Finished Jul 09 06:54:31 PM PDT 24
Peak memory 205520 kb
Host smart-8285ed92-6be7-4361-bea4-417655403ce3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069985282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2069985282
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2023273093
Short name T1025
Test name
Test status
Simulation time 35196242 ps
CPU time 0.73 seconds
Started Jul 09 06:54:27 PM PDT 24
Finished Jul 09 06:54:29 PM PDT 24
Peak memory 205300 kb
Host smart-3041ef0b-ad74-4f8d-ac63-f8df741cbdc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023273093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2023273093
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.708298604
Short name T1082
Test name
Test status
Simulation time 219738269 ps
CPU time 1.49 seconds
Started Jul 09 06:54:28 PM PDT 24
Finished Jul 09 06:54:31 PM PDT 24
Peak memory 205596 kb
Host smart-f9c55eda-081b-4a09-8a18-19adb8891d1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708298604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.708298604
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2782443362
Short name T1076
Test name
Test status
Simulation time 657136217 ps
CPU time 3.13 seconds
Started Jul 09 06:54:26 PM PDT 24
Finished Jul 09 06:54:30 PM PDT 24
Peak memory 214068 kb
Host smart-b96df148-f547-4667-b286-6afeb365be68
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782443362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2782443362
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1851083920
Short name T1064
Test name
Test status
Simulation time 544231250 ps
CPU time 7.89 seconds
Started Jul 09 06:54:22 PM PDT 24
Finished Jul 09 06:54:31 PM PDT 24
Peak memory 214044 kb
Host smart-e9376442-4364-4a5b-9388-765a9c98315b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851083920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1851083920
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3484786087
Short name T931
Test name
Test status
Simulation time 169660373 ps
CPU time 2.84 seconds
Started Jul 09 06:54:24 PM PDT 24
Finished Jul 09 06:54:27 PM PDT 24
Peak memory 216564 kb
Host smart-53eb276c-23be-4b66-88df-e584b76b74b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484786087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3484786087
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.480423981
Short name T963
Test name
Test status
Simulation time 223441733 ps
CPU time 1.67 seconds
Started Jul 09 06:54:32 PM PDT 24
Finished Jul 09 06:54:35 PM PDT 24
Peak memory 213812 kb
Host smart-e0002c65-61ca-42fb-a009-9934907c79b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480423981 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.480423981
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1177862696
Short name T977
Test name
Test status
Simulation time 95265918 ps
CPU time 1.15 seconds
Started Jul 09 06:54:32 PM PDT 24
Finished Jul 09 06:54:34 PM PDT 24
Peak memory 205556 kb
Host smart-1fe714a5-6f96-48c0-9c4f-433bdc990895
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177862696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1177862696
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1853621412
Short name T983
Test name
Test status
Simulation time 15289862 ps
CPU time 0.79 seconds
Started Jul 09 06:54:31 PM PDT 24
Finished Jul 09 06:54:33 PM PDT 24
Peak memory 205308 kb
Host smart-bc7db200-48e0-49a1-83a8-e35705f2b0b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853621412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1853621412
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2011133025
Short name T157
Test name
Test status
Simulation time 121673619 ps
CPU time 2.69 seconds
Started Jul 09 06:54:32 PM PDT 24
Finished Jul 09 06:54:35 PM PDT 24
Peak memory 205564 kb
Host smart-3e55c9b6-875a-452a-a733-e756aeeb412c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011133025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2011133025
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1319090944
Short name T127
Test name
Test status
Simulation time 404454768 ps
CPU time 1.68 seconds
Started Jul 09 06:54:32 PM PDT 24
Finished Jul 09 06:54:34 PM PDT 24
Peak memory 214040 kb
Host smart-66395d6f-ec55-498b-8b2a-eef913fb0b37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319090944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1319090944
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3967375407
Short name T124
Test name
Test status
Simulation time 771295130 ps
CPU time 5.28 seconds
Started Jul 09 06:54:31 PM PDT 24
Finished Jul 09 06:54:37 PM PDT 24
Peak memory 220136 kb
Host smart-0b3dab8a-44f5-4d17-9f5b-b4614cac26f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967375407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3967375407
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3566822694
Short name T989
Test name
Test status
Simulation time 351759856 ps
CPU time 2.78 seconds
Started Jul 09 06:54:33 PM PDT 24
Finished Jul 09 06:54:36 PM PDT 24
Peak memory 213848 kb
Host smart-6bec7fc7-e427-485f-924f-0ced25c705ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566822694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3566822694
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.771834568
Short name T395
Test name
Test status
Simulation time 134482742 ps
CPU time 3.84 seconds
Started Jul 09 06:54:33 PM PDT 24
Finished Jul 09 06:54:38 PM PDT 24
Peak memory 205556 kb
Host smart-d124e13d-2024-4e49-b1bb-322eaeab4653
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771834568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.771834568
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1759021677
Short name T1002
Test name
Test status
Simulation time 64793263 ps
CPU time 1.06 seconds
Started Jul 09 06:54:28 PM PDT 24
Finished Jul 09 06:54:30 PM PDT 24
Peak memory 205616 kb
Host smart-cf69974c-ac14-4fbf-85ea-f88eef8bb9d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759021677 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1759021677
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2915223391
Short name T163
Test name
Test status
Simulation time 25208109 ps
CPU time 1.16 seconds
Started Jul 09 06:54:30 PM PDT 24
Finished Jul 09 06:54:33 PM PDT 24
Peak memory 205412 kb
Host smart-87b24098-19ff-4d59-92a8-29dc33bd8a1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915223391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2915223391
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2890854236
Short name T976
Test name
Test status
Simulation time 21412765 ps
CPU time 0.81 seconds
Started Jul 09 06:54:30 PM PDT 24
Finished Jul 09 06:54:32 PM PDT 24
Peak memory 205308 kb
Host smart-7841ef1a-5cb7-4bbd-bff5-89577b2abf53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890854236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2890854236
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.814965007
Short name T946
Test name
Test status
Simulation time 73082605 ps
CPU time 2.52 seconds
Started Jul 09 06:54:31 PM PDT 24
Finished Jul 09 06:54:35 PM PDT 24
Peak memory 205528 kb
Host smart-55fabcdd-3424-4390-a4a7-ec361937fffd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814965007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.814965007
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3714998471
Short name T1056
Test name
Test status
Simulation time 148767828 ps
CPU time 1.87 seconds
Started Jul 09 06:54:30 PM PDT 24
Finished Jul 09 06:54:33 PM PDT 24
Peak memory 214008 kb
Host smart-40d96c24-cd0d-412c-9c39-9021cc0ee47a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714998471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3714998471
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3921656133
Short name T132
Test name
Test status
Simulation time 1771129412 ps
CPU time 15.78 seconds
Started Jul 09 06:54:30 PM PDT 24
Finished Jul 09 06:54:47 PM PDT 24
Peak memory 213688 kb
Host smart-9dd3d88a-3c09-4db6-8595-31ace17fe276
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921656133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3921656133
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2005076025
Short name T929
Test name
Test status
Simulation time 263401605 ps
CPU time 3.72 seconds
Started Jul 09 06:54:33 PM PDT 24
Finished Jul 09 06:54:38 PM PDT 24
Peak memory 221856 kb
Host smart-d8b2b53b-f177-4c46-a8d9-e4d8797b34ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005076025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2005076025
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1196075736
Short name T962
Test name
Test status
Simulation time 68196312 ps
CPU time 1.2 seconds
Started Jul 09 06:54:40 PM PDT 24
Finished Jul 09 06:54:43 PM PDT 24
Peak memory 213848 kb
Host smart-15005037-4c0b-4e81-9d94-1827d86f5699
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196075736 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1196075736
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.4056917423
Short name T155
Test name
Test status
Simulation time 19326277 ps
CPU time 0.95 seconds
Started Jul 09 06:54:35 PM PDT 24
Finished Jul 09 06:54:37 PM PDT 24
Peak memory 205480 kb
Host smart-68743219-c927-4896-bab7-4f9dfe8ee8b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056917423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.4056917423
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.4126074351
Short name T981
Test name
Test status
Simulation time 20982013 ps
CPU time 0.69 seconds
Started Jul 09 06:54:35 PM PDT 24
Finished Jul 09 06:54:37 PM PDT 24
Peak memory 205376 kb
Host smart-e168cdde-c576-4174-b62d-8f7c3980c62b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126074351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.4126074351
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.520831768
Short name T1052
Test name
Test status
Simulation time 83967338 ps
CPU time 2.09 seconds
Started Jul 09 06:54:35 PM PDT 24
Finished Jul 09 06:54:38 PM PDT 24
Peak memory 205524 kb
Host smart-62494595-2575-43cf-b36a-46a7a4c37eb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520831768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.520831768
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3537647469
Short name T964
Test name
Test status
Simulation time 380610608 ps
CPU time 2.78 seconds
Started Jul 09 06:54:29 PM PDT 24
Finished Jul 09 06:54:33 PM PDT 24
Peak memory 214036 kb
Host smart-09058c43-34c9-4366-b544-38ed3b1ccca9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537647469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3537647469
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1961436062
Short name T961
Test name
Test status
Simulation time 132148825 ps
CPU time 7.4 seconds
Started Jul 09 06:54:33 PM PDT 24
Finished Jul 09 06:54:41 PM PDT 24
Peak memory 220108 kb
Host smart-269224e4-4690-4680-bac4-1c2411b14301
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961436062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1961436062
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1816375578
Short name T925
Test name
Test status
Simulation time 248098173 ps
CPU time 1.94 seconds
Started Jul 09 06:54:29 PM PDT 24
Finished Jul 09 06:54:32 PM PDT 24
Peak memory 216928 kb
Host smart-4299fdcf-acce-49c6-90aa-ddd19d48a948
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816375578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1816375578
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.31702061
Short name T173
Test name
Test status
Simulation time 304088399 ps
CPU time 3.71 seconds
Started Jul 09 06:54:36 PM PDT 24
Finished Jul 09 06:54:41 PM PDT 24
Peak memory 205572 kb
Host smart-c9984a93-6a83-48d8-91b4-b8ee1c618443
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31702061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.31702061
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2729513130
Short name T924
Test name
Test status
Simulation time 613234640 ps
CPU time 2.05 seconds
Started Jul 09 06:54:35 PM PDT 24
Finished Jul 09 06:54:38 PM PDT 24
Peak memory 205704 kb
Host smart-d815c6af-8832-45fa-83d6-cf96f45e6d0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729513130 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2729513130
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.989423088
Short name T399
Test name
Test status
Simulation time 17897727 ps
CPU time 0.93 seconds
Started Jul 09 06:54:36 PM PDT 24
Finished Jul 09 06:54:38 PM PDT 24
Peak memory 205504 kb
Host smart-f226b0f3-bfba-40a9-bf87-b50aec5a06b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989423088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.989423088
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2784854052
Short name T1008
Test name
Test status
Simulation time 28195440 ps
CPU time 1.02 seconds
Started Jul 09 06:54:32 PM PDT 24
Finished Jul 09 06:54:33 PM PDT 24
Peak memory 205608 kb
Host smart-0a82b698-ad28-4c45-9afa-1f1d01a5458a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784854052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2784854052
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3264860034
Short name T1068
Test name
Test status
Simulation time 189254040 ps
CPU time 4.33 seconds
Started Jul 09 06:54:34 PM PDT 24
Finished Jul 09 06:54:40 PM PDT 24
Peak memory 205508 kb
Host smart-c381e7da-c5cd-4eda-ac8a-1d0b1ee93802
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264860034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3264860034
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.705051200
Short name T1045
Test name
Test status
Simulation time 151322046 ps
CPU time 6.4 seconds
Started Jul 09 06:54:38 PM PDT 24
Finished Jul 09 06:54:45 PM PDT 24
Peak memory 220620 kb
Host smart-d30a29f4-9db5-41c6-85d7-4bbb9fc8b5af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705051200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.705051200
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1069015392
Short name T195
Test name
Test status
Simulation time 316521500 ps
CPU time 2.06 seconds
Started Jul 09 06:54:38 PM PDT 24
Finished Jul 09 06:54:41 PM PDT 24
Peak memory 213732 kb
Host smart-eac26889-06c1-4ba9-91e6-65a2feb537d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069015392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1069015392
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.284158257
Short name T1081
Test name
Test status
Simulation time 32501902 ps
CPU time 1.82 seconds
Started Jul 09 06:54:36 PM PDT 24
Finished Jul 09 06:54:39 PM PDT 24
Peak memory 213872 kb
Host smart-2ec9db8c-6b6e-4645-b75c-5f3559ce4be4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284158257 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.284158257
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.4268464855
Short name T1006
Test name
Test status
Simulation time 102050165 ps
CPU time 0.89 seconds
Started Jul 09 06:54:35 PM PDT 24
Finished Jul 09 06:54:37 PM PDT 24
Peak memory 205424 kb
Host smart-2127b4cd-3d9e-4459-b0b7-c2ee43a32cd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268464855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.4268464855
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2724334214
Short name T941
Test name
Test status
Simulation time 18671300 ps
CPU time 0.88 seconds
Started Jul 09 06:54:36 PM PDT 24
Finished Jul 09 06:54:39 PM PDT 24
Peak memory 205280 kb
Host smart-575dc008-c132-4bfd-bd2c-dd3c412732d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724334214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2724334214
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1562675418
Short name T990
Test name
Test status
Simulation time 623525748 ps
CPU time 2.79 seconds
Started Jul 09 06:54:35 PM PDT 24
Finished Jul 09 06:54:38 PM PDT 24
Peak memory 205600 kb
Host smart-1ddca7c7-abe4-4eca-851a-4aa91a11195a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562675418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1562675418
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.286425702
Short name T973
Test name
Test status
Simulation time 77068974 ps
CPU time 1.46 seconds
Started Jul 09 06:54:41 PM PDT 24
Finished Jul 09 06:54:45 PM PDT 24
Peak memory 214088 kb
Host smart-5d74cfea-3f17-4e1c-8699-6621dfb3e942
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286425702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.286425702
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.999892710
Short name T942
Test name
Test status
Simulation time 283184935 ps
CPU time 3.71 seconds
Started Jul 09 06:54:37 PM PDT 24
Finished Jul 09 06:54:42 PM PDT 24
Peak memory 214108 kb
Host smart-c9eb0743-d247-4df2-bdef-ba132f8d1d2d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999892710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.999892710
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3487434101
Short name T927
Test name
Test status
Simulation time 390663275 ps
CPU time 2.66 seconds
Started Jul 09 06:54:36 PM PDT 24
Finished Jul 09 06:54:40 PM PDT 24
Peak memory 214908 kb
Host smart-5f3f1ddb-e988-4431-8ee2-aaccf9faf3a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487434101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3487434101
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.439746445
Short name T922
Test name
Test status
Simulation time 33878602 ps
CPU time 1.35 seconds
Started Jul 09 06:54:41 PM PDT 24
Finished Jul 09 06:54:44 PM PDT 24
Peak memory 213872 kb
Host smart-f38fef5a-b89d-422f-ac0e-ec0ccf51c1f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439746445 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.439746445
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3597557616
Short name T1012
Test name
Test status
Simulation time 35933831 ps
CPU time 1.35 seconds
Started Jul 09 06:54:38 PM PDT 24
Finished Jul 09 06:54:40 PM PDT 24
Peak memory 205568 kb
Host smart-ea420cf1-a3a2-4dbb-bc5a-d604d1d69de8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597557616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3597557616
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2767318635
Short name T930
Test name
Test status
Simulation time 10336620 ps
CPU time 0.72 seconds
Started Jul 09 06:54:34 PM PDT 24
Finished Jul 09 06:54:36 PM PDT 24
Peak memory 205268 kb
Host smart-e15ea749-2193-4a83-b245-0d3e0f921fbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767318635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2767318635
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2174730791
Short name T1058
Test name
Test status
Simulation time 362036974 ps
CPU time 3.29 seconds
Started Jul 09 06:54:39 PM PDT 24
Finished Jul 09 06:54:44 PM PDT 24
Peak memory 205532 kb
Host smart-b78c8e5b-b794-425a-80ae-1bfc80eef24e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174730791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2174730791
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1052633594
Short name T1034
Test name
Test status
Simulation time 81092773 ps
CPU time 1.85 seconds
Started Jul 09 06:54:36 PM PDT 24
Finished Jul 09 06:54:39 PM PDT 24
Peak memory 214148 kb
Host smart-7441980d-8b45-44cc-b407-01a0437cbb39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052633594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1052633594
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.720053040
Short name T1041
Test name
Test status
Simulation time 1823109467 ps
CPU time 4.85 seconds
Started Jul 09 06:54:36 PM PDT 24
Finished Jul 09 06:54:43 PM PDT 24
Peak memory 214016 kb
Host smart-09be92a7-1718-45b4-a24d-9325a9b36a6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720053040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.720053040
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.4098925754
Short name T1051
Test name
Test status
Simulation time 336867255 ps
CPU time 2.46 seconds
Started Jul 09 06:54:36 PM PDT 24
Finished Jul 09 06:54:40 PM PDT 24
Peak memory 213832 kb
Host smart-70bc85e8-9368-4f80-87e8-5c650732db30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098925754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.4098925754
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.378363044
Short name T179
Test name
Test status
Simulation time 947492630 ps
CPU time 5.54 seconds
Started Jul 09 06:54:39 PM PDT 24
Finished Jul 09 06:54:46 PM PDT 24
Peak memory 213796 kb
Host smart-862ca575-1f19-494d-93c2-fe3085a652e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378363044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.378363044
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.571340531
Short name T1024
Test name
Test status
Simulation time 452774315 ps
CPU time 1.89 seconds
Started Jul 09 06:54:41 PM PDT 24
Finished Jul 09 06:54:46 PM PDT 24
Peak memory 214016 kb
Host smart-2d35b461-7bf8-467a-950d-b99d994c6e1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571340531 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.571340531
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1358457588
Short name T1067
Test name
Test status
Simulation time 23668717 ps
CPU time 1.06 seconds
Started Jul 09 06:54:42 PM PDT 24
Finished Jul 09 06:54:47 PM PDT 24
Peak memory 205540 kb
Host smart-ff9d79ad-adf2-4454-9f22-2eb2f71ca259
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358457588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1358457588
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1022325079
Short name T993
Test name
Test status
Simulation time 41276855 ps
CPU time 0.76 seconds
Started Jul 09 06:54:41 PM PDT 24
Finished Jul 09 06:54:45 PM PDT 24
Peak memory 205284 kb
Host smart-4c037a8d-2218-4b0c-ad5e-a70627c862e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022325079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1022325079
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3467288757
Short name T1005
Test name
Test status
Simulation time 490831274 ps
CPU time 3.79 seconds
Started Jul 09 06:54:44 PM PDT 24
Finished Jul 09 06:54:51 PM PDT 24
Peak memory 205520 kb
Host smart-4fd1e0ef-18f2-4d58-8f0f-c20208e2b106
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467288757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3467288757
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2304487442
Short name T1013
Test name
Test status
Simulation time 93506966 ps
CPU time 2.7 seconds
Started Jul 09 06:54:48 PM PDT 24
Finished Jul 09 06:54:53 PM PDT 24
Peak memory 214004 kb
Host smart-9610fd75-d2db-4fc0-b3fe-b21253b5e885
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304487442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2304487442
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.945708370
Short name T131
Test name
Test status
Simulation time 578692259 ps
CPU time 6.5 seconds
Started Jul 09 06:54:48 PM PDT 24
Finished Jul 09 06:54:57 PM PDT 24
Peak memory 214112 kb
Host smart-26f56e7c-32d0-447f-8011-6c6a452e70e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945708370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.945708370
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2934454980
Short name T928
Test name
Test status
Simulation time 32162786 ps
CPU time 1.93 seconds
Started Jul 09 06:54:42 PM PDT 24
Finished Jul 09 06:54:48 PM PDT 24
Peak memory 213740 kb
Host smart-708526d8-965f-4053-a63b-9861f326a4b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934454980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2934454980
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.4087682330
Short name T180
Test name
Test status
Simulation time 1072657682 ps
CPU time 7.15 seconds
Started Jul 09 06:54:41 PM PDT 24
Finished Jul 09 06:54:51 PM PDT 24
Peak memory 205572 kb
Host smart-0677ad8d-ac8c-47d9-8b15-40e539062241
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087682330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.4087682330
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2425929729
Short name T1009
Test name
Test status
Simulation time 414007281 ps
CPU time 10.07 seconds
Started Jul 09 06:53:57 PM PDT 24
Finished Jul 09 06:54:09 PM PDT 24
Peak memory 205500 kb
Host smart-ca3a46e7-7c23-4cf8-9114-ca398a6e2984
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425929729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
425929729
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3613206922
Short name T164
Test name
Test status
Simulation time 2218980807 ps
CPU time 15.42 seconds
Started Jul 09 06:53:59 PM PDT 24
Finished Jul 09 06:54:16 PM PDT 24
Peak memory 205684 kb
Host smart-ad235714-17f6-4ba7-8f12-d6a4a6d378c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613206922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
613206922
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3251499211
Short name T944
Test name
Test status
Simulation time 19681380 ps
CPU time 1.18 seconds
Started Jul 09 06:54:00 PM PDT 24
Finished Jul 09 06:54:03 PM PDT 24
Peak memory 205504 kb
Host smart-9b95c633-73e7-4056-8eea-1f7ffb815d87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251499211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
251499211
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.469090679
Short name T991
Test name
Test status
Simulation time 180984769 ps
CPU time 1.77 seconds
Started Jul 09 06:54:00 PM PDT 24
Finished Jul 09 06:54:03 PM PDT 24
Peak memory 213844 kb
Host smart-3c64f24d-fb2f-44b9-ba13-67fcce95971e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469090679 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.469090679
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.536257728
Short name T1060
Test name
Test status
Simulation time 79176455 ps
CPU time 1.19 seconds
Started Jul 09 06:53:55 PM PDT 24
Finished Jul 09 06:53:58 PM PDT 24
Peak memory 205520 kb
Host smart-61ff72ef-6f18-4851-8b07-964eb2c0f5c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536257728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.536257728
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3873940018
Short name T982
Test name
Test status
Simulation time 45390361 ps
CPU time 0.74 seconds
Started Jul 09 06:54:01 PM PDT 24
Finished Jul 09 06:54:03 PM PDT 24
Peak memory 205400 kb
Host smart-0f27ae54-a098-428e-b41e-bac1985c6a57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873940018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3873940018
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.335680078
Short name T1074
Test name
Test status
Simulation time 182824368 ps
CPU time 2.26 seconds
Started Jul 09 06:53:57 PM PDT 24
Finished Jul 09 06:54:01 PM PDT 24
Peak memory 205576 kb
Host smart-1c518323-07f3-47f5-b926-b5a8d3ab8e51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335680078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.335680078
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2221386174
Short name T1011
Test name
Test status
Simulation time 154681828 ps
CPU time 4.5 seconds
Started Jul 09 06:53:58 PM PDT 24
Finished Jul 09 06:54:04 PM PDT 24
Peak memory 214036 kb
Host smart-765fe797-d432-48dc-8ca9-150b0f5bd6d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221386174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2221386174
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3221574934
Short name T1021
Test name
Test status
Simulation time 899743736 ps
CPU time 9.89 seconds
Started Jul 09 06:53:58 PM PDT 24
Finished Jul 09 06:54:09 PM PDT 24
Peak memory 214076 kb
Host smart-42d750e2-1db0-4908-a9ca-a45861d7596e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221574934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3221574934
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.945385505
Short name T1001
Test name
Test status
Simulation time 58209105 ps
CPU time 3.05 seconds
Started Jul 09 06:53:57 PM PDT 24
Finished Jul 09 06:54:02 PM PDT 24
Peak memory 215908 kb
Host smart-2138ccdc-9777-420e-a9a4-320b11928871
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945385505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.945385505
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1435943840
Short name T1031
Test name
Test status
Simulation time 182283626 ps
CPU time 4.95 seconds
Started Jul 09 06:53:57 PM PDT 24
Finished Jul 09 06:54:04 PM PDT 24
Peak memory 213692 kb
Host smart-12cab930-ca58-4ea5-8ace-6ff45b9199aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435943840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1435943840
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1293066465
Short name T975
Test name
Test status
Simulation time 38610261 ps
CPU time 0.81 seconds
Started Jul 09 06:54:44 PM PDT 24
Finished Jul 09 06:54:48 PM PDT 24
Peak memory 205344 kb
Host smart-d57e444f-a21f-4715-b0a4-02da4b086aef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293066465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1293066465
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.4051505376
Short name T1080
Test name
Test status
Simulation time 12113220 ps
CPU time 0.75 seconds
Started Jul 09 06:54:40 PM PDT 24
Finished Jul 09 06:54:42 PM PDT 24
Peak memory 205332 kb
Host smart-e32c4f2e-330a-4999-80d1-0ff61ba938f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051505376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.4051505376
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2119972691
Short name T999
Test name
Test status
Simulation time 11372771 ps
CPU time 0.79 seconds
Started Jul 09 06:54:41 PM PDT 24
Finished Jul 09 06:54:43 PM PDT 24
Peak memory 205312 kb
Host smart-d4ed774a-c6c1-4710-a316-b26c93623c06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119972691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2119972691
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2364927203
Short name T943
Test name
Test status
Simulation time 9909240 ps
CPU time 0.71 seconds
Started Jul 09 06:54:44 PM PDT 24
Finished Jul 09 06:54:48 PM PDT 24
Peak memory 205344 kb
Host smart-e9339943-bb48-4205-a874-230de22f73d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364927203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2364927203
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2060896747
Short name T1085
Test name
Test status
Simulation time 103713533 ps
CPU time 0.75 seconds
Started Jul 09 06:54:41 PM PDT 24
Finished Jul 09 06:54:43 PM PDT 24
Peak memory 205280 kb
Host smart-397aa5ae-a32b-47b7-9981-f2c7190c8e99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060896747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2060896747
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.504713999
Short name T945
Test name
Test status
Simulation time 23207647 ps
CPU time 0.75 seconds
Started Jul 09 06:54:40 PM PDT 24
Finished Jul 09 06:54:43 PM PDT 24
Peak memory 205292 kb
Host smart-aea1e39b-e880-4b7e-807e-10b65ac0c5aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504713999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.504713999
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3849611446
Short name T950
Test name
Test status
Simulation time 99703127 ps
CPU time 0.78 seconds
Started Jul 09 06:54:40 PM PDT 24
Finished Jul 09 06:54:42 PM PDT 24
Peak memory 205388 kb
Host smart-9db07c41-6253-4e50-8d87-a692e7fea122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849611446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3849611446
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1706658593
Short name T1033
Test name
Test status
Simulation time 29234283 ps
CPU time 0.7 seconds
Started Jul 09 06:54:42 PM PDT 24
Finished Jul 09 06:54:46 PM PDT 24
Peak memory 205332 kb
Host smart-a5ad9800-b557-448a-bd11-747ab23b7273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706658593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1706658593
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.686259500
Short name T1023
Test name
Test status
Simulation time 16860739 ps
CPU time 0.68 seconds
Started Jul 09 06:54:41 PM PDT 24
Finished Jul 09 06:54:44 PM PDT 24
Peak memory 205404 kb
Host smart-eeac0eeb-1086-4050-8811-2a9c900b34a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686259500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.686259500
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.246518385
Short name T1079
Test name
Test status
Simulation time 24721675 ps
CPU time 0.73 seconds
Started Jul 09 06:54:39 PM PDT 24
Finished Jul 09 06:54:41 PM PDT 24
Peak memory 205320 kb
Host smart-ae0cab97-ed9c-4b4b-bd68-82fd661feb2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246518385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.246518385
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2243004158
Short name T1016
Test name
Test status
Simulation time 190099823 ps
CPU time 4.6 seconds
Started Jul 09 06:54:03 PM PDT 24
Finished Jul 09 06:54:09 PM PDT 24
Peak memory 205496 kb
Host smart-fdc4f4db-2d0a-4302-86f6-e8d18d72d0a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243004158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
243004158
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2090803724
Short name T1063
Test name
Test status
Simulation time 4463023085 ps
CPU time 16.47 seconds
Started Jul 09 06:54:03 PM PDT 24
Finished Jul 09 06:54:20 PM PDT 24
Peak memory 205684 kb
Host smart-b9f97b3c-e9cd-4bdc-8415-ad802c5821a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090803724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
090803724
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2920699175
Short name T1043
Test name
Test status
Simulation time 128871826 ps
CPU time 1.05 seconds
Started Jul 09 06:54:02 PM PDT 24
Finished Jul 09 06:54:04 PM PDT 24
Peak memory 205580 kb
Host smart-d888639d-0cb8-4dcf-8f31-95266d2ec5b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920699175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
920699175
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3108156421
Short name T398
Test name
Test status
Simulation time 21230289 ps
CPU time 1.47 seconds
Started Jul 09 06:54:04 PM PDT 24
Finished Jul 09 06:54:06 PM PDT 24
Peak memory 213756 kb
Host smart-0b2850f0-2699-4195-a240-a21de79cc477
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108156421 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3108156421
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.4043440553
Short name T971
Test name
Test status
Simulation time 18126628 ps
CPU time 0.9 seconds
Started Jul 09 06:54:01 PM PDT 24
Finished Jul 09 06:54:03 PM PDT 24
Peak memory 205456 kb
Host smart-3555f5b0-35cb-44b7-961c-d4ee1bc40961
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043440553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.4043440553
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1581070673
Short name T1054
Test name
Test status
Simulation time 14909162 ps
CPU time 0.71 seconds
Started Jul 09 06:54:03 PM PDT 24
Finished Jul 09 06:54:05 PM PDT 24
Peak memory 205332 kb
Host smart-1e14225f-3761-4e86-ac01-63661fcddc4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581070673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1581070673
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3201962582
Short name T1050
Test name
Test status
Simulation time 181468370 ps
CPU time 3.45 seconds
Started Jul 09 06:54:01 PM PDT 24
Finished Jul 09 06:54:05 PM PDT 24
Peak memory 205524 kb
Host smart-70013884-7e57-437a-87cd-8d99febb7538
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201962582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3201962582
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.677603181
Short name T967
Test name
Test status
Simulation time 288971455 ps
CPU time 4.34 seconds
Started Jul 09 06:53:58 PM PDT 24
Finished Jul 09 06:54:04 PM PDT 24
Peak memory 213992 kb
Host smart-75954791-7c4b-41f6-8cdb-ddd6f9a4dbfd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677603181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.677603181
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2597972359
Short name T987
Test name
Test status
Simulation time 208853852 ps
CPU time 4.68 seconds
Started Jul 09 06:53:59 PM PDT 24
Finished Jul 09 06:54:05 PM PDT 24
Peak memory 213968 kb
Host smart-601fb273-f030-4889-b3d8-a529c5d938d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597972359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2597972359
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.546972504
Short name T985
Test name
Test status
Simulation time 218156962 ps
CPU time 1.84 seconds
Started Jul 09 06:54:00 PM PDT 24
Finished Jul 09 06:54:02 PM PDT 24
Peak memory 215884 kb
Host smart-930ea47c-d320-42cc-ae99-ea654bd2dcd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546972504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.546972504
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1091283009
Short name T1083
Test name
Test status
Simulation time 23501879 ps
CPU time 0.87 seconds
Started Jul 09 06:54:43 PM PDT 24
Finished Jul 09 06:54:47 PM PDT 24
Peak memory 205352 kb
Host smart-89bc2f08-c37b-43cd-a0e9-b597084f139b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091283009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1091283009
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1509535022
Short name T923
Test name
Test status
Simulation time 11669442 ps
CPU time 0.7 seconds
Started Jul 09 06:54:48 PM PDT 24
Finished Jul 09 06:54:51 PM PDT 24
Peak memory 205300 kb
Host smart-979a4ac6-c338-48bb-9f4f-6691c4c6f76e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509535022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1509535022
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.304839
Short name T995
Test name
Test status
Simulation time 38623957 ps
CPU time 0.7 seconds
Started Jul 09 06:54:41 PM PDT 24
Finished Jul 09 06:54:44 PM PDT 24
Peak memory 205324 kb
Host smart-5ab63916-3010-4c1d-af00-a01b9aceb3af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.304839
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1772294957
Short name T937
Test name
Test status
Simulation time 125272950 ps
CPU time 0.85 seconds
Started Jul 09 06:54:42 PM PDT 24
Finished Jul 09 06:54:46 PM PDT 24
Peak memory 205408 kb
Host smart-5d27f76c-7ecf-460f-9b39-ab64be8072f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772294957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1772294957
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1400291346
Short name T938
Test name
Test status
Simulation time 15114519 ps
CPU time 0.77 seconds
Started Jul 09 06:54:42 PM PDT 24
Finished Jul 09 06:54:46 PM PDT 24
Peak memory 205380 kb
Host smart-cad81a61-e4b2-4ff2-a989-72aac29c5a49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400291346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1400291346
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1531292365
Short name T1026
Test name
Test status
Simulation time 18968961 ps
CPU time 0.71 seconds
Started Jul 09 06:54:42 PM PDT 24
Finished Jul 09 06:54:46 PM PDT 24
Peak memory 205380 kb
Host smart-dfd31ae3-d051-40ce-b6b0-3a9815f5f169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531292365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1531292365
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4177439430
Short name T1055
Test name
Test status
Simulation time 31548686 ps
CPU time 0.75 seconds
Started Jul 09 06:54:46 PM PDT 24
Finished Jul 09 06:54:49 PM PDT 24
Peak memory 205352 kb
Host smart-388b4c91-6d7c-4a63-90e4-7dbcae9caf4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177439430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.4177439430
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1087774711
Short name T1018
Test name
Test status
Simulation time 43599226 ps
CPU time 0.86 seconds
Started Jul 09 06:54:46 PM PDT 24
Finished Jul 09 06:54:49 PM PDT 24
Peak memory 205332 kb
Host smart-a8a8c760-71ee-4b8f-ad1b-7e020671ba96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087774711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1087774711
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2337821143
Short name T984
Test name
Test status
Simulation time 7449933 ps
CPU time 0.7 seconds
Started Jul 09 06:54:48 PM PDT 24
Finished Jul 09 06:54:51 PM PDT 24
Peak memory 205328 kb
Host smart-cc593e01-da9b-4b5b-ba8e-0ea1cc866766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337821143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2337821143
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.222843990
Short name T960
Test name
Test status
Simulation time 17613401 ps
CPU time 0.71 seconds
Started Jul 09 06:54:46 PM PDT 24
Finished Jul 09 06:54:49 PM PDT 24
Peak memory 205272 kb
Host smart-ca3c23a0-1ca0-4557-a42d-8a386c930405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222843990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.222843990
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.240100688
Short name T1040
Test name
Test status
Simulation time 132237864 ps
CPU time 7.08 seconds
Started Jul 09 06:54:09 PM PDT 24
Finished Jul 09 06:54:17 PM PDT 24
Peak memory 205616 kb
Host smart-9e74d3b3-2c6f-4766-bd4d-c28d26a13ab8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240100688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.240100688
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1621005436
Short name T1048
Test name
Test status
Simulation time 445612377 ps
CPU time 13.39 seconds
Started Jul 09 06:54:09 PM PDT 24
Finished Jul 09 06:54:23 PM PDT 24
Peak memory 205532 kb
Host smart-56a0eaf5-a53b-47ec-9b1e-d6c9422fdc36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621005436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
621005436
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1930113844
Short name T948
Test name
Test status
Simulation time 19047235 ps
CPU time 0.92 seconds
Started Jul 09 06:54:03 PM PDT 24
Finished Jul 09 06:54:04 PM PDT 24
Peak memory 205468 kb
Host smart-7fcf5a73-d8bc-4306-a0d0-251dff015f8a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930113844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
930113844
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3776871249
Short name T1032
Test name
Test status
Simulation time 19612260 ps
CPU time 1.31 seconds
Started Jul 09 06:54:09 PM PDT 24
Finished Jul 09 06:54:11 PM PDT 24
Peak memory 213792 kb
Host smart-f1138f6c-dac7-455b-9a15-1816af1211ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776871249 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3776871249
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.4235949764
Short name T952
Test name
Test status
Simulation time 99197608 ps
CPU time 1.23 seconds
Started Jul 09 06:54:09 PM PDT 24
Finished Jul 09 06:54:11 PM PDT 24
Peak memory 205472 kb
Host smart-7b288d5f-3bb1-40e5-9e48-5ab0cd9a79ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235949764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.4235949764
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3540558112
Short name T1015
Test name
Test status
Simulation time 26900430 ps
CPU time 0.77 seconds
Started Jul 09 06:54:02 PM PDT 24
Finished Jul 09 06:54:04 PM PDT 24
Peak memory 205292 kb
Host smart-7a5c61bb-fe75-440d-88ef-e248b7edf19d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540558112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3540558112
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1872073678
Short name T1022
Test name
Test status
Simulation time 293948882 ps
CPU time 2.48 seconds
Started Jul 09 06:54:08 PM PDT 24
Finished Jul 09 06:54:11 PM PDT 24
Peak memory 205524 kb
Host smart-918be474-6756-4522-8148-4ecb962b5348
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872073678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1872073678
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3215183135
Short name T997
Test name
Test status
Simulation time 612406143 ps
CPU time 2.22 seconds
Started Jul 09 06:54:04 PM PDT 24
Finished Jul 09 06:54:07 PM PDT 24
Peak memory 214036 kb
Host smart-918b6165-0272-4936-86f7-acb699b0bb85
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215183135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3215183135
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2244616136
Short name T130
Test name
Test status
Simulation time 301400608 ps
CPU time 6.57 seconds
Started Jul 09 06:54:02 PM PDT 24
Finished Jul 09 06:54:10 PM PDT 24
Peak memory 213988 kb
Host smart-ad2207c7-bb32-4e95-8077-330380540013
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244616136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2244616136
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2878595762
Short name T966
Test name
Test status
Simulation time 48975848 ps
CPU time 3.36 seconds
Started Jul 09 06:54:02 PM PDT 24
Finished Jul 09 06:54:06 PM PDT 24
Peak memory 213664 kb
Host smart-d3d90ec0-9db6-4a5a-9a6d-4b8d1ff627b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878595762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2878595762
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3930610807
Short name T182
Test name
Test status
Simulation time 288246750 ps
CPU time 5.96 seconds
Started Jul 09 06:54:05 PM PDT 24
Finished Jul 09 06:54:11 PM PDT 24
Peak memory 205532 kb
Host smart-22f4e9a1-c486-4f73-9588-a418205de6e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930610807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3930610807
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3475358975
Short name T951
Test name
Test status
Simulation time 15266277 ps
CPU time 0.8 seconds
Started Jul 09 06:54:46 PM PDT 24
Finished Jul 09 06:54:49 PM PDT 24
Peak memory 205396 kb
Host smart-47185284-4a79-4eea-9806-abf7f918126a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475358975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3475358975
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.869337049
Short name T955
Test name
Test status
Simulation time 19322888 ps
CPU time 0.84 seconds
Started Jul 09 06:54:47 PM PDT 24
Finished Jul 09 06:54:50 PM PDT 24
Peak memory 205352 kb
Host smart-bed56824-1807-4dc2-ac75-f3cf5ea70cfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869337049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.869337049
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3384824955
Short name T1020
Test name
Test status
Simulation time 18114185 ps
CPU time 0.7 seconds
Started Jul 09 06:54:47 PM PDT 24
Finished Jul 09 06:54:49 PM PDT 24
Peak memory 205364 kb
Host smart-039a069c-a9db-465f-8bcc-03bac9d3c630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384824955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3384824955
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2381709597
Short name T920
Test name
Test status
Simulation time 9098703 ps
CPU time 0.82 seconds
Started Jul 09 06:54:46 PM PDT 24
Finished Jul 09 06:54:49 PM PDT 24
Peak memory 205408 kb
Host smart-750ddae1-b64d-4e54-85aa-eacc7e940524
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381709597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2381709597
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.4268188588
Short name T949
Test name
Test status
Simulation time 14994215 ps
CPU time 0.78 seconds
Started Jul 09 06:54:47 PM PDT 24
Finished Jul 09 06:54:50 PM PDT 24
Peak memory 205328 kb
Host smart-c65d0f4a-5b5e-42b6-bb29-a424ec103748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268188588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.4268188588
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3969477411
Short name T957
Test name
Test status
Simulation time 12898692 ps
CPU time 0.87 seconds
Started Jul 09 06:54:47 PM PDT 24
Finished Jul 09 06:54:50 PM PDT 24
Peak memory 205288 kb
Host smart-1a9e1ec6-b9b3-4aea-b21c-0ad915411845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969477411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3969477411
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2947604036
Short name T958
Test name
Test status
Simulation time 46111272 ps
CPU time 0.88 seconds
Started Jul 09 06:54:45 PM PDT 24
Finished Jul 09 06:54:49 PM PDT 24
Peak memory 205396 kb
Host smart-cd686b1c-5d51-4ac3-ac2a-870fbd61339c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947604036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2947604036
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1900214956
Short name T926
Test name
Test status
Simulation time 14767791 ps
CPU time 0.84 seconds
Started Jul 09 06:54:49 PM PDT 24
Finished Jul 09 06:54:52 PM PDT 24
Peak memory 205392 kb
Host smart-b7253db2-fa41-409c-9e43-6fae87f5afde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900214956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1900214956
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.4087577622
Short name T940
Test name
Test status
Simulation time 80134927 ps
CPU time 0.77 seconds
Started Jul 09 06:54:50 PM PDT 24
Finished Jul 09 06:54:53 PM PDT 24
Peak memory 205404 kb
Host smart-395c9951-ae95-4235-9334-f07d35717e2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087577622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.4087577622
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.4081950466
Short name T986
Test name
Test status
Simulation time 11112990 ps
CPU time 0.83 seconds
Started Jul 09 06:54:50 PM PDT 24
Finished Jul 09 06:54:53 PM PDT 24
Peak memory 205404 kb
Host smart-6af63d52-19c6-43a9-aad5-0fab50cd72bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081950466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.4081950466
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1324453670
Short name T1030
Test name
Test status
Simulation time 46312844 ps
CPU time 1.31 seconds
Started Jul 09 06:54:14 PM PDT 24
Finished Jul 09 06:54:16 PM PDT 24
Peak memory 205700 kb
Host smart-1c93e88e-6846-4f65-9e06-46cc0607a792
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324453670 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1324453670
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.616088915
Short name T1059
Test name
Test status
Simulation time 19936463 ps
CPU time 0.88 seconds
Started Jul 09 06:54:13 PM PDT 24
Finished Jul 09 06:54:14 PM PDT 24
Peak memory 205476 kb
Host smart-d3e7284b-51d7-44b0-9892-b0ee04e8edd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616088915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.616088915
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.4173921459
Short name T1065
Test name
Test status
Simulation time 40218803 ps
CPU time 0.87 seconds
Started Jul 09 06:54:10 PM PDT 24
Finished Jul 09 06:54:11 PM PDT 24
Peak memory 205404 kb
Host smart-90cd7f77-db81-4821-b90e-b15ac69ebeaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173921459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.4173921459
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3007685736
Short name T1042
Test name
Test status
Simulation time 93956267 ps
CPU time 1.42 seconds
Started Jul 09 06:54:13 PM PDT 24
Finished Jul 09 06:54:16 PM PDT 24
Peak memory 205604 kb
Host smart-15b1db3c-dc3c-474b-ab8d-bd5d0e8242bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007685736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3007685736
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.93677143
Short name T1049
Test name
Test status
Simulation time 133075362 ps
CPU time 1.99 seconds
Started Jul 09 06:54:07 PM PDT 24
Finished Jul 09 06:54:10 PM PDT 24
Peak memory 214096 kb
Host smart-90fb0741-d1e5-429e-a3eb-0d9f8f66b48c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93677143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_
reg_errors.93677143
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.662051799
Short name T1004
Test name
Test status
Simulation time 826900465 ps
CPU time 5.25 seconds
Started Jul 09 06:54:11 PM PDT 24
Finished Jul 09 06:54:17 PM PDT 24
Peak memory 219964 kb
Host smart-cb04add9-46ec-4c13-8938-a27941c1b65c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662051799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.662051799
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1423755388
Short name T919
Test name
Test status
Simulation time 67564618 ps
CPU time 3.54 seconds
Started Jul 09 06:54:09 PM PDT 24
Finished Jul 09 06:54:13 PM PDT 24
Peak memory 216536 kb
Host smart-bafe520e-05ce-4dc7-9c88-1702404ca452
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423755388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1423755388
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2277725182
Short name T1084
Test name
Test status
Simulation time 274428623 ps
CPU time 4.6 seconds
Started Jul 09 06:54:08 PM PDT 24
Finished Jul 09 06:54:13 PM PDT 24
Peak memory 215096 kb
Host smart-a1bfd044-4d14-497f-99cc-28e4602974b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277725182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2277725182
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3757882716
Short name T1062
Test name
Test status
Simulation time 29934609 ps
CPU time 1.14 seconds
Started Jul 09 06:54:13 PM PDT 24
Finished Jul 09 06:54:15 PM PDT 24
Peak memory 213844 kb
Host smart-37ce156d-0a92-45ca-97f0-a67562e1b0b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757882716 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3757882716
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3928409154
Short name T996
Test name
Test status
Simulation time 32071105 ps
CPU time 1.03 seconds
Started Jul 09 06:54:13 PM PDT 24
Finished Jul 09 06:54:15 PM PDT 24
Peak memory 205584 kb
Host smart-c295f5de-37b5-4352-a492-ceb76151244f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928409154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3928409154
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3627822847
Short name T1027
Test name
Test status
Simulation time 33413217 ps
CPU time 0.84 seconds
Started Jul 09 06:54:14 PM PDT 24
Finished Jul 09 06:54:16 PM PDT 24
Peak memory 205400 kb
Host smart-1d4c16da-8930-4a41-8258-0c10e34d69ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627822847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3627822847
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.252351329
Short name T965
Test name
Test status
Simulation time 37651586 ps
CPU time 2.51 seconds
Started Jul 09 06:54:14 PM PDT 24
Finished Jul 09 06:54:17 PM PDT 24
Peak memory 205628 kb
Host smart-c6b11cf4-bc0d-4405-a8d1-159cddacb428
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252351329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.252351329
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4205502769
Short name T1069
Test name
Test status
Simulation time 149876641 ps
CPU time 1.85 seconds
Started Jul 09 06:54:14 PM PDT 24
Finished Jul 09 06:54:17 PM PDT 24
Peak memory 214112 kb
Host smart-9c52616b-258d-44b0-a29f-5c115d8719ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205502769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.4205502769
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2267063036
Short name T1003
Test name
Test status
Simulation time 107447405 ps
CPU time 1.87 seconds
Started Jul 09 06:54:13 PM PDT 24
Finished Jul 09 06:54:16 PM PDT 24
Peak memory 213792 kb
Host smart-bfc01db7-7c99-48a1-8224-2f0318a469eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267063036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2267063036
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.4137301011
Short name T167
Test name
Test status
Simulation time 953464626 ps
CPU time 7.86 seconds
Started Jul 09 06:54:12 PM PDT 24
Finished Jul 09 06:54:20 PM PDT 24
Peak memory 213912 kb
Host smart-7fa19985-dcf8-470a-942c-a08ee33cf436
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137301011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.4137301011
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2894812307
Short name T1014
Test name
Test status
Simulation time 91870461 ps
CPU time 2.2 seconds
Started Jul 09 06:54:21 PM PDT 24
Finished Jul 09 06:54:24 PM PDT 24
Peak memory 213784 kb
Host smart-f5848058-cf23-44b2-84ce-056550df65f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894812307 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2894812307
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2749337559
Short name T1046
Test name
Test status
Simulation time 44502409 ps
CPU time 1.12 seconds
Started Jul 09 06:54:16 PM PDT 24
Finished Jul 09 06:54:17 PM PDT 24
Peak memory 205388 kb
Host smart-e22fdd69-f296-43a6-b920-4c91581c206f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749337559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2749337559
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.887989726
Short name T1077
Test name
Test status
Simulation time 23377244 ps
CPU time 0.76 seconds
Started Jul 09 06:54:14 PM PDT 24
Finished Jul 09 06:54:16 PM PDT 24
Peak memory 205356 kb
Host smart-3046cddc-ad87-4e0c-b11c-813e07ff6551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887989726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.887989726
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3054565059
Short name T974
Test name
Test status
Simulation time 291649239 ps
CPU time 2.57 seconds
Started Jul 09 06:54:13 PM PDT 24
Finished Jul 09 06:54:17 PM PDT 24
Peak memory 205504 kb
Host smart-0e75e4e6-f267-4a40-a215-f9348308e94b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054565059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3054565059
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3302896917
Short name T998
Test name
Test status
Simulation time 240962541 ps
CPU time 5.72 seconds
Started Jul 09 06:54:12 PM PDT 24
Finished Jul 09 06:54:19 PM PDT 24
Peak memory 214104 kb
Host smart-86fd6b1a-0548-4ebe-b770-7b57a02bb66d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302896917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3302896917
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1689893732
Short name T968
Test name
Test status
Simulation time 436598955 ps
CPU time 14.77 seconds
Started Jul 09 06:54:13 PM PDT 24
Finished Jul 09 06:54:28 PM PDT 24
Peak memory 214068 kb
Host smart-d4b0219c-8762-4d6a-ab9d-136f4efd5a30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689893732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1689893732
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1246610012
Short name T1038
Test name
Test status
Simulation time 363003563 ps
CPU time 2.45 seconds
Started Jul 09 06:54:11 PM PDT 24
Finished Jul 09 06:54:15 PM PDT 24
Peak memory 213804 kb
Host smart-ec9e4455-0350-42d7-973d-8ca0139b05f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246610012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1246610012
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1211431049
Short name T183
Test name
Test status
Simulation time 998650600 ps
CPU time 7.27 seconds
Started Jul 09 06:54:17 PM PDT 24
Finished Jul 09 06:54:25 PM PDT 24
Peak memory 213652 kb
Host smart-23b0308c-0591-4963-a900-a7d7ad9dda28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211431049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1211431049
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1197833520
Short name T959
Test name
Test status
Simulation time 61797959 ps
CPU time 1.21 seconds
Started Jul 09 06:54:19 PM PDT 24
Finished Jul 09 06:54:21 PM PDT 24
Peak memory 213712 kb
Host smart-be8cb2be-6c67-4b08-b487-3685d1fc4b0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197833520 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1197833520
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.373944917
Short name T969
Test name
Test status
Simulation time 111830927 ps
CPU time 1.72 seconds
Started Jul 09 06:54:24 PM PDT 24
Finished Jul 09 06:54:27 PM PDT 24
Peak memory 205544 kb
Host smart-0b03af92-8724-4018-93b4-ddac7ba54cba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373944917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.373944917
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2932341287
Short name T921
Test name
Test status
Simulation time 15947587 ps
CPU time 0.76 seconds
Started Jul 09 06:54:20 PM PDT 24
Finished Jul 09 06:54:22 PM PDT 24
Peak memory 205384 kb
Host smart-94f5c4fa-437d-4f7a-86d0-19779efee2c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932341287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2932341287
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3339302757
Short name T1072
Test name
Test status
Simulation time 400966312 ps
CPU time 3.71 seconds
Started Jul 09 06:54:18 PM PDT 24
Finished Jul 09 06:54:23 PM PDT 24
Peak memory 205608 kb
Host smart-4cc59907-7e48-4c3c-80fd-cec8f9cde96b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339302757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3339302757
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.254859259
Short name T133
Test name
Test status
Simulation time 79983504 ps
CPU time 2.05 seconds
Started Jul 09 06:54:20 PM PDT 24
Finished Jul 09 06:54:23 PM PDT 24
Peak memory 214096 kb
Host smart-2ec7d491-453e-4d90-b581-ab49f45bad04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254859259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.254859259
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2700887498
Short name T972
Test name
Test status
Simulation time 272851229 ps
CPU time 8.53 seconds
Started Jul 09 06:54:21 PM PDT 24
Finished Jul 09 06:54:31 PM PDT 24
Peak memory 213976 kb
Host smart-3fe087f2-8a23-4f49-a5d4-192646d26f68
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700887498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2700887498
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2932671530
Short name T1000
Test name
Test status
Simulation time 160378533 ps
CPU time 2.93 seconds
Started Jul 09 06:54:24 PM PDT 24
Finished Jul 09 06:54:28 PM PDT 24
Peak memory 216848 kb
Host smart-f169dec6-cb06-4a44-aed4-48bfeb81de09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932671530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2932671530
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3515383345
Short name T168
Test name
Test status
Simulation time 168490368 ps
CPU time 4.32 seconds
Started Jul 09 06:54:21 PM PDT 24
Finished Jul 09 06:54:26 PM PDT 24
Peak memory 214816 kb
Host smart-2c473a06-7140-4f5e-807a-dbb022c1711f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515383345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3515383345
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2929566171
Short name T936
Test name
Test status
Simulation time 215644398 ps
CPU time 1.57 seconds
Started Jul 09 06:54:26 PM PDT 24
Finished Jul 09 06:54:28 PM PDT 24
Peak memory 205592 kb
Host smart-dddba9f3-63cf-49fc-bdf6-7eb39d2e8df9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929566171 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2929566171
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3471620748
Short name T1071
Test name
Test status
Simulation time 16501139 ps
CPU time 1.12 seconds
Started Jul 09 06:54:18 PM PDT 24
Finished Jul 09 06:54:21 PM PDT 24
Peak memory 205572 kb
Host smart-c72a96b5-87f7-4ce0-869a-723e097e83d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471620748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3471620748
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1048758139
Short name T956
Test name
Test status
Simulation time 33444063 ps
CPU time 0.71 seconds
Started Jul 09 06:54:20 PM PDT 24
Finished Jul 09 06:54:22 PM PDT 24
Peak memory 205328 kb
Host smart-05ddf211-f0c6-4c63-b37f-f8a716499b6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048758139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1048758139
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1705212958
Short name T1028
Test name
Test status
Simulation time 49794378 ps
CPU time 2.44 seconds
Started Jul 09 06:54:20 PM PDT 24
Finished Jul 09 06:54:24 PM PDT 24
Peak memory 205628 kb
Host smart-5c824313-d61d-4dc8-9af7-e75cc133f068
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705212958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1705212958
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3671582813
Short name T1010
Test name
Test status
Simulation time 139775594 ps
CPU time 2.65 seconds
Started Jul 09 06:54:17 PM PDT 24
Finished Jul 09 06:54:21 PM PDT 24
Peak memory 214388 kb
Host smart-d8d8ea25-c849-4774-b80d-f40748f5f86f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671582813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3671582813
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2878173608
Short name T159
Test name
Test status
Simulation time 262725017 ps
CPU time 7.01 seconds
Started Jul 09 06:54:20 PM PDT 24
Finished Jul 09 06:54:28 PM PDT 24
Peak memory 214076 kb
Host smart-870c2cd8-d03c-49bf-b4ae-a90d92429f9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878173608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2878173608
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.616008004
Short name T1019
Test name
Test status
Simulation time 356518765 ps
CPU time 2.14 seconds
Started Jul 09 06:54:21 PM PDT 24
Finished Jul 09 06:54:24 PM PDT 24
Peak memory 213788 kb
Host smart-a9261d40-35d4-4055-9ef6-21c729e47035
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616008004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.616008004
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1535385295
Short name T181
Test name
Test status
Simulation time 341217658 ps
CPU time 4.57 seconds
Started Jul 09 06:54:22 PM PDT 24
Finished Jul 09 06:54:27 PM PDT 24
Peak memory 213780 kb
Host smart-2dc53861-5bc3-4781-860d-9ac1e94fc221
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535385295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1535385295
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.4107316029
Short name T590
Test name
Test status
Simulation time 13491192 ps
CPU time 0.79 seconds
Started Jul 09 06:59:43 PM PDT 24
Finished Jul 09 06:59:45 PM PDT 24
Peak memory 205988 kb
Host smart-f40af516-31ee-4ff3-bec9-159029552f73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107316029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.4107316029
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.4192655542
Short name T725
Test name
Test status
Simulation time 84840917 ps
CPU time 2.11 seconds
Started Jul 09 06:59:38 PM PDT 24
Finished Jul 09 06:59:42 PM PDT 24
Peak memory 209840 kb
Host smart-24f1ad75-05e5-414a-97ef-c55bf7affe76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192655542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.4192655542
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1270247150
Short name T84
Test name
Test status
Simulation time 94893863 ps
CPU time 3.74 seconds
Started Jul 09 06:59:41 PM PDT 24
Finished Jul 09 06:59:47 PM PDT 24
Peak memory 210232 kb
Host smart-95bf7c84-0ad8-480e-bf7c-02943fec041b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270247150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1270247150
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_random.2769123679
Short name T339
Test name
Test status
Simulation time 6038508544 ps
CPU time 33.27 seconds
Started Jul 09 06:59:38 PM PDT 24
Finished Jul 09 07:00:14 PM PDT 24
Peak memory 214412 kb
Host smart-0f909e9c-aed2-4359-bcbf-480387f05433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769123679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2769123679
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.4001250279
Short name T44
Test name
Test status
Simulation time 1039725343 ps
CPU time 16.65 seconds
Started Jul 09 06:59:43 PM PDT 24
Finished Jul 09 07:00:01 PM PDT 24
Peak memory 230916 kb
Host smart-57fca5be-1835-456b-9bde-9a171ac1f59b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001250279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.4001250279
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.270907470
Short name T830
Test name
Test status
Simulation time 53525064 ps
CPU time 2.32 seconds
Started Jul 09 06:59:40 PM PDT 24
Finished Jul 09 06:59:44 PM PDT 24
Peak memory 208940 kb
Host smart-57b532e2-9aac-470b-953c-c31c534629fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270907470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.270907470
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1035061268
Short name T665
Test name
Test status
Simulation time 77339297 ps
CPU time 3.36 seconds
Started Jul 09 06:59:37 PM PDT 24
Finished Jul 09 06:59:43 PM PDT 24
Peak memory 208332 kb
Host smart-73742d01-0bcf-42c8-b6b2-1c00231918e7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035061268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1035061268
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3774818628
Short name T907
Test name
Test status
Simulation time 609723344 ps
CPU time 17.36 seconds
Started Jul 09 06:59:41 PM PDT 24
Finished Jul 09 07:00:00 PM PDT 24
Peak memory 208672 kb
Host smart-2fe892c3-4bcb-46bd-b977-7070b416e980
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774818628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3774818628
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.519567478
Short name T640
Test name
Test status
Simulation time 237489664 ps
CPU time 3 seconds
Started Jul 09 06:59:38 PM PDT 24
Finished Jul 09 06:59:43 PM PDT 24
Peak memory 206996 kb
Host smart-c78b0afe-b2ad-4d94-b86f-bc236778615a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519567478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.519567478
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.600372240
Short name T507
Test name
Test status
Simulation time 73185048 ps
CPU time 3.07 seconds
Started Jul 09 06:59:38 PM PDT 24
Finished Jul 09 06:59:43 PM PDT 24
Peak memory 210344 kb
Host smart-aea6005e-8bed-43b1-be15-1dc60a78ffb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600372240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.600372240
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3290680947
Short name T695
Test name
Test status
Simulation time 447509486 ps
CPU time 2.81 seconds
Started Jul 09 06:59:38 PM PDT 24
Finished Jul 09 06:59:43 PM PDT 24
Peak memory 208060 kb
Host smart-cd13565b-6d33-4123-bfe7-eb51b34baa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290680947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3290680947
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1385121611
Short name T469
Test name
Test status
Simulation time 62093086 ps
CPU time 4 seconds
Started Jul 09 06:59:38 PM PDT 24
Finished Jul 09 06:59:44 PM PDT 24
Peak memory 214360 kb
Host smart-d77a7a39-8c10-485f-965f-92d7b5bc47a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385121611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1385121611
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3233720591
Short name T618
Test name
Test status
Simulation time 172560612 ps
CPU time 2.27 seconds
Started Jul 09 06:59:40 PM PDT 24
Finished Jul 09 06:59:44 PM PDT 24
Peak memory 210440 kb
Host smart-908338b9-604c-4c90-9ea4-6458773abcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233720591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3233720591
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.596216345
Short name T26
Test name
Test status
Simulation time 70410867 ps
CPU time 3.09 seconds
Started Jul 09 06:59:45 PM PDT 24
Finished Jul 09 06:59:50 PM PDT 24
Peak memory 214152 kb
Host smart-12f6a0bf-e741-4e6a-8eb7-fff93fae381f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596216345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.596216345
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2980150979
Short name T59
Test name
Test status
Simulation time 50136712 ps
CPU time 1.44 seconds
Started Jul 09 06:59:45 PM PDT 24
Finished Jul 09 06:59:48 PM PDT 24
Peak memory 208016 kb
Host smart-c983ff52-aee9-4547-bf66-8728bd9d097a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980150979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2980150979
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.788001261
Short name T580
Test name
Test status
Simulation time 1155635802 ps
CPU time 5.42 seconds
Started Jul 09 06:59:45 PM PDT 24
Finished Jul 09 06:59:52 PM PDT 24
Peak memory 214440 kb
Host smart-b877cac6-a7bc-40d1-8edd-ebe9c0a41706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788001261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.788001261
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3674852808
Short name T313
Test name
Test status
Simulation time 84971469 ps
CPU time 3.92 seconds
Started Jul 09 06:59:44 PM PDT 24
Finished Jul 09 06:59:50 PM PDT 24
Peak memory 214272 kb
Host smart-0ee555dc-91ae-4ade-b999-f5e970206eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674852808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3674852808
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1301293499
Short name T627
Test name
Test status
Simulation time 163765554 ps
CPU time 3.28 seconds
Started Jul 09 06:59:43 PM PDT 24
Finished Jul 09 06:59:47 PM PDT 24
Peak memory 222568 kb
Host smart-a3cbfd2b-4367-4b91-9f4c-8d27ab6d3765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301293499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1301293499
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.4105043315
Short name T524
Test name
Test status
Simulation time 106288266 ps
CPU time 4.83 seconds
Started Jul 09 06:59:44 PM PDT 24
Finished Jul 09 06:59:50 PM PDT 24
Peak memory 210128 kb
Host smart-a81a754c-3b70-4c91-9060-bdd89f1deb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105043315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.4105043315
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3994400879
Short name T352
Test name
Test status
Simulation time 3135540112 ps
CPU time 38.09 seconds
Started Jul 09 06:59:43 PM PDT 24
Finished Jul 09 07:00:22 PM PDT 24
Peak memory 208464 kb
Host smart-4ef86e92-1bc7-4f89-9b90-91781d64e7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994400879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3994400879
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.62247124
Short name T756
Test name
Test status
Simulation time 110671278 ps
CPU time 2.73 seconds
Started Jul 09 06:59:45 PM PDT 24
Finished Jul 09 06:59:49 PM PDT 24
Peak memory 208208 kb
Host smart-1f8a8283-836d-409c-a9f6-153c1cd5cc90
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62247124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.62247124
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3812769168
Short name T707
Test name
Test status
Simulation time 28600011 ps
CPU time 2.16 seconds
Started Jul 09 06:59:45 PM PDT 24
Finished Jul 09 06:59:49 PM PDT 24
Peak memory 207000 kb
Host smart-4c4f6fce-ddfe-487e-867a-cdc5c0ceb201
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812769168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3812769168
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1254676242
Short name T204
Test name
Test status
Simulation time 244692558 ps
CPU time 3.87 seconds
Started Jul 09 06:59:44 PM PDT 24
Finished Jul 09 06:59:49 PM PDT 24
Peak memory 209728 kb
Host smart-301eac78-1ad2-42de-b9c1-7c99e6005b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254676242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1254676242
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3811689300
Short name T436
Test name
Test status
Simulation time 729148772 ps
CPU time 7.93 seconds
Started Jul 09 06:59:44 PM PDT 24
Finished Jul 09 06:59:54 PM PDT 24
Peak memory 208492 kb
Host smart-5eaf3195-7c84-4bf8-9483-1a4a405e5acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811689300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3811689300
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.4242140039
Short name T736
Test name
Test status
Simulation time 1028485702 ps
CPU time 22.68 seconds
Started Jul 09 06:59:49 PM PDT 24
Finished Jul 09 07:00:13 PM PDT 24
Peak memory 222500 kb
Host smart-d824c48f-3dc5-486a-8337-dfdbd8be676e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242140039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.4242140039
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2285264669
Short name T275
Test name
Test status
Simulation time 463740656 ps
CPU time 5.22 seconds
Started Jul 09 06:59:45 PM PDT 24
Finished Jul 09 06:59:52 PM PDT 24
Peak memory 214340 kb
Host smart-b2cf4ec0-8055-468e-b4b3-ff727a017fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285264669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2285264669
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3525833040
Short name T895
Test name
Test status
Simulation time 23245528 ps
CPU time 0.72 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:00:19 PM PDT 24
Peak memory 206016 kb
Host smart-b7ece4b6-f931-432e-9dc2-c55f0ae8ea99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525833040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3525833040
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1994911444
Short name T431
Test name
Test status
Simulation time 2461088521 ps
CPU time 13.26 seconds
Started Jul 09 07:01:34 PM PDT 24
Finished Jul 09 07:01:49 PM PDT 24
Peak memory 214400 kb
Host smart-0766c81c-88fa-4b91-a2cd-7a58533f2a6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1994911444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1994911444
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.526800933
Short name T29
Test name
Test status
Simulation time 177686487 ps
CPU time 2.27 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:00:21 PM PDT 24
Peak memory 221552 kb
Host smart-996550f7-ee27-467e-ac65-a7080c93fa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526800933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.526800933
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3473147141
Short name T702
Test name
Test status
Simulation time 69658394 ps
CPU time 1.78 seconds
Started Jul 09 07:00:14 PM PDT 24
Finished Jul 09 07:00:19 PM PDT 24
Peak memory 214356 kb
Host smart-79201ae5-8b9e-495c-a199-516e0ca0e0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473147141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3473147141
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_random.1712038087
Short name T249
Test name
Test status
Simulation time 534286405 ps
CPU time 9.95 seconds
Started Jul 09 07:00:11 PM PDT 24
Finished Jul 09 07:00:23 PM PDT 24
Peak memory 222404 kb
Host smart-ae536880-c313-4623-83b3-8a767af87d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712038087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1712038087
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.846244823
Short name T577
Test name
Test status
Simulation time 124695388 ps
CPU time 2.35 seconds
Started Jul 09 07:00:12 PM PDT 24
Finished Jul 09 07:00:16 PM PDT 24
Peak memory 206912 kb
Host smart-0547b59e-3bc4-4be5-ad8b-6e7c26b67a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846244823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.846244823
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.504635265
Short name T634
Test name
Test status
Simulation time 254241983 ps
CPU time 3.54 seconds
Started Jul 09 07:00:19 PM PDT 24
Finished Jul 09 07:00:26 PM PDT 24
Peak memory 208732 kb
Host smart-5cf4bede-b063-429d-8be3-90011020e59a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504635265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.504635265
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1376243725
Short name T770
Test name
Test status
Simulation time 229309199 ps
CPU time 6.15 seconds
Started Jul 09 07:00:11 PM PDT 24
Finished Jul 09 07:00:20 PM PDT 24
Peak memory 208820 kb
Host smart-a8fbec3a-22e2-4c2a-a5ff-dc31d28a7022
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376243725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1376243725
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.599999893
Short name T471
Test name
Test status
Simulation time 67433471 ps
CPU time 3.2 seconds
Started Jul 09 07:00:14 PM PDT 24
Finished Jul 09 07:00:21 PM PDT 24
Peak memory 208264 kb
Host smart-52e68d08-c885-492e-9afc-d5a11f76c37c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599999893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.599999893
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.4014206522
Short name T833
Test name
Test status
Simulation time 51037664 ps
CPU time 2.68 seconds
Started Jul 09 07:00:14 PM PDT 24
Finished Jul 09 07:00:20 PM PDT 24
Peak memory 207516 kb
Host smart-3e6f13ec-82a6-477d-adff-ded792fd3df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014206522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.4014206522
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3512743931
Short name T464
Test name
Test status
Simulation time 317109679 ps
CPU time 1.9 seconds
Started Jul 09 07:00:09 PM PDT 24
Finished Jul 09 07:00:14 PM PDT 24
Peak memory 207452 kb
Host smart-767b68cc-5115-489e-93d9-62055744b5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512743931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3512743931
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.93239316
Short name T192
Test name
Test status
Simulation time 1053905178 ps
CPU time 20 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:00:39 PM PDT 24
Peak memory 220988 kb
Host smart-fd37705e-4208-43e2-a99d-557698ae4ba5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93239316 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.93239316
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1308038740
Short name T23
Test name
Test status
Simulation time 62691880 ps
CPU time 2.47 seconds
Started Jul 09 07:00:17 PM PDT 24
Finished Jul 09 07:00:24 PM PDT 24
Peak memory 207376 kb
Host smart-e86df762-6341-46d8-81d4-6a39dc4d3141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308038740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1308038740
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.4061458347
Short name T879
Test name
Test status
Simulation time 700097977 ps
CPU time 9.25 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:00:28 PM PDT 24
Peak memory 210608 kb
Host smart-a606f6e7-d27d-40cd-8e7d-4ff67cad0c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061458347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.4061458347
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2514413925
Short name T442
Test name
Test status
Simulation time 35394843 ps
CPU time 0.83 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:00:20 PM PDT 24
Peak memory 205968 kb
Host smart-f0528ed6-2244-4cb5-a0ab-c233b5fad8df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514413925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2514413925
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.992619037
Short name T365
Test name
Test status
Simulation time 45690188 ps
CPU time 3.28 seconds
Started Jul 09 07:00:21 PM PDT 24
Finished Jul 09 07:00:27 PM PDT 24
Peak memory 214360 kb
Host smart-543b9578-3219-4fa3-a2dc-13d5113ec321
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=992619037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.992619037
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.519151183
Short name T10
Test name
Test status
Simulation time 183232330 ps
CPU time 4.31 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:00:23 PM PDT 24
Peak memory 222824 kb
Host smart-7b80a482-837c-4802-9639-0565d279dce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519151183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.519151183
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2365358235
Short name T69
Test name
Test status
Simulation time 90242387 ps
CPU time 2.83 seconds
Started Jul 09 07:00:17 PM PDT 24
Finished Jul 09 07:00:24 PM PDT 24
Peak memory 208320 kb
Host smart-6ae765ff-bf38-4d48-b261-f89d1d7cb21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365358235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2365358235
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1836528198
Short name T296
Test name
Test status
Simulation time 39559492 ps
CPU time 2.58 seconds
Started Jul 09 07:00:16 PM PDT 24
Finished Jul 09 07:00:23 PM PDT 24
Peak memory 214256 kb
Host smart-4ed84b38-d8cb-4ac0-91bd-1b1018edebb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836528198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1836528198
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3268219328
Short name T153
Test name
Test status
Simulation time 295975266 ps
CPU time 3.46 seconds
Started Jul 09 07:00:16 PM PDT 24
Finished Jul 09 07:00:24 PM PDT 24
Peak memory 207632 kb
Host smart-1b127a92-5a7e-4c3f-a925-09b8cf4f8b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268219328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3268219328
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.877394193
Short name T893
Test name
Test status
Simulation time 1822799320 ps
CPU time 37.02 seconds
Started Jul 09 07:00:17 PM PDT 24
Finished Jul 09 07:00:58 PM PDT 24
Peak memory 208656 kb
Host smart-74402212-6845-4329-ae24-3323a4202da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877394193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.877394193
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3007365925
Short name T872
Test name
Test status
Simulation time 283378194 ps
CPU time 4.25 seconds
Started Jul 09 07:00:14 PM PDT 24
Finished Jul 09 07:00:21 PM PDT 24
Peak memory 208492 kb
Host smart-320118ec-0384-4c63-94eb-4489e716f19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007365925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3007365925
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3591725065
Short name T116
Test name
Test status
Simulation time 343468896 ps
CPU time 7.34 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:00:26 PM PDT 24
Peak memory 208812 kb
Host smart-4fc681d3-4d60-4f19-ab4b-81d83eaccffd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591725065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3591725065
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1499101974
Short name T491
Test name
Test status
Simulation time 267824804 ps
CPU time 5.63 seconds
Started Jul 09 07:00:17 PM PDT 24
Finished Jul 09 07:00:27 PM PDT 24
Peak memory 207924 kb
Host smart-3511c258-4724-420d-9eb1-d31499e9dd1e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499101974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1499101974
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2519450398
Short name T216
Test name
Test status
Simulation time 124427421 ps
CPU time 1.92 seconds
Started Jul 09 07:00:14 PM PDT 24
Finished Jul 09 07:00:20 PM PDT 24
Peak memory 206788 kb
Host smart-683879b6-81a4-4396-943a-546bd92fef53
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519450398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2519450398
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1608128832
Short name T533
Test name
Test status
Simulation time 69095375 ps
CPU time 2.38 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:00:22 PM PDT 24
Peak memory 207584 kb
Host smart-dcb4d23c-0474-4d69-9d7c-531294939bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608128832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1608128832
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1802514281
Short name T529
Test name
Test status
Simulation time 88587775 ps
CPU time 3.59 seconds
Started Jul 09 07:00:17 PM PDT 24
Finished Jul 09 07:00:25 PM PDT 24
Peak memory 207000 kb
Host smart-879daa80-9f65-4070-9dce-68824b10f063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802514281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1802514281
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2019618633
Short name T686
Test name
Test status
Simulation time 2170418684 ps
CPU time 10.7 seconds
Started Jul 09 07:00:16 PM PDT 24
Finished Jul 09 07:00:31 PM PDT 24
Peak memory 209356 kb
Host smart-b4e3cf40-3948-4e74-b43f-b994801900e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019618633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2019618633
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3996903077
Short name T184
Test name
Test status
Simulation time 56996014 ps
CPU time 2.51 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:00:22 PM PDT 24
Peak memory 209988 kb
Host smart-b1f46d29-04b4-46be-b531-b5bf64e0d2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996903077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3996903077
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2422890010
Short name T632
Test name
Test status
Simulation time 11223341 ps
CPU time 0.74 seconds
Started Jul 09 07:00:22 PM PDT 24
Finished Jul 09 07:00:26 PM PDT 24
Peak memory 206012 kb
Host smart-52fbe457-b683-4e64-80b9-3388f065e442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422890010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2422890010
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.249232773
Short name T415
Test name
Test status
Simulation time 60231150 ps
CPU time 4.23 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:00:23 PM PDT 24
Peak memory 215060 kb
Host smart-2acf541e-1841-48c3-8b9e-3d3b5b61c23c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=249232773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.249232773
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.4118582287
Short name T527
Test name
Test status
Simulation time 41177841 ps
CPU time 2.13 seconds
Started Jul 09 07:00:27 PM PDT 24
Finished Jul 09 07:00:30 PM PDT 24
Peak memory 218440 kb
Host smart-44ccf20d-803d-404c-b3c3-3acee128fbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118582287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.4118582287
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.387402195
Short name T279
Test name
Test status
Simulation time 615811965 ps
CPU time 2.22 seconds
Started Jul 09 07:00:21 PM PDT 24
Finished Jul 09 07:00:26 PM PDT 24
Peak memory 214356 kb
Host smart-34b635dc-008d-4eed-8fd6-55c7dc6fc546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387402195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.387402195
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.956304597
Short name T786
Test name
Test status
Simulation time 225202294 ps
CPU time 5.02 seconds
Started Jul 09 07:00:20 PM PDT 24
Finished Jul 09 07:00:28 PM PDT 24
Peak memory 221116 kb
Host smart-f63a5161-cc41-4880-9b50-68fb603397b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956304597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.956304597
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2038081721
Short name T55
Test name
Test status
Simulation time 340173106 ps
CPU time 2.42 seconds
Started Jul 09 07:00:23 PM PDT 24
Finished Jul 09 07:00:28 PM PDT 24
Peak memory 214308 kb
Host smart-aad979ab-df64-4812-9b58-4eb67237fde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038081721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2038081721
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1311584892
Short name T851
Test name
Test status
Simulation time 2250835635 ps
CPU time 10.29 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:00:29 PM PDT 24
Peak memory 208544 kb
Host smart-5af879b0-1376-46b8-9f93-241a6dcbd698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311584892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1311584892
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.4209142025
Short name T865
Test name
Test status
Simulation time 113396805 ps
CPU time 1.85 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:00:21 PM PDT 24
Peak memory 206752 kb
Host smart-b1872984-5b86-4c5f-9268-062bb26598fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209142025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.4209142025
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3214115740
Short name T603
Test name
Test status
Simulation time 66053781 ps
CPU time 2.71 seconds
Started Jul 09 07:00:16 PM PDT 24
Finished Jul 09 07:00:24 PM PDT 24
Peak memory 206980 kb
Host smart-3a887289-fd0a-45f8-a3e7-fb586304aed4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214115740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3214115740
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2927379379
Short name T808
Test name
Test status
Simulation time 85654768 ps
CPU time 2.34 seconds
Started Jul 09 07:00:14 PM PDT 24
Finished Jul 09 07:00:19 PM PDT 24
Peak memory 207532 kb
Host smart-6cef2e28-2039-4643-80fb-a3b067f5861e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927379379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2927379379
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3479839183
Short name T902
Test name
Test status
Simulation time 224017157 ps
CPU time 6.52 seconds
Started Jul 09 07:00:18 PM PDT 24
Finished Jul 09 07:00:29 PM PDT 24
Peak memory 208224 kb
Host smart-6a4f2ab9-cfa9-4a72-b344-11f1bff35083
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479839183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3479839183
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3530958121
Short name T822
Test name
Test status
Simulation time 501187759 ps
CPU time 6.27 seconds
Started Jul 09 07:00:21 PM PDT 24
Finished Jul 09 07:00:30 PM PDT 24
Peak memory 214324 kb
Host smart-02707a0f-dff5-474a-9181-15786075537a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530958121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3530958121
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1917214161
Short name T96
Test name
Test status
Simulation time 48811022 ps
CPU time 1.9 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:00:20 PM PDT 24
Peak memory 208652 kb
Host smart-bd4b77ed-278c-4e06-ab96-7f668d8ad718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917214161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1917214161
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2902869107
Short name T230
Test name
Test status
Simulation time 1039863584 ps
CPU time 19.15 seconds
Started Jul 09 07:00:21 PM PDT 24
Finished Jul 09 07:00:43 PM PDT 24
Peak memory 216484 kb
Host smart-93f8c566-e614-4536-93c4-c65afa2bdace
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902869107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2902869107
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2470731673
Short name T172
Test name
Test status
Simulation time 739567466 ps
CPU time 16.58 seconds
Started Jul 09 07:00:22 PM PDT 24
Finished Jul 09 07:00:41 PM PDT 24
Peak memory 219644 kb
Host smart-da2bda7c-7756-487c-bf14-d7c9c1d8b4c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470731673 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2470731673
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.567742008
Short name T149
Test name
Test status
Simulation time 67307741 ps
CPU time 2.86 seconds
Started Jul 09 07:00:22 PM PDT 24
Finished Jul 09 07:00:27 PM PDT 24
Peak memory 210208 kb
Host smart-d84eda90-0ed5-414d-b364-e60001a16466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567742008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.567742008
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1379381459
Short name T735
Test name
Test status
Simulation time 13989094 ps
CPU time 0.9 seconds
Started Jul 09 07:00:29 PM PDT 24
Finished Jul 09 07:00:31 PM PDT 24
Peak memory 206136 kb
Host smart-9bf21270-5e18-4b3e-a0c0-4abae6c6ad83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379381459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1379381459
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3604483682
Short name T860
Test name
Test status
Simulation time 214933049 ps
CPU time 2.12 seconds
Started Jul 09 07:00:30 PM PDT 24
Finished Jul 09 07:00:34 PM PDT 24
Peak memory 209532 kb
Host smart-123a52e3-1a52-475e-9d14-60b4db304f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604483682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3604483682
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1647351498
Short name T730
Test name
Test status
Simulation time 37287188 ps
CPU time 2.59 seconds
Started Jul 09 07:00:23 PM PDT 24
Finished Jul 09 07:00:28 PM PDT 24
Peak memory 219700 kb
Host smart-3f9370da-3d91-4aa1-84cc-0c4c2b8e75af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647351498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1647351498
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.469180134
Short name T304
Test name
Test status
Simulation time 438204694 ps
CPU time 6.31 seconds
Started Jul 09 07:00:20 PM PDT 24
Finished Jul 09 07:00:30 PM PDT 24
Peak memory 209496 kb
Host smart-550ce2ef-e4ec-4c5a-b689-ce3a03a31451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469180134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.469180134
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1163463664
Short name T224
Test name
Test status
Simulation time 205506537 ps
CPU time 4.02 seconds
Started Jul 09 07:00:21 PM PDT 24
Finished Jul 09 07:00:28 PM PDT 24
Peak memory 208724 kb
Host smart-7af87af8-e9c0-453d-b840-aef45a164dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163463664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1163463664
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.658553006
Short name T262
Test name
Test status
Simulation time 15236509776 ps
CPU time 45.13 seconds
Started Jul 09 07:00:19 PM PDT 24
Finished Jul 09 07:01:08 PM PDT 24
Peak memory 220688 kb
Host smart-9cab9e2f-5ce4-4946-9611-7a4bea3f814d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658553006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.658553006
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3727065902
Short name T787
Test name
Test status
Simulation time 448396842 ps
CPU time 6.02 seconds
Started Jul 09 07:00:22 PM PDT 24
Finished Jul 09 07:00:30 PM PDT 24
Peak memory 208696 kb
Host smart-ae3c98fe-2fa0-4634-be90-e4219fc70808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727065902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3727065902
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2458698081
Short name T214
Test name
Test status
Simulation time 540012760 ps
CPU time 4.86 seconds
Started Jul 09 07:00:20 PM PDT 24
Finished Jul 09 07:00:28 PM PDT 24
Peak memory 206768 kb
Host smart-b8d0b02f-7d8d-4241-8ae0-15f34a0fffc2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458698081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2458698081
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.934852763
Short name T875
Test name
Test status
Simulation time 3071491546 ps
CPU time 20.24 seconds
Started Jul 09 07:00:27 PM PDT 24
Finished Jul 09 07:00:49 PM PDT 24
Peak memory 208248 kb
Host smart-34c0b9dc-8b2a-4d30-a329-32a2ba0704ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934852763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.934852763
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3886526066
Short name T122
Test name
Test status
Simulation time 59959600 ps
CPU time 3.01 seconds
Started Jul 09 07:00:22 PM PDT 24
Finished Jul 09 07:00:28 PM PDT 24
Peak memory 208916 kb
Host smart-9e285afe-bde3-407e-ae9d-29bad4fab9d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886526066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3886526066
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.4116781173
Short name T516
Test name
Test status
Simulation time 291540720 ps
CPU time 5.29 seconds
Started Jul 09 07:00:28 PM PDT 24
Finished Jul 09 07:00:35 PM PDT 24
Peak memory 209252 kb
Host smart-d7074577-47c1-4589-9b05-90194a78bcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116781173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.4116781173
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2037419764
Short name T749
Test name
Test status
Simulation time 82885166 ps
CPU time 2.67 seconds
Started Jul 09 07:00:22 PM PDT 24
Finished Jul 09 07:00:27 PM PDT 24
Peak memory 208812 kb
Host smart-07184eea-3810-46b1-bcff-175641a3050f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037419764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2037419764
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3038988764
Short name T198
Test name
Test status
Simulation time 5295590899 ps
CPU time 51.18 seconds
Started Jul 09 07:00:25 PM PDT 24
Finished Jul 09 07:01:18 PM PDT 24
Peak memory 222668 kb
Host smart-bbcc2f19-f042-461d-b135-38d0de089bb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038988764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3038988764
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1651000168
Short name T813
Test name
Test status
Simulation time 526335127 ps
CPU time 15.02 seconds
Started Jul 09 07:00:27 PM PDT 24
Finished Jul 09 07:00:43 PM PDT 24
Peak memory 221276 kb
Host smart-58fdeeaa-060a-4961-b4a7-0558f7db8b8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651000168 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1651000168
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1693226723
Short name T94
Test name
Test status
Simulation time 49955835 ps
CPU time 3.25 seconds
Started Jul 09 07:00:22 PM PDT 24
Finished Jul 09 07:00:28 PM PDT 24
Peak memory 208292 kb
Host smart-90ea416a-210c-4435-bff6-577ae602550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693226723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1693226723
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3746232885
Short name T201
Test name
Test status
Simulation time 58392877 ps
CPU time 1.76 seconds
Started Jul 09 07:00:28 PM PDT 24
Finished Jul 09 07:00:31 PM PDT 24
Peak memory 209752 kb
Host smart-33691582-740d-4d88-ba04-5bf4fe9426b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746232885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3746232885
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3982034543
Short name T650
Test name
Test status
Simulation time 125677368 ps
CPU time 0.83 seconds
Started Jul 09 07:00:33 PM PDT 24
Finished Jul 09 07:00:35 PM PDT 24
Peak memory 205984 kb
Host smart-a40f199c-a8fd-4865-8b33-aa9ef64c5f30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982034543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3982034543
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3804272380
Short name T419
Test name
Test status
Simulation time 221303692 ps
CPU time 12.2 seconds
Started Jul 09 07:00:29 PM PDT 24
Finished Jul 09 07:00:43 PM PDT 24
Peak memory 215004 kb
Host smart-7dc7867f-9012-451d-a61d-d66405df7109
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804272380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3804272380
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2799950538
Short name T30
Test name
Test status
Simulation time 569176272 ps
CPU time 2.8 seconds
Started Jul 09 07:00:25 PM PDT 24
Finished Jul 09 07:00:29 PM PDT 24
Peak memory 220384 kb
Host smart-e1f4175c-c097-429f-83e1-8be46b272f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799950538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2799950538
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.7959077
Short name T488
Test name
Test status
Simulation time 126195293 ps
CPU time 1.9 seconds
Started Jul 09 07:00:27 PM PDT 24
Finished Jul 09 07:00:30 PM PDT 24
Peak memory 208172 kb
Host smart-e2df5da2-04b3-40bf-9184-5509a835284c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7959077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.7959077
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.4159199420
Short name T825
Test name
Test status
Simulation time 32359440 ps
CPU time 2.5 seconds
Started Jul 09 07:00:28 PM PDT 24
Finished Jul 09 07:00:32 PM PDT 24
Peak memory 214360 kb
Host smart-b148f7cb-8f1d-46c9-89f8-c83e9fbb7d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159199420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.4159199420
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1188910044
Short name T253
Test name
Test status
Simulation time 412631177 ps
CPU time 4.57 seconds
Started Jul 09 07:00:31 PM PDT 24
Finished Jul 09 07:00:36 PM PDT 24
Peak memory 206052 kb
Host smart-af3d29e2-8032-4e44-a570-6a0c9f491038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188910044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1188910044
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3986653813
Short name T903
Test name
Test status
Simulation time 235842813 ps
CPU time 3.55 seconds
Started Jul 09 07:00:28 PM PDT 24
Finished Jul 09 07:00:33 PM PDT 24
Peak memory 208016 kb
Host smart-15a676c8-e48e-46e4-a018-d1e895f19ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986653813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3986653813
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.564197417
Short name T547
Test name
Test status
Simulation time 127510509 ps
CPU time 3.43 seconds
Started Jul 09 07:00:32 PM PDT 24
Finished Jul 09 07:00:37 PM PDT 24
Peak memory 208220 kb
Host smart-59249db2-45d1-4fdc-a749-1d59db51bbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564197417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.564197417
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.239729001
Short name T816
Test name
Test status
Simulation time 342214188 ps
CPU time 3.84 seconds
Started Jul 09 07:00:25 PM PDT 24
Finished Jul 09 07:00:30 PM PDT 24
Peak memory 208748 kb
Host smart-720686f4-1394-4fe0-9d77-1a3a49a85434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239729001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.239729001
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.903722593
Short name T386
Test name
Test status
Simulation time 555720382 ps
CPU time 5.38 seconds
Started Jul 09 07:00:30 PM PDT 24
Finished Jul 09 07:00:37 PM PDT 24
Peak memory 207944 kb
Host smart-f2629cd1-3abd-4cda-8a9c-7fb6590b4b53
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903722593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.903722593
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2277080086
Short name T457
Test name
Test status
Simulation time 814039244 ps
CPU time 6.03 seconds
Started Jul 09 07:00:27 PM PDT 24
Finished Jul 09 07:00:34 PM PDT 24
Peak memory 207804 kb
Host smart-8e7022ed-f20f-443d-ae66-1c48927ad333
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277080086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2277080086
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.4160234546
Short name T462
Test name
Test status
Simulation time 108494792 ps
CPU time 2.12 seconds
Started Jul 09 07:00:25 PM PDT 24
Finished Jul 09 07:00:29 PM PDT 24
Peak memory 206976 kb
Host smart-e776be61-bce9-4301-a40e-9593f6a632ed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160234546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.4160234546
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3162033278
Short name T47
Test name
Test status
Simulation time 97525481 ps
CPU time 2.67 seconds
Started Jul 09 07:00:26 PM PDT 24
Finished Jul 09 07:00:29 PM PDT 24
Peak memory 208072 kb
Host smart-4156a8dc-236c-49a6-9eab-312f8b4fa249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162033278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3162033278
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2023815140
Short name T726
Test name
Test status
Simulation time 59483149 ps
CPU time 2.57 seconds
Started Jul 09 07:00:29 PM PDT 24
Finished Jul 09 07:00:33 PM PDT 24
Peak memory 208348 kb
Host smart-79ec9190-f5cf-469d-b03b-bc3f85f41d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023815140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2023815140
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1626093534
Short name T602
Test name
Test status
Simulation time 1119920842 ps
CPU time 5.96 seconds
Started Jul 09 07:00:27 PM PDT 24
Finished Jul 09 07:00:34 PM PDT 24
Peak memory 214340 kb
Host smart-35fadaac-c4e8-4c48-9d27-e5a1596552d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626093534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1626093534
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3120127461
Short name T42
Test name
Test status
Simulation time 89683149 ps
CPU time 2.59 seconds
Started Jul 09 07:00:25 PM PDT 24
Finished Jul 09 07:00:29 PM PDT 24
Peak memory 210448 kb
Host smart-6c568413-1ba2-4f7e-bd6d-577e1baf7304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120127461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3120127461
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3569957102
Short name T113
Test name
Test status
Simulation time 12541587 ps
CPU time 0.86 seconds
Started Jul 09 07:00:46 PM PDT 24
Finished Jul 09 07:00:49 PM PDT 24
Peak memory 206004 kb
Host smart-dfb16b26-3d18-4207-9ae8-5cf0991920b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569957102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3569957102
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2337473242
Short name T868
Test name
Test status
Simulation time 111768215 ps
CPU time 2.42 seconds
Started Jul 09 07:00:36 PM PDT 24
Finished Jul 09 07:00:40 PM PDT 24
Peak memory 214448 kb
Host smart-a044c55d-93f1-4f62-9f6c-911a36fe728c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2337473242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2337473242
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1591963972
Short name T70
Test name
Test status
Simulation time 53180737 ps
CPU time 2.58 seconds
Started Jul 09 07:00:36 PM PDT 24
Finished Jul 09 07:00:39 PM PDT 24
Peak memory 214336 kb
Host smart-58b2b8fc-940c-4202-a63b-5261a49108b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591963972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1591963972
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3339318117
Short name T109
Test name
Test status
Simulation time 36359841 ps
CPU time 2.58 seconds
Started Jul 09 07:00:36 PM PDT 24
Finished Jul 09 07:00:40 PM PDT 24
Peak memory 222428 kb
Host smart-7fa75c11-3ced-4dee-93a9-c2b3976d2cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339318117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3339318117
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.599149973
Short name T336
Test name
Test status
Simulation time 48107957 ps
CPU time 3.14 seconds
Started Jul 09 07:00:32 PM PDT 24
Finished Jul 09 07:00:36 PM PDT 24
Peak memory 221308 kb
Host smart-ed56820f-a24f-4e23-8f31-210a8841b0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599149973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.599149973
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_random.3473631893
Short name T800
Test name
Test status
Simulation time 175618157 ps
CPU time 5.41 seconds
Started Jul 09 07:00:31 PM PDT 24
Finished Jul 09 07:00:38 PM PDT 24
Peak memory 210020 kb
Host smart-c9d7e316-30ed-45ea-83b1-9bd2ee201997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473631893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3473631893
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.973142740
Short name T708
Test name
Test status
Simulation time 92395442 ps
CPU time 2.62 seconds
Started Jul 09 07:00:31 PM PDT 24
Finished Jul 09 07:00:35 PM PDT 24
Peak memory 206916 kb
Host smart-047e9201-5c0c-4067-b5ac-4d723b540642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973142740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.973142740
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2323302251
Short name T503
Test name
Test status
Simulation time 55950386 ps
CPU time 2.94 seconds
Started Jul 09 07:00:36 PM PDT 24
Finished Jul 09 07:00:40 PM PDT 24
Peak memory 208220 kb
Host smart-5e5a6b0f-6962-4346-84bb-0f1c03ded394
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323302251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2323302251
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2470690864
Short name T631
Test name
Test status
Simulation time 90883264 ps
CPU time 3 seconds
Started Jul 09 07:00:31 PM PDT 24
Finished Jul 09 07:00:35 PM PDT 24
Peak memory 206932 kb
Host smart-0d3a976e-8158-4a13-a470-6c389d7bfaa7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470690864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2470690864
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2335588438
Short name T558
Test name
Test status
Simulation time 73438671 ps
CPU time 3.68 seconds
Started Jul 09 07:00:34 PM PDT 24
Finished Jul 09 07:00:39 PM PDT 24
Peak memory 208696 kb
Host smart-86e4d0e7-8cb8-4666-bb55-dfa1f1797dec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335588438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2335588438
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2651726365
Short name T147
Test name
Test status
Simulation time 64431668 ps
CPU time 1.55 seconds
Started Jul 09 07:00:32 PM PDT 24
Finished Jul 09 07:00:35 PM PDT 24
Peak memory 215500 kb
Host smart-2b0cd1cc-7660-4ba0-aaa9-f2696dc2d328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651726365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2651726365
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1201690836
Short name T737
Test name
Test status
Simulation time 108934236 ps
CPU time 2.2 seconds
Started Jul 09 07:00:37 PM PDT 24
Finished Jul 09 07:00:41 PM PDT 24
Peak memory 206880 kb
Host smart-e8341e49-6900-4bf0-81b6-1b1779672ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201690836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1201690836
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3564612687
Short name T342
Test name
Test status
Simulation time 21764960337 ps
CPU time 59.65 seconds
Started Jul 09 07:00:35 PM PDT 24
Finished Jul 09 07:01:36 PM PDT 24
Peak memory 215028 kb
Host smart-29614b7d-14ac-433f-bce8-4cb2297c7091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564612687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3564612687
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2798550387
Short name T619
Test name
Test status
Simulation time 468756694 ps
CPU time 4.36 seconds
Started Jul 09 07:00:33 PM PDT 24
Finished Jul 09 07:00:38 PM PDT 24
Peak memory 208800 kb
Host smart-0aa6c7a7-929d-40be-9d10-00a35c208453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798550387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2798550387
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3388189180
Short name T196
Test name
Test status
Simulation time 65518551 ps
CPU time 1.24 seconds
Started Jul 09 07:00:32 PM PDT 24
Finished Jul 09 07:00:35 PM PDT 24
Peak memory 208640 kb
Host smart-4ca10775-75d3-4d46-b4ea-dfc15341ad31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388189180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3388189180
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2260784477
Short name T747
Test name
Test status
Simulation time 11288252 ps
CPU time 0.86 seconds
Started Jul 09 07:00:54 PM PDT 24
Finished Jul 09 07:00:58 PM PDT 24
Peak memory 205972 kb
Host smart-9e402383-faca-4bde-892a-1b884ea882d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260784477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2260784477
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2753131208
Short name T535
Test name
Test status
Simulation time 56289556 ps
CPU time 1.98 seconds
Started Jul 09 07:00:36 PM PDT 24
Finished Jul 09 07:00:40 PM PDT 24
Peak memory 222136 kb
Host smart-4dc1f880-733b-434f-b1eb-b2fc628a7b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753131208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2753131208
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3701535482
Short name T604
Test name
Test status
Simulation time 131094273 ps
CPU time 3.2 seconds
Started Jul 09 07:00:30 PM PDT 24
Finished Jul 09 07:00:35 PM PDT 24
Peak memory 218452 kb
Host smart-776f1ab4-f24f-40b0-8e48-653ffa8f264b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701535482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3701535482
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3003706521
Short name T719
Test name
Test status
Simulation time 98900163 ps
CPU time 2.85 seconds
Started Jul 09 07:00:31 PM PDT 24
Finished Jul 09 07:00:35 PM PDT 24
Peak memory 214360 kb
Host smart-1e07f9d6-0168-4669-a53d-1403aaf8b522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003706521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3003706521
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.561421030
Short name T599
Test name
Test status
Simulation time 116798840 ps
CPU time 5.41 seconds
Started Jul 09 07:00:37 PM PDT 24
Finished Jul 09 07:00:44 PM PDT 24
Peak memory 214240 kb
Host smart-c55757bd-df03-47b5-90f9-a73d98425239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561421030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.561421030
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1664717085
Short name T225
Test name
Test status
Simulation time 362835096 ps
CPU time 3.04 seconds
Started Jul 09 07:00:34 PM PDT 24
Finished Jul 09 07:00:38 PM PDT 24
Peak memory 220688 kb
Host smart-baa3aba9-1dbc-4caa-9a9f-9bf8fef39a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664717085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1664717085
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1441310413
Short name T850
Test name
Test status
Simulation time 653262361 ps
CPU time 5.24 seconds
Started Jul 09 07:00:35 PM PDT 24
Finished Jul 09 07:00:41 PM PDT 24
Peak memory 218232 kb
Host smart-0c86e858-b0b7-49c8-b2ad-9f585741d995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441310413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1441310413
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2352433644
Short name T368
Test name
Test status
Simulation time 400290239 ps
CPU time 3.34 seconds
Started Jul 09 07:00:33 PM PDT 24
Finished Jul 09 07:00:37 PM PDT 24
Peak memory 206728 kb
Host smart-5ddfe28a-5c34-4b8b-b646-343f15e0b9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352433644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2352433644
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2282079010
Short name T913
Test name
Test status
Simulation time 184789060 ps
CPU time 2.53 seconds
Started Jul 09 07:00:33 PM PDT 24
Finished Jul 09 07:00:36 PM PDT 24
Peak memory 206976 kb
Host smart-0201c7a0-03e0-45f1-8613-75175fed9424
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282079010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2282079010
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3733011854
Short name T655
Test name
Test status
Simulation time 1446918531 ps
CPU time 22.13 seconds
Started Jul 09 07:00:34 PM PDT 24
Finished Jul 09 07:00:58 PM PDT 24
Peak memory 208684 kb
Host smart-8817944d-a725-46e3-97c5-58604bcf6cad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733011854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3733011854
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.939742145
Short name T363
Test name
Test status
Simulation time 1035756232 ps
CPU time 8.97 seconds
Started Jul 09 07:00:32 PM PDT 24
Finished Jul 09 07:00:42 PM PDT 24
Peak memory 209020 kb
Host smart-a6820003-2c06-451b-abf1-e0ee0b79c9c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939742145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.939742145
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.804009598
Short name T571
Test name
Test status
Simulation time 414864604 ps
CPU time 3 seconds
Started Jul 09 07:00:37 PM PDT 24
Finished Jul 09 07:00:41 PM PDT 24
Peak memory 209412 kb
Host smart-60005067-b031-4cce-9f4b-916955ef8b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804009598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.804009598
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3665579174
Short name T588
Test name
Test status
Simulation time 716653399 ps
CPU time 3.79 seconds
Started Jul 09 07:00:30 PM PDT 24
Finished Jul 09 07:00:35 PM PDT 24
Peak memory 206976 kb
Host smart-2b9129f0-c8d9-4409-87e3-7820e068721b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665579174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3665579174
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3002105628
Short name T223
Test name
Test status
Simulation time 2607636473 ps
CPU time 19.29 seconds
Started Jul 09 07:00:54 PM PDT 24
Finished Jul 09 07:01:15 PM PDT 24
Peak memory 216664 kb
Host smart-da36b0aa-a245-4252-b4dd-0d8bc067e5fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002105628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3002105628
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.799702852
Short name T123
Test name
Test status
Simulation time 403383688 ps
CPU time 15.53 seconds
Started Jul 09 07:00:37 PM PDT 24
Finished Jul 09 07:00:54 PM PDT 24
Peak memory 219392 kb
Host smart-cd757cf1-156b-408b-87fe-f027b12c3a72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799702852 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.799702852
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3818910560
Short name T853
Test name
Test status
Simulation time 557311546 ps
CPU time 6.67 seconds
Started Jul 09 07:00:34 PM PDT 24
Finished Jul 09 07:00:42 PM PDT 24
Peak memory 208320 kb
Host smart-2e70aecb-1766-41ba-9fa1-c9366ba76f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818910560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3818910560
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.841820973
Short name T394
Test name
Test status
Simulation time 114913453 ps
CPU time 1.89 seconds
Started Jul 09 07:00:38 PM PDT 24
Finished Jul 09 07:00:42 PM PDT 24
Peak memory 208844 kb
Host smart-d828ebe7-76fa-4390-8dc1-58260bd82372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841820973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.841820973
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1196845675
Short name T657
Test name
Test status
Simulation time 13151614 ps
CPU time 0.73 seconds
Started Jul 09 07:00:38 PM PDT 24
Finished Jul 09 07:00:41 PM PDT 24
Peak memory 205960 kb
Host smart-1b0e3e34-a2b0-47ce-8346-21e7e2fe4e56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196845675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1196845675
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.689379791
Short name T426
Test name
Test status
Simulation time 210032921 ps
CPU time 11.92 seconds
Started Jul 09 07:00:36 PM PDT 24
Finished Jul 09 07:00:50 PM PDT 24
Peak memory 214348 kb
Host smart-766ac553-27db-4a00-80bc-3e1a395e25d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=689379791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.689379791
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.493073655
Short name T31
Test name
Test status
Simulation time 599811444 ps
CPU time 2.83 seconds
Started Jul 09 07:00:38 PM PDT 24
Finished Jul 09 07:00:42 PM PDT 24
Peak memory 209848 kb
Host smart-399ab9ad-ce72-49db-a775-0bcb205b8bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493073655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.493073655
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3639467823
Short name T545
Test name
Test status
Simulation time 264629906 ps
CPU time 3.33 seconds
Started Jul 09 07:00:54 PM PDT 24
Finished Jul 09 07:01:01 PM PDT 24
Peak memory 207616 kb
Host smart-8e6f2eb3-c93d-4c78-a203-aa055faf9d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639467823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3639467823
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1284444085
Short name T739
Test name
Test status
Simulation time 39424430 ps
CPU time 2.47 seconds
Started Jul 09 07:00:36 PM PDT 24
Finished Jul 09 07:00:40 PM PDT 24
Peak memory 222552 kb
Host smart-52461a52-b046-439d-8167-25ba087102b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284444085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1284444085
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.111911327
Short name T104
Test name
Test status
Simulation time 524098699 ps
CPU time 5.32 seconds
Started Jul 09 07:00:54 PM PDT 24
Finished Jul 09 07:01:03 PM PDT 24
Peak memory 222448 kb
Host smart-1902c0c3-1c00-454a-abd3-54cd6256162d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111911327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.111911327
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1845702805
Short name T56
Test name
Test status
Simulation time 96555754 ps
CPU time 3.05 seconds
Started Jul 09 07:00:39 PM PDT 24
Finished Jul 09 07:00:44 PM PDT 24
Peak memory 215880 kb
Host smart-cac5b345-70e2-4fa5-b3f4-b0233bd1b696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845702805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1845702805
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.65921856
Short name T302
Test name
Test status
Simulation time 164891547 ps
CPU time 7.39 seconds
Started Jul 09 07:00:39 PM PDT 24
Finished Jul 09 07:00:48 PM PDT 24
Peak memory 210192 kb
Host smart-90e2fae2-cc74-48fd-bddf-c35223763e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65921856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.65921856
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3490662671
Short name T144
Test name
Test status
Simulation time 101715498 ps
CPU time 4.43 seconds
Started Jul 09 07:00:37 PM PDT 24
Finished Jul 09 07:00:43 PM PDT 24
Peak memory 208784 kb
Host smart-6ed768f9-0132-4fd7-95e1-7c716adf3593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490662671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3490662671
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2025347202
Short name T519
Test name
Test status
Simulation time 156519200 ps
CPU time 2.74 seconds
Started Jul 09 07:00:39 PM PDT 24
Finished Jul 09 07:00:43 PM PDT 24
Peak memory 206804 kb
Host smart-4017fa21-bd81-48fb-ab59-8982c283434c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025347202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2025347202
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3282970410
Short name T499
Test name
Test status
Simulation time 29798388 ps
CPU time 2.27 seconds
Started Jul 09 07:00:54 PM PDT 24
Finished Jul 09 07:00:59 PM PDT 24
Peak memory 208712 kb
Host smart-e5378d03-5d85-4d22-87e0-3afd5a2cc04e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282970410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3282970410
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.681800398
Short name T828
Test name
Test status
Simulation time 19596132 ps
CPU time 1.78 seconds
Started Jul 09 07:00:37 PM PDT 24
Finished Jul 09 07:00:40 PM PDT 24
Peak memory 206972 kb
Host smart-56023a76-5c3c-409f-8fe7-9f696c82e4a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681800398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.681800398
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.775776702
Short name T544
Test name
Test status
Simulation time 949495125 ps
CPU time 6.25 seconds
Started Jul 09 07:00:38 PM PDT 24
Finished Jul 09 07:00:46 PM PDT 24
Peak memory 218300 kb
Host smart-3d7498de-e0fc-4d09-8e49-844984677ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775776702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.775776702
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.912551280
Short name T744
Test name
Test status
Simulation time 48291728 ps
CPU time 2.27 seconds
Started Jul 09 07:00:54 PM PDT 24
Finished Jul 09 07:01:00 PM PDT 24
Peak memory 206864 kb
Host smart-b10e0941-b24a-42df-ba9b-69b9f06719ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912551280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.912551280
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1902514073
Short name T329
Test name
Test status
Simulation time 1793028011 ps
CPU time 18.8 seconds
Started Jul 09 07:00:40 PM PDT 24
Finished Jul 09 07:01:00 PM PDT 24
Peak memory 222380 kb
Host smart-26c78092-c280-4497-a3ed-67b869040efd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902514073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1902514073
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.73087104
Short name T134
Test name
Test status
Simulation time 571928482 ps
CPU time 11.57 seconds
Started Jul 09 07:00:36 PM PDT 24
Finished Jul 09 07:00:49 PM PDT 24
Peak memory 218632 kb
Host smart-4d7e8d76-7f71-42ff-b388-596bf06cbebc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73087104 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.73087104
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1358114921
Short name T252
Test name
Test status
Simulation time 379624181 ps
CPU time 3.88 seconds
Started Jul 09 07:00:38 PM PDT 24
Finished Jul 09 07:00:43 PM PDT 24
Peak memory 218284 kb
Host smart-de689d0e-c725-4845-a83d-5ba725411607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358114921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1358114921
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3592688390
Short name T146
Test name
Test status
Simulation time 72408168 ps
CPU time 2.49 seconds
Started Jul 09 07:00:37 PM PDT 24
Finished Jul 09 07:00:41 PM PDT 24
Peak memory 210144 kb
Host smart-83cc29c9-3ea4-4c73-9b86-7a18d8bf1944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592688390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3592688390
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.436386057
Short name T593
Test name
Test status
Simulation time 49368264 ps
CPU time 0.83 seconds
Started Jul 09 07:00:51 PM PDT 24
Finished Jul 09 07:00:54 PM PDT 24
Peak memory 206008 kb
Host smart-54473bd6-6e26-421f-9945-03992d8032f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436386057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.436386057
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1901692329
Short name T418
Test name
Test status
Simulation time 213676385 ps
CPU time 4.1 seconds
Started Jul 09 07:00:45 PM PDT 24
Finished Jul 09 07:00:51 PM PDT 24
Peak memory 215392 kb
Host smart-6a5ddea3-7ad6-4153-a96a-304693440409
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1901692329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1901692329
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3099815715
Short name T669
Test name
Test status
Simulation time 78345034 ps
CPU time 2.72 seconds
Started Jul 09 07:00:44 PM PDT 24
Finished Jul 09 07:00:49 PM PDT 24
Peak memory 218820 kb
Host smart-645bf7ec-c00a-4160-9272-21ef2061671f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099815715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3099815715
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3875073371
Short name T584
Test name
Test status
Simulation time 17755983 ps
CPU time 1.51 seconds
Started Jul 09 07:00:42 PM PDT 24
Finished Jul 09 07:00:45 PM PDT 24
Peak memory 207440 kb
Host smart-c86edc29-8be7-4be6-81f8-4df182512663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875073371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3875073371
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2172035637
Short name T718
Test name
Test status
Simulation time 126441918 ps
CPU time 1.9 seconds
Started Jul 09 07:00:46 PM PDT 24
Finished Jul 09 07:00:50 PM PDT 24
Peak memory 206204 kb
Host smart-46f905a5-0c9f-4089-a287-15b93b2c598c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172035637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2172035637
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.227338296
Short name T723
Test name
Test status
Simulation time 388940215 ps
CPU time 4.06 seconds
Started Jul 09 07:00:45 PM PDT 24
Finished Jul 09 07:00:51 PM PDT 24
Peak memory 207400 kb
Host smart-c9fc83e1-39ea-407b-935f-11d4c4f714cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227338296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.227338296
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.332865231
Short name T898
Test name
Test status
Simulation time 20419067 ps
CPU time 1.8 seconds
Started Jul 09 07:00:40 PM PDT 24
Finished Jul 09 07:00:43 PM PDT 24
Peak memory 206724 kb
Host smart-fc1cde64-b078-4b53-92bb-ff7247e4256e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332865231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.332865231
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3049671152
Short name T265
Test name
Test status
Simulation time 231606087 ps
CPU time 2.12 seconds
Started Jul 09 07:00:45 PM PDT 24
Finished Jul 09 07:00:49 PM PDT 24
Peak memory 208972 kb
Host smart-f0a1a41f-624b-4583-b1aa-085a532cf337
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049671152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3049671152
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1701527384
Short name T651
Test name
Test status
Simulation time 241316722 ps
CPU time 2.98 seconds
Started Jul 09 07:00:45 PM PDT 24
Finished Jul 09 07:00:50 PM PDT 24
Peak memory 207024 kb
Host smart-38a5982c-b76e-4f0e-b750-21e3c64d285c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701527384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1701527384
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3377599688
Short name T810
Test name
Test status
Simulation time 1767064349 ps
CPU time 10.36 seconds
Started Jul 09 07:00:43 PM PDT 24
Finished Jul 09 07:00:55 PM PDT 24
Peak memory 207100 kb
Host smart-a965636d-5252-4dcd-ab13-faa33c4aad25
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377599688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3377599688
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1278305773
Short name T546
Test name
Test status
Simulation time 113766790 ps
CPU time 3.09 seconds
Started Jul 09 07:00:42 PM PDT 24
Finished Jul 09 07:00:47 PM PDT 24
Peak memory 215896 kb
Host smart-cdfd51dc-ee19-4915-9ea8-d32772ae912a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278305773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1278305773
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.754078814
Short name T562
Test name
Test status
Simulation time 229233868 ps
CPU time 2.12 seconds
Started Jul 09 07:00:39 PM PDT 24
Finished Jul 09 07:00:43 PM PDT 24
Peak memory 206952 kb
Host smart-d1e70be8-b994-49e5-91ab-9231fa5f5886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754078814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.754078814
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3225815959
Short name T742
Test name
Test status
Simulation time 616959829 ps
CPU time 6.8 seconds
Started Jul 09 07:00:43 PM PDT 24
Finished Jul 09 07:00:51 PM PDT 24
Peak memory 208680 kb
Host smart-b0dc0455-ec05-4670-bf29-150e9ea71214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225815959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3225815959
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.959807261
Short name T722
Test name
Test status
Simulation time 4057093174 ps
CPU time 18.38 seconds
Started Jul 09 07:00:42 PM PDT 24
Finished Jul 09 07:01:01 PM PDT 24
Peak memory 222648 kb
Host smart-94c80f3d-091e-42a7-aafb-9051643ae4a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959807261 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.959807261
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.664273761
Short name T511
Test name
Test status
Simulation time 225535789 ps
CPU time 4.23 seconds
Started Jul 09 07:00:44 PM PDT 24
Finished Jul 09 07:00:51 PM PDT 24
Peak memory 207852 kb
Host smart-a8aee8ca-1ecb-4a6d-98d8-fe0f69039751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664273761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.664273761
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1080002033
Short name T461
Test name
Test status
Simulation time 52200388 ps
CPU time 2.05 seconds
Started Jul 09 07:00:43 PM PDT 24
Finished Jul 09 07:00:46 PM PDT 24
Peak memory 210224 kb
Host smart-c80f0fa0-7f69-4459-9eea-8f0fbcf8a9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080002033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1080002033
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2892672272
Short name T117
Test name
Test status
Simulation time 7867665 ps
CPU time 0.79 seconds
Started Jul 09 07:00:54 PM PDT 24
Finished Jul 09 07:00:58 PM PDT 24
Peak memory 206000 kb
Host smart-edf02aee-62ba-42c6-aaa0-6120f44b10bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892672272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2892672272
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1622721774
Short name T430
Test name
Test status
Simulation time 48303522 ps
CPU time 3.5 seconds
Started Jul 09 07:00:44 PM PDT 24
Finished Jul 09 07:00:49 PM PDT 24
Peak memory 214320 kb
Host smart-60f37626-d16f-48d3-8b20-4c2f9e74e48a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1622721774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1622721774
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3780359129
Short name T232
Test name
Test status
Simulation time 148321161 ps
CPU time 3.79 seconds
Started Jul 09 07:00:54 PM PDT 24
Finished Jul 09 07:01:00 PM PDT 24
Peak memory 208600 kb
Host smart-1a7ce724-1d14-4e80-9be0-3a1ec25bf2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780359129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3780359129
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1364554542
Short name T820
Test name
Test status
Simulation time 512906081 ps
CPU time 5.39 seconds
Started Jul 09 07:00:47 PM PDT 24
Finished Jul 09 07:00:55 PM PDT 24
Peak memory 207664 kb
Host smart-1e2fb151-8020-4694-a212-268d4e3518b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364554542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1364554542
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3843193462
Short name T845
Test name
Test status
Simulation time 95721391 ps
CPU time 3.73 seconds
Started Jul 09 07:00:50 PM PDT 24
Finished Jul 09 07:00:56 PM PDT 24
Peak memory 209524 kb
Host smart-0538436a-b8ee-4191-b4be-1b4c11e59a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843193462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3843193462
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1779801865
Short name T98
Test name
Test status
Simulation time 325329545 ps
CPU time 4.15 seconds
Started Jul 09 07:00:45 PM PDT 24
Finished Jul 09 07:00:51 PM PDT 24
Peak memory 208012 kb
Host smart-64c6cf06-7439-452d-96f6-4e4cecff89b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779801865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1779801865
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2354829399
Short name T791
Test name
Test status
Simulation time 74471454 ps
CPU time 3.16 seconds
Started Jul 09 07:00:47 PM PDT 24
Finished Jul 09 07:00:52 PM PDT 24
Peak memory 208548 kb
Host smart-1564c3e7-bfbe-47f4-8800-7ddc888c6aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354829399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2354829399
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.295242782
Short name T370
Test name
Test status
Simulation time 1373326747 ps
CPU time 31.11 seconds
Started Jul 09 07:00:43 PM PDT 24
Finished Jul 09 07:01:16 PM PDT 24
Peak memory 208596 kb
Host smart-b743645a-c2e9-4b97-a2a3-1437d1aefae9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295242782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.295242782
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2750154584
Short name T812
Test name
Test status
Simulation time 191495224 ps
CPU time 5.85 seconds
Started Jul 09 07:00:46 PM PDT 24
Finished Jul 09 07:00:54 PM PDT 24
Peak memory 208656 kb
Host smart-cb3b7996-3093-4106-adec-dcd3ee29556a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750154584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2750154584
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3267610037
Short name T413
Test name
Test status
Simulation time 241285959 ps
CPU time 3.28 seconds
Started Jul 09 07:00:46 PM PDT 24
Finished Jul 09 07:00:51 PM PDT 24
Peak memory 208864 kb
Host smart-7714ca31-ad70-4aec-8b48-616211f5e329
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267610037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3267610037
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.992511559
Short name T422
Test name
Test status
Simulation time 1041074321 ps
CPU time 2.78 seconds
Started Jul 09 07:00:56 PM PDT 24
Finished Jul 09 07:01:02 PM PDT 24
Peak memory 218220 kb
Host smart-75866663-49fc-4f2c-82f9-2ee1d25d0615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992511559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.992511559
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1180670421
Short name T414
Test name
Test status
Simulation time 151007674 ps
CPU time 1.81 seconds
Started Jul 09 07:00:45 PM PDT 24
Finished Jul 09 07:00:49 PM PDT 24
Peak memory 206828 kb
Host smart-1a853558-9ae8-4d33-8537-9b04d36fd9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180670421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1180670421
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3866896948
Short name T289
Test name
Test status
Simulation time 634054426 ps
CPU time 18.99 seconds
Started Jul 09 07:00:51 PM PDT 24
Finished Jul 09 07:01:12 PM PDT 24
Peak memory 222420 kb
Host smart-2a9ec268-4224-4aae-8169-f3fe5823d31b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866896948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3866896948
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2207140471
Short name T194
Test name
Test status
Simulation time 1441022849 ps
CPU time 14.38 seconds
Started Jul 09 07:00:48 PM PDT 24
Finished Jul 09 07:01:05 PM PDT 24
Peak memory 222456 kb
Host smart-a9ca7998-1c68-4cfa-b7df-f15fd4b01cca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207140471 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2207140471
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.268544533
Short name T383
Test name
Test status
Simulation time 221928070 ps
CPU time 8.09 seconds
Started Jul 09 07:00:47 PM PDT 24
Finished Jul 09 07:00:57 PM PDT 24
Peak memory 208208 kb
Host smart-4b9a55ca-918c-44a2-8952-d4497d01900e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268544533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.268544533
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3044093178
Short name T889
Test name
Test status
Simulation time 77380856 ps
CPU time 2.85 seconds
Started Jul 09 07:00:55 PM PDT 24
Finished Jul 09 07:01:01 PM PDT 24
Peak memory 210056 kb
Host smart-e74239f0-e22f-4ec0-867d-f778f02be162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044093178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3044093178
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1512856801
Short name T537
Test name
Test status
Simulation time 21855482 ps
CPU time 0.77 seconds
Started Jul 09 06:59:51 PM PDT 24
Finished Jul 09 06:59:53 PM PDT 24
Peak memory 206012 kb
Host smart-7de81b54-686e-4768-8753-2e1ac7ca2676
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512856801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1512856801
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3497125895
Short name T423
Test name
Test status
Simulation time 108635880 ps
CPU time 4.14 seconds
Started Jul 09 06:59:49 PM PDT 24
Finished Jul 09 06:59:55 PM PDT 24
Peak memory 214352 kb
Host smart-9f433240-aa9f-4878-83a6-641a5f380d1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3497125895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3497125895
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.153493868
Short name T77
Test name
Test status
Simulation time 646491036 ps
CPU time 13.22 seconds
Started Jul 09 06:59:51 PM PDT 24
Finished Jul 09 07:00:06 PM PDT 24
Peak memory 221300 kb
Host smart-778a42d9-8963-46ed-848a-a280cfe69f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153493868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.153493868
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3908471954
Short name T510
Test name
Test status
Simulation time 253280575 ps
CPU time 2.3 seconds
Started Jul 09 06:59:49 PM PDT 24
Finished Jul 09 06:59:53 PM PDT 24
Peak memory 209876 kb
Host smart-91f6079f-a49f-435d-92ce-15e02f3a7a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908471954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3908471954
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2468106233
Short name T241
Test name
Test status
Simulation time 219403322 ps
CPU time 4.92 seconds
Started Jul 09 06:59:48 PM PDT 24
Finished Jul 09 06:59:55 PM PDT 24
Peak memory 214464 kb
Host smart-030c6407-f688-4e77-a9c2-9af1905f77fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468106233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2468106233
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1739277938
Short name T299
Test name
Test status
Simulation time 71260989 ps
CPU time 3.53 seconds
Started Jul 09 06:59:49 PM PDT 24
Finished Jul 09 06:59:54 PM PDT 24
Peak memory 214300 kb
Host smart-5f7e2a6d-e814-4b0a-9d33-7d6ea2ea4616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739277938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1739277938
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3775108316
Short name T220
Test name
Test status
Simulation time 53683753 ps
CPU time 3.51 seconds
Started Jul 09 06:59:49 PM PDT 24
Finished Jul 09 06:59:54 PM PDT 24
Peak memory 210536 kb
Host smart-8f1bf28f-de3a-4900-8033-e5354a39ce8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775108316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3775108316
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.616379174
Short name T509
Test name
Test status
Simulation time 1497791713 ps
CPU time 9.69 seconds
Started Jul 09 06:59:50 PM PDT 24
Finished Jul 09 07:00:02 PM PDT 24
Peak memory 219140 kb
Host smart-a10cb369-9481-419d-accb-a7118bf1f17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616379174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.616379174
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1086905045
Short name T46
Test name
Test status
Simulation time 1316618181 ps
CPU time 6.38 seconds
Started Jul 09 06:59:51 PM PDT 24
Finished Jul 09 06:59:59 PM PDT 24
Peak memory 234356 kb
Host smart-14e35b1d-dd46-4ea8-896d-a281d3092341
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086905045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1086905045
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.581683903
Short name T490
Test name
Test status
Simulation time 262323903 ps
CPU time 4.42 seconds
Started Jul 09 06:59:49 PM PDT 24
Finished Jul 09 06:59:56 PM PDT 24
Peak memory 207988 kb
Host smart-42af02d8-bee8-49e6-a8bc-0d70689ab659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581683903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.581683903
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1348647848
Short name T755
Test name
Test status
Simulation time 316364361 ps
CPU time 4.25 seconds
Started Jul 09 06:59:47 PM PDT 24
Finished Jul 09 06:59:53 PM PDT 24
Peak memory 208628 kb
Host smart-4d5f9e6e-3f74-4ac7-acfe-c6dba3904a37
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348647848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1348647848
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.400635309
Short name T635
Test name
Test status
Simulation time 72598852 ps
CPU time 2.89 seconds
Started Jul 09 06:59:47 PM PDT 24
Finished Jul 09 06:59:52 PM PDT 24
Peak memory 206880 kb
Host smart-09472716-abd4-42c5-a076-80b619133eaa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400635309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.400635309
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3488255009
Short name T809
Test name
Test status
Simulation time 41683623 ps
CPU time 2.39 seconds
Started Jul 09 06:59:49 PM PDT 24
Finished Jul 09 06:59:54 PM PDT 24
Peak memory 207636 kb
Host smart-29747a5b-b829-4464-99c9-980df4fed329
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488255009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3488255009
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2939828498
Short name T613
Test name
Test status
Simulation time 288676787 ps
CPU time 3.17 seconds
Started Jul 09 06:59:50 PM PDT 24
Finished Jul 09 06:59:55 PM PDT 24
Peak memory 216076 kb
Host smart-9390b1da-a89b-4187-ac34-130729dddc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939828498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2939828498
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2998444082
Short name T520
Test name
Test status
Simulation time 40382863 ps
CPU time 2.62 seconds
Started Jul 09 06:59:47 PM PDT 24
Finished Jul 09 06:59:50 PM PDT 24
Peak memory 208832 kb
Host smart-a242cd25-e1c4-48e0-bfff-db23c434d3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998444082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2998444082
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2423003036
Short name T807
Test name
Test status
Simulation time 1693923229 ps
CPU time 25.95 seconds
Started Jul 09 06:59:48 PM PDT 24
Finished Jul 09 07:00:16 PM PDT 24
Peak memory 222644 kb
Host smart-b04398ff-eabc-4aa9-b7d1-be3373f31c09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423003036 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2423003036
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3894586596
Short name T715
Test name
Test status
Simulation time 928227429 ps
CPU time 6.19 seconds
Started Jul 09 06:59:50 PM PDT 24
Finished Jul 09 06:59:58 PM PDT 24
Peak memory 208516 kb
Host smart-35789191-3578-4325-8bf0-7cf4eec6189a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894586596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3894586596
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1240432665
Short name T170
Test name
Test status
Simulation time 236802787 ps
CPU time 2.74 seconds
Started Jul 09 06:59:48 PM PDT 24
Finished Jul 09 06:59:53 PM PDT 24
Peak memory 210452 kb
Host smart-681db39e-5300-4354-b77f-4bd728a9c449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240432665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1240432665
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.4122848525
Short name T506
Test name
Test status
Simulation time 65116559 ps
CPU time 0.78 seconds
Started Jul 09 07:00:53 PM PDT 24
Finished Jul 09 07:00:57 PM PDT 24
Peak memory 206020 kb
Host smart-166c082f-7455-48a9-a440-1b32ace4ba3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122848525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.4122848525
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3685484452
Short name T79
Test name
Test status
Simulation time 216704102 ps
CPU time 1.94 seconds
Started Jul 09 07:00:53 PM PDT 24
Finished Jul 09 07:00:57 PM PDT 24
Peak memory 209648 kb
Host smart-fe982a26-fa93-48ca-b0d3-5099c2f656f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685484452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3685484452
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.674585692
Short name T333
Test name
Test status
Simulation time 189740557 ps
CPU time 3.19 seconds
Started Jul 09 07:00:53 PM PDT 24
Finished Jul 09 07:00:58 PM PDT 24
Peak memory 214484 kb
Host smart-e6faf7e4-d7c0-476e-9edc-792c0289d742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674585692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.674585692
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2572906068
Short name T614
Test name
Test status
Simulation time 91519798 ps
CPU time 3.32 seconds
Started Jul 09 07:00:48 PM PDT 24
Finished Jul 09 07:00:54 PM PDT 24
Peak memory 214280 kb
Host smart-dc91ec26-df15-4c64-a143-7b4b499bf53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572906068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2572906068
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1105286557
Short name T489
Test name
Test status
Simulation time 502152410 ps
CPU time 3.61 seconds
Started Jul 09 07:00:49 PM PDT 24
Finished Jul 09 07:00:55 PM PDT 24
Peak memory 214312 kb
Host smart-5aeec986-b387-4dd7-941d-c0be3df272e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105286557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1105286557
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2287578254
Short name T794
Test name
Test status
Simulation time 728851272 ps
CPU time 6.24 seconds
Started Jul 09 07:00:48 PM PDT 24
Finished Jul 09 07:00:57 PM PDT 24
Peak memory 214328 kb
Host smart-a9d69d23-ec1b-4ce7-b2b1-642462b4c764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287578254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2287578254
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3464885374
Short name T814
Test name
Test status
Simulation time 52212368 ps
CPU time 2.75 seconds
Started Jul 09 07:00:52 PM PDT 24
Finished Jul 09 07:00:57 PM PDT 24
Peak memory 206944 kb
Host smart-4d488ea5-450f-4bd0-9e4b-a0da84a1f25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464885374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3464885374
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3507194072
Short name T389
Test name
Test status
Simulation time 338434407 ps
CPU time 2.83 seconds
Started Jul 09 07:00:48 PM PDT 24
Finished Jul 09 07:00:53 PM PDT 24
Peak memory 208116 kb
Host smart-8cfb95c9-3d26-40b0-8491-dfe61ab1beb1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507194072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3507194072
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.973563548
Short name T543
Test name
Test status
Simulation time 234053348 ps
CPU time 3.12 seconds
Started Jul 09 07:00:49 PM PDT 24
Finished Jul 09 07:00:55 PM PDT 24
Peak memory 206824 kb
Host smart-806e659d-246d-4f83-8ec8-705e4c728b98
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973563548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.973563548
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3565528080
Short name T552
Test name
Test status
Simulation time 41076185 ps
CPU time 2.38 seconds
Started Jul 09 07:00:50 PM PDT 24
Finished Jul 09 07:00:54 PM PDT 24
Peak memory 207008 kb
Host smart-46e95ad9-1718-4841-a1ce-b08f16bc3afe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565528080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3565528080
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.366167753
Short name T420
Test name
Test status
Simulation time 65947704 ps
CPU time 2.77 seconds
Started Jul 09 07:00:55 PM PDT 24
Finished Jul 09 07:01:01 PM PDT 24
Peak memory 214344 kb
Host smart-b3262edf-c0f6-4a17-aa8f-517e31928452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366167753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.366167753
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.395894663
Short name T789
Test name
Test status
Simulation time 224131549 ps
CPU time 2.76 seconds
Started Jul 09 07:00:53 PM PDT 24
Finished Jul 09 07:00:59 PM PDT 24
Peak memory 208220 kb
Host smart-08455fc5-2848-4c03-b932-939295ff9430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395894663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.395894663
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3373721017
Short name T831
Test name
Test status
Simulation time 286284759 ps
CPU time 11.34 seconds
Started Jul 09 07:00:54 PM PDT 24
Finished Jul 09 07:01:09 PM PDT 24
Peak memory 215152 kb
Host smart-04058a3d-d7d8-4134-8e4f-a9de14b1af0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373721017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3373721017
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3263725464
Short name T325
Test name
Test status
Simulation time 173986242 ps
CPU time 6.4 seconds
Started Jul 09 07:00:52 PM PDT 24
Finished Jul 09 07:01:01 PM PDT 24
Peak memory 218372 kb
Host smart-d59774f1-ff59-4a7a-932a-29e6f4e357c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263725464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3263725464
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2382329622
Short name T454
Test name
Test status
Simulation time 67616106 ps
CPU time 1.91 seconds
Started Jul 09 07:00:48 PM PDT 24
Finished Jul 09 07:00:51 PM PDT 24
Peak memory 209824 kb
Host smart-43df57bc-abc2-4865-8dc7-d1449cbaf87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382329622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2382329622
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1503196622
Short name T532
Test name
Test status
Simulation time 24482863 ps
CPU time 0.83 seconds
Started Jul 09 07:00:55 PM PDT 24
Finished Jul 09 07:00:59 PM PDT 24
Peak memory 206160 kb
Host smart-0cf882de-8086-4e59-8248-d31932b5525e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503196622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1503196622
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2280097127
Short name T404
Test name
Test status
Simulation time 215545665 ps
CPU time 3.97 seconds
Started Jul 09 07:00:50 PM PDT 24
Finished Jul 09 07:00:56 PM PDT 24
Peak memory 214312 kb
Host smart-c5dcc990-fde4-4fa6-9dbb-b81420dd5b82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2280097127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2280097127
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3837499885
Short name T877
Test name
Test status
Simulation time 119937535 ps
CPU time 2.18 seconds
Started Jul 09 07:00:52 PM PDT 24
Finished Jul 09 07:00:56 PM PDT 24
Peak memory 222844 kb
Host smart-a7ef1550-d35b-44e0-bab8-c329e980f329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837499885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3837499885
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1112658697
Short name T591
Test name
Test status
Simulation time 865122875 ps
CPU time 5.7 seconds
Started Jul 09 07:00:49 PM PDT 24
Finished Jul 09 07:00:57 PM PDT 24
Peak memory 214336 kb
Host smart-089c31c9-6492-4acf-a475-1d34652c9099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112658697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1112658697
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1437241873
Short name T654
Test name
Test status
Simulation time 109723227 ps
CPU time 3.43 seconds
Started Jul 09 07:00:48 PM PDT 24
Finished Jul 09 07:00:53 PM PDT 24
Peak memory 214236 kb
Host smart-fe6263cb-2bbb-4b22-bc58-f1aaa97605e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437241873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1437241873
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.647607037
Short name T915
Test name
Test status
Simulation time 333873707 ps
CPU time 2.68 seconds
Started Jul 09 07:00:54 PM PDT 24
Finished Jul 09 07:00:59 PM PDT 24
Peak memory 213368 kb
Host smart-893c6237-39e9-4d1d-9e0a-824df6d00a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647607037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.647607037
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3299305985
Short name T119
Test name
Test status
Simulation time 3698520084 ps
CPU time 25.61 seconds
Started Jul 09 07:00:47 PM PDT 24
Finished Jul 09 07:01:14 PM PDT 24
Peak memory 209572 kb
Host smart-51dd6160-8d0f-4fa1-b170-c00fa3d026ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299305985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3299305985
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2381250790
Short name T373
Test name
Test status
Simulation time 212335190 ps
CPU time 5.87 seconds
Started Jul 09 07:00:51 PM PDT 24
Finished Jul 09 07:00:59 PM PDT 24
Peak memory 209000 kb
Host smart-b92b3067-c75a-4e22-94ba-0bdd25ae2606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381250790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2381250790
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3068642666
Short name T900
Test name
Test status
Simulation time 125174878 ps
CPU time 3.56 seconds
Started Jul 09 07:00:50 PM PDT 24
Finished Jul 09 07:00:56 PM PDT 24
Peak memory 206996 kb
Host smart-faa19d48-b775-4a21-9fee-db5e9a070b7a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068642666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3068642666
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3739082465
Short name T866
Test name
Test status
Simulation time 346514517 ps
CPU time 10.13 seconds
Started Jul 09 07:00:52 PM PDT 24
Finished Jul 09 07:01:04 PM PDT 24
Peak memory 208612 kb
Host smart-78ca998b-afa9-49a7-bb34-13afac8868bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739082465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3739082465
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2266354562
Short name T497
Test name
Test status
Simulation time 1402084022 ps
CPU time 9.79 seconds
Started Jul 09 07:00:49 PM PDT 24
Finished Jul 09 07:01:01 PM PDT 24
Peak memory 208912 kb
Host smart-f3b597a0-e97e-4f75-a18b-fcc77ab2a583
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266354562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2266354562
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3731978372
Short name T598
Test name
Test status
Simulation time 5849297406 ps
CPU time 15.63 seconds
Started Jul 09 07:00:56 PM PDT 24
Finished Jul 09 07:01:15 PM PDT 24
Peak memory 218612 kb
Host smart-68a3921d-861c-47cf-9a7f-822cb71e21ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731978372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3731978372
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.257427601
Short name T472
Test name
Test status
Simulation time 906614950 ps
CPU time 3.21 seconds
Started Jul 09 07:00:54 PM PDT 24
Finished Jul 09 07:01:00 PM PDT 24
Peak memory 207036 kb
Host smart-06024d4f-b4b1-47cc-8ecc-35c91417a5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257427601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.257427601
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.4167636707
Short name T328
Test name
Test status
Simulation time 250816970 ps
CPU time 8.85 seconds
Started Jul 09 07:00:58 PM PDT 24
Finished Jul 09 07:01:10 PM PDT 24
Peak memory 215732 kb
Host smart-0093a94e-b6c9-4f39-af7d-e3305519b246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167636707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.4167636707
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2241215388
Short name T351
Test name
Test status
Simulation time 519571853 ps
CPU time 24.81 seconds
Started Jul 09 07:00:55 PM PDT 24
Finished Jul 09 07:01:24 PM PDT 24
Peak memory 222712 kb
Host smart-73f1128d-22eb-4290-9834-49e9f9a28338
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241215388 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2241215388
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.21814152
Short name T554
Test name
Test status
Simulation time 178271324 ps
CPU time 6.76 seconds
Started Jul 09 07:00:52 PM PDT 24
Finished Jul 09 07:01:01 PM PDT 24
Peak memory 218384 kb
Host smart-c61cf710-4caa-47a6-b522-0fe034d3e05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21814152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.21814152
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2259601448
Short name T705
Test name
Test status
Simulation time 636908856 ps
CPU time 1.62 seconds
Started Jul 09 07:00:58 PM PDT 24
Finished Jul 09 07:01:02 PM PDT 24
Peak memory 210404 kb
Host smart-4f7a5429-b716-4765-a4c2-ee0f38493379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259601448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2259601448
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.666292956
Short name T666
Test name
Test status
Simulation time 44007952 ps
CPU time 0.76 seconds
Started Jul 09 07:00:56 PM PDT 24
Finished Jul 09 07:01:00 PM PDT 24
Peak memory 205996 kb
Host smart-83c1b634-9647-4ab4-84de-75e326ccc815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666292956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.666292956
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2594294654
Short name T424
Test name
Test status
Simulation time 152563055 ps
CPU time 3.13 seconds
Started Jul 09 07:00:58 PM PDT 24
Finished Jul 09 07:01:04 PM PDT 24
Peak memory 214440 kb
Host smart-b3dc3fd3-bdee-4e12-b4be-bb1ca9cdaad1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2594294654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2594294654
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1218893053
Short name T273
Test name
Test status
Simulation time 435157758 ps
CPU time 3.55 seconds
Started Jul 09 07:00:58 PM PDT 24
Finished Jul 09 07:01:05 PM PDT 24
Peak memory 209448 kb
Host smart-394c2158-2a92-42bf-858c-263cf527a85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218893053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1218893053
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1818465854
Short name T238
Test name
Test status
Simulation time 330534306 ps
CPU time 4.37 seconds
Started Jul 09 07:00:57 PM PDT 24
Finished Jul 09 07:01:05 PM PDT 24
Peak memory 214340 kb
Host smart-b0108619-015e-4267-8cc1-085c9cdbe9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818465854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1818465854
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3796571630
Short name T312
Test name
Test status
Simulation time 63838171 ps
CPU time 2.92 seconds
Started Jul 09 07:00:56 PM PDT 24
Finished Jul 09 07:01:02 PM PDT 24
Peak memory 214264 kb
Host smart-cd9e58a4-aad9-4055-b3fe-3a09093a38c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796571630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3796571630
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.647406415
Short name T73
Test name
Test status
Simulation time 219350695 ps
CPU time 3.13 seconds
Started Jul 09 07:00:56 PM PDT 24
Finished Jul 09 07:01:03 PM PDT 24
Peak memory 209020 kb
Host smart-cb5c5d02-dc59-46b2-8a1e-01412ab71916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647406415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.647406415
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3166544268
Short name T858
Test name
Test status
Simulation time 326203349 ps
CPU time 4.02 seconds
Started Jul 09 07:00:57 PM PDT 24
Finished Jul 09 07:01:05 PM PDT 24
Peak memory 207392 kb
Host smart-d77414c3-c59f-4bce-bb00-0dfa8f7f0028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166544268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3166544268
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.231384157
Short name T331
Test name
Test status
Simulation time 410040149 ps
CPU time 3.88 seconds
Started Jul 09 07:00:56 PM PDT 24
Finished Jul 09 07:01:03 PM PDT 24
Peak memory 206896 kb
Host smart-0f5ec200-1c14-48bc-a334-8629565677dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231384157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.231384157
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.926413943
Short name T483
Test name
Test status
Simulation time 1475915941 ps
CPU time 10.58 seconds
Started Jul 09 07:00:58 PM PDT 24
Finished Jul 09 07:01:12 PM PDT 24
Peak memory 208540 kb
Host smart-34141526-29a6-4c0f-b69a-ae78fd95f1f3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926413943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.926413943
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.695040337
Short name T658
Test name
Test status
Simulation time 618763787 ps
CPU time 7.27 seconds
Started Jul 09 07:00:57 PM PDT 24
Finished Jul 09 07:01:07 PM PDT 24
Peak memory 206972 kb
Host smart-50c9d6f1-d933-4ab9-8e42-c77792a03069
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695040337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.695040337
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2383038821
Short name T617
Test name
Test status
Simulation time 224051392 ps
CPU time 5.94 seconds
Started Jul 09 07:00:55 PM PDT 24
Finished Jul 09 07:01:04 PM PDT 24
Peak memory 208624 kb
Host smart-40dbc888-9a3c-41fc-bd50-b47b3c780595
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383038821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2383038821
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3075938068
Short name T536
Test name
Test status
Simulation time 315157581 ps
CPU time 1.89 seconds
Started Jul 09 07:00:58 PM PDT 24
Finished Jul 09 07:01:03 PM PDT 24
Peak memory 209228 kb
Host smart-ed2b5938-ea15-4f1b-977b-e4110f77327d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075938068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3075938068
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.109995971
Short name T5
Test name
Test status
Simulation time 242698667 ps
CPU time 2.73 seconds
Started Jul 09 07:00:56 PM PDT 24
Finished Jul 09 07:01:03 PM PDT 24
Peak memory 206972 kb
Host smart-e91c492e-b1eb-4e2e-905d-ac68504f800a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109995971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.109995971
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.4164911666
Short name T622
Test name
Test status
Simulation time 25581804675 ps
CPU time 69.11 seconds
Started Jul 09 07:00:57 PM PDT 24
Finished Jul 09 07:02:10 PM PDT 24
Peak memory 209932 kb
Host smart-99278722-8de4-482d-88f7-7db82381e047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164911666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.4164911666
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.4190940028
Short name T197
Test name
Test status
Simulation time 114492028 ps
CPU time 2.37 seconds
Started Jul 09 07:00:57 PM PDT 24
Finished Jul 09 07:01:03 PM PDT 24
Peak memory 210176 kb
Host smart-df06b22c-56c4-4f1d-8e56-206d2fbac4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190940028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.4190940028
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2837253057
Short name T539
Test name
Test status
Simulation time 11625013 ps
CPU time 0.73 seconds
Started Jul 09 07:01:09 PM PDT 24
Finished Jul 09 07:01:15 PM PDT 24
Peak memory 205924 kb
Host smart-3c97ed1f-0968-4a4a-8aef-d2ed5dad6900
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837253057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2837253057
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3617172783
Short name T751
Test name
Test status
Simulation time 40687533 ps
CPU time 1.34 seconds
Started Jul 09 07:01:03 PM PDT 24
Finished Jul 09 07:01:08 PM PDT 24
Peak memory 208756 kb
Host smart-57e4c30a-b5d4-4452-9fb0-fe6b812282cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617172783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3617172783
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2281394019
Short name T242
Test name
Test status
Simulation time 81108978 ps
CPU time 2.71 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:14 PM PDT 24
Peak memory 208720 kb
Host smart-d6608165-a6f4-4dc8-86d7-5b29fef8cafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281394019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2281394019
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1856518319
Short name T802
Test name
Test status
Simulation time 633562463 ps
CPU time 2.6 seconds
Started Jul 09 07:01:02 PM PDT 24
Finished Jul 09 07:01:09 PM PDT 24
Peak memory 222440 kb
Host smart-bd38fde2-2c56-4877-8366-8267a06f7d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856518319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1856518319
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2772125926
Short name T740
Test name
Test status
Simulation time 91859766 ps
CPU time 3.25 seconds
Started Jul 09 07:01:04 PM PDT 24
Finished Jul 09 07:01:11 PM PDT 24
Peak memory 214336 kb
Host smart-50418adb-6fbf-4e7c-bde6-729cc7fd88a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772125926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2772125926
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1951765448
Short name T277
Test name
Test status
Simulation time 8619813029 ps
CPU time 58.7 seconds
Started Jul 09 07:01:03 PM PDT 24
Finished Jul 09 07:02:06 PM PDT 24
Peak memory 222372 kb
Host smart-0ca16456-3fda-434f-bf0f-c1b137608558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951765448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1951765448
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3480326556
Short name T763
Test name
Test status
Simulation time 214176071 ps
CPU time 5.38 seconds
Started Jul 09 07:00:56 PM PDT 24
Finished Jul 09 07:01:05 PM PDT 24
Peak memory 208360 kb
Host smart-4c905f59-00ea-4ab7-a0f9-d46b5f4e66b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480326556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3480326556
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.819661967
Short name T683
Test name
Test status
Simulation time 702616880 ps
CPU time 8.33 seconds
Started Jul 09 07:00:57 PM PDT 24
Finished Jul 09 07:01:09 PM PDT 24
Peak memory 208172 kb
Host smart-ce00bef0-9cf4-4370-af91-6f45691d1dce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819661967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.819661967
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2909640978
Short name T476
Test name
Test status
Simulation time 489303105 ps
CPU time 2.61 seconds
Started Jul 09 07:00:54 PM PDT 24
Finished Jul 09 07:01:00 PM PDT 24
Peak memory 206928 kb
Host smart-94448370-017c-43d8-974d-5f0a010f7f4e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909640978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2909640978
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1444965384
Short name T97
Test name
Test status
Simulation time 49402334 ps
CPU time 2.09 seconds
Started Jul 09 07:01:02 PM PDT 24
Finished Jul 09 07:01:08 PM PDT 24
Peak memory 208500 kb
Host smart-888a5a1a-c3a5-42fd-83f8-add5d1f6cef8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444965384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1444965384
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2542020232
Short name T305
Test name
Test status
Simulation time 20745743 ps
CPU time 1.79 seconds
Started Jul 09 07:01:02 PM PDT 24
Finished Jul 09 07:01:07 PM PDT 24
Peak memory 208248 kb
Host smart-019a2e83-7170-46b0-815a-b3d0fa930595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542020232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2542020232
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2635697485
Short name T854
Test name
Test status
Simulation time 112681333 ps
CPU time 2.72 seconds
Started Jul 09 07:00:56 PM PDT 24
Finished Jul 09 07:01:03 PM PDT 24
Peak memory 206804 kb
Host smart-d20a849b-b150-48ae-aca8-419275b13226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635697485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2635697485
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3309498308
Short name T480
Test name
Test status
Simulation time 233071234 ps
CPU time 5.94 seconds
Started Jul 09 07:01:09 PM PDT 24
Finished Jul 09 07:01:20 PM PDT 24
Peak memory 214348 kb
Host smart-84f7782a-1fc3-487d-8607-e9c9d0d9d4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309498308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3309498308
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3405771815
Short name T136
Test name
Test status
Simulation time 732198972 ps
CPU time 7.66 seconds
Started Jul 09 07:01:01 PM PDT 24
Finished Jul 09 07:01:12 PM PDT 24
Peak memory 211196 kb
Host smart-86d2269c-9c97-4bf2-8dba-e6c98b2567ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405771815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3405771815
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1038716521
Short name T676
Test name
Test status
Simulation time 13322159 ps
CPU time 0.86 seconds
Started Jul 09 07:01:02 PM PDT 24
Finished Jul 09 07:01:06 PM PDT 24
Peak memory 205996 kb
Host smart-f74c85e6-5286-4420-9ff4-0d6faa3b81cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038716521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1038716521
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2558350216
Short name T508
Test name
Test status
Simulation time 58203606 ps
CPU time 2.55 seconds
Started Jul 09 07:01:03 PM PDT 24
Finished Jul 09 07:01:10 PM PDT 24
Peak memory 209392 kb
Host smart-12e289d7-0640-4a7a-a712-b4febf99aff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558350216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2558350216
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2425760273
Short name T82
Test name
Test status
Simulation time 155888407 ps
CPU time 4.85 seconds
Started Jul 09 07:01:02 PM PDT 24
Finished Jul 09 07:01:11 PM PDT 24
Peak memory 218200 kb
Host smart-63c5b813-1ad9-4ad8-87de-0d4e5e5a1526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425760273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2425760273
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2521968628
Short name T281
Test name
Test status
Simulation time 102572110 ps
CPU time 3.23 seconds
Started Jul 09 07:01:00 PM PDT 24
Finished Jul 09 07:01:06 PM PDT 24
Peak memory 214644 kb
Host smart-c8922e3a-f85e-4113-aef3-6d3fe6b026e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521968628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2521968628
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3239052801
Short name T221
Test name
Test status
Simulation time 526570257 ps
CPU time 3.59 seconds
Started Jul 09 07:00:59 PM PDT 24
Finished Jul 09 07:01:06 PM PDT 24
Peak memory 217828 kb
Host smart-4d811d8c-a177-4bd2-b1fd-7cd63e311939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239052801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3239052801
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3796140561
Short name T727
Test name
Test status
Simulation time 452535999 ps
CPU time 4.17 seconds
Started Jul 09 07:01:00 PM PDT 24
Finished Jul 09 07:01:08 PM PDT 24
Peak memory 208112 kb
Host smart-ead0347e-4f4b-4ea7-bef9-b3fca01b2dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796140561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3796140561
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1650554488
Short name T795
Test name
Test status
Simulation time 47887707 ps
CPU time 2.81 seconds
Started Jul 09 07:01:04 PM PDT 24
Finished Jul 09 07:01:11 PM PDT 24
Peak memory 208220 kb
Host smart-7d89e479-5022-415c-b64b-71bf358fd73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650554488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1650554488
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2646736953
Short name T796
Test name
Test status
Simulation time 827975191 ps
CPU time 6.32 seconds
Started Jul 09 07:01:10 PM PDT 24
Finished Jul 09 07:01:21 PM PDT 24
Peak memory 208688 kb
Host smart-f25c5412-c8c0-4e21-aae6-4ed1753e8e8b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646736953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2646736953
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.934080230
Short name T43
Test name
Test status
Simulation time 38127171 ps
CPU time 2.48 seconds
Started Jul 09 07:01:03 PM PDT 24
Finished Jul 09 07:01:08 PM PDT 24
Peak memory 208632 kb
Host smart-0c699532-814f-47ff-8b45-6e3459c843a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934080230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.934080230
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.47613690
Short name T494
Test name
Test status
Simulation time 439473659 ps
CPU time 2.69 seconds
Started Jul 09 07:01:03 PM PDT 24
Finished Jul 09 07:01:10 PM PDT 24
Peak memory 206972 kb
Host smart-f999f5d3-5959-4992-84f3-5c800062a6d3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47613690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.47613690
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.125083554
Short name T264
Test name
Test status
Simulation time 5528359664 ps
CPU time 33.25 seconds
Started Jul 09 07:01:03 PM PDT 24
Finished Jul 09 07:01:40 PM PDT 24
Peak memory 210556 kb
Host smart-725df252-56e3-43c2-83f6-572d4e173d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125083554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.125083554
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1963980787
Short name T521
Test name
Test status
Simulation time 87684015 ps
CPU time 2.36 seconds
Started Jul 09 07:01:04 PM PDT 24
Finished Jul 09 07:01:10 PM PDT 24
Peak memory 206924 kb
Host smart-0907c960-318d-4821-ae7e-32295e6ffd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963980787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1963980787
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.331811205
Short name T721
Test name
Test status
Simulation time 1135155422 ps
CPU time 19.24 seconds
Started Jul 09 07:01:03 PM PDT 24
Finished Jul 09 07:01:26 PM PDT 24
Peak memory 221832 kb
Host smart-8915e1cf-7528-4397-865a-2d7080464e8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331811205 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.331811205
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.4007828793
Short name T703
Test name
Test status
Simulation time 147271287 ps
CPU time 3.36 seconds
Started Jul 09 07:00:59 PM PDT 24
Finished Jul 09 07:01:06 PM PDT 24
Peak memory 218512 kb
Host smart-13f429e5-6c78-4068-81f4-0cc42020bde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007828793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.4007828793
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2881984166
Short name T397
Test name
Test status
Simulation time 975165406 ps
CPU time 1.86 seconds
Started Jul 09 07:01:01 PM PDT 24
Finished Jul 09 07:01:06 PM PDT 24
Peak memory 209916 kb
Host smart-9c17bb0b-6db6-4a07-9bf6-a0a99bc94a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881984166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2881984166
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2018406983
Short name T904
Test name
Test status
Simulation time 79372585 ps
CPU time 1.12 seconds
Started Jul 09 07:01:00 PM PDT 24
Finished Jul 09 07:01:05 PM PDT 24
Peak memory 206124 kb
Host smart-0d567c35-622c-4b1c-b2f8-2b94a3f2c41a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018406983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2018406983
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1730422557
Short name T307
Test name
Test status
Simulation time 834002019 ps
CPU time 43.07 seconds
Started Jul 09 07:02:09 PM PDT 24
Finished Jul 09 07:02:58 PM PDT 24
Peak memory 215480 kb
Host smart-bdad1c64-46a0-404b-acb6-06322fd6b35f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730422557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1730422557
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2054743054
Short name T768
Test name
Test status
Simulation time 828782765 ps
CPU time 15.51 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:26 PM PDT 24
Peak memory 208848 kb
Host smart-f643c81b-f9c0-4fcf-9247-041bad485dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054743054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2054743054
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2619011623
Short name T911
Test name
Test status
Simulation time 240579719 ps
CPU time 5.32 seconds
Started Jul 09 07:01:03 PM PDT 24
Finished Jul 09 07:01:12 PM PDT 24
Peak memory 209772 kb
Host smart-1c7de430-6c28-4030-9bdb-120db4b2b4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619011623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2619011623
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3888100297
Short name T100
Test name
Test status
Simulation time 87616535 ps
CPU time 2.81 seconds
Started Jul 09 07:01:00 PM PDT 24
Finished Jul 09 07:01:06 PM PDT 24
Peak memory 214436 kb
Host smart-93ff5bb4-7443-4bf3-94b1-0d72b0ea78a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888100297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3888100297
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2069233348
Short name T58
Test name
Test status
Simulation time 991435278 ps
CPU time 2.63 seconds
Started Jul 09 07:01:11 PM PDT 24
Finished Jul 09 07:01:18 PM PDT 24
Peak memory 214620 kb
Host smart-8eb04174-c347-4213-b40f-3ba5eb6d0e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069233348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2069233348
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.848805297
Short name T574
Test name
Test status
Simulation time 410294088 ps
CPU time 4.42 seconds
Started Jul 09 07:01:02 PM PDT 24
Finished Jul 09 07:01:10 PM PDT 24
Peak memory 218488 kb
Host smart-fb205921-bde9-4f28-804c-c1fc2d6de304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848805297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.848805297
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1812412104
Short name T207
Test name
Test status
Simulation time 232847737 ps
CPU time 2.14 seconds
Started Jul 09 07:01:04 PM PDT 24
Finished Jul 09 07:01:10 PM PDT 24
Peak memory 207520 kb
Host smart-7b32fe92-034c-47cf-bf59-8b4f31d9fc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812412104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1812412104
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3491825681
Short name T704
Test name
Test status
Simulation time 45624628 ps
CPU time 2.6 seconds
Started Jul 09 07:01:03 PM PDT 24
Finished Jul 09 07:01:10 PM PDT 24
Peak memory 208540 kb
Host smart-4fdfc96b-21c6-4add-abd0-5e75cfb3ec9a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491825681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3491825681
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.218531378
Short name T585
Test name
Test status
Simulation time 154557328 ps
CPU time 5.79 seconds
Started Jul 09 07:01:03 PM PDT 24
Finished Jul 09 07:01:13 PM PDT 24
Peak memory 208760 kb
Host smart-2c7f07a9-58a4-4735-914e-a834fd3d4449
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218531378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.218531378
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.679606323
Short name T801
Test name
Test status
Simulation time 1216484679 ps
CPU time 15.37 seconds
Started Jul 09 07:01:01 PM PDT 24
Finished Jul 09 07:01:19 PM PDT 24
Peak memory 207956 kb
Host smart-b0a75475-8bb0-401f-95c0-928fea34db39
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679606323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.679606323
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2793512338
Short name T606
Test name
Test status
Simulation time 396668748 ps
CPU time 2.18 seconds
Started Jul 09 07:01:00 PM PDT 24
Finished Jul 09 07:01:05 PM PDT 24
Peak memory 207836 kb
Host smart-155078ce-e1aa-4101-a691-cfae8b635d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793512338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2793512338
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1063684340
Short name T677
Test name
Test status
Simulation time 60622221 ps
CPU time 2.74 seconds
Started Jul 09 07:01:03 PM PDT 24
Finished Jul 09 07:01:10 PM PDT 24
Peak memory 206916 kb
Host smart-abb91911-0d07-4a9e-8bf0-ce222344c41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063684340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1063684340
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2204252593
Short name T322
Test name
Test status
Simulation time 29569671 ps
CPU time 2.29 seconds
Started Jul 09 07:01:04 PM PDT 24
Finished Jul 09 07:01:11 PM PDT 24
Peak memory 217876 kb
Host smart-6eef0d4a-07a6-49fb-916f-bfcabde4e4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204252593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2204252593
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.4075263567
Short name T492
Test name
Test status
Simulation time 140734083 ps
CPU time 3.08 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:14 PM PDT 24
Peak memory 210768 kb
Host smart-e90ebaaf-22d3-4cdb-b18e-456f1a83b414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075263567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.4075263567
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.818993871
Short name T758
Test name
Test status
Simulation time 39781779 ps
CPU time 0.87 seconds
Started Jul 09 07:01:08 PM PDT 24
Finished Jul 09 07:01:13 PM PDT 24
Peak memory 205968 kb
Host smart-d9cd879f-7306-4ccf-b5d2-9a4523297d25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818993871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.818993871
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2633074952
Short name T842
Test name
Test status
Simulation time 28771864 ps
CPU time 2.51 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:14 PM PDT 24
Peak memory 214320 kb
Host smart-8b812468-e01a-4e0b-9c84-3c372031aa4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2633074952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2633074952
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.351493105
Short name T218
Test name
Test status
Simulation time 1326628704 ps
CPU time 27.41 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:39 PM PDT 24
Peak memory 209580 kb
Host smart-78b98bfe-09cb-48d3-b8e7-aa04e9e8c9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351493105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.351493105
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2167838162
Short name T52
Test name
Test status
Simulation time 548655563 ps
CPU time 4.17 seconds
Started Jul 09 07:01:06 PM PDT 24
Finished Jul 09 07:01:14 PM PDT 24
Peak memory 214692 kb
Host smart-3e8787bc-e063-42d4-9379-14131dfef74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167838162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2167838162
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.928212135
Short name T111
Test name
Test status
Simulation time 44756236 ps
CPU time 3.08 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:15 PM PDT 24
Peak memory 209496 kb
Host smart-e32dc147-eae6-49a3-bb17-460c63c1a97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928212135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.928212135
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1448533269
Short name T258
Test name
Test status
Simulation time 266961899 ps
CPU time 3.45 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:15 PM PDT 24
Peak memory 214420 kb
Host smart-0a74d25f-9d7f-4998-b2c7-e15268101f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448533269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1448533269
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1425147010
Short name T728
Test name
Test status
Simulation time 35895670 ps
CPU time 2.31 seconds
Started Jul 09 07:01:09 PM PDT 24
Finished Jul 09 07:01:15 PM PDT 24
Peak memory 206480 kb
Host smart-89c69580-e05f-4248-9248-3bf8bfcdee23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425147010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1425147010
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.256292106
Short name T513
Test name
Test status
Simulation time 513037037 ps
CPU time 7.65 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:18 PM PDT 24
Peak memory 209660 kb
Host smart-9b29e58e-9329-46f5-9294-acbddc17ba9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256292106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.256292106
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.785052574
Short name T706
Test name
Test status
Simulation time 61639335 ps
CPU time 2.36 seconds
Started Jul 09 07:01:06 PM PDT 24
Finished Jul 09 07:01:12 PM PDT 24
Peak memory 207076 kb
Host smart-21c8ca24-ab33-4011-894e-e9227771cc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785052574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.785052574
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.66575706
Short name T573
Test name
Test status
Simulation time 369100137 ps
CPU time 3.8 seconds
Started Jul 09 07:01:09 PM PDT 24
Finished Jul 09 07:01:17 PM PDT 24
Peak memory 208840 kb
Host smart-e4ebcb52-ed74-41e8-ac4b-19f830b426b1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66575706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.66575706
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1036235193
Short name T538
Test name
Test status
Simulation time 125698203 ps
CPU time 4.73 seconds
Started Jul 09 07:01:09 PM PDT 24
Finished Jul 09 07:01:18 PM PDT 24
Peak memory 206892 kb
Host smart-20600a68-b4a4-4dc8-9286-7429d071ccac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036235193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1036235193
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.865373079
Short name T487
Test name
Test status
Simulation time 3122866351 ps
CPU time 42.27 seconds
Started Jul 09 07:01:10 PM PDT 24
Finished Jul 09 07:01:57 PM PDT 24
Peak memory 207900 kb
Host smart-a2802c54-dbc2-4034-8327-f513ef24a4f5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865373079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.865373079
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.4179633345
Short name T908
Test name
Test status
Simulation time 191914335 ps
CPU time 2.8 seconds
Started Jul 09 07:01:12 PM PDT 24
Finished Jul 09 07:01:18 PM PDT 24
Peak memory 209536 kb
Host smart-738c12d2-b894-41e4-a053-aa886bfa3d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179633345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4179633345
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3481013561
Short name T649
Test name
Test status
Simulation time 60860431 ps
CPU time 2.71 seconds
Started Jul 09 07:01:10 PM PDT 24
Finished Jul 09 07:01:17 PM PDT 24
Peak memory 206832 kb
Host smart-0a93c7f1-d71a-43c6-ba6b-2dd895f6fed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481013561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3481013561
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1714861216
Short name T892
Test name
Test status
Simulation time 347801926 ps
CPU time 17.9 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:29 PM PDT 24
Peak memory 223328 kb
Host smart-3256e365-8a42-4257-9a81-e5df53356d21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714861216 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1714861216
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.933850141
Short name T579
Test name
Test status
Simulation time 7269008664 ps
CPU time 25.12 seconds
Started Jul 09 07:01:06 PM PDT 24
Finished Jul 09 07:01:36 PM PDT 24
Peak memory 209648 kb
Host smart-3a559f9b-1ab9-4e68-8d6e-7d35f5139420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933850141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.933850141
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3879078339
Short name T176
Test name
Test status
Simulation time 260574460 ps
CPU time 3.03 seconds
Started Jul 09 07:01:04 PM PDT 24
Finished Jul 09 07:01:12 PM PDT 24
Peak memory 210032 kb
Host smart-2add816a-5c44-402e-800e-5e14f97fbaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879078339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3879078339
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.4224185328
Short name T528
Test name
Test status
Simulation time 10826407 ps
CPU time 0.87 seconds
Started Jul 09 07:01:06 PM PDT 24
Finished Jul 09 07:01:12 PM PDT 24
Peak memory 205984 kb
Host smart-7c58569d-85a8-4c24-84e2-3f0945d2a6c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224185328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.4224185328
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3588767320
Short name T402
Test name
Test status
Simulation time 252328401 ps
CPU time 4.21 seconds
Started Jul 09 07:01:09 PM PDT 24
Finished Jul 09 07:01:17 PM PDT 24
Peak memory 214352 kb
Host smart-9ab5324e-bbcd-4b7c-85f6-2efe44162d27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3588767320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3588767320
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3364330528
Short name T772
Test name
Test status
Simulation time 224887487 ps
CPU time 3.82 seconds
Started Jul 09 07:01:11 PM PDT 24
Finished Jul 09 07:01:19 PM PDT 24
Peak memory 214736 kb
Host smart-63047511-bdf7-4556-beb1-6830020b98b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364330528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3364330528
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.590364271
Short name T839
Test name
Test status
Simulation time 52664797 ps
CPU time 2.64 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:14 PM PDT 24
Peak memory 207568 kb
Host smart-4e459960-29e7-40d3-b8e3-5baf60e115be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590364271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.590364271
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2226874313
Short name T103
Test name
Test status
Simulation time 100845626 ps
CPU time 2.99 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:14 PM PDT 24
Peak memory 222460 kb
Host smart-0c103c9a-ad2e-4112-9926-2c5d2293c97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226874313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2226874313
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.4124276470
Short name T897
Test name
Test status
Simulation time 461554968 ps
CPU time 5.38 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:16 PM PDT 24
Peak memory 214292 kb
Host smart-7d708920-4780-4fe3-8758-c181d1dafb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124276470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.4124276470
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1469213024
Short name T63
Test name
Test status
Simulation time 410156333 ps
CPU time 4.1 seconds
Started Jul 09 07:01:06 PM PDT 24
Finished Jul 09 07:01:14 PM PDT 24
Peak memory 220300 kb
Host smart-b53bf2b9-12d5-4cf2-b955-7e2cbf3f2d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469213024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1469213024
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1804728444
Short name T681
Test name
Test status
Simulation time 1758277901 ps
CPU time 54.42 seconds
Started Jul 09 07:01:10 PM PDT 24
Finished Jul 09 07:02:09 PM PDT 24
Peak memory 208116 kb
Host smart-d3d589c5-9be4-4916-b87b-aeef4cac9220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804728444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1804728444
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3883769926
Short name T143
Test name
Test status
Simulation time 387187126 ps
CPU time 3.24 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:15 PM PDT 24
Peak memory 206892 kb
Host smart-12d26980-4697-414d-b778-679f8f7d512a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883769926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3883769926
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2717733023
Short name T754
Test name
Test status
Simulation time 3423071763 ps
CPU time 24.63 seconds
Started Jul 09 07:01:09 PM PDT 24
Finished Jul 09 07:01:38 PM PDT 24
Peak memory 208880 kb
Host smart-b1835225-1492-4f04-9baa-3cf86208dc1f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717733023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2717733023
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3557350148
Short name T504
Test name
Test status
Simulation time 55347267 ps
CPU time 2.61 seconds
Started Jul 09 07:01:09 PM PDT 24
Finished Jul 09 07:01:15 PM PDT 24
Peak memory 208420 kb
Host smart-e568250c-3f0f-43ae-b62a-182c20fdc010
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557350148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3557350148
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.240606795
Short name T501
Test name
Test status
Simulation time 3506063355 ps
CPU time 14.93 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:26 PM PDT 24
Peak memory 208480 kb
Host smart-eaa7af9a-6212-4cf5-8e36-b30d7f8eb874
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240606795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.240606795
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3155809129
Short name T437
Test name
Test status
Simulation time 248524758 ps
CPU time 2.5 seconds
Started Jul 09 07:01:07 PM PDT 24
Finished Jul 09 07:01:13 PM PDT 24
Peak memory 206944 kb
Host smart-3a9a9d00-04f4-4ae6-8793-f45f5d830856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155809129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3155809129
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.4121445107
Short name T270
Test name
Test status
Simulation time 1117912095 ps
CPU time 15.11 seconds
Started Jul 09 07:01:09 PM PDT 24
Finished Jul 09 07:01:28 PM PDT 24
Peak memory 222588 kb
Host smart-7389724c-b5e6-457a-a830-6aa0073cb1dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121445107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.4121445107
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1519200320
Short name T771
Test name
Test status
Simulation time 303503116 ps
CPU time 5.93 seconds
Started Jul 09 07:01:05 PM PDT 24
Finished Jul 09 07:01:16 PM PDT 24
Peak memory 207456 kb
Host smart-43b45e80-150b-4800-81c8-ef50d4e3c5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519200320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1519200320
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1038821014
Short name T452
Test name
Test status
Simulation time 139941876 ps
CPU time 2.47 seconds
Started Jul 09 07:01:10 PM PDT 24
Finished Jul 09 07:01:17 PM PDT 24
Peak memory 209640 kb
Host smart-a2803d6b-14b1-428f-be90-4ef8b3215f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038821014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1038821014
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3112190375
Short name T466
Test name
Test status
Simulation time 25730619 ps
CPU time 0.88 seconds
Started Jul 09 07:01:12 PM PDT 24
Finished Jul 09 07:01:17 PM PDT 24
Peak memory 206020 kb
Host smart-b1824ce1-2a12-4dc2-b6a2-f5d7ef24344b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112190375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3112190375
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2561817352
Short name T416
Test name
Test status
Simulation time 79298912 ps
CPU time 4.16 seconds
Started Jul 09 07:01:12 PM PDT 24
Finished Jul 09 07:01:20 PM PDT 24
Peak memory 215424 kb
Host smart-c8a7fbff-f457-4336-b539-50bab9aaecae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2561817352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2561817352
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3836599309
Short name T783
Test name
Test status
Simulation time 500890543 ps
CPU time 5.95 seconds
Started Jul 09 07:01:14 PM PDT 24
Finished Jul 09 07:01:23 PM PDT 24
Peak memory 214348 kb
Host smart-3480c092-0cf5-4286-881d-35bd8cadb789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836599309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3836599309
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2920578631
Short name T240
Test name
Test status
Simulation time 195844037 ps
CPU time 5.3 seconds
Started Jul 09 07:01:15 PM PDT 24
Finished Jul 09 07:01:24 PM PDT 24
Peak memory 209328 kb
Host smart-e868ae31-6f65-4e39-a1a3-cca05951a1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920578631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2920578631
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3736235540
Short name T48
Test name
Test status
Simulation time 138952114 ps
CPU time 4.2 seconds
Started Jul 09 07:01:13 PM PDT 24
Finished Jul 09 07:01:21 PM PDT 24
Peak memory 214324 kb
Host smart-f553d9ec-1ec4-42fa-9386-7b390b60c74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736235540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3736235540
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2211959537
Short name T608
Test name
Test status
Simulation time 2121881208 ps
CPU time 52.37 seconds
Started Jul 09 07:01:12 PM PDT 24
Finished Jul 09 07:02:08 PM PDT 24
Peak memory 208716 kb
Host smart-190b8a8f-9bdf-4f3d-8b72-97f8b9b43575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211959537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2211959537
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3567385813
Short name T597
Test name
Test status
Simulation time 212375663 ps
CPU time 3.08 seconds
Started Jul 09 07:01:11 PM PDT 24
Finished Jul 09 07:01:18 PM PDT 24
Peak memory 208848 kb
Host smart-8685d884-2e13-48a9-b4a6-89009762be89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567385813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3567385813
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.70850544
Short name T697
Test name
Test status
Simulation time 88902986 ps
CPU time 2.66 seconds
Started Jul 09 07:01:16 PM PDT 24
Finished Jul 09 07:01:21 PM PDT 24
Peak memory 206912 kb
Host smart-781fd6ad-32e5-41ad-860f-ad2a09b56673
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70850544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.70850544
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1532615166
Short name T486
Test name
Test status
Simulation time 80472176 ps
CPU time 3.38 seconds
Started Jul 09 07:01:10 PM PDT 24
Finished Jul 09 07:01:18 PM PDT 24
Peak memory 208064 kb
Host smart-e63a6542-1683-4f53-831c-5e1aa9374dc6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532615166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1532615166
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.274522529
Short name T671
Test name
Test status
Simulation time 427565023 ps
CPU time 2.74 seconds
Started Jul 09 07:01:12 PM PDT 24
Finished Jul 09 07:01:19 PM PDT 24
Peak memory 208824 kb
Host smart-a53a98e2-d605-40c5-bc52-8ec6deb1f348
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274522529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.274522529
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.164319623
Short name T594
Test name
Test status
Simulation time 202634815 ps
CPU time 2.77 seconds
Started Jul 09 07:01:13 PM PDT 24
Finished Jul 09 07:01:19 PM PDT 24
Peak memory 207784 kb
Host smart-7359ed9b-63d6-4ec3-92ac-7b1b97058cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164319623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.164319623
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1228099947
Short name T569
Test name
Test status
Simulation time 164394870 ps
CPU time 5.55 seconds
Started Jul 09 07:01:14 PM PDT 24
Finished Jul 09 07:01:23 PM PDT 24
Peak memory 208700 kb
Host smart-8a865d5c-7bc1-45c6-a169-7357023d3c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228099947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1228099947
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.773553615
Short name T896
Test name
Test status
Simulation time 24724774520 ps
CPU time 427.64 seconds
Started Jul 09 07:01:13 PM PDT 24
Finished Jul 09 07:08:24 PM PDT 24
Peak memory 222576 kb
Host smart-cc3a0df7-3ceb-4408-9c5f-1e3512e78347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773553615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.773553615
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3675859492
Short name T283
Test name
Test status
Simulation time 821710877 ps
CPU time 5.17 seconds
Started Jul 09 07:01:11 PM PDT 24
Finished Jul 09 07:01:20 PM PDT 24
Peak memory 210560 kb
Host smart-e98ce00e-c1b0-469b-b8d0-55e01f318330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675859492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3675859492
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3683072578
Short name T531
Test name
Test status
Simulation time 26722635 ps
CPU time 0.89 seconds
Started Jul 09 07:01:17 PM PDT 24
Finished Jul 09 07:01:21 PM PDT 24
Peak memory 205960 kb
Host smart-c3a20e93-2dc3-4227-889e-26a5d60d3896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683072578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3683072578
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2204798927
Short name T161
Test name
Test status
Simulation time 85568004 ps
CPU time 3.39 seconds
Started Jul 09 07:01:13 PM PDT 24
Finished Jul 09 07:01:20 PM PDT 24
Peak memory 214304 kb
Host smart-099cc457-e81f-4deb-b798-1a5d41af7e6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2204798927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2204798927
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1027717836
Short name T641
Test name
Test status
Simulation time 4832704830 ps
CPU time 32.97 seconds
Started Jul 09 07:01:11 PM PDT 24
Finished Jul 09 07:01:48 PM PDT 24
Peak memory 214396 kb
Host smart-965f400d-7e79-47c4-a511-d21fa425c2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027717836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1027717836
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.4202632944
Short name T906
Test name
Test status
Simulation time 46998270 ps
CPU time 2.16 seconds
Started Jul 09 07:01:17 PM PDT 24
Finished Jul 09 07:01:23 PM PDT 24
Peak memory 214288 kb
Host smart-05f90c5f-b3bd-4bfc-9625-b6b8fa5e2fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202632944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.4202632944
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2712989224
Short name T35
Test name
Test status
Simulation time 56999343 ps
CPU time 2.01 seconds
Started Jul 09 07:01:17 PM PDT 24
Finished Jul 09 07:01:23 PM PDT 24
Peak memory 214308 kb
Host smart-498303d4-2e7a-4550-a6e2-ad2e732eaf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712989224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2712989224
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.639285163
Short name T343
Test name
Test status
Simulation time 127395371 ps
CPU time 5.33 seconds
Started Jul 09 07:01:13 PM PDT 24
Finished Jul 09 07:01:22 PM PDT 24
Peak memory 222568 kb
Host smart-0beb3fab-1ad6-40d0-8050-20f635e932f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639285163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.639285163
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.802928813
Short name T647
Test name
Test status
Simulation time 311738901 ps
CPU time 3.86 seconds
Started Jul 09 07:01:17 PM PDT 24
Finished Jul 09 07:01:24 PM PDT 24
Peak memory 208044 kb
Host smart-debf3546-9775-400e-95fa-0f8410f511bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802928813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.802928813
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1774801392
Short name T629
Test name
Test status
Simulation time 51792306 ps
CPU time 2.18 seconds
Started Jul 09 07:01:16 PM PDT 24
Finished Jul 09 07:01:21 PM PDT 24
Peak memory 207612 kb
Host smart-d902ef1b-a0d2-439d-9b3d-9ac0d29df201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774801392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1774801392
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1558434912
Short name T846
Test name
Test status
Simulation time 877692189 ps
CPU time 3.8 seconds
Started Jul 09 07:01:11 PM PDT 24
Finished Jul 09 07:01:19 PM PDT 24
Peak memory 207024 kb
Host smart-f4e0c88a-7988-41c9-aa05-a2772f0e6349
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558434912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1558434912
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1662166498
Short name T799
Test name
Test status
Simulation time 42113860 ps
CPU time 2.59 seconds
Started Jul 09 07:01:17 PM PDT 24
Finished Jul 09 07:01:23 PM PDT 24
Peak memory 208456 kb
Host smart-bd8f6081-8fac-4426-aec5-d934acd8e03e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662166498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1662166498
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.339471064
Short name T878
Test name
Test status
Simulation time 274392549 ps
CPU time 3.2 seconds
Started Jul 09 07:01:10 PM PDT 24
Finished Jul 09 07:01:18 PM PDT 24
Peak memory 209016 kb
Host smart-5e5fff98-1327-4356-b221-6896f8c0f5ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339471064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.339471064
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2469682951
Short name T586
Test name
Test status
Simulation time 122791853 ps
CPU time 3.59 seconds
Started Jul 09 07:01:17 PM PDT 24
Finished Jul 09 07:01:24 PM PDT 24
Peak memory 210448 kb
Host smart-d98e3784-8647-4b10-8b5a-fa423821b4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469682951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2469682951
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1274908359
Short name T208
Test name
Test status
Simulation time 101614028 ps
CPU time 3.76 seconds
Started Jul 09 07:01:14 PM PDT 24
Finished Jul 09 07:01:21 PM PDT 24
Peak memory 206712 kb
Host smart-fd9cbe8d-f5b0-4dc8-8721-3d3abd338c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274908359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1274908359
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.4198099054
Short name T716
Test name
Test status
Simulation time 1659194368 ps
CPU time 15.98 seconds
Started Jul 09 07:01:20 PM PDT 24
Finished Jul 09 07:01:39 PM PDT 24
Peak memory 222680 kb
Host smart-c7338a16-bed7-46a7-a5f7-13f5534ed32c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198099054 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.4198099054
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2709681865
Short name T512
Test name
Test status
Simulation time 273890399 ps
CPU time 6.74 seconds
Started Jul 09 07:01:19 PM PDT 24
Finished Jul 09 07:01:29 PM PDT 24
Peak memory 209976 kb
Host smart-e5307487-9322-49dd-94ce-78ab38159f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709681865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2709681865
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3937465955
Short name T541
Test name
Test status
Simulation time 29468076 ps
CPU time 1.72 seconds
Started Jul 09 07:01:24 PM PDT 24
Finished Jul 09 07:01:27 PM PDT 24
Peak memory 209680 kb
Host smart-884555a3-95cf-472c-af82-395a033a8810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937465955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3937465955
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2612572206
Short name T757
Test name
Test status
Simulation time 19010760 ps
CPU time 0.74 seconds
Started Jul 09 06:59:54 PM PDT 24
Finished Jul 09 06:59:56 PM PDT 24
Peak memory 205948 kb
Host smart-ea395dd5-d7f4-40da-94e5-7769ee5f53ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612572206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2612572206
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3090476436
Short name T76
Test name
Test status
Simulation time 67809152 ps
CPU time 1.53 seconds
Started Jul 09 06:59:54 PM PDT 24
Finished Jul 09 06:59:57 PM PDT 24
Peak memory 210432 kb
Host smart-3eaabf52-5a6f-4b71-b78e-acf73e76a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090476436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3090476436
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.188398880
Short name T282
Test name
Test status
Simulation time 1149894163 ps
CPU time 19.34 seconds
Started Jul 09 06:59:49 PM PDT 24
Finished Jul 09 07:00:10 PM PDT 24
Peak memory 214332 kb
Host smart-c95e869d-893f-42f4-a279-1a86594ce4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188398880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.188398880
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3294950675
Short name T22
Test name
Test status
Simulation time 328770480 ps
CPU time 4.63 seconds
Started Jul 09 06:59:55 PM PDT 24
Finished Jul 09 07:00:01 PM PDT 24
Peak memory 217556 kb
Host smart-e3f3b223-702e-453f-a232-37973a6c1b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294950675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3294950675
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1913924411
Short name T335
Test name
Test status
Simulation time 56732130 ps
CPU time 2.04 seconds
Started Jul 09 06:59:56 PM PDT 24
Finished Jul 09 06:59:59 PM PDT 24
Peak memory 214248 kb
Host smart-5ef16533-0778-4f56-91cf-4492ac4de8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913924411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1913924411
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2004956330
Short name T609
Test name
Test status
Simulation time 146420971 ps
CPU time 3.78 seconds
Started Jul 09 06:59:56 PM PDT 24
Finished Jul 09 07:00:01 PM PDT 24
Peak memory 222560 kb
Host smart-4aa9dce8-58ee-4d01-9eb2-e49415c5087f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004956330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2004956330
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1776795506
Short name T615
Test name
Test status
Simulation time 966083784 ps
CPU time 3.67 seconds
Started Jul 09 06:59:47 PM PDT 24
Finished Jul 09 06:59:52 PM PDT 24
Peak memory 208148 kb
Host smart-abe5f231-9971-41fc-9546-f4e2443a7468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776795506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1776795506
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3844898974
Short name T13
Test name
Test status
Simulation time 575323559 ps
CPU time 6.95 seconds
Started Jul 09 06:59:54 PM PDT 24
Finished Jul 09 07:00:03 PM PDT 24
Peak memory 237904 kb
Host smart-1a44daf5-b2e8-4808-8d1f-428a417ab28a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844898974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3844898974
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3135834930
Short name T720
Test name
Test status
Simulation time 39669032 ps
CPU time 2.5 seconds
Started Jul 09 06:59:52 PM PDT 24
Finished Jul 09 06:59:56 PM PDT 24
Peak memory 207440 kb
Host smart-45d5f325-4163-43f6-b62d-3356e0526b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135834930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3135834930
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2242898485
Short name T475
Test name
Test status
Simulation time 170073499 ps
CPU time 4.29 seconds
Started Jul 09 06:59:48 PM PDT 24
Finished Jul 09 06:59:54 PM PDT 24
Peak memory 208444 kb
Host smart-d00d4239-92e8-4d34-9bff-b8d0cdff4b1d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242898485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2242898485
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1395176003
Short name T319
Test name
Test status
Simulation time 138966660 ps
CPU time 2.51 seconds
Started Jul 09 06:59:51 PM PDT 24
Finished Jul 09 06:59:55 PM PDT 24
Peak memory 207684 kb
Host smart-73285226-3e38-4711-b010-810ac47d97fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395176003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1395176003
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.4236942164
Short name T566
Test name
Test status
Simulation time 81459612 ps
CPU time 2.83 seconds
Started Jul 09 06:59:50 PM PDT 24
Finished Jul 09 06:59:55 PM PDT 24
Peak memory 206896 kb
Host smart-9c189013-fb6d-469a-96b2-3ff9de450dea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236942164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.4236942164
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3434846827
Short name T642
Test name
Test status
Simulation time 1182217276 ps
CPU time 2.99 seconds
Started Jul 09 07:00:03 PM PDT 24
Finished Jul 09 07:00:08 PM PDT 24
Peak memory 214296 kb
Host smart-3d6e07c6-ebd7-4f87-868b-2a8e2d09765b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434846827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3434846827
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3646335319
Short name T790
Test name
Test status
Simulation time 90590070 ps
CPU time 1.94 seconds
Started Jul 09 06:59:52 PM PDT 24
Finished Jul 09 06:59:56 PM PDT 24
Peak memory 208752 kb
Host smart-cd6d51c4-3725-464f-9dcc-8433e70ad6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646335319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3646335319
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2992983814
Short name T827
Test name
Test status
Simulation time 166580281 ps
CPU time 8.29 seconds
Started Jul 09 06:59:56 PM PDT 24
Finished Jul 09 07:00:05 PM PDT 24
Peak memory 216444 kb
Host smart-2c08dd1d-f01c-47a9-b023-a684f6b1139d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992983814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2992983814
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.4072874475
Short name T514
Test name
Test status
Simulation time 4121441199 ps
CPU time 15.25 seconds
Started Jul 09 06:59:56 PM PDT 24
Finished Jul 09 07:00:13 PM PDT 24
Peak memory 219896 kb
Host smart-536cc229-f575-47da-b367-0efab12a4d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072874475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.4072874475
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2013581619
Short name T712
Test name
Test status
Simulation time 152978450 ps
CPU time 2.53 seconds
Started Jul 09 07:00:04 PM PDT 24
Finished Jul 09 07:00:08 PM PDT 24
Peak memory 209860 kb
Host smart-f701b499-2424-4903-8cd5-5aa3fe1f3002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013581619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2013581619
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1620080987
Short name T616
Test name
Test status
Simulation time 76075085 ps
CPU time 0.74 seconds
Started Jul 09 07:01:25 PM PDT 24
Finished Jul 09 07:01:27 PM PDT 24
Peak memory 205904 kb
Host smart-788eede1-3f0d-432a-b083-eab2e6410e46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620080987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1620080987
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.315026718
Short name T433
Test name
Test status
Simulation time 3004044888 ps
CPU time 35.67 seconds
Started Jul 09 07:01:17 PM PDT 24
Finished Jul 09 07:01:56 PM PDT 24
Peak memory 214408 kb
Host smart-d370e89a-42a8-4c84-9ff1-f70948325328
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=315026718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.315026718
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2589575973
Short name T362
Test name
Test status
Simulation time 1032616643 ps
CPU time 6.9 seconds
Started Jul 09 07:01:17 PM PDT 24
Finished Jul 09 07:01:27 PM PDT 24
Peak memory 214328 kb
Host smart-85e4b33f-7b2f-4c3c-a5d6-a9a34a419f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589575973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2589575973
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2854993435
Short name T105
Test name
Test status
Simulation time 335383865 ps
CPU time 5.49 seconds
Started Jul 09 07:01:25 PM PDT 24
Finished Jul 09 07:01:32 PM PDT 24
Peak memory 221992 kb
Host smart-dd57a43f-3aa3-4931-83a2-206252d095e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854993435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2854993435
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1021407151
Short name T297
Test name
Test status
Simulation time 89792213 ps
CPU time 1.97 seconds
Started Jul 09 07:01:20 PM PDT 24
Finished Jul 09 07:01:25 PM PDT 24
Peak memory 214264 kb
Host smart-b36e7d2c-002e-48c9-b37f-8ebd1c599494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021407151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1021407151
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.142340411
Short name T870
Test name
Test status
Simulation time 57879149 ps
CPU time 3.41 seconds
Started Jul 09 07:01:21 PM PDT 24
Finished Jul 09 07:01:27 PM PDT 24
Peak memory 210540 kb
Host smart-61e6ce80-f5f0-475e-939d-afb95ef253ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142340411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.142340411
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2778074944
Short name T300
Test name
Test status
Simulation time 288126941 ps
CPU time 7.76 seconds
Started Jul 09 07:01:16 PM PDT 24
Finished Jul 09 07:01:27 PM PDT 24
Peak memory 210104 kb
Host smart-458ee06b-f15d-44f3-a7a1-adf8be43ce56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778074944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2778074944
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3951548488
Short name T855
Test name
Test status
Simulation time 319539683 ps
CPU time 2.93 seconds
Started Jul 09 07:01:18 PM PDT 24
Finished Jul 09 07:01:24 PM PDT 24
Peak memory 206796 kb
Host smart-806a5859-f241-4e39-b5ba-a32eaa6144f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951548488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3951548488
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.833992426
Short name T557
Test name
Test status
Simulation time 394066727 ps
CPU time 2.46 seconds
Started Jul 09 07:01:18 PM PDT 24
Finished Jul 09 07:01:24 PM PDT 24
Peak memory 207316 kb
Host smart-5ed4897a-32cd-460c-b2d0-ec9ba25196e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833992426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.833992426
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3400428099
Short name T269
Test name
Test status
Simulation time 213990605 ps
CPU time 4.14 seconds
Started Jul 09 07:01:19 PM PDT 24
Finished Jul 09 07:01:27 PM PDT 24
Peak memory 206828 kb
Host smart-beaf48e9-6b88-42a2-927f-65301615f46a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400428099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3400428099
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.495733958
Short name T568
Test name
Test status
Simulation time 374659797 ps
CPU time 5.57 seconds
Started Jul 09 07:01:25 PM PDT 24
Finished Jul 09 07:01:32 PM PDT 24
Peak memory 207884 kb
Host smart-886ffb32-ece5-4f3f-b078-84d66b20d0b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495733958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.495733958
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.900865096
Short name T287
Test name
Test status
Simulation time 29079364 ps
CPU time 2.21 seconds
Started Jul 09 07:01:19 PM PDT 24
Finished Jul 09 07:01:25 PM PDT 24
Peak memory 215760 kb
Host smart-171e3e6d-5dd5-4ba5-bd15-389f6216630f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900865096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.900865096
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1811930026
Short name T714
Test name
Test status
Simulation time 33421721 ps
CPU time 2.24 seconds
Started Jul 09 07:01:18 PM PDT 24
Finished Jul 09 07:01:23 PM PDT 24
Peak memory 206708 kb
Host smart-29cb4f08-c84e-400a-a761-02785c4895d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811930026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1811930026
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.868070699
Short name T71
Test name
Test status
Simulation time 2269645084 ps
CPU time 15.07 seconds
Started Jul 09 07:01:24 PM PDT 24
Finished Jul 09 07:01:40 PM PDT 24
Peak memory 222432 kb
Host smart-36edd043-46db-46b6-9d44-483bff97a82b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868070699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.868070699
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3237723110
Short name T248
Test name
Test status
Simulation time 612981367 ps
CPU time 12.92 seconds
Started Jul 09 07:01:19 PM PDT 24
Finished Jul 09 07:01:35 PM PDT 24
Peak memory 209508 kb
Host smart-2835e553-9933-41d1-ae99-d05fd59c27e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237723110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3237723110
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2958569483
Short name T502
Test name
Test status
Simulation time 98964137 ps
CPU time 2.65 seconds
Started Jul 09 07:01:21 PM PDT 24
Finished Jul 09 07:01:26 PM PDT 24
Peak memory 210248 kb
Host smart-7881efdd-c866-4968-b0dd-0ab88006c317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958569483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2958569483
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1678301414
Short name T444
Test name
Test status
Simulation time 11771528 ps
CPU time 0.72 seconds
Started Jul 09 07:01:25 PM PDT 24
Finished Jul 09 07:01:27 PM PDT 24
Peak memory 205972 kb
Host smart-e17f1233-3e50-4bf3-9be8-562a503815e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678301414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1678301414
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2410114725
Short name T306
Test name
Test status
Simulation time 57261414 ps
CPU time 4.02 seconds
Started Jul 09 07:01:18 PM PDT 24
Finished Jul 09 07:01:26 PM PDT 24
Peak memory 215240 kb
Host smart-8e047cbb-0687-4b21-af1d-2960cb1132e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2410114725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2410114725
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1049909217
Short name T731
Test name
Test status
Simulation time 149242398 ps
CPU time 5.54 seconds
Started Jul 09 07:01:21 PM PDT 24
Finished Jul 09 07:01:30 PM PDT 24
Peak memory 223124 kb
Host smart-0c5dc1e0-e1b3-488c-8bef-7709ced0658c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049909217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1049909217
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3985187561
Short name T288
Test name
Test status
Simulation time 343959315 ps
CPU time 4.31 seconds
Started Jul 09 07:01:21 PM PDT 24
Finished Jul 09 07:01:28 PM PDT 24
Peak memory 207280 kb
Host smart-420aff9c-ba57-48c7-b364-514b425da24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985187561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3985187561
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1953297415
Short name T601
Test name
Test status
Simulation time 360986098 ps
CPU time 3.84 seconds
Started Jul 09 07:01:25 PM PDT 24
Finished Jul 09 07:01:30 PM PDT 24
Peak memory 214360 kb
Host smart-82a8505f-6971-431f-81e3-0c109bf8c46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953297415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1953297415
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.460768018
Short name T582
Test name
Test status
Simulation time 115840786 ps
CPU time 2.28 seconds
Started Jul 09 07:01:21 PM PDT 24
Finished Jul 09 07:01:26 PM PDT 24
Peak memory 210328 kb
Host smart-058df1ef-7ce0-4d16-8bbb-3ecde490061d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460768018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.460768018
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2405811148
Short name T675
Test name
Test status
Simulation time 3242119701 ps
CPU time 8.31 seconds
Started Jul 09 07:01:17 PM PDT 24
Finished Jul 09 07:01:29 PM PDT 24
Peak memory 218500 kb
Host smart-22972791-5d6e-4efd-a540-09f357fa0762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405811148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2405811148
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3592308262
Short name T338
Test name
Test status
Simulation time 265099724 ps
CPU time 3.25 seconds
Started Jul 09 07:01:19 PM PDT 24
Finished Jul 09 07:01:26 PM PDT 24
Peak memory 208928 kb
Host smart-ab35071c-6abc-446c-aaa3-5a2892141dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592308262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3592308262
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1844041970
Short name T687
Test name
Test status
Simulation time 927918724 ps
CPU time 6.48 seconds
Started Jul 09 07:01:25 PM PDT 24
Finished Jul 09 07:01:33 PM PDT 24
Peak memory 207816 kb
Host smart-47bfdd58-b8e3-429d-aca4-e0de9b07121b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844041970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1844041970
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3588812170
Short name T886
Test name
Test status
Simulation time 244968999 ps
CPU time 3.25 seconds
Started Jul 09 07:01:19 PM PDT 24
Finished Jul 09 07:01:25 PM PDT 24
Peak memory 207012 kb
Host smart-3e811085-7f04-49be-ae9f-500f2999f2f7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588812170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3588812170
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3171670603
Short name T852
Test name
Test status
Simulation time 29935266446 ps
CPU time 37.71 seconds
Started Jul 09 07:01:19 PM PDT 24
Finished Jul 09 07:02:00 PM PDT 24
Peak memory 209260 kb
Host smart-79b1e193-1ac7-4b31-98ce-f53df03ad11b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171670603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3171670603
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2643486921
Short name T581
Test name
Test status
Simulation time 4753863626 ps
CPU time 22.6 seconds
Started Jul 09 07:01:22 PM PDT 24
Finished Jul 09 07:01:47 PM PDT 24
Peak memory 214388 kb
Host smart-a18ea1eb-7d47-464d-9779-2a152af9f3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643486921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2643486921
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3959340636
Short name T443
Test name
Test status
Simulation time 90674832 ps
CPU time 1.82 seconds
Started Jul 09 07:01:20 PM PDT 24
Finished Jul 09 07:01:25 PM PDT 24
Peak memory 208592 kb
Host smart-2dd85346-b018-4107-9d4f-8b7b684086eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959340636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3959340636
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3517047878
Short name T89
Test name
Test status
Simulation time 648634341 ps
CPU time 15.22 seconds
Started Jul 09 07:01:24 PM PDT 24
Finished Jul 09 07:01:41 PM PDT 24
Peak memory 222320 kb
Host smart-ae592e9e-bf3b-405e-a3dd-c004896d8ffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517047878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3517047878
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1583844687
Short name T871
Test name
Test status
Simulation time 1577721705 ps
CPU time 36.45 seconds
Started Jul 09 07:01:21 PM PDT 24
Finished Jul 09 07:02:00 PM PDT 24
Peak memory 214284 kb
Host smart-94d3466b-0030-4826-9a2d-f4371a3f6293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583844687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1583844687
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3002329181
Short name T517
Test name
Test status
Simulation time 170745888 ps
CPU time 3.1 seconds
Started Jul 09 07:01:22 PM PDT 24
Finished Jul 09 07:01:28 PM PDT 24
Peak memory 210444 kb
Host smart-e6f962d8-c632-4aa0-88ef-b39ebc99c000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002329181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3002329181
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1366626130
Short name T474
Test name
Test status
Simulation time 29506081 ps
CPU time 0.76 seconds
Started Jul 09 07:01:32 PM PDT 24
Finished Jul 09 07:01:34 PM PDT 24
Peak memory 206016 kb
Host smart-db05d38a-9db2-446b-93f0-2ec2e1bae195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366626130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1366626130
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2183636678
Short name T429
Test name
Test status
Simulation time 60183155 ps
CPU time 3.16 seconds
Started Jul 09 07:01:29 PM PDT 24
Finished Jul 09 07:01:33 PM PDT 24
Peak memory 214320 kb
Host smart-d0ab6c31-8e22-4012-a99c-4004f976e183
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2183636678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2183636678
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1721375006
Short name T738
Test name
Test status
Simulation time 1757541106 ps
CPU time 51.46 seconds
Started Jul 09 07:01:27 PM PDT 24
Finished Jul 09 07:02:20 PM PDT 24
Peak memory 217832 kb
Host smart-a53d7dbc-b3e6-4a58-b980-ace4d632705e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721375006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1721375006
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3476750202
Short name T684
Test name
Test status
Simulation time 259934710 ps
CPU time 2.79 seconds
Started Jul 09 07:02:40 PM PDT 24
Finished Jul 09 07:02:44 PM PDT 24
Peak memory 208160 kb
Host smart-012f8e03-9547-4df5-8a62-9abf30d2369d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476750202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3476750202
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3033959246
Short name T882
Test name
Test status
Simulation time 178965373 ps
CPU time 5.52 seconds
Started Jul 09 07:01:33 PM PDT 24
Finished Jul 09 07:01:41 PM PDT 24
Peak memory 209440 kb
Host smart-cab2e676-e2e5-4676-a02f-7b8cfb6d1d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033959246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3033959246
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1717583083
Short name T274
Test name
Test status
Simulation time 2338192861 ps
CPU time 23.4 seconds
Started Jul 09 07:01:27 PM PDT 24
Finished Jul 09 07:01:51 PM PDT 24
Peak memory 222504 kb
Host smart-20856dff-fe45-452e-b0b3-9ec2e88555ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717583083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1717583083
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1161080889
Short name T32
Test name
Test status
Simulation time 69414477 ps
CPU time 3.26 seconds
Started Jul 09 07:01:29 PM PDT 24
Finished Jul 09 07:01:33 PM PDT 24
Peak memory 209584 kb
Host smart-c9231a20-4f7e-41f9-890e-cc467292b324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161080889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1161080889
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3774882998
Short name T638
Test name
Test status
Simulation time 153157697 ps
CPU time 3.69 seconds
Started Jul 09 07:01:30 PM PDT 24
Finished Jul 09 07:01:36 PM PDT 24
Peak memory 214344 kb
Host smart-2e01cf90-75fb-455b-a829-5dd1db1d302e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774882998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3774882998
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1600600149
Short name T824
Test name
Test status
Simulation time 28362622 ps
CPU time 1.93 seconds
Started Jul 09 07:01:25 PM PDT 24
Finished Jul 09 07:01:28 PM PDT 24
Peak memory 207412 kb
Host smart-4a8df5f6-9123-4ddc-9ba1-526ea7269cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600600149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1600600149
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.4118725494
Short name T495
Test name
Test status
Simulation time 2305071796 ps
CPU time 46.13 seconds
Started Jul 09 07:01:23 PM PDT 24
Finished Jul 09 07:02:11 PM PDT 24
Peak memory 208320 kb
Host smart-f3428d80-b7f4-4621-a0b2-be62edf333fd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118725494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.4118725494
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1896920642
Short name T371
Test name
Test status
Simulation time 60919549 ps
CPU time 3.11 seconds
Started Jul 09 07:01:21 PM PDT 24
Finished Jul 09 07:01:27 PM PDT 24
Peak memory 207020 kb
Host smart-22f1b47c-8c49-497d-be80-cb603aadf361
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896920642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1896920642
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1935319300
Short name T453
Test name
Test status
Simulation time 125864150 ps
CPU time 2.42 seconds
Started Jul 09 07:01:29 PM PDT 24
Finished Jul 09 07:01:33 PM PDT 24
Peak memory 206812 kb
Host smart-d8732cbe-5e65-488e-ab20-ea0747b91428
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935319300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1935319300
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1981014636
Short name T856
Test name
Test status
Simulation time 293989647 ps
CPU time 3.32 seconds
Started Jul 09 07:01:32 PM PDT 24
Finished Jul 09 07:01:38 PM PDT 24
Peak memory 218444 kb
Host smart-d69a5635-98a8-401d-9c40-ad6eb29da11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981014636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1981014636
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.4207613654
Short name T205
Test name
Test status
Simulation time 64485504 ps
CPU time 2.85 seconds
Started Jul 09 07:01:23 PM PDT 24
Finished Jul 09 07:01:28 PM PDT 24
Peak memory 208520 kb
Host smart-10684e2f-f128-4ae2-aad7-9f7694fac820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207613654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.4207613654
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.125071160
Short name T894
Test name
Test status
Simulation time 1537222109 ps
CPU time 8.81 seconds
Started Jul 09 07:01:44 PM PDT 24
Finished Jul 09 07:01:56 PM PDT 24
Peak memory 208652 kb
Host smart-c9edb9fa-dabd-49f9-bb9d-1f2f0e0ec17b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125071160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.125071160
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.493810432
Short name T847
Test name
Test status
Simulation time 1553467790 ps
CPU time 17.78 seconds
Started Jul 09 07:01:29 PM PDT 24
Finished Jul 09 07:01:48 PM PDT 24
Peak memory 222616 kb
Host smart-c9b13f8f-559f-43b6-a9ae-e4f51b1043f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493810432 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.493810432
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2054780166
Short name T610
Test name
Test status
Simulation time 742405476 ps
CPU time 14.24 seconds
Started Jul 09 07:01:30 PM PDT 24
Finished Jul 09 07:01:47 PM PDT 24
Peak memory 208316 kb
Host smart-0f710069-bb4a-4046-a4e5-1ec8b2c04808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054780166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2054780166
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2945864984
Short name T60
Test name
Test status
Simulation time 114078552 ps
CPU time 1.66 seconds
Started Jul 09 07:01:30 PM PDT 24
Finished Jul 09 07:01:33 PM PDT 24
Peak memory 210244 kb
Host smart-b4f54dc0-d62d-4344-94a3-96b84102d0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945864984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2945864984
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.797938196
Short name T448
Test name
Test status
Simulation time 39221614 ps
CPU time 0.85 seconds
Started Jul 09 07:01:30 PM PDT 24
Finished Jul 09 07:01:33 PM PDT 24
Peak memory 205968 kb
Host smart-02425d82-e653-4cbd-8fff-97a22a9b7bdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797938196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.797938196
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2043903961
Short name T128
Test name
Test status
Simulation time 656549594 ps
CPU time 35.64 seconds
Started Jul 09 07:01:28 PM PDT 24
Finished Jul 09 07:02:05 PM PDT 24
Peak memory 214428 kb
Host smart-18649046-7ef9-42a7-9366-8f2c3d40aff6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2043903961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2043903961
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3729036800
Short name T24
Test name
Test status
Simulation time 204619788 ps
CPU time 5.41 seconds
Started Jul 09 07:01:31 PM PDT 24
Finished Jul 09 07:01:39 PM PDT 24
Peak memory 209848 kb
Host smart-33175b32-c2bd-4307-bb45-e847439cc976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729036800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3729036800
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.842832672
Short name T857
Test name
Test status
Simulation time 716588955 ps
CPU time 9.66 seconds
Started Jul 09 07:01:28 PM PDT 24
Finished Jul 09 07:01:39 PM PDT 24
Peak memory 218340 kb
Host smart-e635ba23-4883-488a-a73e-405fbab41281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842832672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.842832672
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1853246338
Short name T314
Test name
Test status
Simulation time 169495152 ps
CPU time 3.31 seconds
Started Jul 09 07:01:33 PM PDT 24
Finished Jul 09 07:01:39 PM PDT 24
Peak memory 214320 kb
Host smart-3dce03f0-6e48-4319-9359-20c585dea1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853246338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1853246338
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.262315966
Short name T280
Test name
Test status
Simulation time 40688055 ps
CPU time 2.23 seconds
Started Jul 09 07:01:28 PM PDT 24
Finished Jul 09 07:01:31 PM PDT 24
Peak memory 214296 kb
Host smart-8a68c782-4a79-40c4-b465-92b3385f6525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262315966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.262315966
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3220356966
Short name T484
Test name
Test status
Simulation time 111155779 ps
CPU time 4.88 seconds
Started Jul 09 07:01:32 PM PDT 24
Finished Jul 09 07:01:39 PM PDT 24
Peak memory 210220 kb
Host smart-6930557c-dbd4-4891-b213-98cf62f25f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220356966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3220356966
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.767413472
Short name T374
Test name
Test status
Simulation time 91203059 ps
CPU time 4.5 seconds
Started Jul 09 07:01:27 PM PDT 24
Finished Jul 09 07:01:33 PM PDT 24
Peak memory 208400 kb
Host smart-aa23861e-08cc-405d-8c65-8a0b99f53b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767413472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.767413472
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3898854961
Short name T901
Test name
Test status
Simulation time 181377036 ps
CPU time 2.92 seconds
Started Jul 09 07:01:28 PM PDT 24
Finished Jul 09 07:01:32 PM PDT 24
Peak memory 208444 kb
Host smart-94c2eb56-8a52-4421-a4ab-c372e73b5719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898854961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3898854961
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1580788313
Short name T380
Test name
Test status
Simulation time 614840773 ps
CPU time 7.89 seconds
Started Jul 09 07:01:30 PM PDT 24
Finished Jul 09 07:01:40 PM PDT 24
Peak memory 208800 kb
Host smart-c686d98b-01fb-40de-8001-b0c67b198f39
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580788313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1580788313
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1828113430
Short name T525
Test name
Test status
Simulation time 527649669 ps
CPU time 4.65 seconds
Started Jul 09 07:01:32 PM PDT 24
Finished Jul 09 07:01:39 PM PDT 24
Peak memory 208044 kb
Host smart-dedc56c5-8bdd-4da6-9ad5-03df968a86c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828113430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1828113430
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1720113169
Short name T518
Test name
Test status
Simulation time 250412069 ps
CPU time 3.69 seconds
Started Jul 09 07:01:30 PM PDT 24
Finished Jul 09 07:01:35 PM PDT 24
Peak memory 206924 kb
Host smart-58f06b06-47b9-4af2-9c9e-513b7f0294ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720113169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1720113169
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.138051986
Short name T284
Test name
Test status
Simulation time 514924492 ps
CPU time 11.76 seconds
Started Jul 09 07:01:30 PM PDT 24
Finished Jul 09 07:01:43 PM PDT 24
Peak memory 220252 kb
Host smart-c95fb24b-63c4-4e47-b0ab-0be504aa6ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138051986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.138051986
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2384058950
Short name T447
Test name
Test status
Simulation time 91520589 ps
CPU time 3.35 seconds
Started Jul 09 07:01:31 PM PDT 24
Finished Jul 09 07:01:37 PM PDT 24
Peak memory 207264 kb
Host smart-1d0ee23c-d4a6-486a-a5bd-990ce6a2a4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384058950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2384058950
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.187412585
Short name T732
Test name
Test status
Simulation time 151598827 ps
CPU time 6.82 seconds
Started Jul 09 07:01:29 PM PDT 24
Finished Jul 09 07:01:37 PM PDT 24
Peak memory 210376 kb
Host smart-8fde59cc-5802-4639-ad7d-c9cab2b9ce21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187412585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.187412585
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1697793192
Short name T246
Test name
Test status
Simulation time 665647605 ps
CPU time 12.86 seconds
Started Jul 09 07:01:33 PM PDT 24
Finished Jul 09 07:01:48 PM PDT 24
Peak memory 208084 kb
Host smart-a79dc7f0-0391-4d9b-aa2d-dceb4ad37aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697793192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1697793192
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1353859035
Short name T788
Test name
Test status
Simulation time 162671402 ps
CPU time 2.41 seconds
Started Jul 09 07:01:30 PM PDT 24
Finished Jul 09 07:01:34 PM PDT 24
Peak memory 210148 kb
Host smart-06643445-fe4a-49a2-870f-5366c0acb1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353859035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1353859035
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1260203380
Short name T435
Test name
Test status
Simulation time 53339647 ps
CPU time 0.92 seconds
Started Jul 09 07:01:34 PM PDT 24
Finished Jul 09 07:01:37 PM PDT 24
Peak memory 205904 kb
Host smart-140b76f1-0325-49b2-9c5b-994808598644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260203380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1260203380
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2348745593
Short name T349
Test name
Test status
Simulation time 370831461 ps
CPU time 10.87 seconds
Started Jul 09 07:01:37 PM PDT 24
Finished Jul 09 07:01:51 PM PDT 24
Peak memory 214396 kb
Host smart-4647f392-eb16-4627-8eec-b5391e8b13b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2348745593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2348745593
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1170437352
Short name T28
Test name
Test status
Simulation time 205326625 ps
CPU time 2.44 seconds
Started Jul 09 07:01:37 PM PDT 24
Finished Jul 09 07:01:42 PM PDT 24
Peak memory 210400 kb
Host smart-8dae36e6-8e72-4260-9088-b5431aaabdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170437352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1170437352
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.10127804
Short name T83
Test name
Test status
Simulation time 28742730 ps
CPU time 1.8 seconds
Started Jul 09 07:01:36 PM PDT 24
Finished Jul 09 07:01:40 PM PDT 24
Peak memory 208980 kb
Host smart-f2917f02-19b1-42f8-90b4-fc13747e71f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10127804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.10127804
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.4127630238
Short name T836
Test name
Test status
Simulation time 637492772 ps
CPU time 5.34 seconds
Started Jul 09 07:01:35 PM PDT 24
Finished Jul 09 07:01:43 PM PDT 24
Peak memory 209716 kb
Host smart-9f534d32-00c7-4225-a126-cd50d65c5c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127630238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.4127630238
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.673753700
Short name T555
Test name
Test status
Simulation time 99098882 ps
CPU time 2.36 seconds
Started Jul 09 07:01:33 PM PDT 24
Finished Jul 09 07:01:37 PM PDT 24
Peak memory 222400 kb
Host smart-691cf503-8a80-4197-af06-eae2fe1439df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673753700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.673753700
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.4138970163
Short name T777
Test name
Test status
Simulation time 120883163 ps
CPU time 4.58 seconds
Started Jul 09 07:01:32 PM PDT 24
Finished Jul 09 07:01:39 PM PDT 24
Peak memory 209888 kb
Host smart-0bf0382e-f4b5-43e1-bb6f-9473f00974e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138970163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.4138970163
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3289345419
Short name T611
Test name
Test status
Simulation time 696113138 ps
CPU time 3.74 seconds
Started Jul 09 07:01:35 PM PDT 24
Finished Jul 09 07:01:40 PM PDT 24
Peak memory 208772 kb
Host smart-8fc21b28-ffbb-4590-a65f-06dde406202f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289345419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3289345419
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2765037653
Short name T534
Test name
Test status
Simulation time 255958083 ps
CPU time 2.88 seconds
Started Jul 09 07:01:34 PM PDT 24
Finished Jul 09 07:01:39 PM PDT 24
Peak memory 208644 kb
Host smart-51d59c5a-27d1-478f-a25f-d92dbe837b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765037653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2765037653
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3074943534
Short name T759
Test name
Test status
Simulation time 52612234 ps
CPU time 2.97 seconds
Started Jul 09 07:01:36 PM PDT 24
Finished Jul 09 07:01:41 PM PDT 24
Peak memory 208468 kb
Host smart-6cb15ffd-cba1-4bc4-a38e-0a0a0b0922ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074943534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3074943534
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.987509592
Short name T276
Test name
Test status
Simulation time 115150447 ps
CPU time 3.88 seconds
Started Jul 09 07:01:35 PM PDT 24
Finished Jul 09 07:01:41 PM PDT 24
Peak memory 208596 kb
Host smart-9eaa2eb6-c95e-45a9-b5ac-c4a6ce513ae4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987509592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.987509592
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.249351523
Short name T440
Test name
Test status
Simulation time 164632993 ps
CPU time 6.59 seconds
Started Jul 09 07:01:34 PM PDT 24
Finished Jul 09 07:01:43 PM PDT 24
Peak memory 207032 kb
Host smart-9c842450-ca7e-4459-947a-b29095a4fdd8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249351523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.249351523
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.4186502993
Short name T478
Test name
Test status
Simulation time 120792850 ps
CPU time 1.36 seconds
Started Jul 09 07:01:36 PM PDT 24
Finished Jul 09 07:01:39 PM PDT 24
Peak memory 207396 kb
Host smart-d8f51080-4f55-44e9-b6d8-1e4d42e404d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186502993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4186502993
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.310801997
Short name T821
Test name
Test status
Simulation time 190281623 ps
CPU time 3.18 seconds
Started Jul 09 07:01:30 PM PDT 24
Finished Jul 09 07:01:36 PM PDT 24
Peak memory 206852 kb
Host smart-2749ebf4-0731-4fc2-ae07-47dba3254fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310801997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.310801997
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3676737589
Short name T191
Test name
Test status
Simulation time 290585259 ps
CPU time 8.6 seconds
Started Jul 09 07:01:32 PM PDT 24
Finished Jul 09 07:01:43 PM PDT 24
Peak memory 222492 kb
Host smart-8cbf6d5c-1791-482b-a6f0-38414b696100
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676737589 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3676737589
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1088862220
Short name T376
Test name
Test status
Simulation time 273876847 ps
CPU time 6.13 seconds
Started Jul 09 07:01:32 PM PDT 24
Finished Jul 09 07:01:41 PM PDT 24
Peak memory 208720 kb
Host smart-c47f699a-db72-4a08-93e2-9ab518062180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088862220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1088862220
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.570727718
Short name T145
Test name
Test status
Simulation time 147805107 ps
CPU time 3.04 seconds
Started Jul 09 07:01:34 PM PDT 24
Finished Jul 09 07:01:39 PM PDT 24
Peak memory 210880 kb
Host smart-888315b9-954d-4efb-9bf9-87e2ebfd6a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570727718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.570727718
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.975776513
Short name T733
Test name
Test status
Simulation time 35189589 ps
CPU time 0.82 seconds
Started Jul 09 07:01:40 PM PDT 24
Finished Jul 09 07:01:43 PM PDT 24
Peak memory 206020 kb
Host smart-261c7719-6dfd-4263-ae4b-8e07740c28ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975776513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.975776513
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.98819914
Short name T271
Test name
Test status
Simulation time 62933932 ps
CPU time 2.66 seconds
Started Jul 09 07:01:37 PM PDT 24
Finished Jul 09 07:01:42 PM PDT 24
Peak memory 214456 kb
Host smart-902e1b93-5039-4199-a6d3-9f3fc5b301dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98819914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.98819914
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1157011867
Short name T25
Test name
Test status
Simulation time 472089054 ps
CPU time 3.93 seconds
Started Jul 09 07:01:32 PM PDT 24
Finished Jul 09 07:01:39 PM PDT 24
Peak memory 209564 kb
Host smart-077c43ff-ef46-45fe-9b99-176ebfbd880d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157011867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1157011867
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.611521836
Short name T589
Test name
Test status
Simulation time 138491711 ps
CPU time 2.1 seconds
Started Jul 09 07:01:37 PM PDT 24
Finished Jul 09 07:01:41 PM PDT 24
Peak memory 208828 kb
Host smart-ecbadf1f-7936-415a-9a98-197c35236c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611521836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.611521836
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2688598713
Short name T652
Test name
Test status
Simulation time 275328631 ps
CPU time 5.43 seconds
Started Jul 09 07:01:36 PM PDT 24
Finished Jul 09 07:01:44 PM PDT 24
Peak memory 214500 kb
Host smart-d1236d9e-69f5-465c-9ae4-cbf200a0fadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688598713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2688598713
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2668580419
Short name T255
Test name
Test status
Simulation time 153630705 ps
CPU time 1.83 seconds
Started Jul 09 07:01:39 PM PDT 24
Finished Jul 09 07:01:43 PM PDT 24
Peak memory 214280 kb
Host smart-fba23fff-4859-42bc-9b09-484fb0a0a130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668580419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2668580419
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.109033235
Short name T237
Test name
Test status
Simulation time 40288912 ps
CPU time 2.85 seconds
Started Jul 09 07:01:32 PM PDT 24
Finished Jul 09 07:01:37 PM PDT 24
Peak memory 216616 kb
Host smart-fecda291-197d-4c24-9041-6b05ba9e7c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109033235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.109033235
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.336659604
Short name T91
Test name
Test status
Simulation time 223469888 ps
CPU time 3.83 seconds
Started Jul 09 07:01:34 PM PDT 24
Finished Jul 09 07:01:40 PM PDT 24
Peak memory 207384 kb
Host smart-e547e15c-3663-4070-8e3e-31b1c1689df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336659604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.336659604
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1678511454
Short name T493
Test name
Test status
Simulation time 76689272 ps
CPU time 2.13 seconds
Started Jul 09 07:01:32 PM PDT 24
Finished Jul 09 07:01:37 PM PDT 24
Peak memory 206836 kb
Host smart-e5eebf86-b8aa-42ba-9a65-fbbf0581d03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678511454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1678511454
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.4115309458
Short name T914
Test name
Test status
Simulation time 655606446 ps
CPU time 2.75 seconds
Started Jul 09 07:01:32 PM PDT 24
Finished Jul 09 07:01:37 PM PDT 24
Peak memory 207020 kb
Host smart-3bf9c2c8-f51f-47a0-9144-5bae4df4eb37
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115309458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.4115309458
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1465180387
Short name T479
Test name
Test status
Simulation time 5053537861 ps
CPU time 12.37 seconds
Started Jul 09 07:01:32 PM PDT 24
Finished Jul 09 07:01:46 PM PDT 24
Peak memory 208204 kb
Host smart-b93b8c43-66b5-4c2b-a40f-cca2154c1201
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465180387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1465180387
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1353971455
Short name T743
Test name
Test status
Simulation time 122536833 ps
CPU time 3.26 seconds
Started Jul 09 07:01:35 PM PDT 24
Finished Jul 09 07:01:41 PM PDT 24
Peak memory 207004 kb
Host smart-cbce6438-9ac3-453c-bbb7-a2553b8c8d82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353971455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1353971455
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1422002004
Short name T17
Test name
Test status
Simulation time 527877901 ps
CPU time 4.47 seconds
Started Jul 09 07:01:35 PM PDT 24
Finished Jul 09 07:01:41 PM PDT 24
Peak memory 209928 kb
Host smart-d66d5b2a-f815-4855-b5cd-358c201b3466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422002004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1422002004
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2413203179
Short name T891
Test name
Test status
Simulation time 38359703 ps
CPU time 2.08 seconds
Started Jul 09 07:01:38 PM PDT 24
Finished Jul 09 07:01:42 PM PDT 24
Peak memory 206936 kb
Host smart-0d0dc30f-f477-452f-8b13-0bebdc8a7c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413203179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2413203179
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1311457854
Short name T14
Test name
Test status
Simulation time 228519424 ps
CPU time 3.96 seconds
Started Jul 09 07:01:33 PM PDT 24
Finished Jul 09 07:01:39 PM PDT 24
Peak memory 218524 kb
Host smart-bdc0ac9b-80c4-4064-a5b6-55e8e3f96f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311457854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1311457854
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2299130536
Short name T729
Test name
Test status
Simulation time 1950364398 ps
CPU time 5.75 seconds
Started Jul 09 07:01:37 PM PDT 24
Finished Jul 09 07:01:45 PM PDT 24
Peak memory 210576 kb
Host smart-52b2702d-49b4-4066-9ecf-93fc520bdcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299130536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2299130536
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1220847847
Short name T505
Test name
Test status
Simulation time 41213002 ps
CPU time 0.93 seconds
Started Jul 09 07:01:42 PM PDT 24
Finished Jul 09 07:01:46 PM PDT 24
Peak memory 205992 kb
Host smart-12b52518-2249-471d-853a-5752f6d8dc77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220847847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1220847847
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.441691805
Short name T793
Test name
Test status
Simulation time 150856719 ps
CPU time 1.97 seconds
Started Jul 09 07:01:41 PM PDT 24
Finished Jul 09 07:01:46 PM PDT 24
Peak memory 209416 kb
Host smart-9ba37667-3ea3-493b-a9d9-9670404659f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441691805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.441691805
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.52154602
Short name T316
Test name
Test status
Simulation time 39081250 ps
CPU time 2.6 seconds
Started Jul 09 07:01:43 PM PDT 24
Finished Jul 09 07:01:48 PM PDT 24
Peak memory 222600 kb
Host smart-f5bd1168-392e-47b2-b45e-23171ce235d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52154602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.52154602
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.313459432
Short name T522
Test name
Test status
Simulation time 1044442911 ps
CPU time 4.56 seconds
Started Jul 09 07:01:42 PM PDT 24
Finished Jul 09 07:01:50 PM PDT 24
Peak memory 214372 kb
Host smart-a1ba2478-443c-450d-a68c-90c7b0e71bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313459432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.313459432
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.4207434933
Short name T710
Test name
Test status
Simulation time 201435416 ps
CPU time 4.82 seconds
Started Jul 09 07:01:38 PM PDT 24
Finished Jul 09 07:01:45 PM PDT 24
Peak memory 222508 kb
Host smart-ec6dc332-1ba4-49bb-b591-c76451e24b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207434933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.4207434933
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.696397966
Short name T910
Test name
Test status
Simulation time 1159639995 ps
CPU time 37.94 seconds
Started Jul 09 07:01:39 PM PDT 24
Finished Jul 09 07:02:20 PM PDT 24
Peak memory 222440 kb
Host smart-9371e47f-42c1-42b4-b0a0-53d6d8915cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696397966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.696397966
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.4288344424
Short name T841
Test name
Test status
Simulation time 45050816 ps
CPU time 2.67 seconds
Started Jul 09 07:01:40 PM PDT 24
Finished Jul 09 07:01:45 PM PDT 24
Peak memory 208516 kb
Host smart-fd496f0b-b4ca-495b-83dc-d899b5bf7213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288344424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.4288344424
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.971099233
Short name T869
Test name
Test status
Simulation time 864270138 ps
CPU time 3.01 seconds
Started Jul 09 07:01:40 PM PDT 24
Finished Jul 09 07:01:45 PM PDT 24
Peak memory 207484 kb
Host smart-a33e6f93-3451-4835-99ea-3cb1e9c7ef26
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971099233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.971099233
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.673985614
Short name T785
Test name
Test status
Simulation time 348414130 ps
CPU time 8.54 seconds
Started Jul 09 07:01:40 PM PDT 24
Finished Jul 09 07:01:51 PM PDT 24
Peak memory 207880 kb
Host smart-469e9c95-670e-4c67-a0bd-9f5ccddf2ed7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673985614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.673985614
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2067878207
Short name T724
Test name
Test status
Simulation time 25948193 ps
CPU time 2.05 seconds
Started Jul 09 07:01:41 PM PDT 24
Finished Jul 09 07:01:46 PM PDT 24
Peak memory 208752 kb
Host smart-f83f30e5-c5b8-40df-828e-9e37fa7f3fbc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067878207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2067878207
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2487499946
Short name T873
Test name
Test status
Simulation time 25758019 ps
CPU time 1.92 seconds
Started Jul 09 07:01:48 PM PDT 24
Finished Jul 09 07:01:52 PM PDT 24
Peak memory 209264 kb
Host smart-fbabec8f-48f5-4bd4-bb77-5d0f69f50972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487499946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2487499946
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1090363640
Short name T465
Test name
Test status
Simulation time 306053172 ps
CPU time 9.48 seconds
Started Jul 09 07:01:40 PM PDT 24
Finished Jul 09 07:01:53 PM PDT 24
Peak memory 208672 kb
Host smart-f9e13da8-4aad-4619-9a10-e9cd3450085b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090363640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1090363640
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.700610532
Short name T87
Test name
Test status
Simulation time 1322092338 ps
CPU time 15.41 seconds
Started Jul 09 07:01:39 PM PDT 24
Finished Jul 09 07:01:57 PM PDT 24
Peak memory 222504 kb
Host smart-cf41dca5-c57e-455e-a45d-a3a88ada3a35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700610532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.700610532
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3081598090
Short name T148
Test name
Test status
Simulation time 824218088 ps
CPU time 15.84 seconds
Started Jul 09 07:01:41 PM PDT 24
Finished Jul 09 07:02:00 PM PDT 24
Peak memory 222536 kb
Host smart-a636dae5-64a0-4280-92c6-c2c154d6a163
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081598090 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3081598090
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2694434837
Short name T211
Test name
Test status
Simulation time 542702972 ps
CPU time 5.63 seconds
Started Jul 09 07:01:41 PM PDT 24
Finished Jul 09 07:01:50 PM PDT 24
Peak memory 207756 kb
Host smart-65ab88d1-32f6-41eb-a5f4-f26ae1216520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694434837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2694434837
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2137725851
Short name T67
Test name
Test status
Simulation time 141000135 ps
CPU time 2.51 seconds
Started Jul 09 07:01:39 PM PDT 24
Finished Jul 09 07:01:45 PM PDT 24
Peak memory 210388 kb
Host smart-6ee8de69-7323-48a3-8312-da8fbfe7aba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137725851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2137725851
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.418742831
Short name T114
Test name
Test status
Simulation time 27166206 ps
CPU time 0.73 seconds
Started Jul 09 07:01:41 PM PDT 24
Finished Jul 09 07:01:45 PM PDT 24
Peak memory 206020 kb
Host smart-60c59f99-ab45-4366-bb86-ef9fda49d7b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418742831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.418742831
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2863753274
Short name T401
Test name
Test status
Simulation time 117461400 ps
CPU time 4.44 seconds
Started Jul 09 07:01:43 PM PDT 24
Finished Jul 09 07:01:51 PM PDT 24
Peak memory 215536 kb
Host smart-0fa5c003-bd54-421d-a368-f45aae3e9c73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2863753274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2863753274
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2070685326
Short name T674
Test name
Test status
Simulation time 573333255 ps
CPU time 5.07 seconds
Started Jul 09 07:01:40 PM PDT 24
Finished Jul 09 07:01:48 PM PDT 24
Peak memory 214736 kb
Host smart-499e696f-ec17-4f36-8a0c-ff85c6a8655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070685326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2070685326
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2526238039
Short name T294
Test name
Test status
Simulation time 138624073 ps
CPU time 2.55 seconds
Started Jul 09 07:01:49 PM PDT 24
Finished Jul 09 07:01:54 PM PDT 24
Peak memory 209892 kb
Host smart-4de1325e-097e-4f9b-ac4b-faee516875ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526238039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2526238039
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2132859196
Short name T110
Test name
Test status
Simulation time 103581957 ps
CPU time 4.69 seconds
Started Jul 09 07:01:41 PM PDT 24
Finished Jul 09 07:01:49 PM PDT 24
Peak memory 209616 kb
Host smart-7631556a-4ef9-4f6f-b9eb-6258c72c82be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132859196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2132859196
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2320735271
Short name T393
Test name
Test status
Simulation time 157158734 ps
CPU time 2.71 seconds
Started Jul 09 07:01:40 PM PDT 24
Finished Jul 09 07:01:45 PM PDT 24
Peak memory 214200 kb
Host smart-556deeac-cfea-497e-add6-68872b24cd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320735271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2320735271
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3747545844
Short name T682
Test name
Test status
Simulation time 103436577 ps
CPU time 2.63 seconds
Started Jul 09 07:01:42 PM PDT 24
Finished Jul 09 07:01:48 PM PDT 24
Peak memory 220272 kb
Host smart-1c566fa3-e753-4ad7-a234-fbae539c35f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747545844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3747545844
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.4107209932
Short name T805
Test name
Test status
Simulation time 187938263 ps
CPU time 4.12 seconds
Started Jul 09 07:01:42 PM PDT 24
Finished Jul 09 07:01:49 PM PDT 24
Peak memory 207460 kb
Host smart-1a8d6a16-8ddc-4642-b1b7-5103b247d917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107209932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.4107209932
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.942268141
Short name T880
Test name
Test status
Simulation time 137977714 ps
CPU time 3.35 seconds
Started Jul 09 07:01:39 PM PDT 24
Finished Jul 09 07:01:44 PM PDT 24
Peak memory 207284 kb
Host smart-b6804615-7352-47d7-b42d-b1ba10735ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942268141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.942268141
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2982634478
Short name T575
Test name
Test status
Simulation time 72566012 ps
CPU time 1.73 seconds
Started Jul 09 07:01:39 PM PDT 24
Finished Jul 09 07:01:44 PM PDT 24
Peak memory 206992 kb
Host smart-fb5660cd-1f4c-446d-8ac8-3e51ae8126c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982634478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2982634478
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1261090096
Short name T859
Test name
Test status
Simulation time 1897344127 ps
CPU time 55.4 seconds
Started Jul 09 07:01:48 PM PDT 24
Finished Jul 09 07:02:46 PM PDT 24
Peak memory 208596 kb
Host smart-cb278cfa-939b-4886-b4de-c3bcdf350faf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261090096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1261090096
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.863318497
Short name T748
Test name
Test status
Simulation time 5093145801 ps
CPU time 37.6 seconds
Started Jul 09 07:01:41 PM PDT 24
Finished Jul 09 07:02:22 PM PDT 24
Peak memory 208676 kb
Host smart-0bad2d22-37f3-4b88-9400-f2b102fc3a0b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863318497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.863318497
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.447742284
Short name T624
Test name
Test status
Simulation time 217506517 ps
CPU time 2.98 seconds
Started Jul 09 07:01:48 PM PDT 24
Finished Jul 09 07:01:54 PM PDT 24
Peak memory 208772 kb
Host smart-f3763ed1-2920-4d30-b6de-22a05dd88e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447742284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.447742284
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.503746710
Short name T717
Test name
Test status
Simulation time 125347659 ps
CPU time 3.1 seconds
Started Jul 09 07:01:48 PM PDT 24
Finished Jul 09 07:01:54 PM PDT 24
Peak memory 208740 kb
Host smart-251fbbc0-1bba-4bdc-81c8-1472881876c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503746710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.503746710
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3045642789
Short name T260
Test name
Test status
Simulation time 668657120 ps
CPU time 6.71 seconds
Started Jul 09 07:01:41 PM PDT 24
Finished Jul 09 07:01:51 PM PDT 24
Peak memory 210364 kb
Host smart-d1cd9085-3dd1-4feb-8618-a6e4cf9252f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045642789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3045642789
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3356321848
Short name T663
Test name
Test status
Simulation time 155201553 ps
CPU time 1.86 seconds
Started Jul 09 07:01:42 PM PDT 24
Finished Jul 09 07:01:47 PM PDT 24
Peak memory 209840 kb
Host smart-a3a3ed8d-1b0d-4d61-ae67-b390971dbaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356321848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3356321848
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.132443302
Short name T451
Test name
Test status
Simulation time 12866829 ps
CPU time 0.88 seconds
Started Jul 09 07:01:45 PM PDT 24
Finished Jul 09 07:01:49 PM PDT 24
Peak memory 206012 kb
Host smart-fe4feac4-0bda-4b2d-ae7c-a37b148dbd63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132443302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.132443302
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2062531026
Short name T664
Test name
Test status
Simulation time 526181869 ps
CPU time 7.97 seconds
Started Jul 09 07:01:46 PM PDT 24
Finished Jul 09 07:01:57 PM PDT 24
Peak memory 221660 kb
Host smart-32dc5b73-b92f-4ea3-891a-19dc45a40cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062531026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2062531026
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3000551819
Short name T353
Test name
Test status
Simulation time 208354189 ps
CPU time 6.81 seconds
Started Jul 09 07:01:48 PM PDT 24
Finished Jul 09 07:01:57 PM PDT 24
Peak memory 208636 kb
Host smart-b2c0268d-028d-4921-834d-c23800b5f949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000551819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3000551819
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.4110100025
Short name T899
Test name
Test status
Simulation time 834947590 ps
CPU time 4.76 seconds
Started Jul 09 07:01:45 PM PDT 24
Finished Jul 09 07:01:53 PM PDT 24
Peak memory 214344 kb
Host smart-753d0c11-9054-42c4-b922-23c6bae463e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110100025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.4110100025
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2360446474
Short name T699
Test name
Test status
Simulation time 36565615 ps
CPU time 2.44 seconds
Started Jul 09 07:01:45 PM PDT 24
Finished Jul 09 07:01:51 PM PDT 24
Peak memory 214276 kb
Host smart-bcefde64-b578-4108-88fd-f35ccc655786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360446474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2360446474
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2763126874
Short name T222
Test name
Test status
Simulation time 30181946 ps
CPU time 2.35 seconds
Started Jul 09 07:01:42 PM PDT 24
Finished Jul 09 07:01:48 PM PDT 24
Peak memory 222768 kb
Host smart-02ea288f-ec36-4251-8649-50d536238a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763126874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2763126874
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3582072988
Short name T326
Test name
Test status
Simulation time 1582185113 ps
CPU time 4.96 seconds
Started Jul 09 07:01:41 PM PDT 24
Finished Jul 09 07:01:49 PM PDT 24
Peak memory 218124 kb
Host smart-bdeb7550-a611-445f-94fb-8f5c59b7a59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582072988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3582072988
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3614887582
Short name T689
Test name
Test status
Simulation time 65425981 ps
CPU time 3.1 seconds
Started Jul 09 07:01:41 PM PDT 24
Finished Jul 09 07:01:47 PM PDT 24
Peak memory 208144 kb
Host smart-4de7e08e-3bc8-4f34-9d08-4afbca97c413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614887582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3614887582
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3641373762
Short name T595
Test name
Test status
Simulation time 225857135 ps
CPU time 4.53 seconds
Started Jul 09 07:01:38 PM PDT 24
Finished Jul 09 07:01:45 PM PDT 24
Peak memory 208840 kb
Host smart-7c656161-1eb7-4b86-ab55-def96970c32a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641373762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3641373762
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.393806295
Short name T456
Test name
Test status
Simulation time 380917079 ps
CPU time 5.71 seconds
Started Jul 09 07:01:37 PM PDT 24
Finished Jul 09 07:01:45 PM PDT 24
Peak memory 208108 kb
Host smart-fd785d93-b3a7-4475-9bc2-2afc02dfd912
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393806295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.393806295
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.394494688
Short name T485
Test name
Test status
Simulation time 47148980 ps
CPU time 2.25 seconds
Started Jul 09 07:01:42 PM PDT 24
Finished Jul 09 07:01:48 PM PDT 24
Peak memory 206888 kb
Host smart-67065aab-46eb-44ce-9df3-7955ccbba5fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394494688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.394494688
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.127137215
Short name T559
Test name
Test status
Simulation time 70696851 ps
CPU time 2.51 seconds
Started Jul 09 07:01:46 PM PDT 24
Finished Jul 09 07:01:51 PM PDT 24
Peak memory 207808 kb
Host smart-6526badd-d690-41f4-bddd-a48a481ccb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127137215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.127137215
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1728849235
Short name T660
Test name
Test status
Simulation time 2238983005 ps
CPU time 18.02 seconds
Started Jul 09 07:01:39 PM PDT 24
Finished Jul 09 07:01:59 PM PDT 24
Peak memory 208248 kb
Host smart-a95a36be-8190-43d4-8b2d-bffdc1474809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728849235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1728849235
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2660855965
Short name T388
Test name
Test status
Simulation time 13837412287 ps
CPU time 181.91 seconds
Started Jul 09 07:01:47 PM PDT 24
Finished Jul 09 07:04:51 PM PDT 24
Peak memory 216144 kb
Host smart-da7d9c38-1905-4bfc-a180-1d1d97cb80b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660855965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2660855965
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3158405258
Short name T774
Test name
Test status
Simulation time 297583197 ps
CPU time 8.13 seconds
Started Jul 09 07:01:46 PM PDT 24
Finished Jul 09 07:01:57 PM PDT 24
Peak memory 214276 kb
Host smart-0f7e6a4c-35d4-4344-8c39-89089d602b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158405258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3158405258
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2016906532
Short name T553
Test name
Test status
Simulation time 136636370 ps
CPU time 2.18 seconds
Started Jul 09 07:01:44 PM PDT 24
Finished Jul 09 07:01:49 PM PDT 24
Peak memory 209964 kb
Host smart-4949bcaa-db56-417e-aebf-cd010f4fa0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016906532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2016906532
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1559144006
Short name T1
Test name
Test status
Simulation time 15340226 ps
CPU time 0.75 seconds
Started Jul 09 07:01:50 PM PDT 24
Finished Jul 09 07:01:53 PM PDT 24
Peak memory 206016 kb
Host smart-1e37bda4-c550-4c8e-904d-b3eed109c91f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559144006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1559144006
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3491855006
Short name T293
Test name
Test status
Simulation time 108709946 ps
CPU time 2.65 seconds
Started Jul 09 07:01:49 PM PDT 24
Finished Jul 09 07:01:54 PM PDT 24
Peak memory 218208 kb
Host smart-0b6ed5f5-0f3a-476c-98af-6df6094683a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491855006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3491855006
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3814861861
Short name T711
Test name
Test status
Simulation time 278265174 ps
CPU time 3.04 seconds
Started Jul 09 07:01:44 PM PDT 24
Finished Jul 09 07:01:50 PM PDT 24
Peak memory 214520 kb
Host smart-01e74652-4d13-4f6d-83eb-ae77f4d06dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814861861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3814861861
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3213753777
Short name T101
Test name
Test status
Simulation time 105065492 ps
CPU time 2.23 seconds
Started Jul 09 07:01:44 PM PDT 24
Finished Jul 09 07:01:50 PM PDT 24
Peak memory 214300 kb
Host smart-100d6b7f-ec59-454e-aea8-d25ae026a8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213753777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3213753777
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2681400421
Short name T421
Test name
Test status
Simulation time 100513048 ps
CPU time 3.07 seconds
Started Jul 09 07:01:46 PM PDT 24
Finished Jul 09 07:01:52 PM PDT 24
Peak memory 207456 kb
Host smart-c907dca1-720e-40ec-970f-1455f661cb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681400421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2681400421
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.370123662
Short name T481
Test name
Test status
Simulation time 732165257 ps
CPU time 3.07 seconds
Started Jul 09 07:01:46 PM PDT 24
Finished Jul 09 07:01:52 PM PDT 24
Peak memory 218424 kb
Host smart-8faf93a6-4a8e-4d03-b23f-7df6d5e3f50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370123662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.370123662
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3478793444
Short name T441
Test name
Test status
Simulation time 164678451 ps
CPU time 2.18 seconds
Started Jul 09 07:01:46 PM PDT 24
Finished Jul 09 07:01:51 PM PDT 24
Peak memory 206920 kb
Host smart-b2a83081-15a4-4bbe-8d55-6725ae374558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478793444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3478793444
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3251097050
Short name T596
Test name
Test status
Simulation time 19413307 ps
CPU time 1.74 seconds
Started Jul 09 07:01:44 PM PDT 24
Finished Jul 09 07:01:49 PM PDT 24
Peak memory 206912 kb
Host smart-90f425c4-0d49-4560-98c5-dcf3497d4113
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251097050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3251097050
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2012118183
Short name T323
Test name
Test status
Simulation time 826150028 ps
CPU time 5.06 seconds
Started Jul 09 07:01:47 PM PDT 24
Finished Jul 09 07:01:55 PM PDT 24
Peak memory 208484 kb
Host smart-bae2268a-0026-42b5-8901-ec2e2688a14c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012118183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2012118183
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3981387316
Short name T691
Test name
Test status
Simulation time 495802138 ps
CPU time 4.32 seconds
Started Jul 09 07:01:47 PM PDT 24
Finished Jul 09 07:01:54 PM PDT 24
Peak memory 208772 kb
Host smart-58a6e3f6-5c08-4fa6-a243-1f959f003e66
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981387316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3981387316
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1136354519
Short name T16
Test name
Test status
Simulation time 64659201 ps
CPU time 3.04 seconds
Started Jul 09 07:01:45 PM PDT 24
Finished Jul 09 07:01:51 PM PDT 24
Peak memory 214348 kb
Host smart-1fc5dae1-40c8-4860-816f-e21308b8d217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136354519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1136354519
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3002690360
Short name T909
Test name
Test status
Simulation time 384800583 ps
CPU time 2.84 seconds
Started Jul 09 07:03:24 PM PDT 24
Finished Jul 09 07:03:28 PM PDT 24
Peak memory 207044 kb
Host smart-61822773-b7dd-4273-a8cc-55ae19c89c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002690360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3002690360
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2626714186
Short name T387
Test name
Test status
Simulation time 851812128 ps
CPU time 9.67 seconds
Started Jul 09 07:01:43 PM PDT 24
Finished Jul 09 07:01:56 PM PDT 24
Peak memory 214324 kb
Host smart-3764aec3-96b2-4b26-ac9d-2702a348644f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626714186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2626714186
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.4242216307
Short name T623
Test name
Test status
Simulation time 159867273 ps
CPU time 1.99 seconds
Started Jul 09 07:01:44 PM PDT 24
Finished Jul 09 07:01:49 PM PDT 24
Peak memory 210264 kb
Host smart-4738a48a-e8d8-40e4-b47b-6e0cc765a769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242216307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.4242216307
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2821059547
Short name T572
Test name
Test status
Simulation time 13156406 ps
CPU time 0.83 seconds
Started Jul 09 06:59:59 PM PDT 24
Finished Jul 09 07:00:02 PM PDT 24
Peak memory 206008 kb
Host smart-f56cbe81-5c7b-4e1f-851f-6fad2fddb8df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821059547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2821059547
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.479088571
Short name T263
Test name
Test status
Simulation time 67991078 ps
CPU time 4.68 seconds
Started Jul 09 06:59:56 PM PDT 24
Finished Jul 09 07:00:01 PM PDT 24
Peak memory 222472 kb
Host smart-d781a83d-543f-443e-a432-603ed76dd231
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=479088571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.479088571
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1889672860
Short name T7
Test name
Test status
Simulation time 365602953 ps
CPU time 12.96 seconds
Started Jul 09 06:59:56 PM PDT 24
Finished Jul 09 07:00:10 PM PDT 24
Peak memory 221976 kb
Host smart-7e6f8e9b-c17f-44e4-9f01-4615f544d24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889672860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1889672860
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.818230422
Short name T709
Test name
Test status
Simulation time 55649394 ps
CPU time 1.83 seconds
Started Jul 09 06:59:53 PM PDT 24
Finished Jul 09 06:59:56 PM PDT 24
Peak memory 207248 kb
Host smart-1a95c2ec-aba0-4846-9507-2fe703743980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818230422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.818230422
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3212196705
Short name T61
Test name
Test status
Simulation time 282910361 ps
CPU time 4.4 seconds
Started Jul 09 07:01:02 PM PDT 24
Finished Jul 09 07:01:09 PM PDT 24
Peak memory 210236 kb
Host smart-6fadb3bd-bf8c-49ac-a582-b9323ddbf013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212196705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3212196705
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2103325481
Short name T390
Test name
Test status
Simulation time 292100604 ps
CPU time 4.15 seconds
Started Jul 09 06:59:54 PM PDT 24
Finished Jul 09 07:00:00 PM PDT 24
Peak memory 207200 kb
Host smart-3efb610b-fbcf-4f84-bca8-44895a77a8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103325481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2103325481
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3898489251
Short name T12
Test name
Test status
Simulation time 554583861 ps
CPU time 9.03 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:12 PM PDT 24
Peak memory 231484 kb
Host smart-1c7b495f-5a30-40e8-84b0-0bab2ff3d3c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898489251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3898489251
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3541144008
Short name T350
Test name
Test status
Simulation time 1436996549 ps
CPU time 44.75 seconds
Started Jul 09 06:59:55 PM PDT 24
Finished Jul 09 07:00:41 PM PDT 24
Peak memory 208624 kb
Host smart-12183421-e5ce-465a-99bc-631b043513c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541144008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3541144008
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3741061503
Short name T550
Test name
Test status
Simulation time 690021796 ps
CPU time 18.29 seconds
Started Jul 09 06:59:55 PM PDT 24
Finished Jul 09 07:00:15 PM PDT 24
Peak memory 209016 kb
Host smart-0288c898-b1c7-4785-a36f-843c72d43bce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741061503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3741061503
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1293269778
Short name T612
Test name
Test status
Simulation time 258799680 ps
CPU time 4.97 seconds
Started Jul 09 06:59:53 PM PDT 24
Finished Jul 09 06:59:59 PM PDT 24
Peak memory 207052 kb
Host smart-aea686cc-6a8a-4cb4-90b7-419c4390c5b1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293269778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1293269778
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.608768933
Short name T530
Test name
Test status
Simulation time 3220028923 ps
CPU time 15.7 seconds
Started Jul 09 07:00:04 PM PDT 24
Finished Jul 09 07:00:21 PM PDT 24
Peak memory 207020 kb
Host smart-4c2dff12-f8c4-48d8-a98f-75be07332180
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608768933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.608768933
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2490242006
Short name T468
Test name
Test status
Simulation time 105523328 ps
CPU time 2.07 seconds
Started Jul 09 06:59:54 PM PDT 24
Finished Jul 09 06:59:57 PM PDT 24
Peak memory 209040 kb
Host smart-ae1a63af-7c9a-4d2d-9670-148cac876f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490242006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2490242006
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1662373620
Short name T412
Test name
Test status
Simulation time 1183744219 ps
CPU time 23.04 seconds
Started Jul 09 06:59:54 PM PDT 24
Finished Jul 09 07:00:18 PM PDT 24
Peak memory 208644 kb
Host smart-414701bc-2732-4428-bf9d-408553ad62fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662373620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1662373620
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3209600917
Short name T139
Test name
Test status
Simulation time 1246751390 ps
CPU time 18.84 seconds
Started Jul 09 06:59:55 PM PDT 24
Finished Jul 09 07:00:16 PM PDT 24
Peak memory 222732 kb
Host smart-d82cf424-1cfa-40fc-bd32-1e4cbb240cb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209600917 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3209600917
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3847911669
Short name T341
Test name
Test status
Simulation time 131345433 ps
CPU time 5.84 seconds
Started Jul 09 06:59:53 PM PDT 24
Finished Jul 09 07:00:01 PM PDT 24
Peak memory 209748 kb
Host smart-44e71dae-13c8-441d-8289-41963ccf2189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847911669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3847911669
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3732693046
Short name T567
Test name
Test status
Simulation time 51996328 ps
CPU time 2.17 seconds
Started Jul 09 06:59:54 PM PDT 24
Finished Jul 09 06:59:58 PM PDT 24
Peak memory 210388 kb
Host smart-7adb8eec-44c5-4ea4-9c9a-5e1d6110b403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732693046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3732693046
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.904778499
Short name T450
Test name
Test status
Simulation time 15882351 ps
CPU time 0.8 seconds
Started Jul 09 07:01:49 PM PDT 24
Finished Jul 09 07:01:52 PM PDT 24
Peak memory 205972 kb
Host smart-8dd7fd00-c3de-4b1d-98ba-c143fcd9233f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904778499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.904778499
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.397358360
Short name T673
Test name
Test status
Simulation time 38848138 ps
CPU time 2.25 seconds
Started Jul 09 07:01:48 PM PDT 24
Finished Jul 09 07:01:53 PM PDT 24
Peak memory 207896 kb
Host smart-e2b10050-d8a6-48ad-8389-843e1718ccbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397358360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.397358360
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3894310369
Short name T746
Test name
Test status
Simulation time 184911210 ps
CPU time 3.22 seconds
Started Jul 09 07:01:51 PM PDT 24
Finished Jul 09 07:01:57 PM PDT 24
Peak memory 209116 kb
Host smart-56de10a1-05ea-410a-84f1-ddc0cb1aad4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894310369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3894310369
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1192874601
Short name T862
Test name
Test status
Simulation time 79159719 ps
CPU time 1.83 seconds
Started Jul 09 07:01:51 PM PDT 24
Finished Jul 09 07:01:56 PM PDT 24
Peak memory 214356 kb
Host smart-ccf3c2ff-23c1-4c9b-88c0-d7a285806be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192874601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1192874601
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.889735684
Short name T761
Test name
Test status
Simulation time 1055712534 ps
CPU time 5.45 seconds
Started Jul 09 07:01:50 PM PDT 24
Finished Jul 09 07:01:59 PM PDT 24
Peak memory 222432 kb
Host smart-dd443162-2b4b-4ff8-8ea7-b84c662966bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889735684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.889735684
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_random.1477842912
Short name T917
Test name
Test status
Simulation time 443643406 ps
CPU time 4.79 seconds
Started Jul 09 07:01:50 PM PDT 24
Finished Jul 09 07:01:58 PM PDT 24
Peak memory 209220 kb
Host smart-1271a8ad-c71e-4999-9d7a-3c2b13e6b4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477842912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1477842912
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2625526221
Short name T741
Test name
Test status
Simulation time 294061806 ps
CPU time 3.55 seconds
Started Jul 09 07:01:52 PM PDT 24
Finished Jul 09 07:01:58 PM PDT 24
Peak memory 208856 kb
Host smart-ac7df5b5-06fa-4cf3-a2e0-1dcf6841f04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625526221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2625526221
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2580948222
Short name T90
Test name
Test status
Simulation time 149127806 ps
CPU time 3.24 seconds
Started Jul 09 07:01:51 PM PDT 24
Finished Jul 09 07:01:57 PM PDT 24
Peak memory 207188 kb
Host smart-4189609f-1e1c-4eab-bad3-c1f3d5c151dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580948222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2580948222
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1064552008
Short name T700
Test name
Test status
Simulation time 348851691 ps
CPU time 7.35 seconds
Started Jul 09 07:01:51 PM PDT 24
Finished Jul 09 07:02:01 PM PDT 24
Peak memory 208756 kb
Host smart-8ae35f4e-ed88-4391-8893-54ae872a90dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064552008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1064552008
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.614530840
Short name T458
Test name
Test status
Simulation time 263889485 ps
CPU time 2.84 seconds
Started Jul 09 07:01:49 PM PDT 24
Finished Jul 09 07:01:54 PM PDT 24
Peak memory 206904 kb
Host smart-55bd6d44-b706-4746-b84f-b323f3129fb8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614530840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.614530840
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2182014030
Short name T209
Test name
Test status
Simulation time 69907483 ps
CPU time 2.93 seconds
Started Jul 09 07:01:50 PM PDT 24
Finished Jul 09 07:01:56 PM PDT 24
Peak memory 218300 kb
Host smart-65d9cddc-4b7e-41e0-9c74-6d212faa8b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182014030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2182014030
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.630566292
Short name T696
Test name
Test status
Simulation time 126044363 ps
CPU time 2.34 seconds
Started Jul 09 07:01:52 PM PDT 24
Finished Jul 09 07:01:57 PM PDT 24
Peak memory 206868 kb
Host smart-9e0f54e6-f89a-42b0-a015-b9ac64a39f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630566292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.630566292
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3772146427
Short name T784
Test name
Test status
Simulation time 1511142955 ps
CPU time 27.33 seconds
Started Jul 09 07:01:56 PM PDT 24
Finished Jul 09 07:02:25 PM PDT 24
Peak memory 216336 kb
Host smart-a797f298-aefd-40fb-9501-6d709ab37559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772146427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3772146427
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3896422163
Short name T890
Test name
Test status
Simulation time 150880485 ps
CPU time 3.01 seconds
Started Jul 09 07:01:55 PM PDT 24
Finished Jul 09 07:02:00 PM PDT 24
Peak memory 218244 kb
Host smart-255222b4-8ae8-4029-be65-2a09a1a6724e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896422163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3896422163
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.571205358
Short name T200
Test name
Test status
Simulation time 164633379 ps
CPU time 2.6 seconds
Started Jul 09 07:01:59 PM PDT 24
Finished Jul 09 07:02:04 PM PDT 24
Peak memory 209780 kb
Host smart-8423b056-1414-440c-b7bc-cc1a30119c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571205358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.571205358
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.179523588
Short name T463
Test name
Test status
Simulation time 33775139 ps
CPU time 0.76 seconds
Started Jul 09 07:01:52 PM PDT 24
Finished Jul 09 07:01:56 PM PDT 24
Peak memory 206008 kb
Host smart-bb9cdbf1-70e9-4cd6-81af-af01c55e83f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179523588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.179523588
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.92685068
Short name T874
Test name
Test status
Simulation time 71942418 ps
CPU time 4.72 seconds
Started Jul 09 07:01:51 PM PDT 24
Finished Jul 09 07:01:59 PM PDT 24
Peak memory 214288 kb
Host smart-44bb2358-ca97-4198-9dff-8692b0f9b328
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92685068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.92685068
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1585178634
Short name T698
Test name
Test status
Simulation time 423982393 ps
CPU time 3.73 seconds
Started Jul 09 07:01:52 PM PDT 24
Finished Jul 09 07:01:58 PM PDT 24
Peak memory 216316 kb
Host smart-9b2d8bd8-3c33-4d8d-b6ca-5db483ae5ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585178634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1585178634
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3176111519
Short name T80
Test name
Test status
Simulation time 67080997 ps
CPU time 3.13 seconds
Started Jul 09 07:01:50 PM PDT 24
Finished Jul 09 07:01:56 PM PDT 24
Peak memory 218432 kb
Host smart-1a8a9dcd-295f-4300-b3b5-fabb40d55c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176111519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3176111519
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1454230347
Short name T99
Test name
Test status
Simulation time 3468333766 ps
CPU time 11.8 seconds
Started Jul 09 07:01:50 PM PDT 24
Finished Jul 09 07:02:04 PM PDT 24
Peak memory 219300 kb
Host smart-598d5c9c-c279-4d66-ab59-91160d4dff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454230347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1454230347
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.569478602
Short name T315
Test name
Test status
Simulation time 379200370 ps
CPU time 3.38 seconds
Started Jul 09 07:01:49 PM PDT 24
Finished Jul 09 07:01:55 PM PDT 24
Peak memory 214240 kb
Host smart-0953efca-40ae-4f70-a327-3791294306ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569478602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.569478602
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3346752684
Short name T72
Test name
Test status
Simulation time 489281616 ps
CPU time 4.42 seconds
Started Jul 09 07:02:00 PM PDT 24
Finished Jul 09 07:02:07 PM PDT 24
Peak memory 209084 kb
Host smart-c8c40fc6-e010-4df3-9a8d-2228259d4d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346752684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3346752684
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2887888024
Short name T639
Test name
Test status
Simulation time 137344716 ps
CPU time 4.92 seconds
Started Jul 09 07:01:54 PM PDT 24
Finished Jul 09 07:02:01 PM PDT 24
Peak memory 207428 kb
Host smart-c5ca8a41-ea12-466c-9ce3-afdbf05fa673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887888024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2887888024
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3880938900
Short name T775
Test name
Test status
Simulation time 58237694 ps
CPU time 2.93 seconds
Started Jul 09 07:01:54 PM PDT 24
Finished Jul 09 07:01:59 PM PDT 24
Peak memory 208044 kb
Host smart-689971e7-c976-44d4-a5e1-feabaec549ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880938900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3880938900
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3284750
Short name T318
Test name
Test status
Simulation time 414478290 ps
CPU time 3.6 seconds
Started Jul 09 07:01:49 PM PDT 24
Finished Jul 09 07:01:55 PM PDT 24
Peak memory 208316 kb
Host smart-0e5d702a-adcf-47dd-8cc8-7a7925242c4a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3284750
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1772321622
Short name T250
Test name
Test status
Simulation time 233716117 ps
CPU time 3.01 seconds
Started Jul 09 07:01:51 PM PDT 24
Finished Jul 09 07:01:57 PM PDT 24
Peak memory 208612 kb
Host smart-51f6be8e-7175-46d8-a87c-45fe769bcace
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772321622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1772321622
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1303784993
Short name T470
Test name
Test status
Simulation time 228762903 ps
CPU time 3.26 seconds
Started Jul 09 07:01:59 PM PDT 24
Finished Jul 09 07:02:05 PM PDT 24
Peak memory 206848 kb
Host smart-9c7bea75-f729-411e-8f93-e0729f160e69
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303784993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1303784993
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.181959814
Short name T268
Test name
Test status
Simulation time 647627987 ps
CPU time 5.28 seconds
Started Jul 09 07:01:51 PM PDT 24
Finished Jul 09 07:01:59 PM PDT 24
Peak memory 218408 kb
Host smart-65f3765e-95a6-4726-b417-d2bd7c8949f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181959814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.181959814
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.395961531
Short name T449
Test name
Test status
Simulation time 730042275 ps
CPU time 6.9 seconds
Started Jul 09 07:01:54 PM PDT 24
Finished Jul 09 07:02:03 PM PDT 24
Peak memory 208632 kb
Host smart-6e2a8df8-5b55-46ff-9523-185ef82ac1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395961531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.395961531
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.77756442
Short name T317
Test name
Test status
Simulation time 1410891246 ps
CPU time 25.79 seconds
Started Jul 09 07:01:51 PM PDT 24
Finished Jul 09 07:02:20 PM PDT 24
Peak memory 214536 kb
Host smart-81c82020-ea1d-4a79-8e2e-ddc85e0f2f50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77756442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.77756442
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.434022390
Short name T570
Test name
Test status
Simulation time 390992648 ps
CPU time 9.24 seconds
Started Jul 09 07:01:52 PM PDT 24
Finished Jul 09 07:02:04 PM PDT 24
Peak memory 209216 kb
Host smart-2b40c409-02dd-4710-bd71-9a9afd7df7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434022390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.434022390
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.502758375
Short name T39
Test name
Test status
Simulation time 105545249 ps
CPU time 1.85 seconds
Started Jul 09 07:01:49 PM PDT 24
Finished Jul 09 07:01:54 PM PDT 24
Peak memory 210040 kb
Host smart-d37b20c8-327f-4de0-a697-61f5c87411ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502758375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.502758375
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.341726695
Short name T556
Test name
Test status
Simulation time 16901591 ps
CPU time 0.87 seconds
Started Jul 09 07:02:00 PM PDT 24
Finished Jul 09 07:02:03 PM PDT 24
Peak memory 205992 kb
Host smart-de68091b-65b7-44e9-ae45-b99867848934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341726695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.341726695
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2590092288
Short name T151
Test name
Test status
Simulation time 36603614 ps
CPU time 2.69 seconds
Started Jul 09 07:01:57 PM PDT 24
Finished Jul 09 07:02:01 PM PDT 24
Peak memory 214348 kb
Host smart-661d2855-1bdd-4764-9edb-2b0a670e1734
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2590092288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2590092288
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1389475455
Short name T637
Test name
Test status
Simulation time 75872142 ps
CPU time 4.12 seconds
Started Jul 09 07:01:58 PM PDT 24
Finished Jul 09 07:02:04 PM PDT 24
Peak memory 208920 kb
Host smart-7e9e540b-ade1-4a91-85df-f595fde07155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389475455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1389475455
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1341697086
Short name T295
Test name
Test status
Simulation time 25961743 ps
CPU time 1.99 seconds
Started Jul 09 07:01:56 PM PDT 24
Finished Jul 09 07:02:00 PM PDT 24
Peak memory 208840 kb
Host smart-fbf0025b-8230-467a-9b82-b5c9fc005ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341697086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1341697086
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3652055793
Short name T778
Test name
Test status
Simulation time 120399534 ps
CPU time 4.94 seconds
Started Jul 09 07:01:59 PM PDT 24
Finished Jul 09 07:02:06 PM PDT 24
Peak memory 214360 kb
Host smart-37916b67-6d22-4dcc-a3e0-47db9faa99e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652055793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3652055793
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1176079585
Short name T356
Test name
Test status
Simulation time 440797546 ps
CPU time 3.84 seconds
Started Jul 09 07:01:55 PM PDT 24
Finished Jul 09 07:02:01 PM PDT 24
Peak memory 221292 kb
Host smart-537af809-d7b8-4b07-b180-6ce0ea8e403f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176079585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1176079585
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3417472505
Short name T68
Test name
Test status
Simulation time 82507730 ps
CPU time 4.38 seconds
Started Jul 09 07:01:56 PM PDT 24
Finished Jul 09 07:02:02 PM PDT 24
Peak memory 220172 kb
Host smart-f2e17b98-d137-4247-a0ec-4a84d8bfcda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417472505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3417472505
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3230915960
Short name T817
Test name
Test status
Simulation time 173661620 ps
CPU time 6.57 seconds
Started Jul 09 07:02:05 PM PDT 24
Finished Jul 09 07:02:16 PM PDT 24
Peak memory 207288 kb
Host smart-35dd54af-1a54-497d-934c-eff6e9eeec7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230915960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3230915960
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2618434336
Short name T685
Test name
Test status
Simulation time 3225258628 ps
CPU time 5.55 seconds
Started Jul 09 07:01:54 PM PDT 24
Finished Jul 09 07:02:02 PM PDT 24
Peak memory 208104 kb
Host smart-b8732fd7-19ab-4fd8-9fcc-c90626f5eef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618434336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2618434336
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3616618752
Short name T636
Test name
Test status
Simulation time 65324975 ps
CPU time 2.36 seconds
Started Jul 09 07:01:53 PM PDT 24
Finished Jul 09 07:01:58 PM PDT 24
Peak memory 207336 kb
Host smart-8e9aca4f-b95e-4cf6-9269-2f2114fcd4ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616618752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3616618752
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.4052374616
Short name T885
Test name
Test status
Simulation time 34330451 ps
CPU time 2.32 seconds
Started Jul 09 07:01:53 PM PDT 24
Finished Jul 09 07:01:58 PM PDT 24
Peak memory 206804 kb
Host smart-724f11f8-6287-4548-a1bf-b7c4bad69e2d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052374616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.4052374616
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2810312451
Short name T753
Test name
Test status
Simulation time 406091697 ps
CPU time 5.49 seconds
Started Jul 09 07:02:00 PM PDT 24
Finished Jul 09 07:02:07 PM PDT 24
Peak memory 208408 kb
Host smart-f04b67af-a60f-49c1-9027-81607a51a043
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810312451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2810312451
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3535315141
Short name T762
Test name
Test status
Simulation time 247750881 ps
CPU time 3.26 seconds
Started Jul 09 07:01:57 PM PDT 24
Finished Jul 09 07:02:02 PM PDT 24
Peak memory 209868 kb
Host smart-0108ca84-fb95-48c2-ab88-ef1a9d4d28f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535315141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3535315141
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2371762756
Short name T459
Test name
Test status
Simulation time 107856268 ps
CPU time 2.16 seconds
Started Jul 09 07:01:51 PM PDT 24
Finished Jul 09 07:01:55 PM PDT 24
Peak memory 206140 kb
Host smart-397e676a-c3ae-42f0-8a37-214816109088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371762756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2371762756
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2530247921
Short name T233
Test name
Test status
Simulation time 309055595 ps
CPU time 12.11 seconds
Started Jul 09 07:01:57 PM PDT 24
Finished Jul 09 07:02:10 PM PDT 24
Peak memory 215812 kb
Host smart-1160249b-76a5-4d30-9b2c-247d2f2b1956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530247921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2530247921
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.2072989188
Short name T309
Test name
Test status
Simulation time 1467272610 ps
CPU time 21.13 seconds
Started Jul 09 07:01:56 PM PDT 24
Finished Jul 09 07:02:19 PM PDT 24
Peak memory 222620 kb
Host smart-2aa21613-bebe-4237-bed6-83de55f10f22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072989188 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.2072989188
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.647229073
Short name T668
Test name
Test status
Simulation time 234541021 ps
CPU time 8.47 seconds
Started Jul 09 07:02:00 PM PDT 24
Finished Jul 09 07:02:12 PM PDT 24
Peak memory 208860 kb
Host smart-54abde80-e283-4e2f-a48b-cc58b66ac630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647229073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.647229073
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1705180763
Short name T202
Test name
Test status
Simulation time 86854044 ps
CPU time 2.08 seconds
Started Jul 09 07:02:01 PM PDT 24
Finished Jul 09 07:02:06 PM PDT 24
Peak memory 210500 kb
Host smart-1da89d1c-bcaf-4b9e-8d46-77beed66bde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705180763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1705180763
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.798830560
Short name T701
Test name
Test status
Simulation time 24672309 ps
CPU time 0.85 seconds
Started Jul 09 07:02:05 PM PDT 24
Finished Jul 09 07:02:10 PM PDT 24
Peak memory 205964 kb
Host smart-c1462c44-1a8d-4482-a025-82cb6345ec91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798830560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.798830560
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1348694365
Short name T797
Test name
Test status
Simulation time 113094380 ps
CPU time 3.74 seconds
Started Jul 09 07:01:55 PM PDT 24
Finished Jul 09 07:02:01 PM PDT 24
Peak memory 207360 kb
Host smart-90e0ff74-a5de-429d-9ef1-d0fa2fb15423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348694365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1348694365
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.844762508
Short name T108
Test name
Test status
Simulation time 561557276 ps
CPU time 5.02 seconds
Started Jul 09 07:01:58 PM PDT 24
Finished Jul 09 07:02:04 PM PDT 24
Peak memory 209136 kb
Host smart-d5ac9000-3ab5-45c6-bd0e-47a4a4b24685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844762508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.844762508
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1873631904
Short name T354
Test name
Test status
Simulation time 303575301 ps
CPU time 7.36 seconds
Started Jul 09 07:01:57 PM PDT 24
Finished Jul 09 07:02:05 PM PDT 24
Peak memory 222512 kb
Host smart-0d1e4c33-326e-4443-aacc-9ff963887467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873631904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1873631904
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3952959506
Short name T219
Test name
Test status
Simulation time 109431790 ps
CPU time 2.23 seconds
Started Jul 09 07:01:55 PM PDT 24
Finished Jul 09 07:01:59 PM PDT 24
Peak memory 208780 kb
Host smart-e8b1972a-9a4a-43ee-a40b-f6ae9c46798c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952959506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3952959506
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1617948199
Short name T303
Test name
Test status
Simulation time 761667926 ps
CPU time 6.41 seconds
Started Jul 09 07:02:00 PM PDT 24
Finished Jul 09 07:02:09 PM PDT 24
Peak memory 218152 kb
Host smart-3f172e76-2082-4e2c-8327-d3949e9c1d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617948199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1617948199
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.71997358
Short name T367
Test name
Test status
Simulation time 34090156 ps
CPU time 2.52 seconds
Started Jul 09 07:02:00 PM PDT 24
Finished Jul 09 07:02:05 PM PDT 24
Peak memory 208952 kb
Host smart-bb6c7425-27f5-4058-922e-38ba1c958437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71997358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.71997358
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.4055970463
Short name T330
Test name
Test status
Simulation time 327816110 ps
CPU time 3.39 seconds
Started Jul 09 07:01:57 PM PDT 24
Finished Jul 09 07:02:02 PM PDT 24
Peak memory 208716 kb
Host smart-8d89462d-03b8-408b-9a0f-ee91ec5dd286
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055970463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.4055970463
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.528957936
Short name T346
Test name
Test status
Simulation time 1548503669 ps
CPU time 7.35 seconds
Started Jul 09 07:01:57 PM PDT 24
Finished Jul 09 07:02:06 PM PDT 24
Peak memory 208924 kb
Host smart-4bfa71ad-ed67-495d-8fb0-78a362752a61
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528957936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.528957936
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2409305970
Short name T215
Test name
Test status
Simulation time 180594487 ps
CPU time 6.64 seconds
Started Jul 09 07:01:58 PM PDT 24
Finished Jul 09 07:02:06 PM PDT 24
Peak memory 207916 kb
Host smart-f7af6167-0795-495f-bed7-7b85d749beae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409305970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2409305970
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.55428776
Short name T247
Test name
Test status
Simulation time 45367987 ps
CPU time 2.86 seconds
Started Jul 09 07:02:06 PM PDT 24
Finished Jul 09 07:02:13 PM PDT 24
Peak memory 214344 kb
Host smart-067cbd52-46b8-4094-ab74-72e958b5d0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55428776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.55428776
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.105453939
Short name T765
Test name
Test status
Simulation time 448712717 ps
CPU time 3.31 seconds
Started Jul 09 07:02:01 PM PDT 24
Finished Jul 09 07:02:07 PM PDT 24
Peak memory 208576 kb
Host smart-618cc2dd-81dd-44c4-81a0-6a602b1df4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105453939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.105453939
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.831790398
Short name T234
Test name
Test status
Simulation time 549654509 ps
CPU time 26.15 seconds
Started Jul 09 07:01:59 PM PDT 24
Finished Jul 09 07:02:28 PM PDT 24
Peak memory 215148 kb
Host smart-666ee3d3-1375-44c3-b0f6-e090fda30fb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831790398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.831790398
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.3788710531
Short name T734
Test name
Test status
Simulation time 2186045702 ps
CPU time 17.63 seconds
Started Jul 09 07:01:59 PM PDT 24
Finished Jul 09 07:02:18 PM PDT 24
Peak memory 222624 kb
Host smart-4a9b3d06-b980-4d13-8130-6c56f017c180
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788710531 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.3788710531
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1765489459
Short name T563
Test name
Test status
Simulation time 539777040 ps
CPU time 5.86 seconds
Started Jul 09 07:01:55 PM PDT 24
Finished Jul 09 07:02:03 PM PDT 24
Peak memory 207688 kb
Host smart-fbd4535b-862d-4bed-a1e4-f2a510260b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765489459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1765489459
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2319654318
Short name T773
Test name
Test status
Simulation time 53884854 ps
CPU time 0.88 seconds
Started Jul 09 07:02:06 PM PDT 24
Finished Jul 09 07:02:12 PM PDT 24
Peak memory 205920 kb
Host smart-bd29c288-abd0-4b99-950c-9f4f982aad11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319654318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2319654318
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2662816407
Short name T19
Test name
Test status
Simulation time 88200363 ps
CPU time 3.1 seconds
Started Jul 09 07:02:02 PM PDT 24
Finished Jul 09 07:02:07 PM PDT 24
Peak memory 222876 kb
Host smart-d4f4867f-600b-48c4-b7e4-d7e619744b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662816407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2662816407
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.4233252548
Short name T407
Test name
Test status
Simulation time 34088557 ps
CPU time 1.59 seconds
Started Jul 09 07:02:02 PM PDT 24
Finished Jul 09 07:02:06 PM PDT 24
Peak memory 207064 kb
Host smart-ae4f052a-b365-43f9-a1a5-226f2c738af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233252548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.4233252548
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.481372752
Short name T321
Test name
Test status
Simulation time 229501177 ps
CPU time 5.93 seconds
Started Jul 09 07:02:03 PM PDT 24
Finished Jul 09 07:02:12 PM PDT 24
Peak memory 218656 kb
Host smart-043de667-7fa9-4f88-af2b-f0dea0c198f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481372752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.481372752
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3724417571
Short name T337
Test name
Test status
Simulation time 204907202 ps
CPU time 2.36 seconds
Started Jul 09 07:02:00 PM PDT 24
Finished Jul 09 07:02:06 PM PDT 24
Peak memory 222436 kb
Host smart-d6ee04b7-4c8e-47ed-b54e-6bb7665097be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724417571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3724417571
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_random.1106614024
Short name T523
Test name
Test status
Simulation time 2905936369 ps
CPU time 16.16 seconds
Started Jul 09 07:01:59 PM PDT 24
Finished Jul 09 07:02:18 PM PDT 24
Peak memory 208220 kb
Host smart-031d09d5-8b08-4d52-923d-4d3a8ce1db3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106614024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1106614024
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.4094912702
Short name T849
Test name
Test status
Simulation time 171271364 ps
CPU time 5.75 seconds
Started Jul 09 07:02:01 PM PDT 24
Finished Jul 09 07:02:09 PM PDT 24
Peak memory 208916 kb
Host smart-4e8589d0-27a6-4e95-bf58-150a9d15ac6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094912702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.4094912702
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3845780929
Short name T385
Test name
Test status
Simulation time 1110636578 ps
CPU time 6.04 seconds
Started Jul 09 07:02:04 PM PDT 24
Finished Jul 09 07:02:14 PM PDT 24
Peak memory 208056 kb
Host smart-1b2a45e7-2014-427b-8b6d-7fceffd3e592
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845780929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3845780929
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2086193878
Short name T620
Test name
Test status
Simulation time 71418324 ps
CPU time 3.03 seconds
Started Jul 09 07:02:01 PM PDT 24
Finished Jul 09 07:02:07 PM PDT 24
Peak memory 208148 kb
Host smart-b607e1f4-2d78-41b2-a9b3-da031f663b38
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086193878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2086193878
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1810280982
Short name T359
Test name
Test status
Simulation time 305014563 ps
CPU time 5.36 seconds
Started Jul 09 07:02:05 PM PDT 24
Finished Jul 09 07:02:15 PM PDT 24
Peak memory 208664 kb
Host smart-b4bb73b4-38fe-4b04-a9be-fcc5414a4c43
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810280982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1810280982
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.984732703
Short name T713
Test name
Test status
Simulation time 106273926 ps
CPU time 2.76 seconds
Started Jul 09 07:02:00 PM PDT 24
Finished Jul 09 07:02:05 PM PDT 24
Peak memory 209532 kb
Host smart-2042944f-42d2-408c-97ac-fba9c8a17633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984732703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.984732703
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3778449754
Short name T438
Test name
Test status
Simulation time 497106860 ps
CPU time 2.62 seconds
Started Jul 09 07:02:03 PM PDT 24
Finished Jul 09 07:02:07 PM PDT 24
Peak memory 208708 kb
Host smart-5f1d538c-009e-4a30-8986-c4ee61b95102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778449754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3778449754
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.3643350774
Short name T140
Test name
Test status
Simulation time 1823168772 ps
CPU time 13.04 seconds
Started Jul 09 07:02:06 PM PDT 24
Finished Jul 09 07:02:24 PM PDT 24
Peak memory 222512 kb
Host smart-50829aea-78b2-4dae-8e43-7a7b2ecd1117
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643350774 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.3643350774
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.4050575778
Short name T324
Test name
Test status
Simulation time 551139951 ps
CPU time 5.19 seconds
Started Jul 09 07:02:06 PM PDT 24
Finished Jul 09 07:02:17 PM PDT 24
Peak memory 208288 kb
Host smart-30b8ec4e-9753-4f5e-8f25-7f7f4d3df7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050575778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.4050575778
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3644762676
Short name T175
Test name
Test status
Simulation time 404239609 ps
CPU time 2.9 seconds
Started Jul 09 07:02:04 PM PDT 24
Finished Jul 09 07:02:10 PM PDT 24
Peak memory 210488 kb
Host smart-0b09c16f-0124-4af6-a5f0-3ce135bf1aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644762676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3644762676
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.616814838
Short name T679
Test name
Test status
Simulation time 147220531 ps
CPU time 0.92 seconds
Started Jul 09 07:02:00 PM PDT 24
Finished Jul 09 07:02:04 PM PDT 24
Peak memory 205948 kb
Host smart-982cbf65-9ea0-4201-965f-b674f38b797b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616814838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.616814838
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3356150914
Short name T428
Test name
Test status
Simulation time 170578131 ps
CPU time 8.91 seconds
Started Jul 09 07:01:59 PM PDT 24
Finished Jul 09 07:02:10 PM PDT 24
Peak memory 214332 kb
Host smart-2d9c21a3-a704-478f-94e9-24eb6312b026
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3356150914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3356150914
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2021017540
Short name T916
Test name
Test status
Simulation time 64137960 ps
CPU time 2.89 seconds
Started Jul 09 07:02:03 PM PDT 24
Finished Jul 09 07:02:09 PM PDT 24
Peak memory 214396 kb
Host smart-06ef00da-9928-4d56-8ff6-55fb10941f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021017540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2021017540
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.129052650
Short name T86
Test name
Test status
Simulation time 90242365 ps
CPU time 3.67 seconds
Started Jul 09 07:02:03 PM PDT 24
Finished Jul 09 07:02:10 PM PDT 24
Peak memory 207528 kb
Host smart-d523a6e1-cb51-4b22-9a78-d40fb048fc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129052650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.129052650
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.928625464
Short name T107
Test name
Test status
Simulation time 120925978 ps
CPU time 4.87 seconds
Started Jul 09 07:02:00 PM PDT 24
Finished Jul 09 07:02:08 PM PDT 24
Peak memory 214264 kb
Host smart-77c96b25-4420-45e0-9e1b-7eab5f69a417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928625464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.928625464
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.991124431
Short name T391
Test name
Test status
Simulation time 79946076 ps
CPU time 3.1 seconds
Started Jul 09 07:02:02 PM PDT 24
Finished Jul 09 07:02:07 PM PDT 24
Peak memory 222360 kb
Host smart-840ed109-f0e4-4d57-b046-6c75d518a08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991124431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.991124431
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.4207422967
Short name T670
Test name
Test status
Simulation time 118391293 ps
CPU time 4.08 seconds
Started Jul 09 07:02:05 PM PDT 24
Finished Jul 09 07:02:12 PM PDT 24
Peak memory 214260 kb
Host smart-cd975265-4838-4133-a2fe-0396d5699294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207422967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.4207422967
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1432783258
Short name T332
Test name
Test status
Simulation time 7792293152 ps
CPU time 47.62 seconds
Started Jul 09 07:02:02 PM PDT 24
Finished Jul 09 07:02:52 PM PDT 24
Peak memory 208108 kb
Host smart-c2392efc-1287-440a-8c58-1cacf0e90a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432783258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1432783258
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2961439166
Short name T473
Test name
Test status
Simulation time 74239390 ps
CPU time 1.9 seconds
Started Jul 09 07:02:06 PM PDT 24
Finished Jul 09 07:02:12 PM PDT 24
Peak memory 207392 kb
Host smart-c53a454d-68f3-4a95-9ae6-d347b04bc4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961439166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2961439166
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.4254791260
Short name T477
Test name
Test status
Simulation time 364029121 ps
CPU time 1.84 seconds
Started Jul 09 07:02:05 PM PDT 24
Finished Jul 09 07:02:10 PM PDT 24
Peak memory 206928 kb
Host smart-0c1e52ab-2eac-47d8-a467-f9ead65ddf24
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254791260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.4254791260
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1279547417
Short name T2
Test name
Test status
Simulation time 133032517 ps
CPU time 4.2 seconds
Started Jul 09 07:02:00 PM PDT 24
Finished Jul 09 07:02:08 PM PDT 24
Peak memory 207944 kb
Host smart-293da56b-7ee2-4a55-9035-53713f372bb1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279547417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1279547417
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1239905905
Short name T526
Test name
Test status
Simulation time 339846894 ps
CPU time 3.08 seconds
Started Jul 09 07:02:03 PM PDT 24
Finished Jul 09 07:02:08 PM PDT 24
Peak memory 208904 kb
Host smart-8b2ae9ec-ef29-4053-a38a-33c79172ed1f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239905905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1239905905
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2043123343
Short name T285
Test name
Test status
Simulation time 483027202 ps
CPU time 4.36 seconds
Started Jul 09 07:02:04 PM PDT 24
Finished Jul 09 07:02:12 PM PDT 24
Peak memory 214280 kb
Host smart-fc592728-9118-4c06-b151-96087f87eef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043123343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2043123343
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1961911834
Short name T745
Test name
Test status
Simulation time 397786586 ps
CPU time 7.66 seconds
Started Jul 09 07:02:03 PM PDT 24
Finished Jul 09 07:02:14 PM PDT 24
Peak memory 206844 kb
Host smart-33bd3583-429d-46a4-8caf-3fdb62cac024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961911834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1961911834
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1718651354
Short name T290
Test name
Test status
Simulation time 553648054 ps
CPU time 4.3 seconds
Started Jul 09 07:02:04 PM PDT 24
Finished Jul 09 07:02:11 PM PDT 24
Peak memory 207468 kb
Host smart-c6697b3c-c88f-4fef-bc33-dab4c56dff60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718651354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1718651354
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2451172165
Short name T203
Test name
Test status
Simulation time 1874738501 ps
CPU time 12.93 seconds
Started Jul 09 07:02:05 PM PDT 24
Finished Jul 09 07:02:22 PM PDT 24
Peak memory 214300 kb
Host smart-e2b716b1-d433-4d65-b085-393d3f1c0744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451172165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2451172165
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.544806702
Short name T410
Test name
Test status
Simulation time 48508842 ps
CPU time 1.58 seconds
Started Jul 09 07:02:06 PM PDT 24
Finished Jul 09 07:02:13 PM PDT 24
Peak memory 209644 kb
Host smart-3a52b3c8-07f5-46e2-afdd-b08731d12549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544806702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.544806702
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2823643147
Short name T625
Test name
Test status
Simulation time 10809802 ps
CPU time 0.85 seconds
Started Jul 09 07:02:07 PM PDT 24
Finished Jul 09 07:02:13 PM PDT 24
Peak memory 206000 kb
Host smart-2c1bc1d1-9f96-4bc4-a604-6aec769ca71a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823643147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2823643147
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2659161343
Short name T400
Test name
Test status
Simulation time 52433311 ps
CPU time 4.29 seconds
Started Jul 09 07:02:09 PM PDT 24
Finished Jul 09 07:02:19 PM PDT 24
Peak memory 215276 kb
Host smart-fc94db78-8540-4766-8266-12f2d79a9c1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2659161343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2659161343
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.4031205923
Short name T267
Test name
Test status
Simulation time 147983915 ps
CPU time 4.36 seconds
Started Jul 09 07:02:08 PM PDT 24
Finished Jul 09 07:02:17 PM PDT 24
Peak memory 208928 kb
Host smart-a085a4d7-289b-4004-ade1-aa5bc0bfbdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031205923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.4031205923
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3673716392
Short name T551
Test name
Test status
Simulation time 214228572 ps
CPU time 3.73 seconds
Started Jul 09 07:02:05 PM PDT 24
Finished Jul 09 07:02:14 PM PDT 24
Peak memory 214428 kb
Host smart-9daed257-4c55-4f04-b3c1-2f2af1373042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673716392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3673716392
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1816397883
Short name T861
Test name
Test status
Simulation time 381119282 ps
CPU time 3.15 seconds
Started Jul 09 07:02:06 PM PDT 24
Finished Jul 09 07:02:14 PM PDT 24
Peak memory 219932 kb
Host smart-d11b39a6-8b69-462c-97db-d2f34ac373a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816397883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1816397883
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.753610551
Short name T578
Test name
Test status
Simulation time 2431026540 ps
CPU time 6.9 seconds
Started Jul 09 07:02:06 PM PDT 24
Finished Jul 09 07:02:17 PM PDT 24
Peak memory 209300 kb
Host smart-d63e3355-5154-4d90-8c9c-7a7facaeaba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753610551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.753610551
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1701736491
Short name T876
Test name
Test status
Simulation time 634024402 ps
CPU time 7.35 seconds
Started Jul 09 07:02:08 PM PDT 24
Finished Jul 09 07:02:21 PM PDT 24
Peak memory 206960 kb
Host smart-b5b814d7-3820-4349-b540-47e4d772b48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701736491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1701736491
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.34865516
Short name T95
Test name
Test status
Simulation time 161471556 ps
CPU time 5.23 seconds
Started Jul 09 07:02:14 PM PDT 24
Finished Jul 09 07:02:23 PM PDT 24
Peak memory 208444 kb
Host smart-7980ee8b-ced3-40b6-938e-aa59a71b55b9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34865516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.34865516
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1421590681
Short name T887
Test name
Test status
Simulation time 36334002 ps
CPU time 2.53 seconds
Started Jul 09 07:02:12 PM PDT 24
Finished Jul 09 07:02:18 PM PDT 24
Peak memory 208708 kb
Host smart-fae68a30-4b69-4594-a208-11fe6b448752
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421590681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1421590681
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1936414997
Short name T576
Test name
Test status
Simulation time 94569698 ps
CPU time 3.14 seconds
Started Jul 09 07:02:08 PM PDT 24
Finished Jul 09 07:02:16 PM PDT 24
Peak memory 206928 kb
Host smart-dc4886e7-50cd-487d-8708-5ccda9b56e7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936414997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1936414997
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1259269717
Short name T661
Test name
Test status
Simulation time 360318430 ps
CPU time 4.37 seconds
Started Jul 09 07:02:06 PM PDT 24
Finished Jul 09 07:02:16 PM PDT 24
Peak memory 214324 kb
Host smart-04aca2ad-26a7-40f2-ae66-8df1b6284a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259269717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1259269717
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.372420764
Short name T782
Test name
Test status
Simulation time 2010623484 ps
CPU time 18.6 seconds
Started Jul 09 07:02:08 PM PDT 24
Finished Jul 09 07:02:32 PM PDT 24
Peak memory 209000 kb
Host smart-1bde5ffe-fd12-4de1-bfe5-2eb73568a349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372420764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.372420764
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1320156579
Short name T888
Test name
Test status
Simulation time 2211573274 ps
CPU time 12.56 seconds
Started Jul 09 07:02:13 PM PDT 24
Finished Jul 09 07:02:29 PM PDT 24
Peak memory 216548 kb
Host smart-7f4d826e-5bac-4d21-b6d1-91ffa8454458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320156579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1320156579
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.4219176721
Short name T826
Test name
Test status
Simulation time 1055007711 ps
CPU time 6.82 seconds
Started Jul 09 07:02:11 PM PDT 24
Finished Jul 09 07:02:22 PM PDT 24
Peak memory 218552 kb
Host smart-c7028822-ca60-4d92-a59a-38dc1eae2f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219176721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.4219176721
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1553735232
Short name T792
Test name
Test status
Simulation time 444296638 ps
CPU time 7.44 seconds
Started Jul 09 07:02:06 PM PDT 24
Finished Jul 09 07:02:18 PM PDT 24
Peak memory 211180 kb
Host smart-229b65fc-41c0-4174-b3a4-bb9cd99fe0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553735232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1553735232
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2127475537
Short name T694
Test name
Test status
Simulation time 11103121 ps
CPU time 0.87 seconds
Started Jul 09 07:02:16 PM PDT 24
Finished Jul 09 07:02:20 PM PDT 24
Peak memory 206016 kb
Host smart-2276ea3c-4fcb-4dfb-a2da-b28a8f151299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127475537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2127475537
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.18240595
Short name T835
Test name
Test status
Simulation time 2179625074 ps
CPU time 14.37 seconds
Started Jul 09 07:02:12 PM PDT 24
Finished Jul 09 07:02:31 PM PDT 24
Peak memory 209996 kb
Host smart-0539eae2-67bc-4739-b5f5-4a39a85df1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18240595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.18240595
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.306139079
Short name T834
Test name
Test status
Simulation time 1305017655 ps
CPU time 11.48 seconds
Started Jul 09 07:02:07 PM PDT 24
Finished Jul 09 07:02:23 PM PDT 24
Peak memory 222496 kb
Host smart-7b2ab346-9d37-4cf4-b233-c0ad314b76e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306139079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.306139079
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1034806649
Short name T254
Test name
Test status
Simulation time 75454920 ps
CPU time 2.54 seconds
Started Jul 09 07:02:05 PM PDT 24
Finished Jul 09 07:02:12 PM PDT 24
Peak memory 214284 kb
Host smart-806f8479-bedc-4ffe-90f3-0d8ea82c8fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034806649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1034806649
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2091771519
Short name T229
Test name
Test status
Simulation time 46106114 ps
CPU time 3.07 seconds
Started Jul 09 07:02:09 PM PDT 24
Finished Jul 09 07:02:17 PM PDT 24
Peak memory 210120 kb
Host smart-7bb8a61e-f7a4-490a-853c-1dc4f3ae3267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091771519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2091771519
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.607367119
Short name T692
Test name
Test status
Simulation time 1075696539 ps
CPU time 7.04 seconds
Started Jul 09 07:02:08 PM PDT 24
Finished Jul 09 07:02:20 PM PDT 24
Peak memory 208860 kb
Host smart-a94f16c9-f9e4-4bf3-82b3-06ed63f0de5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607367119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.607367119
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2305239511
Short name T344
Test name
Test status
Simulation time 1515594470 ps
CPU time 3.84 seconds
Started Jul 09 07:02:12 PM PDT 24
Finished Jul 09 07:02:20 PM PDT 24
Peak memory 207388 kb
Host smart-c303a4d4-79f4-4547-a584-ebcbeadef6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305239511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2305239511
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.850228524
Short name T360
Test name
Test status
Simulation time 61952913 ps
CPU time 3.02 seconds
Started Jul 09 07:02:13 PM PDT 24
Finished Jul 09 07:02:20 PM PDT 24
Peak memory 208600 kb
Host smart-46376260-e052-41da-a91f-007d7c0afa7e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850228524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.850228524
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1972244675
Short name T375
Test name
Test status
Simulation time 61755920 ps
CPU time 2.96 seconds
Started Jul 09 07:02:12 PM PDT 24
Finished Jul 09 07:02:19 PM PDT 24
Peak memory 206996 kb
Host smart-ef8eff52-1d4e-4d0e-98f8-ec39105edd57
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972244675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1972244675
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2264086328
Short name T425
Test name
Test status
Simulation time 904585852 ps
CPU time 8.75 seconds
Started Jul 09 07:02:15 PM PDT 24
Finished Jul 09 07:02:27 PM PDT 24
Peak memory 209492 kb
Host smart-313e1c2a-ef3f-48e1-9c5c-6b933f4b8fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264086328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2264086328
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1316582024
Short name T446
Test name
Test status
Simulation time 90909555 ps
CPU time 2.32 seconds
Started Jul 09 07:02:10 PM PDT 24
Finished Jul 09 07:02:17 PM PDT 24
Peak memory 208148 kb
Host smart-c0e189fb-9d6b-4546-b2ba-d098e9194844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316582024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1316582024
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.987542956
Short name T678
Test name
Test status
Simulation time 427899695 ps
CPU time 4.31 seconds
Started Jul 09 07:02:07 PM PDT 24
Finished Jul 09 07:02:17 PM PDT 24
Peak memory 208668 kb
Host smart-52cfce91-d012-4413-bfa2-82f27f733d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987542956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.987542956
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2453087940
Short name T120
Test name
Test status
Simulation time 39231550 ps
CPU time 1.8 seconds
Started Jul 09 07:02:13 PM PDT 24
Finished Jul 09 07:02:18 PM PDT 24
Peak memory 209948 kb
Host smart-314e3126-9e1f-40be-9ef2-1492113ab3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453087940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2453087940
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1713686722
Short name T656
Test name
Test status
Simulation time 48884369 ps
CPU time 0.89 seconds
Started Jul 09 07:02:16 PM PDT 24
Finished Jul 09 07:02:20 PM PDT 24
Peak memory 206028 kb
Host smart-1e73e877-5fcc-4941-8cfc-783c742e00bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713686722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1713686722
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3966330525
Short name T417
Test name
Test status
Simulation time 844866526 ps
CPU time 41.26 seconds
Started Jul 09 07:02:15 PM PDT 24
Finished Jul 09 07:03:00 PM PDT 24
Peak memory 215752 kb
Host smart-9ec37f4a-4043-4848-b437-4bf2c5b91221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3966330525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3966330525
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.237848693
Short name T693
Test name
Test status
Simulation time 32155831 ps
CPU time 1.33 seconds
Started Jul 09 07:02:25 PM PDT 24
Finished Jul 09 07:02:28 PM PDT 24
Peak memory 216516 kb
Host smart-a70ff00f-455b-410e-81ea-991150e43822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237848693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.237848693
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1678110607
Short name T272
Test name
Test status
Simulation time 68745818 ps
CPU time 2.24 seconds
Started Jul 09 07:02:11 PM PDT 24
Finished Jul 09 07:02:18 PM PDT 24
Peak memory 208808 kb
Host smart-378bac89-3ad6-493d-ab94-15992f76605a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678110607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1678110607
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3414560928
Short name T760
Test name
Test status
Simulation time 48342742 ps
CPU time 3.09 seconds
Started Jul 09 07:02:13 PM PDT 24
Finished Jul 09 07:02:20 PM PDT 24
Peak memory 214348 kb
Host smart-78c88b19-8099-4e9f-8005-ae4d61bdbbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414560928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3414560928
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.881034120
Short name T863
Test name
Test status
Simulation time 161049012 ps
CPU time 4.12 seconds
Started Jul 09 07:02:16 PM PDT 24
Finished Jul 09 07:02:23 PM PDT 24
Peak memory 214308 kb
Host smart-a8aacb0c-991c-41ac-aec3-09771adfe5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881034120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.881034120
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_random.2278157821
Short name T213
Test name
Test status
Simulation time 1698124749 ps
CPU time 24.96 seconds
Started Jul 09 07:02:19 PM PDT 24
Finished Jul 09 07:02:46 PM PDT 24
Peak memory 209720 kb
Host smart-ed0e52ae-fa63-4049-b7d4-61b301268f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278157821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2278157821
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1317534115
Short name T644
Test name
Test status
Simulation time 181035542 ps
CPU time 5.11 seconds
Started Jul 09 07:02:13 PM PDT 24
Finished Jul 09 07:02:22 PM PDT 24
Peak memory 207888 kb
Host smart-756ed896-8221-442c-9d59-fa1231d17546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317534115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1317534115
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2488413558
Short name T561
Test name
Test status
Simulation time 107662130 ps
CPU time 3.39 seconds
Started Jul 09 07:02:15 PM PDT 24
Finished Jul 09 07:02:22 PM PDT 24
Peak memory 208312 kb
Host smart-96f6c8b2-fed3-4716-8ab1-12714c86dfad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488413558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2488413558
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1450911887
Short name T764
Test name
Test status
Simulation time 73276799 ps
CPU time 2.44 seconds
Started Jul 09 07:02:13 PM PDT 24
Finished Jul 09 07:02:20 PM PDT 24
Peak memory 206948 kb
Host smart-1ad7bba9-feeb-44b9-9485-a4ac732a904a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450911887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1450911887
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.837447120
Short name T455
Test name
Test status
Simulation time 1724329676 ps
CPU time 53.77 seconds
Started Jul 09 07:02:12 PM PDT 24
Finished Jul 09 07:03:10 PM PDT 24
Peak memory 208600 kb
Host smart-12fe1054-bb72-4b4e-b790-1e74eeefcd5a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837447120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.837447120
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1674387969
Short name T752
Test name
Test status
Simulation time 898416634 ps
CPU time 8.1 seconds
Started Jul 09 07:02:15 PM PDT 24
Finished Jul 09 07:02:26 PM PDT 24
Peak memory 209172 kb
Host smart-9b04e4bd-39f4-4360-afef-f3558be2d41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674387969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1674387969
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.4262639328
Short name T542
Test name
Test status
Simulation time 292706432 ps
CPU time 3.26 seconds
Started Jul 09 07:02:14 PM PDT 24
Finished Jul 09 07:02:21 PM PDT 24
Peak memory 208324 kb
Host smart-1aa42822-ec86-4bfa-8ed2-107fdb6e0456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262639328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.4262639328
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2439006531
Short name T819
Test name
Test status
Simulation time 166236443 ps
CPU time 6.99 seconds
Started Jul 09 07:02:11 PM PDT 24
Finished Jul 09 07:02:23 PM PDT 24
Peak memory 215452 kb
Host smart-65bda50f-2784-4953-ad1c-07df9056be36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439006531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2439006531
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3040777444
Short name T292
Test name
Test status
Simulation time 162615402 ps
CPU time 4.49 seconds
Started Jul 09 07:05:07 PM PDT 24
Finished Jul 09 07:05:13 PM PDT 24
Peak memory 209244 kb
Host smart-84266dc5-8bd1-476a-925d-8937ff79222f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040777444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3040777444
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.687491291
Short name T482
Test name
Test status
Simulation time 228474400 ps
CPU time 2 seconds
Started Jul 09 07:02:15 PM PDT 24
Finished Jul 09 07:02:21 PM PDT 24
Peak memory 209988 kb
Host smart-91625d37-26f1-4abf-b431-f34cef6dcc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687491291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.687491291
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.210092142
Short name T141
Test name
Test status
Simulation time 19855993 ps
CPU time 0.85 seconds
Started Jul 09 07:02:15 PM PDT 24
Finished Jul 09 07:02:19 PM PDT 24
Peak memory 206040 kb
Host smart-325fbccb-e931-4a84-b6f1-13ef8d0b9efd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210092142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.210092142
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1702926035
Short name T41
Test name
Test status
Simulation time 131208165 ps
CPU time 3.85 seconds
Started Jul 09 07:02:17 PM PDT 24
Finished Jul 09 07:02:24 PM PDT 24
Peak memory 221060 kb
Host smart-c2dca8d5-9dc5-4f33-9f68-10535227201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702926035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1702926035
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.943292342
Short name T377
Test name
Test status
Simulation time 414964375 ps
CPU time 2.8 seconds
Started Jul 09 07:02:17 PM PDT 24
Finished Jul 09 07:02:23 PM PDT 24
Peak memory 210152 kb
Host smart-daedb3cd-efbe-45ed-a5ab-1b39c4dfb6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943292342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.943292342
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.909684530
Short name T378
Test name
Test status
Simulation time 394301722 ps
CPU time 3.46 seconds
Started Jul 09 07:02:16 PM PDT 24
Finished Jul 09 07:02:22 PM PDT 24
Peak memory 214672 kb
Host smart-88a73a7c-1896-444d-a51d-88be0b2f9912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909684530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.909684530
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1988720503
Short name T583
Test name
Test status
Simulation time 315232424 ps
CPU time 2.72 seconds
Started Jul 09 07:02:20 PM PDT 24
Finished Jul 09 07:02:25 PM PDT 24
Peak memory 214272 kb
Host smart-db64e11a-6123-427e-92d1-017d8381b23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988720503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1988720503
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1251869842
Short name T251
Test name
Test status
Simulation time 203859300 ps
CPU time 3.11 seconds
Started Jul 09 07:02:13 PM PDT 24
Finished Jul 09 07:02:20 PM PDT 24
Peak memory 206908 kb
Host smart-01b1778d-39dc-42db-a8e9-0d1144930314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251869842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1251869842
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.4088281908
Short name T460
Test name
Test status
Simulation time 1778330023 ps
CPU time 60.55 seconds
Started Jul 09 07:02:17 PM PDT 24
Finished Jul 09 07:03:20 PM PDT 24
Peak memory 208256 kb
Host smart-37280276-7745-4667-8227-6e7fc20099ad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088281908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4088281908
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2080626973
Short name T832
Test name
Test status
Simulation time 47792570 ps
CPU time 2.09 seconds
Started Jul 09 07:02:19 PM PDT 24
Finished Jul 09 07:02:24 PM PDT 24
Peak memory 208544 kb
Host smart-7525edec-0bab-47ea-8f39-795750a949c8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080626973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2080626973
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3259094673
Short name T646
Test name
Test status
Simulation time 202364643 ps
CPU time 2.59 seconds
Started Jul 09 07:02:16 PM PDT 24
Finished Jul 09 07:02:22 PM PDT 24
Peak memory 207076 kb
Host smart-8ebe17fc-f972-46cf-97cd-66f41dc6339e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259094673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3259094673
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3862696130
Short name T565
Test name
Test status
Simulation time 610528319 ps
CPU time 2.67 seconds
Started Jul 09 07:02:31 PM PDT 24
Finished Jul 09 07:02:34 PM PDT 24
Peak memory 218136 kb
Host smart-fe3cc4e4-05f4-481b-8ccd-1646ffc4aec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862696130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3862696130
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3907649768
Short name T662
Test name
Test status
Simulation time 306239025 ps
CPU time 3.53 seconds
Started Jul 09 07:02:16 PM PDT 24
Finished Jul 09 07:02:22 PM PDT 24
Peak memory 208644 kb
Host smart-99b36290-c553-4629-a5b8-e4f456a6ee8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907649768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3907649768
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.696000384
Short name T645
Test name
Test status
Simulation time 263881307 ps
CPU time 7.51 seconds
Started Jul 09 07:02:20 PM PDT 24
Finished Jul 09 07:02:29 PM PDT 24
Peak memory 215924 kb
Host smart-6c692b27-cd3a-4b53-9d0f-e4140d73d750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696000384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.696000384
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.75962498
Short name T408
Test name
Test status
Simulation time 572806744 ps
CPU time 9.25 seconds
Started Jul 09 07:02:19 PM PDT 24
Finished Jul 09 07:02:31 PM PDT 24
Peak memory 220964 kb
Host smart-792908a2-5823-48b7-8179-4e52b394d792
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75962498 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.75962498
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1059334683
Short name T843
Test name
Test status
Simulation time 86493551 ps
CPU time 4.31 seconds
Started Jul 09 07:02:22 PM PDT 24
Finished Jul 09 07:02:28 PM PDT 24
Peak memory 209184 kb
Host smart-f3d6834e-2093-4728-a72d-891023823f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059334683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1059334683
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3744596258
Short name T396
Test name
Test status
Simulation time 125975296 ps
CPU time 2.85 seconds
Started Jul 09 07:02:27 PM PDT 24
Finished Jul 09 07:02:30 PM PDT 24
Peak memory 210224 kb
Host smart-ad0c35e0-5eaa-4d6e-9a8c-cdb4b703714a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744596258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3744596258
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.4009855529
Short name T838
Test name
Test status
Simulation time 19328110 ps
CPU time 0.84 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:03 PM PDT 24
Peak memory 206004 kb
Host smart-cab64116-b0a1-4330-bdbe-4845af528211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009855529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.4009855529
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2713520724
Short name T403
Test name
Test status
Simulation time 128638567 ps
CPU time 2.95 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:10 PM PDT 24
Peak memory 222524 kb
Host smart-0ad893a6-bda7-4c87-9668-d7d393496c81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713520724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2713520724
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2643460314
Short name T690
Test name
Test status
Simulation time 230915452 ps
CPU time 2.72 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:04 PM PDT 24
Peak memory 214344 kb
Host smart-0ffa70d4-35a3-4604-a57f-87259854328b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643460314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2643460314
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1938740036
Short name T883
Test name
Test status
Simulation time 590652524 ps
CPU time 7.6 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:09 PM PDT 24
Peak memory 214340 kb
Host smart-c1e7716e-9d85-47ca-88a9-1cf97ea54ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938740036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1938740036
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3158586707
Short name T54
Test name
Test status
Simulation time 70340821 ps
CPU time 1.84 seconds
Started Jul 09 06:59:59 PM PDT 24
Finished Jul 09 07:00:01 PM PDT 24
Peak memory 214300 kb
Host smart-ec567aa9-52f2-4f0b-aa84-9d4ffa4e0323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158586707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3158586707
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3363074378
Short name T776
Test name
Test status
Simulation time 94209203 ps
CPU time 2.41 seconds
Started Jul 09 07:00:03 PM PDT 24
Finished Jul 09 07:00:07 PM PDT 24
Peak memory 209364 kb
Host smart-d8aae384-46db-47d4-b9c3-b7a34b44006c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363074378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3363074378
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.625225280
Short name T905
Test name
Test status
Simulation time 1590520532 ps
CPU time 8.01 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:10 PM PDT 24
Peak memory 209884 kb
Host smart-4ec121d9-7a00-4c8f-8bfe-612739ac1129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625225280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.625225280
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.294637244
Short name T564
Test name
Test status
Simulation time 211964695 ps
CPU time 2.81 seconds
Started Jul 09 07:00:01 PM PDT 24
Finished Jul 09 07:00:06 PM PDT 24
Peak memory 206928 kb
Host smart-1befdeae-bd1a-4861-81b1-9143a7c69a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294637244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.294637244
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3187785772
Short name T411
Test name
Test status
Simulation time 103853499 ps
CPU time 2.91 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:11 PM PDT 24
Peak memory 207940 kb
Host smart-8478468b-ab9e-4d5e-81f8-f25a279d7ee6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187785772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3187785772
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3288353685
Short name T261
Test name
Test status
Simulation time 151493858 ps
CPU time 4.31 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:07 PM PDT 24
Peak memory 208624 kb
Host smart-4eb8cb11-fe4b-4ef1-9a40-d6515dbbb091
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288353685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3288353685
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3343683283
Short name T643
Test name
Test status
Simulation time 414144266 ps
CPU time 3.53 seconds
Started Jul 09 07:00:01 PM PDT 24
Finished Jul 09 07:00:07 PM PDT 24
Peak memory 207972 kb
Host smart-dac2dcfd-fd21-459a-8eb4-a5877508fbcd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343683283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3343683283
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1807603605
Short name T259
Test name
Test status
Simulation time 739187725 ps
CPU time 4.71 seconds
Started Jul 09 07:00:02 PM PDT 24
Finished Jul 09 07:00:09 PM PDT 24
Peak memory 214272 kb
Host smart-494f327b-05cb-42df-819e-719adc0564d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807603605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1807603605
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3471464247
Short name T848
Test name
Test status
Simulation time 71525351 ps
CPU time 3.15 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:06 PM PDT 24
Peak memory 207376 kb
Host smart-56eefe7f-a335-4e14-a572-8d4737e96e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471464247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3471464247
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.276306672
Short name T384
Test name
Test status
Simulation time 1245211839 ps
CPU time 20.56 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:23 PM PDT 24
Peak memory 222504 kb
Host smart-1085ff4f-b9eb-43ca-9549-b1765bcec3d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276306672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.276306672
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2286986448
Short name T348
Test name
Test status
Simulation time 295699631 ps
CPU time 7.76 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:15 PM PDT 24
Peak memory 219576 kb
Host smart-9ad98e79-94e5-4f7d-bdbd-a0dbf8982c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286986448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2286986448
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1392243864
Short name T621
Test name
Test status
Simulation time 129409300 ps
CPU time 1.97 seconds
Started Jul 09 06:59:59 PM PDT 24
Finished Jul 09 07:00:03 PM PDT 24
Peak memory 209988 kb
Host smart-c83b5f65-efb5-4e56-ace5-e0c9f37c3a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392243864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1392243864
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2364287868
Short name T496
Test name
Test status
Simulation time 14160706 ps
CPU time 0.76 seconds
Started Jul 09 07:00:07 PM PDT 24
Finished Jul 09 07:00:10 PM PDT 24
Peak memory 205996 kb
Host smart-2a1edbec-ed9e-4f04-adad-d1bcce903e83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364287868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2364287868
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2594312586
Short name T245
Test name
Test status
Simulation time 63539317 ps
CPU time 2.67 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:04 PM PDT 24
Peak memory 222576 kb
Host smart-e346885f-5de8-469e-89ca-9a361d271cc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2594312586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2594312586
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.725894230
Short name T806
Test name
Test status
Simulation time 60483086 ps
CPU time 2.74 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:10 PM PDT 24
Peak memory 208752 kb
Host smart-650a73a9-a375-4044-8d3e-74a968577bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725894230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.725894230
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2915254082
Short name T837
Test name
Test status
Simulation time 280562863 ps
CPU time 2.56 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:05 PM PDT 24
Peak memory 214344 kb
Host smart-facf42a3-7dc1-4d15-9994-2cbcb1ba178e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915254082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2915254082
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3479980058
Short name T780
Test name
Test status
Simulation time 31901921 ps
CPU time 2.36 seconds
Started Jul 09 06:59:59 PM PDT 24
Finished Jul 09 07:00:03 PM PDT 24
Peak memory 214264 kb
Host smart-483fe8b4-9f57-489e-b418-2c708b7deefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479980058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3479980058
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2095343846
Short name T560
Test name
Test status
Simulation time 386326086 ps
CPU time 2.9 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:05 PM PDT 24
Peak memory 209372 kb
Host smart-5499705f-5b1c-4bf5-95cd-ff238e021469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095343846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2095343846
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3452083174
Short name T467
Test name
Test status
Simulation time 211455805 ps
CPU time 4.28 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:12 PM PDT 24
Peak memory 218340 kb
Host smart-9f5f6f56-82a4-49cf-9c56-ac3feeaffba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452083174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3452083174
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3350218472
Short name T121
Test name
Test status
Simulation time 106511942 ps
CPU time 4.18 seconds
Started Jul 09 07:00:01 PM PDT 24
Finished Jul 09 07:00:07 PM PDT 24
Peak memory 208680 kb
Host smart-a2badd03-0dba-4de5-bf86-0ae993070ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350218472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3350218472
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3936625798
Short name T779
Test name
Test status
Simulation time 302034468 ps
CPU time 4.12 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:06 PM PDT 24
Peak memory 208716 kb
Host smart-3e89191b-992e-45ca-9ea1-f245a2afb626
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936625798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3936625798
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2684693902
Short name T409
Test name
Test status
Simulation time 721654766 ps
CPU time 5.94 seconds
Started Jul 09 07:00:01 PM PDT 24
Finished Jul 09 07:00:10 PM PDT 24
Peak memory 207832 kb
Host smart-07e9befb-3609-4964-ae8c-88564e4419a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684693902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2684693902
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3963359538
Short name T680
Test name
Test status
Simulation time 60534916 ps
CPU time 2.85 seconds
Started Jul 09 07:00:02 PM PDT 24
Finished Jul 09 07:00:07 PM PDT 24
Peak memory 206904 kb
Host smart-8242cbf0-2f51-442b-9f9b-3dfcf9254bb4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963359538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3963359538
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2331822515
Short name T750
Test name
Test status
Simulation time 72770418 ps
CPU time 3.45 seconds
Started Jul 09 07:00:01 PM PDT 24
Finished Jul 09 07:00:07 PM PDT 24
Peak memory 218224 kb
Host smart-ff758551-2b6b-41be-a51f-4dff6d9119d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331822515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2331822515
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2120758993
Short name T406
Test name
Test status
Simulation time 37768948 ps
CPU time 1.74 seconds
Started Jul 09 06:59:59 PM PDT 24
Finished Jul 09 07:00:03 PM PDT 24
Peak memory 207164 kb
Host smart-433d6f15-5c56-4b3a-9600-9f31312b893d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120758993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2120758993
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.365922646
Short name T228
Test name
Test status
Simulation time 1317215313 ps
CPU time 26.48 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:29 PM PDT 24
Peak memory 222508 kb
Host smart-596db796-63a5-4a3c-a346-36ca5ee06665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365922646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.365922646
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2384161328
Short name T137
Test name
Test status
Simulation time 1324887448 ps
CPU time 22.21 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:30 PM PDT 24
Peak memory 222636 kb
Host smart-06153e22-eefb-4c39-851e-9af8f3bca27e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384161328 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2384161328
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.207207933
Short name T142
Test name
Test status
Simulation time 1061137188 ps
CPU time 12.67 seconds
Started Jul 09 06:59:59 PM PDT 24
Finished Jul 09 07:00:12 PM PDT 24
Peak memory 214336 kb
Host smart-089f27ae-0d58-4379-8fcb-8c6346baf56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207207933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.207207933
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4260504766
Short name T818
Test name
Test status
Simulation time 159709836 ps
CPU time 4.58 seconds
Started Jul 09 07:00:00 PM PDT 24
Finished Jul 09 07:00:07 PM PDT 24
Peak memory 210576 kb
Host smart-efef756b-a624-4810-97ae-b197323ae4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260504766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4260504766
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1464923501
Short name T587
Test name
Test status
Simulation time 17898550 ps
CPU time 0.84 seconds
Started Jul 09 07:00:08 PM PDT 24
Finished Jul 09 07:00:12 PM PDT 24
Peak memory 205952 kb
Host smart-f1286d59-3d96-4ef5-babd-f23e5280bdfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464923501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1464923501
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2236760824
Short name T630
Test name
Test status
Simulation time 79803264 ps
CPU time 2.35 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:09 PM PDT 24
Peak memory 208788 kb
Host smart-ea42ff24-bd4b-486e-8181-19c78dcd2080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236760824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2236760824
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3053938265
Short name T767
Test name
Test status
Simulation time 568902744 ps
CPU time 2.46 seconds
Started Jul 09 07:00:14 PM PDT 24
Finished Jul 09 07:00:20 PM PDT 24
Peak memory 214308 kb
Host smart-16ef8005-36a0-4225-a1ab-88268676d77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053938265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3053938265
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1386238311
Short name T340
Test name
Test status
Simulation time 112090991 ps
CPU time 4.49 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:12 PM PDT 24
Peak memory 222468 kb
Host smart-e2a5d9aa-fa2d-4000-ade6-fd751ca6cbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386238311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1386238311
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1363223661
Short name T515
Test name
Test status
Simulation time 50925534 ps
CPU time 3.09 seconds
Started Jul 09 07:00:07 PM PDT 24
Finished Jul 09 07:00:13 PM PDT 24
Peak memory 218604 kb
Host smart-ce7c57c4-f1fb-4a94-b588-ce0167790c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363223661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1363223661
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1918277857
Short name T781
Test name
Test status
Simulation time 1253354940 ps
CPU time 8.38 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:15 PM PDT 24
Peak memory 209552 kb
Host smart-1b9d3c10-972c-45d0-94c8-1c79d977bab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918277857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1918277857
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1555166654
Short name T549
Test name
Test status
Simulation time 732282931 ps
CPU time 6.71 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:14 PM PDT 24
Peak memory 208676 kb
Host smart-dda910cb-4850-4517-8c60-569d89b5200b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555166654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1555166654
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3983082639
Short name T884
Test name
Test status
Simulation time 304492163 ps
CPU time 4.89 seconds
Started Jul 09 07:00:06 PM PDT 24
Finished Jul 09 07:00:13 PM PDT 24
Peak memory 207988 kb
Host smart-140a163e-dd62-4523-b39f-8422792ef60f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983082639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3983082639
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1916943873
Short name T500
Test name
Test status
Simulation time 48108269 ps
CPU time 1.88 seconds
Started Jul 09 07:00:08 PM PDT 24
Finished Jul 09 07:00:13 PM PDT 24
Peak memory 206864 kb
Host smart-8b82a09c-3903-435d-b0d0-be01994188f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916943873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1916943873
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3455918897
Short name T600
Test name
Test status
Simulation time 592452836 ps
CPU time 6.47 seconds
Started Jul 09 07:00:04 PM PDT 24
Finished Jul 09 07:00:12 PM PDT 24
Peak memory 208184 kb
Host smart-107f9dfc-e0d4-4a82-be42-5e2a142e4150
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455918897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3455918897
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1249690764
Short name T648
Test name
Test status
Simulation time 190235428 ps
CPU time 2.85 seconds
Started Jul 09 07:00:14 PM PDT 24
Finished Jul 09 07:00:20 PM PDT 24
Peak memory 214300 kb
Host smart-111b58a4-75fd-4cfd-ad9f-4a2f6ae0b986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249690764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1249690764
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1328709745
Short name T439
Test name
Test status
Simulation time 73035072 ps
CPU time 3.01 seconds
Started Jul 09 07:00:07 PM PDT 24
Finished Jul 09 07:00:13 PM PDT 24
Peak memory 207912 kb
Host smart-641ca0b0-f5d9-4f8f-a195-2a81d1f4691c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328709745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1328709745
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2559803522
Short name T829
Test name
Test status
Simulation time 768176447 ps
CPU time 3.39 seconds
Started Jul 09 07:00:08 PM PDT 24
Finished Jul 09 07:00:15 PM PDT 24
Peak memory 208448 kb
Host smart-277a23c5-ad69-4b92-a7f8-fd8ca15f0ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559803522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2559803522
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1875065541
Short name T804
Test name
Test status
Simulation time 86199390 ps
CPU time 1.97 seconds
Started Jul 09 07:00:10 PM PDT 24
Finished Jul 09 07:00:14 PM PDT 24
Peak memory 209928 kb
Host smart-e68bfb85-803b-49ba-a5b8-f9bc028b754d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875065541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1875065541
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3414917545
Short name T840
Test name
Test status
Simulation time 49325959 ps
CPU time 0.75 seconds
Started Jul 09 07:00:12 PM PDT 24
Finished Jul 09 07:00:15 PM PDT 24
Peak memory 205936 kb
Host smart-7362f513-bd3f-42cb-8269-68ee99aecc25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414917545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3414917545
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.181882078
Short name T769
Test name
Test status
Simulation time 217827582 ps
CPU time 3.75 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:00:22 PM PDT 24
Peak memory 214260 kb
Host smart-df95a42e-ec56-4fe9-97b2-561ee637a71a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=181882078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.181882078
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.4102462083
Short name T592
Test name
Test status
Simulation time 250614278 ps
CPU time 6.43 seconds
Started Jul 09 07:00:15 PM PDT 24
Finished Jul 09 07:00:25 PM PDT 24
Peak memory 210556 kb
Host smart-da74917a-a8e5-41db-93b2-6f47c5a3e279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102462083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.4102462083
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1521399147
Short name T15
Test name
Test status
Simulation time 72012133 ps
CPU time 2.03 seconds
Started Jul 09 07:00:09 PM PDT 24
Finished Jul 09 07:00:13 PM PDT 24
Peak memory 207392 kb
Host smart-f3f1aead-2ba1-40b5-96a1-f28a3aa161db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521399147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1521399147
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.4070516598
Short name T112
Test name
Test status
Simulation time 284785756 ps
CPU time 3.9 seconds
Started Jul 09 07:00:04 PM PDT 24
Finished Jul 09 07:00:10 PM PDT 24
Peak memory 209312 kb
Host smart-2d1a97d9-77ed-4c7a-bd25-d7702fde165d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070516598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.4070516598
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2699086366
Short name T298
Test name
Test status
Simulation time 82971311 ps
CPU time 3.27 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:10 PM PDT 24
Peak memory 214236 kb
Host smart-dc93da85-015a-41b5-b873-0bac443f6c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699086366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2699086366
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3344031208
Short name T607
Test name
Test status
Simulation time 287791034 ps
CPU time 4.11 seconds
Started Jul 09 07:00:14 PM PDT 24
Finished Jul 09 07:00:21 PM PDT 24
Peak memory 218908 kb
Host smart-135023c0-b91f-4fab-ae23-bdc730066c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344031208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3344031208
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2766889581
Short name T798
Test name
Test status
Simulation time 184551504 ps
CPU time 5.57 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:14 PM PDT 24
Peak memory 207876 kb
Host smart-a02ef6d6-d35d-4c2e-9522-9531fecf2adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766889581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2766889581
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.998092946
Short name T358
Test name
Test status
Simulation time 852323415 ps
CPU time 29.17 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:37 PM PDT 24
Peak memory 209004 kb
Host smart-ba0b08a9-2c7a-420c-962e-6329cab5eb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998092946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.998092946
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3859885626
Short name T286
Test name
Test status
Simulation time 244477033 ps
CPU time 3.39 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:11 PM PDT 24
Peak memory 208904 kb
Host smart-b1262c45-c364-496c-8f5b-2849548b8c44
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859885626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3859885626
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3490143143
Short name T653
Test name
Test status
Simulation time 521629701 ps
CPU time 6.78 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:15 PM PDT 24
Peak memory 208680 kb
Host smart-aabf38eb-36c7-4d98-b683-2c217ec05a03
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490143143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3490143143
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1878894957
Short name T628
Test name
Test status
Simulation time 157721990 ps
CPU time 3.51 seconds
Started Jul 09 07:00:08 PM PDT 24
Finished Jul 09 07:00:14 PM PDT 24
Peak memory 208576 kb
Host smart-201df860-0e8b-4f9b-a4e6-a68ae6c6beba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878894957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1878894957
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.217259174
Short name T540
Test name
Test status
Simulation time 136909699 ps
CPU time 2.36 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:09 PM PDT 24
Peak memory 209028 kb
Host smart-bb7ed289-3cf9-4ddf-a842-98da478d06dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217259174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.217259174
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.555953085
Short name T605
Test name
Test status
Simulation time 396398442 ps
CPU time 5.11 seconds
Started Jul 09 07:00:09 PM PDT 24
Finished Jul 09 07:00:17 PM PDT 24
Peak memory 207720 kb
Host smart-c18655e5-5e7d-4e48-b0ee-b80d9c1c2b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555953085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.555953085
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2767617939
Short name T844
Test name
Test status
Simulation time 325547815 ps
CPU time 12.35 seconds
Started Jul 09 07:00:10 PM PDT 24
Finished Jul 09 07:00:25 PM PDT 24
Peak memory 215112 kb
Host smart-703503b1-e932-4cc6-8fa7-813e612bb46d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767617939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2767617939
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3811349243
Short name T135
Test name
Test status
Simulation time 615839559 ps
CPU time 12.93 seconds
Started Jul 09 07:00:09 PM PDT 24
Finished Jul 09 07:00:25 PM PDT 24
Peak memory 222556 kb
Host smart-c51f90fa-2c5a-46e5-9da2-1cf09cedc914
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811349243 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3811349243
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3032116213
Short name T912
Test name
Test status
Simulation time 373638883 ps
CPU time 4.39 seconds
Started Jul 09 07:00:13 PM PDT 24
Finished Jul 09 07:00:21 PM PDT 24
Peak memory 214340 kb
Host smart-e64845a5-61f6-4fa6-ac21-727b23b2d393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032116213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3032116213
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2150847126
Short name T626
Test name
Test status
Simulation time 33969959 ps
CPU time 1.76 seconds
Started Jul 09 07:00:05 PM PDT 24
Finished Jul 09 07:00:08 PM PDT 24
Peak memory 209876 kb
Host smart-1426d4c3-3407-44ac-9bc9-b46721205ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150847126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2150847126
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1604602882
Short name T92
Test name
Test status
Simulation time 12357181 ps
CPU time 0.74 seconds
Started Jul 09 07:00:19 PM PDT 24
Finished Jul 09 07:00:24 PM PDT 24
Peak memory 206008 kb
Host smart-fa3167b3-70b4-460d-8d21-2ac41c1941cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604602882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1604602882
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1667602640
Short name T432
Test name
Test status
Simulation time 574463183 ps
CPU time 6.96 seconds
Started Jul 09 07:00:09 PM PDT 24
Finished Jul 09 07:00:18 PM PDT 24
Peak memory 214396 kb
Host smart-aa40e78c-0e37-41a9-9124-9e6fdca998b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1667602640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1667602640
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1936111573
Short name T27
Test name
Test status
Simulation time 46408032 ps
CPU time 2.37 seconds
Started Jul 09 07:00:11 PM PDT 24
Finished Jul 09 07:00:16 PM PDT 24
Peak memory 215880 kb
Host smart-64f7056e-9c58-45f5-8695-022364054195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936111573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1936111573
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.287936733
Short name T659
Test name
Test status
Simulation time 72311096 ps
CPU time 3.24 seconds
Started Jul 09 07:00:21 PM PDT 24
Finished Jul 09 07:00:27 PM PDT 24
Peak memory 208548 kb
Host smart-02e12e77-fd2e-462d-9a21-ab92f8dc6f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287936733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.287936733
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1133057498
Short name T823
Test name
Test status
Simulation time 126643887 ps
CPU time 2.57 seconds
Started Jul 09 07:00:14 PM PDT 24
Finished Jul 09 07:00:20 PM PDT 24
Peak memory 214344 kb
Host smart-75e5eedf-cb1c-41f7-bbcd-76c8d2040f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133057498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1133057498
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2124009036
Short name T867
Test name
Test status
Simulation time 204535155 ps
CPU time 2.78 seconds
Started Jul 09 07:00:12 PM PDT 24
Finished Jul 09 07:00:17 PM PDT 24
Peak memory 214312 kb
Host smart-5dc8b1e6-a16b-4ed3-a195-ee92a446bd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124009036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2124009036
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3584223499
Short name T766
Test name
Test status
Simulation time 123583098 ps
CPU time 3.35 seconds
Started Jul 09 07:00:13 PM PDT 24
Finished Jul 09 07:00:20 PM PDT 24
Peak memory 220408 kb
Host smart-09e6467d-6bad-4bbb-b0ce-41c705918a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584223499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3584223499
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3182530314
Short name T811
Test name
Test status
Simulation time 708852813 ps
CPU time 22.77 seconds
Started Jul 09 07:00:13 PM PDT 24
Finished Jul 09 07:00:39 PM PDT 24
Peak memory 208352 kb
Host smart-1b2633de-3c9d-4abc-b6e5-ae81d3aea8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182530314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3182530314
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1225522344
Short name T881
Test name
Test status
Simulation time 224530187 ps
CPU time 3.35 seconds
Started Jul 09 07:00:13 PM PDT 24
Finished Jul 09 07:00:19 PM PDT 24
Peak memory 208496 kb
Host smart-f909fd1e-94bf-43b8-8d18-cfa1ab30e53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225522344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1225522344
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.512176080
Short name T548
Test name
Test status
Simulation time 51144227 ps
CPU time 2.76 seconds
Started Jul 09 07:00:12 PM PDT 24
Finished Jul 09 07:00:17 PM PDT 24
Peak memory 207052 kb
Host smart-6e463edb-df67-46fc-922a-f76000a895b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512176080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.512176080
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.128884876
Short name T803
Test name
Test status
Simulation time 1210452391 ps
CPU time 12.47 seconds
Started Jul 09 07:00:09 PM PDT 24
Finished Jul 09 07:00:25 PM PDT 24
Peak memory 208092 kb
Host smart-7355d42b-522f-4d8c-a86f-7d443ae66ca7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128884876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.128884876
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3215242622
Short name T688
Test name
Test status
Simulation time 741106863 ps
CPU time 17.44 seconds
Started Jul 09 07:00:19 PM PDT 24
Finished Jul 09 07:00:40 PM PDT 24
Peak memory 207920 kb
Host smart-fe2d0dd7-6a55-4d91-b209-52b56a8fd3cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215242622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3215242622
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1563967523
Short name T405
Test name
Test status
Simulation time 184220021 ps
CPU time 2.47 seconds
Started Jul 09 07:00:09 PM PDT 24
Finished Jul 09 07:00:15 PM PDT 24
Peak memory 209108 kb
Host smart-395732e1-b1d5-4eef-9f70-04d90388399d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563967523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1563967523
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3400586282
Short name T118
Test name
Test status
Simulation time 151739281 ps
CPU time 2.33 seconds
Started Jul 09 07:00:11 PM PDT 24
Finished Jul 09 07:00:16 PM PDT 24
Peak memory 208600 kb
Host smart-ec507db7-9a7e-4a66-8891-b023faa8f315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400586282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3400586282
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1984687710
Short name T667
Test name
Test status
Simulation time 3963294842 ps
CPU time 32.46 seconds
Started Jul 09 07:00:14 PM PDT 24
Finished Jul 09 07:00:49 PM PDT 24
Peak memory 215216 kb
Host smart-b4140e9e-f938-4622-867e-a9ace918502d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984687710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1984687710
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2359847802
Short name T193
Test name
Test status
Simulation time 1076908753 ps
CPU time 10.8 seconds
Started Jul 09 07:00:10 PM PDT 24
Finished Jul 09 07:00:24 PM PDT 24
Peak memory 218596 kb
Host smart-bfe3394b-a8b5-4a0d-b765-7f22787cdd61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359847802 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2359847802
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.4060429123
Short name T434
Test name
Test status
Simulation time 4359541593 ps
CPU time 40.12 seconds
Started Jul 09 07:00:19 PM PDT 24
Finished Jul 09 07:01:03 PM PDT 24
Peak memory 208832 kb
Host smart-40d06c7c-783d-48cd-b8ea-618da49c04d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060429123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.4060429123
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1865021961
Short name T633
Test name
Test status
Simulation time 105527603 ps
CPU time 3.82 seconds
Started Jul 09 07:00:09 PM PDT 24
Finished Jul 09 07:00:15 PM PDT 24
Peak memory 210256 kb
Host smart-74381a41-db84-4fd9-b082-948b388e4627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865021961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1865021961
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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