Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11136

1

T2

4

T4

2

T5

5

auto[Attestation]

7585

1

T2

1

T3

1

T4

6

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2704	1			T6	2		T36	1		T26	4
auto[Aes]	3512	1			T2	2		T6	8		T36	2
auto[Kmac]	3358	1			T2	1		T4	8		T5	8
auto[Otbn]	3363	1			T17	8		T19	8		T36	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7533	1			T2	1		T3	2		T4	8
auto[OpGenId]	5784	1			T2	2		T3	1		T6	11
auto[OpGenSwOut]	5870	1			T2	1		T6	11		T36	5
auto[OpGenHwOut]	7067	1			T2	2		T4	8		T5	8
auto[OpDisable]	130	1			T39	2		T50	1		T54	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10467

1

T2

1

T3

3

T4

8

auto[OpDoneFail]

15917

1

T2

5

T4

8

T5

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6663	1			T2	5		T3	1		T4	1
auto[StInit]	3535	1			T2	1		T3	1		T4	2
auto[StCreatorRootKey]	3168	1			T3	1		T4	2		T5	2
auto[StOwnerIntKey]	2687	1			T4	2		T5	2		T15	2
auto[StOwnerKey]	2454	1			T4	2		T5	2		T15	2
auto[StDisabled]	7877	1			T4	7		T5	7		T15	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	329	1			T6	2		T28	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	89	1			T23	1		T63	1		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	80	1			T28	1		T39	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	62	1			T39	1		T70	1		T9	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	53	1			T39	3		T50	2		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	209	1			T29	1		T39	8		T209	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	368	1			T6	5		T36	2		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	94	1			T23	1		T63	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	75	1			T63	2		T50	3		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	72	1			T50	1		T134	1		T8	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	56	1			T26	1		T68	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	217	1			T6	1		T26	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	354	1			T2	1		T29	4		T42	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	111	1			T41	1		T28	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	92	1			T39	1		T8	1		T70	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	55	1			T26	2		T39	1		T54	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	68	1			T39	2		T47	1		T210	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	196	1			T6	1		T27	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	354	1			T29	1		T20	2		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	82	1			T20	1		T39	1		T58	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	77	1			T50	2		T8	1		T105	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	62	1			T94	1		T158	1		T211	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	63	1			T47	1		T61	1		T51	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	218	1			T26	1		T39	2		T209	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	73	1			T39	1		T50	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	85	1			T41	1		T28	1		T157	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	78	1			T39	1		T63	1		T111	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	70	1			T27	1		T63	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	58	1			T212	1		T143	1		T8	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	227	1			T26	1		T27	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	80	1			T50	3		T59	2		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	103	1			T6	1		T68	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	84	1			T27	1		T43	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	76	1			T26	1		T39	1		T63	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	76	1			T26	1		T209	1		T138	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	205	1			T6	1		T26	1		T39	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	79	1			T50	3		T59	2		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	91	1			T26	1		T27	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	95	1			T36	1		T39	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	59	1			T24	1		T70	1		T61	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	60	1			T36	1		T50	1		T208	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	220	1			T39	1		T50	4		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	73	1			T39	1		T50	1		T59	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	96	1			T36	1		T27	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	81	1			T209	1		T61	2		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T54	1		T143	1		T213	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	63	1			T26	1		T39	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	237	1			T29	1		T39	7		T111	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	314	1			T36	1		T28	3		T29	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	88	1			T28	1		T23	1		T54	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	77	1			T26	1		T68	1		T59	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	54	1			T39	1		T50	1		T105	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	55	1			T214	1		T51	2		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	176	1			T157	1		T23	2		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	572	1			T2	2		T26	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	112	1			T23	3		T38	1		T39	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	115	1			T50	1		T138	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	95	1			T26	1		T29	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	87	1			T39	3		T212	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	290	1			T27	1		T157	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	431	1			T16	14		T29	2		T20	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	108	1			T5	1		T15	1		T114	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	106	1			T15	1		T38	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	94	1			T16	1		T36	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	99	1			T15	1		T16	1		T212	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	273	1			T4	2		T5	4		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	439	1			T28	1		T29	1		T50	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	124	1			T19	1		T26	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	119	1			T17	1		T29	1		T115	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	88	1			T209	1		T50	1		T216	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	74	1			T19	1		T115	1		T216	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	318	1			T17	2		T29	1		T157	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	58	1			T50	2		T59	4		T61	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	89	1			T23	1		T7	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	67	1			T39	1		T54	1		T8	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	58	1			T61	1		T217	1		T218	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	52	1			T219	1		T134	1		T137	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	203	1			T26	2		T27	3		T157	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	47	1			T70	2		T61	2		T127	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	121	1			T23	1		T50	2		T220	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	109	1			T38	3		T50	1		T220	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	100	1			T111	1		T50	1		T220	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	79	1			T23	2		T220	1		T221	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	279	1			T29	2		T157	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	63	1			T50	1		T59	3		T61	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	113	1			T4	1		T16	1		T157	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	105	1			T4	1		T5	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	94	1			T4	1		T5	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	100	1			T4	1		T5	1		T157	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	292	1			T4	2		T15	3		T16	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	48	1			T50	1		T59	1		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	109	1			T17	1		T23	2		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	111	1			T19	1		T39	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	89	1			T17	1		T19	1		T115	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	91	1			T17	1		T23	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	282	1			T17	2		T19	4		T36	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	175	1			T39	5		T50	2		T59	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	647	1			T6	2		T28	2		T29	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	188	1			T68	1		T39	1		T63	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	694	1			T6	6		T36	2		T26	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	196	1			T26	1		T39	4		T54	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	680	1			T2	1		T6	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	189	1			T50	2		T47	1		T8	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	667	1			T26	1		T29	1		T20	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	192	1			T27	1		T39	1		T63	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	399	1			T26	1		T41	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	218	1			T26	2		T27	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	406	1			T6	2		T26	1		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	201	1			T36	2		T39	1		T50	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	403	1			T26	1		T27	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	188	1			T26	1		T39	1		T209	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	427	1			T36	1		T27	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	166	1			T26	1		T68	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	598	1			T36	1		T28	4		T29	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	286	1			T26	1		T29	1		T39	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	985	1			T2	2		T26	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	284	1			T15	2		T16	2		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	827	1			T4	2		T5	5		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	261	1			T17	1		T19	1		T115	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	901	1			T17	2		T19	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	157	1			T39	1		T219	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	370	1			T26	2		T27	3		T157	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	276	1			T23	2		T38	3		T111	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	459	1			T29	2		T157	1		T23	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	281	1			T4	3		T5	3		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	486	1			T4	3		T15	3		T16	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	274	1			T17	2		T19	2		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	456	1			T17	3		T19	4		T36	1