Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32476

1

T2

7

T3

3

T4

21

auto[1]

307

1

T122

4

T158

25

T159

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32482	1			T2	7		T3	3		T4	21
auto[134217728:268435455]	3	1			T416	1		T266	1		T417	1
auto[268435456:402653183]	13	1			T122	1		T158	1		T245	1
auto[402653184:536870911]	8	1			T159	1		T267	1		T418	1
auto[536870912:671088639]	9	1			T159	1		T93	1		T267	1
auto[671088640:805306367]	8	1			T158	1		T93	1		T373	1
auto[805306368:939524095]	13	1			T158	1		T299	1		T146	1
auto[939524096:1073741823]	12	1			T158	1		T93	2		T419	1
auto[1073741824:1207959551]	11	1			T158	2		T418	1		T405	1
auto[1207959552:1342177279]	9	1			T405	1		T416	2		T362	1
auto[1342177280:1476395007]	8	1			T267	1		T416	2		T280	1
auto[1476395008:1610612735]	7	1			T158	1		T146	1		T360	1
auto[1610612736:1744830463]	11	1			T158	1		T93	1		T267	2
auto[1744830464:1879048191]	11	1			T158	1		T144	1		T146	1
auto[1879048192:2013265919]	4	1			T122	1		T405	1		T420	1
auto[2013265920:2147483647]	8	1			T299	1		T146	1		T93	1
auto[2147483648:2281701375]	8	1			T158	1		T144	1		T93	1
auto[2281701376:2415919103]	15	1			T158	1		T146	1		T245	1
auto[2415919104:2550136831]	14	1			T146	1		T93	1		T267	1
auto[2550136832:2684354559]	10	1			T158	1		T266	1		T406	1
auto[2684354560:2818572287]	9	1			T290	1		T373	1		T416	1
auto[2818572288:2952790015]	4	1			T276	1		T421	1		T422	1
auto[2952790016:3087007743]	8	1			T158	1		T159	1		T418	1
auto[3087007744:3221225471]	10	1			T158	1		T290	2		T360	1
auto[3221225472:3355443199]	11	1			T122	1		T158	2		T93	1
auto[3355443200:3489660927]	14	1			T158	1		T159	1		T299	1
auto[3489660928:3623878655]	6	1			T158	1		T290	1		T267	1
auto[3623878656:3758096383]	11	1			T158	1		T299	1		T146	1
auto[3758096384:3892314111]	9	1			T158	1		T90	1		T360	1
auto[3892314112:4026531839]	15	1			T158	3		T146	1		T416	2
auto[4026531840:4160749567]	15	1			T122	1		T158	1		T159	1
auto[4160749568:4294967295]	7	1			T158	1		T299	1		T373	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32476	1			T2	7		T3	3		T4	21
auto[0:134217727]	auto[1]	6	1			T93	1		T247	2		T346	1
auto[134217728:268435455]	auto[1]	3	1			T416	1		T266	1		T417	1
auto[268435456:402653183]	auto[1]	13	1			T122	1		T158	1		T245	1
auto[402653184:536870911]	auto[1]	8	1			T159	1		T267	1		T418	1
auto[536870912:671088639]	auto[1]	9	1			T159	1		T93	1		T267	1
auto[671088640:805306367]	auto[1]	8	1			T158	1		T93	1		T373	1
auto[805306368:939524095]	auto[1]	13	1			T158	1		T299	1		T146	1
auto[939524096:1073741823]	auto[1]	12	1			T158	1		T93	2		T419	1
auto[1073741824:1207959551]	auto[1]	11	1			T158	2		T418	1		T405	1
auto[1207959552:1342177279]	auto[1]	9	1			T405	1		T416	2		T362	1
auto[1342177280:1476395007]	auto[1]	8	1			T267	1		T416	2		T280	1
auto[1476395008:1610612735]	auto[1]	7	1			T158	1		T146	1		T360	1
auto[1610612736:1744830463]	auto[1]	11	1			T158	1		T93	1		T267	2
auto[1744830464:1879048191]	auto[1]	11	1			T158	1		T144	1		T146	1
auto[1879048192:2013265919]	auto[1]	4	1			T122	1		T405	1		T420	1
auto[2013265920:2147483647]	auto[1]	8	1			T299	1		T146	1		T93	1
auto[2147483648:2281701375]	auto[1]	8	1			T158	1		T144	1		T93	1
auto[2281701376:2415919103]	auto[1]	15	1			T158	1		T146	1		T245	1
auto[2415919104:2550136831]	auto[1]	14	1			T146	1		T93	1		T267	1
auto[2550136832:2684354559]	auto[1]	10	1			T158	1		T266	1		T406	1
auto[2684354560:2818572287]	auto[1]	9	1			T290	1		T373	1		T416	1
auto[2818572288:2952790015]	auto[1]	4	1			T276	1		T421	1		T422	1
auto[2952790016:3087007743]	auto[1]	8	1			T158	1		T159	1		T418	1
auto[3087007744:3221225471]	auto[1]	10	1			T158	1		T290	2		T360	1
auto[3221225472:3355443199]	auto[1]	11	1			T122	1		T158	2		T93	1
auto[3355443200:3489660927]	auto[1]	14	1			T158	1		T159	1		T299	1
auto[3489660928:3623878655]	auto[1]	6	1			T158	1		T290	1		T267	1
auto[3623878656:3758096383]	auto[1]	11	1			T158	1		T299	1		T146	1
auto[3758096384:3892314111]	auto[1]	9	1			T158	1		T90	1		T360	1
auto[3892314112:4026531839]	auto[1]	15	1			T158	3		T146	1		T416	2
auto[4026531840:4160749567]	auto[1]	15	1			T122	1		T158	1		T159	1
auto[4160749568:4294967295]	auto[1]	7	1			T158	1		T299	1		T373	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1531

1

T3

2

T18

4

T26

1

auto[1]

1750

1

T2

2

T18

1

T26

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	89	1			T26	1		T29	1		T20	1
auto[134217728:268435455]	105	1			T3	1		T18	1		T157	1
auto[268435456:402653183]	93	1			T18	1		T50	2		T122	1
auto[402653184:536870911]	111	1			T2	1		T23	1		T39	1
auto[536870912:671088639]	99	1			T63	1		T8	1		T274	1
auto[671088640:805306367]	87	1			T39	1		T58	1		T24	1
auto[805306368:939524095]	101	1			T26	1		T39	2		T50	3
auto[939524096:1073741823]	107	1			T26	1		T39	2		T212	1
auto[1073741824:1207959551]	119	1			T3	1		T38	1		T39	1
auto[1207959552:1342177279]	91	1			T68	2		T39	2		T50	1
auto[1342177280:1476395007]	110	1			T28	1		T68	1		T63	1
auto[1476395008:1610612735]	106	1			T42	1		T39	2		T63	1
auto[1610612736:1744830463]	106	1			T113	1		T209	1		T105	1
auto[1744830464:1879048191]	113	1			T50	2		T58	1		T59	1
auto[1879048192:2013265919]	100	1			T39	1		T10	1		T209	1
auto[2013265920:2147483647]	94	1			T157	1		T50	1		T58	1
auto[2147483648:2281701375]	97	1			T18	1		T42	1		T54	1
auto[2281701376:2415919103]	114	1			T28	1		T20	2		T10	1
auto[2415919104:2550136831]	106	1			T18	1		T68	1		T133	1
auto[2550136832:2684354559]	93	1			T68	1		T39	2		T50	2
auto[2684354560:2818572287]	101	1			T28	1		T7	1		T63	1
auto[2818572288:2952790015]	89	1			T18	1		T26	1		T27	1
auto[2952790016:3087007743]	98	1			T2	1		T42	1		T39	1
auto[3087007744:3221225471]	99	1			T28	1		T29	1		T50	1
auto[3221225472:3355443199]	124	1			T28	1		T50	1		T59	1
auto[3355443200:3489660927]	104	1			T29	1		T55	2		T98	1
auto[3489660928:3623878655]	125	1			T27	1		T68	1		T20	1
auto[3623878656:3758096383]	99	1			T26	1		T29	2		T50	4
auto[3758096384:3892314111]	87	1			T209	1		T50	1		T105	1
auto[3892314112:4026531839]	104	1			T157	1		T50	1		T54	1
auto[4026531840:4160749567]	102	1			T29	1		T23	1		T209	1
auto[4160749568:4294967295]	108	1			T29	1		T42	1		T63	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	38	1			T29	1		T20	1		T10	1
auto[0:134217727]	auto[1]	51	1			T26	1		T23	1		T59	2
auto[134217728:268435455]	auto[0]	44	1			T3	1		T18	1		T157	1
auto[134217728:268435455]	auto[1]	61	1			T63	1		T50	1		T59	1
auto[268435456:402653183]	auto[0]	47	1			T18	1		T122	1		T105	1
auto[268435456:402653183]	auto[1]	46	1			T50	2		T70	2		T158	1
auto[402653184:536870911]	auto[0]	54	1			T23	1		T32	1		T61	2
auto[402653184:536870911]	auto[1]	57	1			T2	1		T39	1		T63	1
auto[536870912:671088639]	auto[0]	44	1			T63	1		T61	1		T255	1
auto[536870912:671088639]	auto[1]	55	1			T8	1		T274	1		T104	1
auto[671088640:805306367]	auto[0]	35	1			T24	1		T51	1		T30	1
auto[671088640:805306367]	auto[1]	52	1			T39	1		T58	1		T211	1
auto[805306368:939524095]	auto[0]	54	1			T59	2		T55	1		T8	1
auto[805306368:939524095]	auto[1]	47	1			T26	1		T39	2		T50	3
auto[939524096:1073741823]	auto[0]	42	1			T26	1		T122	1		T61	1
auto[939524096:1073741823]	auto[1]	65	1			T39	2		T212	1		T8	2
auto[1073741824:1207959551]	auto[0]	58	1			T3	1		T50	1		T98	1
auto[1073741824:1207959551]	auto[1]	61	1			T38	1		T39	1		T59	1
auto[1207959552:1342177279]	auto[0]	36	1			T68	2		T50	1		T58	1
auto[1207959552:1342177279]	auto[1]	55	1			T39	2		T59	1		T55	1
auto[1342177280:1476395007]	auto[0]	51	1			T63	1		T302	1		T61	1
auto[1342177280:1476395007]	auto[1]	59	1			T28	1		T68	1		T61	1
auto[1476395008:1610612735]	auto[0]	49	1			T39	1		T63	1		T8	1
auto[1476395008:1610612735]	auto[1]	57	1			T42	1		T39	1		T70	1
auto[1610612736:1744830463]	auto[0]	56	1			T113	1		T61	2		T9	1
auto[1610612736:1744830463]	auto[1]	50	1			T209	1		T105	1		T61	2
auto[1744830464:1879048191]	auto[0]	54	1			T50	1		T58	1		T59	1
auto[1744830464:1879048191]	auto[1]	59	1			T50	1		T134	1		T137	1
auto[1879048192:2013265919]	auto[0]	54	1			T209	1		T50	2		T8	1
auto[1879048192:2013265919]	auto[1]	46	1			T39	1		T10	1		T212	1
auto[2013265920:2147483647]	auto[0]	39	1			T58	1		T8	1		T51	2
auto[2013265920:2147483647]	auto[1]	55	1			T157	1		T50	1		T212	1
auto[2147483648:2281701375]	auto[0]	48	1			T55	2		T274	1		T296	1
auto[2147483648:2281701375]	auto[1]	49	1			T18	1		T42	1		T54	1
auto[2281701376:2415919103]	auto[0]	59	1			T20	2		T70	1		T9	1
auto[2281701376:2415919103]	auto[1]	55	1			T28	1		T10	1		T50	1
auto[2415919104:2550136831]	auto[0]	53	1			T18	1		T68	1		T133	1
auto[2415919104:2550136831]	auto[1]	53	1			T8	1		T70	1		T61	1
auto[2550136832:2684354559]	auto[0]	37	1			T39	1		T50	1		T9	1
auto[2550136832:2684354559]	auto[1]	56	1			T68	1		T39	1		T50	1
auto[2684354560:2818572287]	auto[0]	49	1			T63	1		T50	1		T32	1
auto[2684354560:2818572287]	auto[1]	52	1			T28	1		T7	1		T50	1
auto[2818572288:2952790015]	auto[0]	42	1			T18	1		T55	1		T8	2
auto[2818572288:2952790015]	auto[1]	47	1			T26	1		T27	1		T42	1
auto[2952790016:3087007743]	auto[0]	44	1			T32	1		T59	1		T133	1
auto[2952790016:3087007743]	auto[1]	54	1			T2	1		T42	1		T39	1
auto[3087007744:3221225471]	auto[0]	50	1			T29	1		T55	1		T94	2
auto[3087007744:3221225471]	auto[1]	49	1			T28	1		T50	1		T94	1
auto[3221225472:3355443199]	auto[0]	48	1			T59	1		T98	1		T274	1
auto[3221225472:3355443199]	auto[1]	76	1			T28	1		T50	1		T134	1
auto[3355443200:3489660927]	auto[0]	51	1			T29	1		T98	1		T302	1
auto[3355443200:3489660927]	auto[1]	53	1			T55	2		T61	3		T9	1
auto[3489660928:3623878655]	auto[0]	67	1			T27	1		T68	1		T113	1
auto[3489660928:3623878655]	auto[1]	58	1			T20	1		T209	1		T50	3
auto[3623878656:3758096383]	auto[0]	45	1			T29	1		T50	2		T58	1
auto[3623878656:3758096383]	auto[1]	54	1			T26	1		T29	1		T50	2
auto[3758096384:3892314111]	auto[0]	42	1			T209	1		T9	1		T258	1
auto[3758096384:3892314111]	auto[1]	45	1			T50	1		T105	1		T62	1
auto[3892314112:4026531839]	auto[0]	44	1			T50	1		T59	1		T251	1
auto[3892314112:4026531839]	auto[1]	60	1			T157	1		T54	1		T59	1
auto[4026531840:4160749567]	auto[0]	47	1			T29	1		T275	1		T62	1
auto[4026531840:4160749567]	auto[1]	55	1			T23	1		T209	1		T137	1
auto[4160749568:4294967295]	auto[0]	50	1			T63	1		T133	1		T251	1
auto[4160749568:4294967295]	auto[1]	58	1			T29	1		T42	1		T50	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1525

1

T3

2

T18

4

T26

1

auto[1]

1756

1

T2

2

T18

1

T26

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T28	1		T157	1		T23	1
auto[134217728:268435455]	124	1			T29	1		T50	1		T212	1
auto[268435456:402653183]	81	1			T28	1		T29	1		T42	1
auto[402653184:536870911]	90	1			T3	1		T212	1		T59	2
auto[536870912:671088639]	104	1			T18	1		T39	1		T302	1
auto[671088640:805306367]	79	1			T28	1		T209	1		T50	1
auto[805306368:939524095]	128	1			T39	1		T10	1		T209	1
auto[939524096:1073741823]	112	1			T27	1		T50	1		T32	1
auto[1073741824:1207959551]	107	1			T29	1		T68	1		T157	1
auto[1207959552:1342177279]	95	1			T68	1		T50	1		T32	1
auto[1342177280:1476395007]	119	1			T39	1		T10	1		T50	1
auto[1476395008:1610612735]	105	1			T26	1		T38	1		T39	1
auto[1610612736:1744830463]	104	1			T29	2		T209	1		T50	1
auto[1744830464:1879048191]	106	1			T2	2		T42	1		T50	1
auto[1879048192:2013265919]	108	1			T26	1		T63	1		T59	1
auto[2013265920:2147483647]	105	1			T20	1		T39	2		T50	1
auto[2147483648:2281701375]	95	1			T18	1		T29	1		T68	1
auto[2281701376:2415919103]	94	1			T3	1		T26	1		T68	1
auto[2415919104:2550136831]	120	1			T18	1		T20	1		T42	1
auto[2550136832:2684354559]	110	1			T18	1		T39	1		T209	1
auto[2684354560:2818572287]	105	1			T28	1		T209	1		T50	2
auto[2818572288:2952790015]	106	1			T29	1		T39	3		T50	2
auto[2952790016:3087007743]	114	1			T26	1		T63	1		T59	3
auto[3087007744:3221225471]	99	1			T23	1		T42	1		T39	1
auto[3221225472:3355443199]	88	1			T63	1		T50	1		T59	1
auto[3355443200:3489660927]	102	1			T18	1		T26	1		T68	2
auto[3489660928:3623878655]	89	1			T7	1		T39	1		T94	2
auto[3623878656:3758096383]	96	1			T28	1		T20	1		T157	1
auto[3758096384:3892314111]	89	1			T20	1		T50	2		T70	2
auto[3892314112:4026531839]	109	1			T23	1		T63	1		T113	1
auto[4026531840:4160749567]	93	1			T50	2		T105	1		T158	1
auto[4160749568:4294967295]	100	1			T27	1		T39	1		T8	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T157	1		T63	1		T122	1
auto[0:134217727]	auto[1]	60	1			T28	1		T23	1		T42	1
auto[134217728:268435455]	auto[0]	53	1			T29	1		T133	1		T98	1
auto[134217728:268435455]	auto[1]	71	1			T50	1		T212	1		T59	1
auto[268435456:402653183]	auto[0]	35	1			T55	1		T275	1		T61	1
auto[268435456:402653183]	auto[1]	46	1			T28	1		T29	1		T42	1
auto[402653184:536870911]	auto[0]	40	1			T3	1		T59	1		T55	1
auto[402653184:536870911]	auto[1]	50	1			T212	1		T59	1		T8	1
auto[536870912:671088639]	auto[0]	43	1			T18	1		T127	1		T195	1
auto[536870912:671088639]	auto[1]	61	1			T39	1		T302	1		T71	1
auto[671088640:805306367]	auto[0]	36	1			T50	1		T55	1		T24	1
auto[671088640:805306367]	auto[1]	43	1			T28	1		T209	1		T59	1
auto[805306368:939524095]	auto[0]	52	1			T10	1		T8	1		T258	1
auto[805306368:939524095]	auto[1]	76	1			T39	1		T209	1		T59	1
auto[939524096:1073741823]	auto[0]	59	1			T27	1		T50	1		T32	1
auto[939524096:1073741823]	auto[1]	53	1			T94	1		T122	1		T9	1
auto[1073741824:1207959551]	auto[0]	54	1			T50	1		T61	1		T51	1
auto[1073741824:1207959551]	auto[1]	53	1			T29	1		T68	1		T157	1
auto[1207959552:1342177279]	auto[0]	47	1			T32	1		T8	1		T94	1
auto[1207959552:1342177279]	auto[1]	48	1			T68	1		T50	1		T54	1
auto[1342177280:1476395007]	auto[0]	52	1			T62	1		T51	2		T30	1
auto[1342177280:1476395007]	auto[1]	67	1			T39	1		T10	1		T50	1
auto[1476395008:1610612735]	auto[0]	52	1			T39	1		T63	1		T58	1
auto[1476395008:1610612735]	auto[1]	53	1			T26	1		T38	1		T10	1
auto[1610612736:1744830463]	auto[0]	50	1			T29	2		T209	1		T55	1
auto[1610612736:1744830463]	auto[1]	54	1			T50	1		T55	1		T104	1
auto[1744830464:1879048191]	auto[0]	51	1			T58	1		T133	1		T24	1
auto[1744830464:1879048191]	auto[1]	55	1			T2	2		T42	1		T50	1
auto[1879048192:2013265919]	auto[0]	55	1			T63	1		T59	1		T133	1
auto[1879048192:2013265919]	auto[1]	53	1			T26	1		T8	2		T61	1
auto[2013265920:2147483647]	auto[0]	57	1			T20	1		T50	1		T58	1
auto[2013265920:2147483647]	auto[1]	48	1			T39	2		T134	1		T122	1
auto[2147483648:2281701375]	auto[0]	50	1			T29	1		T68	1		T63	1
auto[2147483648:2281701375]	auto[1]	45	1			T18	1		T98	1		T70	1
auto[2281701376:2415919103]	auto[0]	37	1			T3	1		T68	1		T50	1
auto[2281701376:2415919103]	auto[1]	57	1			T26	1		T58	1		T8	1
auto[2415919104:2550136831]	auto[0]	49	1			T18	1		T58	1		T8	1
auto[2415919104:2550136831]	auto[1]	71	1			T20	1		T42	1		T50	1
auto[2550136832:2684354559]	auto[0]	45	1			T18	1		T98	1		T302	1
auto[2550136832:2684354559]	auto[1]	65	1			T39	1		T209	1		T50	2
auto[2684354560:2818572287]	auto[0]	53	1			T50	1		T133	1		T8	1
auto[2684354560:2818572287]	auto[1]	52	1			T28	1		T209	1		T50	1
auto[2818572288:2952790015]	auto[0]	45	1			T29	1		T39	1		T50	2
auto[2818572288:2952790015]	auto[1]	61	1			T39	2		T70	1		T211	1
auto[2952790016:3087007743]	auto[0]	59	1			T63	1		T59	2		T134	1
auto[2952790016:3087007743]	auto[1]	55	1			T26	1		T59	1		T104	1
auto[3087007744:3221225471]	auto[0]	40	1			T23	1		T55	1		T98	1
auto[3087007744:3221225471]	auto[1]	59	1			T42	1		T39	1		T134	1
auto[3221225472:3355443199]	auto[0]	43	1			T61	1		T9	1		T51	1
auto[3221225472:3355443199]	auto[1]	45	1			T63	1		T50	1		T59	1
auto[3355443200:3489660927]	auto[0]	50	1			T18	1		T26	1		T68	1
auto[3355443200:3489660927]	auto[1]	52	1			T68	1		T50	2		T55	1
auto[3489660928:3623878655]	auto[0]	45	1			T94	1		T70	1		T159	1
auto[3489660928:3623878655]	auto[1]	44	1			T7	1		T39	1		T94	1
auto[3623878656:3758096383]	auto[0]	49	1			T20	1		T113	1		T55	1
auto[3623878656:3758096383]	auto[1]	47	1			T28	1		T157	1		T39	1
auto[3758096384:3892314111]	auto[0]	38	1			T20	1		T50	1		T70	1
auto[3758096384:3892314111]	auto[1]	51	1			T50	1		T70	1		T61	1
auto[3892314112:4026531839]	auto[0]	60	1			T113	1		T50	1		T58	1
auto[3892314112:4026531839]	auto[1]	49	1			T23	1		T63	1		T50	1
auto[4026531840:4160749567]	auto[0]	38	1			T251	1		T255	1		T51	1
auto[4026531840:4160749567]	auto[1]	55	1			T50	2		T105	1		T158	1
auto[4160749568:4294967295]	auto[0]	43	1			T39	1		T8	1		T94	1
auto[4160749568:4294967295]	auto[1]	57	1			T27	1		T70	1		T61	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1533

1

T3

2

T18

4

T26

1

auto[1]

1748

1

T2

2

T18

1

T26

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T2	1		T39	3		T59	1
auto[134217728:268435455]	99	1			T3	1		T26	1		T27	1
auto[268435456:402653183]	104	1			T18	1		T28	1		T63	1
auto[402653184:536870911]	87	1			T68	2		T10	1		T50	2
auto[536870912:671088639]	89	1			T42	1		T50	1		T8	1
auto[671088640:805306367]	93	1			T26	1		T28	1		T157	1
auto[805306368:939524095]	117	1			T38	1		T63	1		T209	1
auto[939524096:1073741823]	93	1			T23	1		T39	1		T209	1
auto[1073741824:1207959551]	92	1			T18	1		T29	1		T50	3
auto[1207959552:1342177279]	103	1			T18	1		T26	1		T59	1
auto[1342177280:1476395007]	93	1			T29	1		T157	1		T54	1
auto[1476395008:1610612735]	90	1			T39	1		T209	1		T50	1
auto[1610612736:1744830463]	110	1			T39	1		T50	1		T59	1
auto[1744830464:1879048191]	121	1			T29	1		T68	1		T157	1
auto[1879048192:2013265919]	98	1			T27	1		T28	1		T113	1
auto[2013265920:2147483647]	100	1			T2	1		T3	1		T29	1
auto[2147483648:2281701375]	105	1			T18	1		T26	2		T42	1
auto[2281701376:2415919103]	96	1			T68	1		T20	1		T39	1
auto[2415919104:2550136831]	117	1			T28	1		T23	1		T42	1
auto[2550136832:2684354559]	102	1			T59	1		T55	1		T133	1
auto[2684354560:2818572287]	116	1			T29	1		T20	1		T209	1
auto[2818572288:2952790015]	120	1			T50	2		T55	1		T8	1
auto[2952790016:3087007743]	97	1			T28	1		T20	1		T63	1
auto[3087007744:3221225471]	110	1			T10	1		T59	2		T55	1
auto[3221225472:3355443199]	115	1			T20	1		T39	1		T63	1
auto[3355443200:3489660927]	92	1			T42	1		T39	1		T8	2
auto[3489660928:3623878655]	95	1			T29	1		T68	1		T50	1
auto[3623878656:3758096383]	103	1			T50	1		T133	1		T134	1
auto[3758096384:3892314111]	114	1			T63	1		T50	2		T58	1
auto[3892314112:4026531839]	120	1			T18	1		T68	1		T39	1
auto[4026531840:4160749567]	101	1			T23	1		T50	2		T54	1
auto[4160749568:4294967295]	89	1			T29	1		T39	2		T71	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	39	1			T39	1		T61	1		T62	1
auto[0:134217727]	auto[1]	61	1			T2	1		T39	2		T59	1
auto[134217728:268435455]	auto[0]	43	1			T3	1		T27	1		T59	1
auto[134217728:268435455]	auto[1]	56	1			T26	1		T50	2		T61	3
auto[268435456:402653183]	auto[0]	42	1			T18	1		T122	1		T252	1
auto[268435456:402653183]	auto[1]	62	1			T28	1		T63	1		T50	1
auto[402653184:536870911]	auto[0]	38	1			T68	2		T50	1		T98	1
auto[402653184:536870911]	auto[1]	49	1			T10	1		T50	1		T54	1
auto[536870912:671088639]	auto[0]	33	1			T8	1		T70	1		T215	1
auto[536870912:671088639]	auto[1]	56	1			T42	1		T50	1		T61	2
auto[671088640:805306367]	auto[0]	42	1			T157	1		T59	1		T55	1
auto[671088640:805306367]	auto[1]	51	1			T26	1		T28	1		T42	1
auto[805306368:939524095]	auto[0]	55	1			T63	1		T32	1		T251	1
auto[805306368:939524095]	auto[1]	62	1			T38	1		T209	1		T50	1
auto[939524096:1073741823]	auto[0]	40	1			T39	1		T50	1		T24	2
auto[939524096:1073741823]	auto[1]	53	1			T23	1		T209	1		T50	1
auto[1073741824:1207959551]	auto[0]	39	1			T18	1		T29	1		T50	2
auto[1073741824:1207959551]	auto[1]	53	1			T50	1		T137	1		T302	1
auto[1207959552:1342177279]	auto[0]	53	1			T18	1		T26	1		T55	1
auto[1207959552:1342177279]	auto[1]	50	1			T59	1		T70	1		T61	2
auto[1342177280:1476395007]	auto[0]	32	1			T29	1		T95	1		T51	1
auto[1342177280:1476395007]	auto[1]	61	1			T157	1		T54	1		T137	1
auto[1476395008:1610612735]	auto[0]	49	1			T209	1		T50	1		T59	1
auto[1476395008:1610612735]	auto[1]	41	1			T39	1		T62	1		T276	1
auto[1610612736:1744830463]	auto[0]	54	1			T50	1		T274	1		T296	1
auto[1610612736:1744830463]	auto[1]	56	1			T39	1		T59	1		T8	1
auto[1744830464:1879048191]	auto[0]	51	1			T29	1		T157	1		T302	1
auto[1744830464:1879048191]	auto[1]	70	1			T68	1		T39	1		T209	1
auto[1879048192:2013265919]	auto[0]	50	1			T113	1		T50	2		T24	1
auto[1879048192:2013265919]	auto[1]	48	1			T27	1		T28	1		T98	1
auto[2013265920:2147483647]	auto[0]	48	1			T3	1		T29	1		T113	1
auto[2013265920:2147483647]	auto[1]	52	1			T2	1		T39	1		T70	1
auto[2147483648:2281701375]	auto[0]	57	1			T18	1		T50	1		T58	1
auto[2147483648:2281701375]	auto[1]	48	1			T26	2		T42	1		T50	1
auto[2281701376:2415919103]	auto[0]	51	1			T20	1		T10	1		T59	1
auto[2281701376:2415919103]	auto[1]	45	1			T68	1		T39	1		T8	2
auto[2415919104:2550136831]	auto[0]	61	1			T23	1		T50	1		T58	1
auto[2415919104:2550136831]	auto[1]	56	1			T28	1		T42	1		T39	1
auto[2550136832:2684354559]	auto[0]	51	1			T133	1		T51	1		T127	1
auto[2550136832:2684354559]	auto[1]	51	1			T59	1		T55	1		T70	1
auto[2684354560:2818572287]	auto[0]	71	1			T29	1		T20	1		T32	1
auto[2684354560:2818572287]	auto[1]	45	1			T209	1		T50	1		T70	1
auto[2818572288:2952790015]	auto[0]	59	1			T50	2		T55	1		T105	1
auto[2818572288:2952790015]	auto[1]	61	1			T8	1		T61	3		T9	1
auto[2952790016:3087007743]	auto[0]	42	1			T63	1		T98	1		T9	1
auto[2952790016:3087007743]	auto[1]	55	1			T28	1		T20	1		T50	1
auto[3087007744:3221225471]	auto[0]	64	1			T10	1		T59	2		T133	1
auto[3087007744:3221225471]	auto[1]	46	1			T55	1		T8	1		T9	1
auto[3221225472:3355443199]	auto[0]	47	1			T20	1		T63	1		T98	1
auto[3221225472:3355443199]	auto[1]	68	1			T39	1		T50	2		T212	1
auto[3355443200:3489660927]	auto[0]	39	1			T8	1		T98	1		T302	1
auto[3355443200:3489660927]	auto[1]	53	1			T42	1		T39	1		T8	1
auto[3489660928:3623878655]	auto[0]	45	1			T58	1		T274	1		T24	1
auto[3489660928:3623878655]	auto[1]	50	1			T29	1		T68	1		T50	1
auto[3623878656:3758096383]	auto[0]	49	1			T133	1		T296	1		T61	2
auto[3623878656:3758096383]	auto[1]	54	1			T50	1		T134	1		T122	1
auto[3758096384:3892314111]	auto[0]	53	1			T55	1		T137	1		T251	1
auto[3758096384:3892314111]	auto[1]	61	1			T63	1		T50	2		T58	1
auto[3892314112:4026531839]	auto[0]	62	1			T68	1		T63	1		T32	1
auto[3892314112:4026531839]	auto[1]	58	1			T18	1		T39	1		T50	1
auto[4026531840:4160749567]	auto[0]	36	1			T23	1		T8	1		T9	1
auto[4026531840:4160749567]	auto[1]	65	1			T50	2		T54	1		T212	1
auto[4160749568:4294967295]	auto[0]	38	1			T29	1		T275	1		T127	1
auto[4160749568:4294967295]	auto[1]	51	1			T39	2		T71	1		T255	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1538

1

T3

2

T18

4

T26

1

auto[1]

1743

1

T2

2

T18

1

T26

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	125	1			T18	1		T29	1		T20	1
auto[134217728:268435455]	110	1			T26	1		T28	1		T29	1
auto[268435456:402653183]	91	1			T18	1		T39	1		T113	1
auto[402653184:536870911]	102	1			T39	1		T71	1		T61	1
auto[536870912:671088639]	98	1			T29	1		T63	1		T50	2
auto[671088640:805306367]	106	1			T7	1		T63	1		T55	2
auto[805306368:939524095]	96	1			T39	1		T10	1		T50	2
auto[939524096:1073741823]	78	1			T26	1		T209	1		T98	1
auto[1073741824:1207959551]	103	1			T50	1		T55	1		T94	1
auto[1207959552:1342177279]	92	1			T50	1		T55	1		T122	1
auto[1342177280:1476395007]	95	1			T42	1		T50	2		T59	1
auto[1476395008:1610612735]	100	1			T26	1		T28	1		T55	1
auto[1610612736:1744830463]	123	1			T20	1		T50	1		T158	1
auto[1744830464:1879048191]	110	1			T26	1		T157	1		T42	1
auto[1879048192:2013265919]	134	1			T26	1		T28	1		T39	1
auto[2013265920:2147483647]	87	1			T29	1		T68	1		T54	1
auto[2147483648:2281701375]	97	1			T23	1		T39	2		T50	1
auto[2281701376:2415919103]	102	1			T3	1		T68	1		T38	1
auto[2415919104:2550136831]	98	1			T50	1		T55	1		T122	1
auto[2550136832:2684354559]	101	1			T68	2		T63	1		T209	1
auto[2684354560:2818572287]	116	1			T29	1		T157	1		T42	1
auto[2818572288:2952790015]	111	1			T39	1		T63	1		T10	1
auto[2952790016:3087007743]	85	1			T20	1		T63	1		T50	1
auto[3087007744:3221225471]	103	1			T2	1		T18	1		T39	1
auto[3221225472:3355443199]	95	1			T27	1		T23	1		T42	1
auto[3355443200:3489660927]	115	1			T27	1		T157	1		T209	1
auto[3489660928:3623878655]	120	1			T18	1		T39	1		T209	1
auto[3623878656:3758096383]	108	1			T39	1		T50	3		T8	1
auto[3758096384:3892314111]	86	1			T3	1		T28	1		T68	2
auto[3892314112:4026531839]	106	1			T2	1		T29	1		T63	1
auto[4026531840:4160749567]	93	1			T50	2		T59	1		T55	1
auto[4160749568:4294967295]	95	1			T18	1		T28	1		T29	1