dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4410 1 T2 4 T3 2 T18 8
auto[1] 2152 1 T3 2 T18 2 T27 2



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 214 1 T39 2 T63 2 T10 2
auto[134217728:268435455] 200 1 T29 2 T68 2 T42 2
auto[268435456:402653183] 208 1 T26 4 T68 2 T39 2
auto[402653184:536870911] 186 1 T18 2 T122 2 T70 2
auto[536870912:671088639] 190 1 T29 2 T157 2 T39 2
auto[671088640:805306367] 176 1 T20 2 T50 6 T212 2
auto[805306368:939524095] 216 1 T157 2 T39 2 T50 2
auto[939524096:1073741823] 200 1 T3 2 T29 2 T23 2
auto[1073741824:1207959551] 208 1 T18 2 T68 2 T20 2
auto[1207959552:1342177279] 204 1 T32 2 T55 2 T24 2
auto[1342177280:1476395007] 186 1 T26 2 T29 2 T133 2
auto[1476395008:1610612735] 240 1 T18 2 T26 2 T39 2
auto[1610612736:1744830463] 228 1 T68 2 T50 4 T8 4
auto[1744830464:1879048191] 206 1 T2 2 T28 2 T42 2
auto[1879048192:2013265919] 226 1 T42 2 T50 2 T59 2
auto[2013265920:2147483647] 242 1 T2 2 T28 2 T39 2
auto[2147483648:2281701375] 236 1 T39 2 T209 2 T212 2
auto[2281701376:2415919103] 252 1 T29 4 T20 2 T42 2
auto[2415919104:2550136831] 162 1 T68 2 T113 2 T133 2
auto[2550136832:2684354559] 206 1 T23 2 T39 4 T55 2
auto[2684354560:2818572287] 208 1 T20 2 T209 2 T59 4
auto[2818572288:2952790015] 198 1 T27 2 T39 2 T55 2
auto[2952790016:3087007743] 178 1 T3 2 T27 2 T113 2
auto[3087007744:3221225471] 176 1 T18 2 T29 2 T63 2
auto[3221225472:3355443199] 244 1 T50 2 T8 4 T61 4
auto[3355443200:3489660927] 190 1 T209 2 T50 4 T58 6
auto[3489660928:3623878655] 172 1 T26 2 T23 2 T39 2
auto[3623878656:3758096383] 214 1 T63 2 T59 2 T8 4
auto[3758096384:3892314111] 176 1 T28 2 T157 2 T50 2
auto[3892314112:4026531839] 184 1 T39 2 T63 2 T58 2
auto[4026531840:4160749567] 226 1 T18 2 T28 2 T39 4
auto[4160749568:4294967295] 210 1 T28 2 T68 2 T42 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 142 1 T63 2 T10 2 T209 2
auto[0:134217727] auto[1] 72 1 T39 2 T70 2 T61 2
auto[134217728:268435455] auto[0] 128 1 T68 2 T50 4 T59 6
auto[134217728:268435455] auto[1] 72 1 T29 2 T42 2 T10 2
auto[268435456:402653183] auto[0] 146 1 T26 4 T63 2 T50 4
auto[268435456:402653183] auto[1] 62 1 T68 2 T39 2 T50 4
auto[402653184:536870911] auto[0] 108 1 T18 2 T122 2 T9 2
auto[402653184:536870911] auto[1] 78 1 T70 2 T9 4 T62 2
auto[536870912:671088639] auto[0] 128 1 T157 2 T39 2 T134 2
auto[536870912:671088639] auto[1] 62 1 T29 2 T98 2 T302 2
auto[671088640:805306367] auto[0] 124 1 T50 4 T64 2 T9 2
auto[671088640:805306367] auto[1] 52 1 T20 2 T50 2 T212 2
auto[805306368:939524095] auto[0] 142 1 T157 2 T39 2 T50 2
auto[805306368:939524095] auto[1] 74 1 T94 2 T61 2 T9 2
auto[939524096:1073741823] auto[0] 116 1 T3 2 T23 2 T63 2
auto[939524096:1073741823] auto[1] 84 1 T29 2 T209 2 T8 2
auto[1073741824:1207959551] auto[0] 124 1 T18 2 T68 2 T50 6
auto[1073741824:1207959551] auto[1] 84 1 T20 2 T9 2 T51 2
auto[1207959552:1342177279] auto[0] 132 1 T55 2 T61 2 T9 2
auto[1207959552:1342177279] auto[1] 72 1 T32 2 T24 2 T211 2
auto[1342177280:1476395007] auto[0] 120 1 T26 2 T133 2 T8 2
auto[1342177280:1476395007] auto[1] 66 1 T29 2 T104 2 T61 4
auto[1476395008:1610612735] auto[0] 174 1 T18 2 T26 2 T39 2
auto[1476395008:1610612735] auto[1] 66 1 T50 2 T105 2 T195 2
auto[1610612736:1744830463] auto[0] 168 1 T68 2 T50 4 T8 2
auto[1610612736:1744830463] auto[1] 60 1 T8 2 T70 2 T254 2
auto[1744830464:1879048191] auto[0] 158 1 T2 2 T28 2 T42 2
auto[1744830464:1879048191] auto[1] 48 1 T38 2 T104 2 T64 2
auto[1879048192:2013265919] auto[0] 152 1 T50 2 T59 2 T105 2
auto[1879048192:2013265919] auto[1] 74 1 T42 2 T158 2 T159 2
auto[2013265920:2147483647] auto[0] 150 1 T2 2 T39 2 T63 2
auto[2013265920:2147483647] auto[1] 92 1 T28 2 T137 2 T302 2
auto[2147483648:2281701375] auto[0] 166 1 T39 2 T209 2 T55 2
auto[2147483648:2281701375] auto[1] 70 1 T212 2 T214 2 T296 4
auto[2281701376:2415919103] auto[0] 174 1 T39 2 T55 2 T8 2
auto[2281701376:2415919103] auto[1] 78 1 T29 4 T20 2 T42 2
auto[2415919104:2550136831] auto[0] 106 1 T68 2 T133 2 T8 2
auto[2415919104:2550136831] auto[1] 56 1 T113 2 T302 2 T303 2
auto[2550136832:2684354559] auto[0] 134 1 T23 2 T39 2 T55 2
auto[2550136832:2684354559] auto[1] 72 1 T39 2 T8 2 T70 2
auto[2684354560:2818572287] auto[0] 140 1 T209 2 T59 4 T55 2
auto[2684354560:2818572287] auto[1] 68 1 T20 2 T423 2 T61 2
auto[2818572288:2952790015] auto[0] 132 1 T39 2 T8 2 T98 2
auto[2818572288:2952790015] auto[1] 66 1 T27 2 T55 2 T137 2
auto[2952790016:3087007743] auto[0] 116 1 T27 2 T54 2 T59 2
auto[2952790016:3087007743] auto[1] 62 1 T3 2 T113 2 T50 2
auto[3087007744:3221225471] auto[0] 138 1 T63 2 T59 2 T122 2
auto[3087007744:3221225471] auto[1] 38 1 T18 2 T29 2 T137 2
auto[3221225472:3355443199] auto[0] 170 1 T50 2 T8 2 T61 4
auto[3221225472:3355443199] auto[1] 74 1 T8 2 T356 2 T52 4
auto[3355443200:3489660927] auto[0] 138 1 T50 4 T58 6 T59 2
auto[3355443200:3489660927] auto[1] 52 1 T209 2 T104 2 T70 2
auto[3489660928:3623878655] auto[0] 132 1 T26 2 T23 2 T39 2
auto[3489660928:3623878655] auto[1] 40 1 T50 2 T134 2 T312 2
auto[3623878656:3758096383] auto[0] 132 1 T63 2 T59 2 T8 4
auto[3623878656:3758096383] auto[1] 82 1 T70 4 T252 2 T356 2
auto[3758096384:3892314111] auto[0] 114 1 T28 2 T50 2 T55 2
auto[3758096384:3892314111] auto[1] 62 1 T157 2 T61 2 T197 2
auto[3892314112:4026531839] auto[0] 118 1 T63 2 T55 2 T61 4
auto[3892314112:4026531839] auto[1] 66 1 T39 2 T58 2 T8 2
auto[4026531840:4160749567] auto[0] 152 1 T18 2 T28 2 T50 2
auto[4026531840:4160749567] auto[1] 74 1 T39 4 T50 4 T54 2
auto[4160749568:4294967295] auto[0] 136 1 T68 2 T50 2 T32 2
auto[4160749568:4294967295] auto[1] 74 1 T28 2 T42 2 T50 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%