Unified Coverage Report :: Group Instance : salt_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2848

1

T2

2

T3

1

T18

5

auto[1]

295

1

T122

8

T158

15

T159

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T26	1		T29	1		T50	2
auto[134217728:268435455]	89	1			T28	1		T209	1		T54	1
auto[268435456:402653183]	88	1			T27	1		T28	1		T50	1
auto[402653184:536870911]	107	1			T209	1		T50	1		T133	1
auto[536870912:671088639]	102	1			T26	1		T29	1		T42	2
auto[671088640:805306367]	85	1			T59	1		T134	1		T8	1
auto[805306368:939524095]	92	1			T2	1		T39	1		T8	1
auto[939524096:1073741823]	99	1			T29	1		T50	3		T134	2
auto[1073741824:1207959551]	102	1			T209	1		T50	1		T98	2
auto[1207959552:1342177279]	95	1			T39	1		T63	1		T50	2
auto[1342177280:1476395007]	103	1			T42	1		T39	2		T50	2
auto[1476395008:1610612735]	99	1			T28	1		T20	1		T50	1
auto[1610612736:1744830463]	105	1			T3	1		T18	1		T58	1
auto[1744830464:1879048191]	98	1			T2	1		T29	1		T39	1
auto[1879048192:2013265919]	91	1			T26	1		T68	1		T63	1
auto[2013265920:2147483647]	106	1			T18	1		T157	1		T10	1
auto[2147483648:2281701375]	99	1			T20	1		T157	1		T23	1
auto[2281701376:2415919103]	104	1			T42	1		T50	2		T59	2
auto[2415919104:2550136831]	101	1			T26	1		T29	1		T39	1
auto[2550136832:2684354559]	92	1			T29	1		T39	1		T63	1
auto[2684354560:2818572287]	88	1			T23	1		T39	1		T32	1
auto[2818572288:2952790015]	103	1			T18	1		T55	1		T98	1
auto[2952790016:3087007743]	108	1			T18	1		T29	1		T50	3
auto[3087007744:3221225471]	93	1			T32	1		T8	1		T71	1
auto[3221225472:3355443199]	91	1			T28	1		T212	1		T104	1
auto[3355443200:3489660927]	103	1			T23	1		T42	1		T50	1
auto[3489660928:3623878655]	102	1			T18	1		T157	1		T10	1
auto[3623878656:3758096383]	101	1			T26	1		T209	1		T50	1
auto[3758096384:3892314111]	89	1			T27	1		T68	1		T20	1
auto[3892314112:4026531839]	94	1			T28	1		T38	1		T39	2
auto[4026531840:4160749567]	107	1			T59	1		T8	1		T94	2
auto[4160749568:4294967295]	104	1			T50	1		T59	2		T98	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	94	1			T26	1		T29	1		T50	2
auto[0:134217727]	auto[1]	9	1			T122	2		T90	1		T267	1
auto[134217728:268435455]	auto[0]	82	1			T28	1		T209	1		T54	1
auto[134217728:268435455]	auto[1]	7	1			T158	1		T405	1		T360	1
auto[268435456:402653183]	auto[0]	80	1			T27	1		T28	1		T50	1
auto[268435456:402653183]	auto[1]	8	1			T146	1		T93	1		T418	1
auto[402653184:536870911]	auto[0]	96	1			T209	1		T50	1		T133	1
auto[402653184:536870911]	auto[1]	11	1			T122	3		T159	1		T146	1
auto[536870912:671088639]	auto[0]	93	1			T26	1		T29	1		T42	2
auto[536870912:671088639]	auto[1]	9	1			T93	1		T267	1		T416	1
auto[671088640:805306367]	auto[0]	79	1			T59	1		T134	1		T8	1
auto[671088640:805306367]	auto[1]	6	1			T122	1		T146	1		T93	1
auto[805306368:939524095]	auto[0]	83	1			T2	1		T39	1		T8	1
auto[805306368:939524095]	auto[1]	9	1			T93	1		T267	1		T405	1
auto[939524096:1073741823]	auto[0]	88	1			T29	1		T50	3		T134	2
auto[939524096:1073741823]	auto[1]	11	1			T158	1		T144	1		T418	1
auto[1073741824:1207959551]	auto[0]	85	1			T209	1		T50	1		T98	2
auto[1073741824:1207959551]	auto[1]	17	1			T158	3		T299	1		T90	1
auto[1207959552:1342177279]	auto[0]	83	1			T39	1		T63	1		T50	2
auto[1207959552:1342177279]	auto[1]	12	1			T158	1		T299	1		T93	1
auto[1342177280:1476395007]	auto[0]	95	1			T42	1		T39	2		T50	2
auto[1342177280:1476395007]	auto[1]	8	1			T144	1		T93	1		T419	1
auto[1476395008:1610612735]	auto[0]	89	1			T28	1		T20	1		T50	1
auto[1476395008:1610612735]	auto[1]	10	1			T158	1		T299	1		T394	1
auto[1610612736:1744830463]	auto[0]	98	1			T3	1		T18	1		T58	1
auto[1610612736:1744830463]	auto[1]	7	1			T158	3		T299	1		T416	1
auto[1744830464:1879048191]	auto[0]	89	1			T2	1		T29	1		T39	1
auto[1744830464:1879048191]	auto[1]	9	1			T158	1		T245	1		T418	1
auto[1879048192:2013265919]	auto[0]	82	1			T26	1		T68	1		T63	1
auto[1879048192:2013265919]	auto[1]	9	1			T299	1		T280	1		T346	1
auto[2013265920:2147483647]	auto[0]	97	1			T18	1		T157	1		T10	1
auto[2013265920:2147483647]	auto[1]	9	1			T93	1		T290	1		T373	1
auto[2147483648:2281701375]	auto[0]	87	1			T20	1		T157	1		T23	1
auto[2147483648:2281701375]	auto[1]	12	1			T299	1		T290	2		T405	1
auto[2281701376:2415919103]	auto[0]	97	1			T42	1		T50	2		T59	2
auto[2281701376:2415919103]	auto[1]	7	1			T93	1		T373	1		T406	1
auto[2415919104:2550136831]	auto[0]	96	1			T26	1		T29	1		T39	1
auto[2415919104:2550136831]	auto[1]	5	1			T122	1		T159	1		T346	1
auto[2550136832:2684354559]	auto[0]	85	1			T29	1		T39	1		T63	1
auto[2550136832:2684354559]	auto[1]	7	1			T159	1		T416	1		T362	1
auto[2684354560:2818572287]	auto[0]	78	1			T23	1		T39	1		T32	1
auto[2684354560:2818572287]	auto[1]	10	1			T144	1		T90	1		T360	1
auto[2818572288:2952790015]	auto[0]	91	1			T18	1		T55	1		T98	1
auto[2818572288:2952790015]	auto[1]	12	1			T144	1		T146	1		T418	1
auto[2952790016:3087007743]	auto[0]	100	1			T18	1		T29	1		T50	3
auto[2952790016:3087007743]	auto[1]	8	1			T158	1		T394	1		T266	2
auto[3087007744:3221225471]	auto[0]	84	1			T32	1		T8	1		T71	1
auto[3087007744:3221225471]	auto[1]	9	1			T93	2		T394	1		T418	1
auto[3221225472:3355443199]	auto[0]	81	1			T28	1		T212	1		T104	1
auto[3221225472:3355443199]	auto[1]	10	1			T158	1		T144	1		T93	1
auto[3355443200:3489660927]	auto[0]	88	1			T23	1		T42	1		T50	1
auto[3355443200:3489660927]	auto[1]	15	1			T144	1		T290	2		T267	2
auto[3489660928:3623878655]	auto[0]	90	1			T18	1		T157	1		T10	1
auto[3489660928:3623878655]	auto[1]	12	1			T159	1		T299	1		T90	1
auto[3623878656:3758096383]	auto[0]	92	1			T26	1		T209	1		T50	1
auto[3623878656:3758096383]	auto[1]	9	1			T276	1		T93	1		T405	1
auto[3758096384:3892314111]	auto[0]	81	1			T27	1		T68	1		T20	1
auto[3758096384:3892314111]	auto[1]	8	1			T299	2		T246	1		T362	2
auto[3892314112:4026531839]	auto[0]	86	1			T28	1		T38	1		T39	2
auto[3892314112:4026531839]	auto[1]	8	1			T159	1		T290	2		T246	1
auto[4026531840:4160749567]	auto[0]	100	1			T59	1		T8	1		T94	2
auto[4026531840:4160749567]	auto[1]	7	1			T122	1		T158	1		T146	1
auto[4160749568:4294967295]	auto[0]	99	1			T50	1		T59	2		T98	1
auto[4160749568:4294967295]	auto[1]	5	1			T158	1		T159	1		T299	1