Unified Coverage Report :: Group Instance : sealing_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1537

1

T3

2

T18

4

T27

1

auto[1]

1744

1

T2

2

T18

1

T26

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	122	1			T2	1		T42	1		T39	2
auto[134217728:268435455]	95	1			T29	1		T50	1		T212	1
auto[268435456:402653183]	100	1			T134	2		T137	1		T8	1
auto[402653184:536870911]	94	1			T18	1		T59	1		T55	1
auto[536870912:671088639]	106	1			T18	1		T50	1		T58	1
auto[671088640:805306367]	103	1			T26	1		T28	1		T29	1
auto[805306368:939524095]	92	1			T39	1		T10	1		T50	1
auto[939524096:1073741823]	112	1			T28	1		T29	1		T20	2
auto[1073741824:1207959551]	106	1			T28	1		T50	2		T32	1
auto[1207959552:1342177279]	99	1			T68	1		T209	1		T54	1
auto[1342177280:1476395007]	96	1			T209	1		T32	1		T212	1
auto[1476395008:1610612735]	113	1			T18	1		T26	1		T63	1
auto[1610612736:1744830463]	98	1			T23	1		T63	1		T50	2
auto[1744830464:1879048191]	101	1			T50	1		T58	1		T59	1
auto[1879048192:2013265919]	101	1			T7	1		T39	1		T63	1
auto[2013265920:2147483647]	108	1			T68	1		T42	1		T38	1
auto[2147483648:2281701375]	106	1			T26	1		T50	2		T133	1
auto[2281701376:2415919103]	98	1			T3	1		T18	1		T27	1
auto[2415919104:2550136831]	104	1			T157	1		T39	1		T63	1
auto[2550136832:2684354559]	99	1			T3	1		T68	1		T39	2
auto[2684354560:2818572287]	95	1			T39	1		T50	1		T8	1
auto[2818572288:2952790015]	114	1			T26	1		T28	1		T42	1
auto[2952790016:3087007743]	113	1			T26	1		T29	1		T50	2
auto[3087007744:3221225471]	114	1			T27	1		T157	1		T58	1
auto[3221225472:3355443199]	95	1			T39	1		T113	1		T50	1
auto[3355443200:3489660927]	116	1			T29	1		T23	1		T39	1
auto[3489660928:3623878655]	96	1			T2	1		T20	1		T98	1
auto[3623878656:3758096383]	96	1			T28	1		T157	1		T39	1
auto[3758096384:3892314111]	98	1			T68	1		T42	1		T50	1
auto[3892314112:4026531839]	87	1			T209	1		T50	1		T58	1
auto[4026531840:4160749567]	94	1			T29	2		T68	1		T209	1
auto[4160749568:4294967295]	110	1			T18	1		T68	1		T42	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	64	1			T39	1		T63	1		T113	1
auto[0:134217727]	auto[1]	58	1			T2	1		T42	1		T39	1
auto[134217728:268435455]	auto[0]	43	1			T29	1		T50	1		T302	1
auto[134217728:268435455]	auto[1]	52	1			T212	1		T55	1		T61	1
auto[268435456:402653183]	auto[0]	44	1			T8	1		T62	1		T127	1
auto[268435456:402653183]	auto[1]	56	1			T134	2		T137	1		T423	1
auto[402653184:536870911]	auto[0]	46	1			T18	1		T64	1		T61	1
auto[402653184:536870911]	auto[1]	48	1			T59	1		T55	1		T302	1
auto[536870912:671088639]	auto[0]	51	1			T18	1		T50	1		T58	1
auto[536870912:671088639]	auto[1]	55	1			T8	1		T98	1		T275	1
auto[671088640:805306367]	auto[0]	45	1			T23	1		T10	1		T98	1
auto[671088640:805306367]	auto[1]	58	1			T26	1		T28	1		T29	1
auto[805306368:939524095]	auto[0]	39	1			T55	2		T274	1		T252	1
auto[805306368:939524095]	auto[1]	53	1			T39	1		T10	1		T50	1
auto[939524096:1073741823]	auto[0]	57	1			T29	1		T20	2		T59	1
auto[939524096:1073741823]	auto[1]	55	1			T28	1		T50	1		T134	2
auto[1073741824:1207959551]	auto[0]	45	1			T50	1		T32	1		T59	1
auto[1073741824:1207959551]	auto[1]	61	1			T28	1		T50	1		T8	1
auto[1207959552:1342177279]	auto[0]	45	1			T68	1		T209	1		T59	1
auto[1207959552:1342177279]	auto[1]	54	1			T54	1		T212	1		T137	1
auto[1342177280:1476395007]	auto[0]	45	1			T32	1		T94	1		T296	1
auto[1342177280:1476395007]	auto[1]	51	1			T209	1		T212	1		T61	2
auto[1476395008:1610612735]	auto[0]	53	1			T18	1		T63	1		T50	1
auto[1476395008:1610612735]	auto[1]	60	1			T26	1		T50	1		T159	2
auto[1610612736:1744830463]	auto[0]	52	1			T50	2		T59	1		T98	1
auto[1610612736:1744830463]	auto[1]	46	1			T23	1		T63	1		T59	1
auto[1744830464:1879048191]	auto[0]	57	1			T50	1		T59	1		T302	1
auto[1744830464:1879048191]	auto[1]	44	1			T58	1		T61	1		T127	1
auto[1879048192:2013265919]	auto[0]	46	1			T63	1		T55	1		T8	1
auto[1879048192:2013265919]	auto[1]	55	1			T7	1		T39	1		T50	2
auto[2013265920:2147483647]	auto[0]	55	1			T63	1		T32	1		T54	1
auto[2013265920:2147483647]	auto[1]	53	1			T68	1		T42	1		T38	1
auto[2147483648:2281701375]	auto[0]	51	1			T133	1		T251	1		T199	1
auto[2147483648:2281701375]	auto[1]	55	1			T26	1		T50	2		T70	1
auto[2281701376:2415919103]	auto[0]	54	1			T3	1		T50	1		T55	2
auto[2281701376:2415919103]	auto[1]	44	1			T18	1		T27	1		T39	1
auto[2415919104:2550136831]	auto[0]	45	1			T157	1		T58	1		T70	1
auto[2415919104:2550136831]	auto[1]	59	1			T39	1		T63	1		T24	1
auto[2550136832:2684354559]	auto[0]	49	1			T3	1		T68	1		T39	1
auto[2550136832:2684354559]	auto[1]	50	1			T39	1		T59	1		T274	1
auto[2684354560:2818572287]	auto[0]	53	1			T50	1		T8	1		T122	1
auto[2684354560:2818572287]	auto[1]	42	1			T39	1		T94	1		T61	1
auto[2818572288:2952790015]	auto[0]	48	1			T59	1		T24	1		T70	1
auto[2818572288:2952790015]	auto[1]	66	1			T26	1		T28	1		T42	1
auto[2952790016:3087007743]	auto[0]	51	1			T29	1		T55	1		T98	1
auto[2952790016:3087007743]	auto[1]	62	1			T26	1		T50	2		T104	1
auto[3087007744:3221225471]	auto[0]	53	1			T27	1		T157	1		T58	1
auto[3087007744:3221225471]	auto[1]	61	1			T59	1		T8	1		T275	1
auto[3221225472:3355443199]	auto[0]	44	1			T113	1		T50	1		T8	1
auto[3221225472:3355443199]	auto[1]	51	1			T39	1		T54	1		T134	1
auto[3355443200:3489660927]	auto[0]	49	1			T29	1		T50	1		T8	1
auto[3355443200:3489660927]	auto[1]	67	1			T23	1		T39	1		T63	1
auto[3489660928:3623878655]	auto[0]	33	1			T20	1		T98	1		T24	1
auto[3489660928:3623878655]	auto[1]	63	1			T2	1		T71	1		T423	1
auto[3623878656:3758096383]	auto[0]	44	1			T58	1		T133	1		T8	1
auto[3623878656:3758096383]	auto[1]	52	1			T28	1		T157	1		T39	1
auto[3758096384:3892314111]	auto[0]	49	1			T68	1		T59	1		T55	1
auto[3758096384:3892314111]	auto[1]	49	1			T42	1		T50	1		T8	1
auto[3892314112:4026531839]	auto[0]	33	1			T209	1		T58	1		T24	1
auto[3892314112:4026531839]	auto[1]	54	1			T50	1		T104	1		T105	1
auto[4026531840:4160749567]	auto[0]	43	1			T29	1		T55	1		T8	1
auto[4026531840:4160749567]	auto[1]	51	1			T29	1		T68	1		T209	1
auto[4160749568:4294967295]	auto[0]	51	1			T18	1		T68	1		T39	1
auto[4160749568:4294967295]	auto[1]	59	1			T42	1		T133	1		T137	1