Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4526

1

T2

2

T3

2

T18

8

auto[1]

2036

1

T2

2

T3

2

T18

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	206	1			T28	2		T50	2		T58	2
auto[134217728:268435455]	186	1			T42	4		T50	2		T32	2
auto[268435456:402653183]	230	1			T18	2		T42	2		T10	2
auto[402653184:536870911]	208	1			T29	2		T7	2		T63	2
auto[536870912:671088639]	218	1			T18	2		T29	2		T209	2
auto[671088640:805306367]	188	1			T39	2		T50	2		T94	2
auto[805306368:939524095]	182	1			T28	2		T63	2		T58	2
auto[939524096:1073741823]	194	1			T18	2		T29	2		T50	2
auto[1073741824:1207959551]	170	1			T27	2		T50	4		T122	2
auto[1207959552:1342177279]	196	1			T18	2		T29	2		T39	2
auto[1342177280:1476395007]	204	1			T68	2		T157	2		T39	2
auto[1476395008:1610612735]	212	1			T26	4		T28	2		T29	2
auto[1610612736:1744830463]	248	1			T68	2		T209	2		T50	6
auto[1744830464:1879048191]	212	1			T28	2		T23	2		T39	6
auto[1879048192:2013265919]	212	1			T29	2		T20	2		T63	2
auto[2013265920:2147483647]	188	1			T3	2		T26	2		T113	2
auto[2147483648:2281701375]	254	1			T42	2		T39	2		T209	2
auto[2281701376:2415919103]	224	1			T26	2		T20	2		T50	4
auto[2415919104:2550136831]	204	1			T68	2		T113	2		T50	2
auto[2550136832:2684354559]	196	1			T39	2		T50	2		T32	2
auto[2684354560:2818572287]	244	1			T68	2		T20	2		T157	2
auto[2818572288:2952790015]	210	1			T18	2		T68	2		T39	4
auto[2952790016:3087007743]	220	1			T39	2		T59	2		T98	4
auto[3087007744:3221225471]	210	1			T42	2		T54	2		T252	2
auto[3221225472:3355443199]	232	1			T23	2		T63	4		T50	4
auto[3355443200:3489660927]	202	1			T20	2		T38	2		T10	2
auto[3489660928:3623878655]	184	1			T3	2		T27	2		T39	2
auto[3623878656:3758096383]	192	1			T55	4		T134	2		T8	4
auto[3758096384:3892314111]	188	1			T26	2		T28	2		T39	4
auto[3892314112:4026531839]	194	1			T39	2		T63	2		T59	2
auto[4026531840:4160749567]	172	1			T2	2		T68	2		T50	2
auto[4160749568:4294967295]	182	1			T2	2		T29	2		T157	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	136	1			T50	2		T58	2		T59	2
auto[0:134217727]	auto[1]	70	1			T28	2		T8	2		T51	2
auto[134217728:268435455]	auto[0]	116	1			T42	2		T50	2		T32	2
auto[134217728:268435455]	auto[1]	70	1			T42	2		T274	2		T24	2
auto[268435456:402653183]	auto[0]	174	1			T18	2		T42	2		T212	2
auto[268435456:402653183]	auto[1]	56	1			T10	2		T275	2		T62	2
auto[402653184:536870911]	auto[0]	154	1			T29	2		T7	2		T63	2
auto[402653184:536870911]	auto[1]	54	1			T97	2		T300	2		T268	2
auto[536870912:671088639]	auto[0]	154	1			T18	2		T29	2		T209	2
auto[536870912:671088639]	auto[1]	64	1			T133	2		T158	2		T9	2
auto[671088640:805306367]	auto[0]	124	1			T39	2		T50	2		T94	2
auto[671088640:805306367]	auto[1]	64	1			T24	2		T71	2		T70	2
auto[805306368:939524095]	auto[0]	142	1			T28	2		T63	2		T58	2
auto[805306368:939524095]	auto[1]	40	1			T61	2		T62	2		T297	2
auto[939524096:1073741823]	auto[0]	140	1			T18	2		T29	2		T58	2
auto[939524096:1073741823]	auto[1]	54	1			T50	2		T24	2		T9	2
auto[1073741824:1207959551]	auto[0]	102	1			T50	4		T122	2		T296	2
auto[1073741824:1207959551]	auto[1]	68	1			T27	2		T252	2		T61	2
auto[1207959552:1342177279]	auto[0]	132	1			T18	2		T29	2		T39	2
auto[1207959552:1342177279]	auto[1]	64	1			T32	2		T251	2		T51	2
auto[1342177280:1476395007]	auto[0]	146	1			T68	2		T39	2		T50	2
auto[1342177280:1476395007]	auto[1]	58	1			T157	2		T137	2		T105	2
auto[1476395008:1610612735]	auto[0]	144	1			T26	2		T28	2		T29	2
auto[1476395008:1610612735]	auto[1]	68	1			T26	2		T23	2		T211	2
auto[1610612736:1744830463]	auto[0]	174	1			T68	2		T209	2		T50	4
auto[1610612736:1744830463]	auto[1]	74	1			T50	2		T214	2		T296	2
auto[1744830464:1879048191]	auto[0]	124	1			T28	2		T23	2		T50	6
auto[1744830464:1879048191]	auto[1]	88	1			T39	6		T70	2		T9	2
auto[1879048192:2013265919]	auto[0]	152	1			T29	2		T20	2		T63	2
auto[1879048192:2013265919]	auto[1]	60	1			T50	4		T51	4		T127	4
auto[2013265920:2147483647]	auto[0]	138	1			T26	2		T113	2		T50	2
auto[2013265920:2147483647]	auto[1]	50	1			T3	2		T50	2		T8	2
auto[2147483648:2281701375]	auto[0]	170	1			T42	2		T39	2		T209	2
auto[2147483648:2281701375]	auto[1]	84	1			T59	2		T8	2		T275	2
auto[2281701376:2415919103]	auto[0]	156	1			T26	2		T50	4		T58	2
auto[2281701376:2415919103]	auto[1]	68	1			T20	2		T94	2		T70	2
auto[2415919104:2550136831]	auto[0]	146	1			T68	2		T113	2		T58	2
auto[2415919104:2550136831]	auto[1]	58	1			T50	2		T55	2		T64	2
auto[2550136832:2684354559]	auto[0]	140	1			T39	2		T50	2		T54	2
auto[2550136832:2684354559]	auto[1]	56	1			T32	2		T137	2		T251	2
auto[2684354560:2818572287]	auto[0]	188	1			T68	2		T20	2		T157	2
auto[2684354560:2818572287]	auto[1]	56	1			T94	2		T64	2		T9	2
auto[2818572288:2952790015]	auto[0]	140	1			T68	2		T39	4		T50	6
auto[2818572288:2952790015]	auto[1]	70	1			T18	2		T50	2		T55	2
auto[2952790016:3087007743]	auto[0]	160	1			T39	2		T59	2		T98	2
auto[2952790016:3087007743]	auto[1]	60	1			T98	2		T70	2		T251	2
auto[3087007744:3221225471]	auto[0]	132	1			T42	2		T61	2		T9	2
auto[3087007744:3221225471]	auto[1]	78	1			T54	2		T252	2		T61	2
auto[3221225472:3355443199]	auto[0]	152	1			T63	4		T50	4		T212	2
auto[3221225472:3355443199]	auto[1]	80	1			T23	2		T105	2		T64	2
auto[3355443200:3489660927]	auto[0]	130	1			T20	2		T10	2		T50	2
auto[3355443200:3489660927]	auto[1]	72	1			T38	2		T8	2		T24	2
auto[3489660928:3623878655]	auto[0]	136	1			T3	2		T59	4		T302	2
auto[3489660928:3623878655]	auto[1]	48	1			T27	2		T39	2		T50	2
auto[3623878656:3758096383]	auto[0]	136	1			T55	2		T8	4		T98	2
auto[3623878656:3758096383]	auto[1]	56	1			T55	2		T134	2		T9	2
auto[3758096384:3892314111]	auto[0]	132	1			T26	2		T28	2		T39	4
auto[3758096384:3892314111]	auto[1]	56	1			T61	2		T254	2		T387	2
auto[3892314112:4026531839]	auto[0]	118	1			T39	2		T63	2		T59	2
auto[3892314112:4026531839]	auto[1]	76	1			T24	2		T104	2		T423	4
auto[4026531840:4160749567]	auto[0]	134	1			T2	2		T68	2		T50	2
auto[4026531840:4160749567]	auto[1]	38	1			T258	2		T75	2		T128	2
auto[4160749568:4294967295]	auto[0]	104	1			T29	2		T157	2		T63	2
auto[4160749568:4294967295]	auto[1]	78	1			T2	2		T70	2		T159	2