Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.71 99.04 97.91 98.33 100.00 99.02 98.41 91.24


Total test records in report: 1084
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T1009 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.998032936 Jul 10 05:46:30 PM PDT 24 Jul 10 05:46:46 PM PDT 24 4946269906 ps
T1010 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.271517874 Jul 10 05:47:15 PM PDT 24 Jul 10 05:47:17 PM PDT 24 28963815 ps
T1011 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.298843796 Jul 10 05:47:12 PM PDT 24 Jul 10 05:47:14 PM PDT 24 39886776 ps
T1012 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1880554199 Jul 10 05:46:59 PM PDT 24 Jul 10 05:47:05 PM PDT 24 82764765 ps
T1013 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.296316060 Jul 10 05:46:40 PM PDT 24 Jul 10 05:46:42 PM PDT 24 22827523 ps
T1014 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2222814532 Jul 10 05:47:05 PM PDT 24 Jul 10 05:47:07 PM PDT 24 34960702 ps
T1015 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2818103572 Jul 10 05:46:51 PM PDT 24 Jul 10 05:46:55 PM PDT 24 156305845 ps
T1016 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.4241319099 Jul 10 05:46:56 PM PDT 24 Jul 10 05:47:00 PM PDT 24 42416795 ps
T1017 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1182769129 Jul 10 05:47:24 PM PDT 24 Jul 10 05:47:27 PM PDT 24 10616995 ps
T1018 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1889235419 Jul 10 05:46:51 PM PDT 24 Jul 10 05:46:55 PM PDT 24 95895611 ps
T1019 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3645465374 Jul 10 05:47:24 PM PDT 24 Jul 10 05:47:27 PM PDT 24 12658181 ps
T1020 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3484533778 Jul 10 05:47:15 PM PDT 24 Jul 10 05:47:18 PM PDT 24 122730437 ps
T1021 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3446417358 Jul 10 05:46:50 PM PDT 24 Jul 10 05:47:00 PM PDT 24 243788491 ps
T1022 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.366558083 Jul 10 05:46:31 PM PDT 24 Jul 10 05:46:33 PM PDT 24 116277318 ps
T1023 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.483154182 Jul 10 05:47:00 PM PDT 24 Jul 10 05:47:04 PM PDT 24 27598375 ps
T1024 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2104759712 Jul 10 05:46:54 PM PDT 24 Jul 10 05:46:58 PM PDT 24 77749560 ps
T1025 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2209326837 Jul 10 05:47:08 PM PDT 24 Jul 10 05:47:14 PM PDT 24 133411582 ps
T1026 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1155952208 Jul 10 05:46:45 PM PDT 24 Jul 10 05:46:49 PM PDT 24 57267022 ps
T1027 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.239431150 Jul 10 05:46:51 PM PDT 24 Jul 10 05:46:58 PM PDT 24 1130084567 ps
T1028 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1266427861 Jul 10 05:47:26 PM PDT 24 Jul 10 05:47:30 PM PDT 24 41053933 ps
T1029 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1644594764 Jul 10 05:46:47 PM PDT 24 Jul 10 05:46:51 PM PDT 24 184767096 ps
T1030 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2023822231 Jul 10 05:46:47 PM PDT 24 Jul 10 05:46:53 PM PDT 24 486504078 ps
T1031 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3352301476 Jul 10 05:46:58 PM PDT 24 Jul 10 05:47:02 PM PDT 24 99768677 ps
T175 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1547714440 Jul 10 05:47:18 PM PDT 24 Jul 10 05:47:28 PM PDT 24 219108437 ps
T397 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1901142066 Jul 10 05:47:00 PM PDT 24 Jul 10 05:47:05 PM PDT 24 919394806 ps
T1032 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1408879871 Jul 10 05:47:17 PM PDT 24 Jul 10 05:47:19 PM PDT 24 20776127 ps
T176 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2599936804 Jul 10 05:46:33 PM PDT 24 Jul 10 05:46:41 PM PDT 24 516085910 ps
T1033 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3260584398 Jul 10 05:46:46 PM PDT 24 Jul 10 05:46:50 PM PDT 24 55433766 ps
T1034 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1316066560 Jul 10 05:46:39 PM PDT 24 Jul 10 05:46:42 PM PDT 24 67130846 ps
T1035 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2233521782 Jul 10 05:46:45 PM PDT 24 Jul 10 05:46:50 PM PDT 24 272186288 ps
T1036 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.81357536 Jul 10 05:46:56 PM PDT 24 Jul 10 05:47:00 PM PDT 24 10543065 ps
T1037 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3195047769 Jul 10 05:46:51 PM PDT 24 Jul 10 05:46:54 PM PDT 24 51239422 ps
T1038 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1241482547 Jul 10 05:47:16 PM PDT 24 Jul 10 05:47:18 PM PDT 24 29888478 ps
T1039 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3116923549 Jul 10 05:46:57 PM PDT 24 Jul 10 05:47:01 PM PDT 24 29416125 ps
T171 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.30345076 Jul 10 05:46:58 PM PDT 24 Jul 10 05:47:11 PM PDT 24 356556812 ps
T1040 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.348684534 Jul 10 05:47:18 PM PDT 24 Jul 10 05:47:20 PM PDT 24 10280868 ps
T1041 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.219556892 Jul 10 05:46:45 PM PDT 24 Jul 10 05:46:48 PM PDT 24 25973377 ps
T1042 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4231997402 Jul 10 05:46:50 PM PDT 24 Jul 10 05:46:54 PM PDT 24 89618794 ps
T1043 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2232833065 Jul 10 05:46:39 PM PDT 24 Jul 10 05:46:43 PM PDT 24 875466008 ps
T1044 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1353703035 Jul 10 05:47:23 PM PDT 24 Jul 10 05:47:26 PM PDT 24 10006189 ps
T1045 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1893907058 Jul 10 05:47:04 PM PDT 24 Jul 10 05:47:07 PM PDT 24 31196774 ps
T1046 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2367409757 Jul 10 05:46:31 PM PDT 24 Jul 10 05:46:37 PM PDT 24 302222447 ps
T1047 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2754392711 Jul 10 05:47:24 PM PDT 24 Jul 10 05:47:27 PM PDT 24 20403139 ps
T178 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1551224311 Jul 10 05:46:50 PM PDT 24 Jul 10 05:46:58 PM PDT 24 3250148616 ps
T1048 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1290404083 Jul 10 05:47:17 PM PDT 24 Jul 10 05:47:24 PM PDT 24 205206790 ps
T1049 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1960445030 Jul 10 05:46:38 PM PDT 24 Jul 10 05:46:44 PM PDT 24 128053363 ps
T1050 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2126576430 Jul 10 05:46:31 PM PDT 24 Jul 10 05:46:34 PM PDT 24 190979871 ps
T1051 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2424419810 Jul 10 05:46:32 PM PDT 24 Jul 10 05:46:34 PM PDT 24 44064756 ps
T1052 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.540905771 Jul 10 05:47:22 PM PDT 24 Jul 10 05:47:23 PM PDT 24 7596579 ps
T1053 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1803691383 Jul 10 05:46:49 PM PDT 24 Jul 10 05:47:03 PM PDT 24 363288415 ps
T1054 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1801188578 Jul 10 05:46:51 PM PDT 24 Jul 10 05:46:54 PM PDT 24 35839979 ps
T1055 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2705948325 Jul 10 05:47:04 PM PDT 24 Jul 10 05:47:06 PM PDT 24 38925480 ps
T1056 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2625750040 Jul 10 05:47:16 PM PDT 24 Jul 10 05:47:17 PM PDT 24 31972633 ps
T1057 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.4089994055 Jul 10 05:47:16 PM PDT 24 Jul 10 05:47:17 PM PDT 24 81269071 ps
T1058 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3645619653 Jul 10 05:46:53 PM PDT 24 Jul 10 05:46:57 PM PDT 24 111657298 ps
T1059 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2664038741 Jul 10 05:46:40 PM PDT 24 Jul 10 05:46:49 PM PDT 24 242629055 ps
T1060 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.984716625 Jul 10 05:47:16 PM PDT 24 Jul 10 05:47:19 PM PDT 24 141758676 ps
T1061 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1005977341 Jul 10 05:46:47 PM PDT 24 Jul 10 05:46:51 PM PDT 24 25876617 ps
T177 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3465429440 Jul 10 05:46:44 PM PDT 24 Jul 10 05:46:50 PM PDT 24 144129574 ps
T1062 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3497484279 Jul 10 05:46:37 PM PDT 24 Jul 10 05:46:54 PM PDT 24 4748032590 ps
T1063 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2045619671 Jul 10 05:46:31 PM PDT 24 Jul 10 05:46:35 PM PDT 24 125390618 ps
T1064 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3511689792 Jul 10 05:47:15 PM PDT 24 Jul 10 05:47:18 PM PDT 24 34345270 ps
T1065 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.4286435104 Jul 10 05:46:34 PM PDT 24 Jul 10 05:46:37 PM PDT 24 74986345 ps
T1066 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.582417287 Jul 10 05:46:51 PM PDT 24 Jul 10 05:46:56 PM PDT 24 631519072 ps
T1067 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3584249806 Jul 10 05:46:26 PM PDT 24 Jul 10 05:46:29 PM PDT 24 85126953 ps
T1068 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3456470964 Jul 10 05:46:52 PM PDT 24 Jul 10 05:46:56 PM PDT 24 80869427 ps
T1069 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3602461134 Jul 10 05:46:57 PM PDT 24 Jul 10 05:47:04 PM PDT 24 890706996 ps
T179 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.526765101 Jul 10 05:46:48 PM PDT 24 Jul 10 05:46:56 PM PDT 24 629016794 ps
T1070 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2999651093 Jul 10 05:47:15 PM PDT 24 Jul 10 05:47:16 PM PDT 24 14594442 ps
T1071 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3053466076 Jul 10 05:47:04 PM PDT 24 Jul 10 05:47:06 PM PDT 24 19606604 ps
T1072 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3266258142 Jul 10 05:46:31 PM PDT 24 Jul 10 05:46:57 PM PDT 24 1951810563 ps
T1073 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2896882750 Jul 10 05:47:20 PM PDT 24 Jul 10 05:47:23 PM PDT 24 123838074 ps
T172 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1310772801 Jul 10 05:46:33 PM PDT 24 Jul 10 05:46:41 PM PDT 24 126329789 ps
T1074 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1602252612 Jul 10 05:46:45 PM PDT 24 Jul 10 05:46:48 PM PDT 24 59905346 ps
T1075 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2669547911 Jul 10 05:47:18 PM PDT 24 Jul 10 05:47:21 PM PDT 24 61900853 ps
T1076 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3186072337 Jul 10 05:47:06 PM PDT 24 Jul 10 05:47:11 PM PDT 24 201963574 ps
T1077 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.485934221 Jul 10 05:46:48 PM PDT 24 Jul 10 05:46:51 PM PDT 24 22394779 ps
T1078 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1348765197 Jul 10 05:47:25 PM PDT 24 Jul 10 05:47:29 PM PDT 24 10376877 ps
T1079 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2017560309 Jul 10 05:46:58 PM PDT 24 Jul 10 05:47:04 PM PDT 24 543348146 ps
T1080 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2481577267 Jul 10 05:47:09 PM PDT 24 Jul 10 05:47:13 PM PDT 24 36923806 ps
T1081 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4159341362 Jul 10 05:46:29 PM PDT 24 Jul 10 05:46:32 PM PDT 24 35068001 ps
T1082 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1666188686 Jul 10 05:46:57 PM PDT 24 Jul 10 05:47:02 PM PDT 24 102579110 ps
T1083 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.692655114 Jul 10 05:46:58 PM PDT 24 Jul 10 05:47:17 PM PDT 24 877054195 ps
T1084 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.228231538 Jul 10 05:46:26 PM PDT 24 Jul 10 05:46:31 PM PDT 24 175919744 ps

Test location /workspace/coverage/default/45.keymgr_custom_cm.1221928883
Short name T3
Test name
Test status
Simulation time 195036071 ps
CPU time 1.88 seconds
Started Jul 10 05:50:37 PM PDT 24
Finished Jul 10 05:50:40 PM PDT 24
Peak memory 217084 kb
Host smart-c6e7888f-1c35-402c-8451-f46204b8d3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221928883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1221928883
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.4079134014
Short name T50
Test name
Test status
Simulation time 602882548 ps
CPU time 26.36 seconds
Started Jul 10 05:49:36 PM PDT 24
Finished Jul 10 05:50:04 PM PDT 24
Peak memory 222324 kb
Host smart-e6709e7e-031e-4680-92ea-25fca778ee40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079134014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.4079134014
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2695489869
Short name T26
Test name
Test status
Simulation time 1185026914 ps
CPU time 9.02 seconds
Started Jul 10 05:48:09 PM PDT 24
Finished Jul 10 05:48:20 PM PDT 24
Peak memory 214316 kb
Host smart-f7c88836-8eda-4f8b-b745-fc901bf741ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695489869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2695489869
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3920583804
Short name T61
Test name
Test status
Simulation time 3711828285 ps
CPU time 37.18 seconds
Started Jul 10 05:48:16 PM PDT 24
Finished Jul 10 05:48:55 PM PDT 24
Peak memory 222556 kb
Host smart-3614d2f3-5127-4c78-b849-789779209c4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920583804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3920583804
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1294569863
Short name T12
Test name
Test status
Simulation time 279219409 ps
CPU time 8.82 seconds
Started Jul 10 05:48:11 PM PDT 24
Finished Jul 10 05:48:21 PM PDT 24
Peak memory 229264 kb
Host smart-3f08ca06-8e11-4ba0-850c-322169810af4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294569863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1294569863
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1610687569
Short name T52
Test name
Test status
Simulation time 464303320 ps
CPU time 15.31 seconds
Started Jul 10 05:48:59 PM PDT 24
Finished Jul 10 05:49:16 PM PDT 24
Peak memory 222448 kb
Host smart-15933c6f-b4e9-49e1-abd2-80050b2f6ed4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610687569 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1610687569
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2632948460
Short name T8
Test name
Test status
Simulation time 2821708970 ps
CPU time 28.94 seconds
Started Jul 10 05:48:36 PM PDT 24
Finished Jul 10 05:49:06 PM PDT 24
Peak memory 222604 kb
Host smart-c58429f0-e3a6-43a6-915e-482aff8a2546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632948460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2632948460
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3656234214
Short name T18
Test name
Test status
Simulation time 798657328 ps
CPU time 4.23 seconds
Started Jul 10 05:49:40 PM PDT 24
Finished Jul 10 05:49:45 PM PDT 24
Peak memory 214340 kb
Host smart-9c9f248c-f192-44c5-b032-ac24b2022bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656234214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3656234214
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2716699774
Short name T158
Test name
Test status
Simulation time 968556659 ps
CPU time 50.41 seconds
Started Jul 10 05:50:07 PM PDT 24
Finished Jul 10 05:51:01 PM PDT 24
Peak memory 214340 kb
Host smart-2a5e263a-d940-46c4-92cf-d45a12b83a30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716699774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2716699774
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.4219836654
Short name T10
Test name
Test status
Simulation time 171359120 ps
CPU time 5.12 seconds
Started Jul 10 05:50:30 PM PDT 24
Finished Jul 10 05:50:38 PM PDT 24
Peak memory 210372 kb
Host smart-db2a5812-bdb9-4d2e-8e44-116edf21770b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219836654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.4219836654
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2720926098
Short name T9
Test name
Test status
Simulation time 1067959994 ps
CPU time 20.79 seconds
Started Jul 10 05:50:28 PM PDT 24
Finished Jul 10 05:50:51 PM PDT 24
Peak memory 222616 kb
Host smart-49d93e0b-d09b-44e3-bfb2-c0469585f333
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720926098 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2720926098
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.485279423
Short name T116
Test name
Test status
Simulation time 291192137 ps
CPU time 2.3 seconds
Started Jul 10 05:47:02 PM PDT 24
Finished Jul 10 05:47:06 PM PDT 24
Peak memory 214008 kb
Host smart-1035750c-1f31-492b-bdd5-64bf904a0ec9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485279423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.485279423
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1909220854
Short name T51
Test name
Test status
Simulation time 1908590434 ps
CPU time 53.57 seconds
Started Jul 10 05:50:02 PM PDT 24
Finished Jul 10 05:50:58 PM PDT 24
Peak memory 216744 kb
Host smart-77bc92c8-3cfe-42c3-b217-32b2edc90bda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909220854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1909220854
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3215901346
Short name T23
Test name
Test status
Simulation time 2011992789 ps
CPU time 10.34 seconds
Started Jul 10 05:50:44 PM PDT 24
Finished Jul 10 05:50:56 PM PDT 24
Peak memory 214312 kb
Host smart-6cd77cd1-d69d-49b3-b203-ea9556e2a50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215901346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3215901346
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1772400580
Short name T416
Test name
Test status
Simulation time 1154212550 ps
CPU time 59.21 seconds
Started Jul 10 05:50:47 PM PDT 24
Finished Jul 10 05:51:48 PM PDT 24
Peak memory 215340 kb
Host smart-7b111ae7-8594-442e-8be5-b9f4bba89199
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772400580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1772400580
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.585174831
Short name T165
Test name
Test status
Simulation time 62820731 ps
CPU time 3.42 seconds
Started Jul 10 05:46:59 PM PDT 24
Finished Jul 10 05:47:05 PM PDT 24
Peak memory 213652 kb
Host smart-382000ab-d31e-4d83-8e41-f9cd85965720
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585174831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.585174831
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1410185366
Short name T122
Test name
Test status
Simulation time 106427717 ps
CPU time 6.37 seconds
Started Jul 10 05:48:58 PM PDT 24
Finished Jul 10 05:49:05 PM PDT 24
Peak memory 214332 kb
Host smart-131760b1-2607-4e5d-ad94-5d5b4a7435ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1410185366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1410185366
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3975747549
Short name T299
Test name
Test status
Simulation time 3613170072 ps
CPU time 53.54 seconds
Started Jul 10 05:49:24 PM PDT 24
Finished Jul 10 05:50:22 PM PDT 24
Peak memory 215908 kb
Host smart-e2341285-8cde-44a7-9ceb-29b53cc11831
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3975747549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3975747549
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3251495696
Short name T70
Test name
Test status
Simulation time 2646770030 ps
CPU time 22.16 seconds
Started Jul 10 05:49:54 PM PDT 24
Finished Jul 10 05:50:17 PM PDT 24
Peak memory 222740 kb
Host smart-c2563ba2-4372-4403-9bee-3a7332ccebad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251495696 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3251495696
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3718658392
Short name T39
Test name
Test status
Simulation time 10040192203 ps
CPU time 258.79 seconds
Started Jul 10 05:49:54 PM PDT 24
Finished Jul 10 05:54:14 PM PDT 24
Peak memory 216832 kb
Host smart-30ae631f-35d6-438d-a0ee-a43515b23f31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718658392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3718658392
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.4068393134
Short name T429
Test name
Test status
Simulation time 151504413 ps
CPU time 8.24 seconds
Started Jul 10 05:50:00 PM PDT 24
Finished Jul 10 05:50:10 PM PDT 24
Peak memory 214704 kb
Host smart-6be13f73-2711-4ff9-ae2f-0daa10c4c065
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4068393134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.4068393134
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1622518101
Short name T41
Test name
Test status
Simulation time 130399468 ps
CPU time 1.48 seconds
Started Jul 10 05:49:45 PM PDT 24
Finished Jul 10 05:49:48 PM PDT 24
Peak memory 210576 kb
Host smart-cf12fcf1-da86-4928-86b5-a33e42ee3e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622518101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1622518101
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.3484082307
Short name T127
Test name
Test status
Simulation time 465734639 ps
CPU time 15.38 seconds
Started Jul 10 05:50:01 PM PDT 24
Finished Jul 10 05:50:18 PM PDT 24
Peak memory 220864 kb
Host smart-457be6f4-6fe1-4cfe-9f27-b2455a42eb8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484082307 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.3484082307
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2307611291
Short name T360
Test name
Test status
Simulation time 3142829430 ps
CPU time 46.38 seconds
Started Jul 10 05:49:16 PM PDT 24
Finished Jul 10 05:50:05 PM PDT 24
Peak memory 214924 kb
Host smart-4d0c82ba-5ad2-4358-a799-771777c42ae0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2307611291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2307611291
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.681268995
Short name T46
Test name
Test status
Simulation time 103781241 ps
CPU time 4.03 seconds
Started Jul 10 05:50:24 PM PDT 24
Finished Jul 10 05:50:30 PM PDT 24
Peak memory 214296 kb
Host smart-4505360f-1dea-48a0-8891-35be2f064ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681268995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.681268995
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2557896354
Short name T77
Test name
Test status
Simulation time 2325322869 ps
CPU time 31.15 seconds
Started Jul 10 05:49:45 PM PDT 24
Finished Jul 10 05:50:17 PM PDT 24
Peak memory 215408 kb
Host smart-f8ae34d8-e512-489c-8fa6-b58e6b175bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557896354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2557896354
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1920406189
Short name T362
Test name
Test status
Simulation time 236254902 ps
CPU time 12.84 seconds
Started Jul 10 05:48:35 PM PDT 24
Finished Jul 10 05:48:50 PM PDT 24
Peak memory 214428 kb
Host smart-8adefa60-c331-463f-83cd-66aaf5f612be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1920406189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1920406189
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2422701891
Short name T161
Test name
Test status
Simulation time 220946042 ps
CPU time 10.55 seconds
Started Jul 10 05:48:29 PM PDT 24
Finished Jul 10 05:48:41 PM PDT 24
Peak memory 222700 kb
Host smart-2db2f649-8760-4078-b354-e5a2a40632ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422701891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2422701891
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3392260606
Short name T33
Test name
Test status
Simulation time 265167641 ps
CPU time 4.45 seconds
Started Jul 10 05:49:17 PM PDT 24
Finished Jul 10 05:49:24 PM PDT 24
Peak memory 220024 kb
Host smart-79f8a8b0-5ab2-4d39-9e1e-e7257afcff74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392260606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3392260606
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.279818203
Short name T258
Test name
Test status
Simulation time 450351842 ps
CPU time 5.51 seconds
Started Jul 10 05:49:41 PM PDT 24
Finished Jul 10 05:49:48 PM PDT 24
Peak memory 206140 kb
Host smart-7b4e28f9-7e6d-4856-986c-1b44e7afd542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279818203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.279818203
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2490368801
Short name T422
Test name
Test status
Simulation time 671194762 ps
CPU time 9.01 seconds
Started Jul 10 05:49:35 PM PDT 24
Finished Jul 10 05:49:46 PM PDT 24
Peak memory 214248 kb
Host smart-5de7b066-5932-4df3-81b2-3ca3ef1bd6d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2490368801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2490368801
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.735487904
Short name T20
Test name
Test status
Simulation time 129410086 ps
CPU time 4.26 seconds
Started Jul 10 05:48:14 PM PDT 24
Finished Jul 10 05:48:21 PM PDT 24
Peak memory 214692 kb
Host smart-ab40da29-6954-44e6-aa15-975ad1de6c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735487904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.735487904
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3645841289
Short name T59
Test name
Test status
Simulation time 646087724 ps
CPU time 12.07 seconds
Started Jul 10 05:49:40 PM PDT 24
Finished Jul 10 05:49:53 PM PDT 24
Peak memory 223048 kb
Host smart-9b35a017-3278-43c8-8758-aba1b1c6def8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645841289 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3645841289
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1408519056
Short name T149
Test name
Test status
Simulation time 2566031685 ps
CPU time 8.36 seconds
Started Jul 10 05:46:30 PM PDT 24
Finished Jul 10 05:46:40 PM PDT 24
Peak memory 205512 kb
Host smart-8935d4cf-4a0f-43ae-a363-c9a9949a26d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408519056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
408519056
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3082540176
Short name T438
Test name
Test status
Simulation time 12954346 ps
CPU time 0.74 seconds
Started Jul 10 05:48:43 PM PDT 24
Finished Jul 10 05:48:45 PM PDT 24
Peak memory 205936 kb
Host smart-daeb3c11-92ec-46a7-98d4-29c6d228c705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082540176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3082540176
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2599936804
Short name T176
Test name
Test status
Simulation time 516085910 ps
CPU time 7.08 seconds
Started Jul 10 05:46:33 PM PDT 24
Finished Jul 10 05:46:41 PM PDT 24
Peak memory 216012 kb
Host smart-4de1718b-7c3c-461d-a9ec-8c286586143b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599936804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2599936804
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.555569012
Short name T146
Test name
Test status
Simulation time 164123868 ps
CPU time 5.6 seconds
Started Jul 10 05:50:34 PM PDT 24
Finished Jul 10 05:50:41 PM PDT 24
Peak memory 214320 kb
Host smart-3906012b-ca12-433c-8357-1260838ba004
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=555569012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.555569012
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.4068159712
Short name T319
Test name
Test status
Simulation time 780428683 ps
CPU time 21.19 seconds
Started Jul 10 05:50:56 PM PDT 24
Finished Jul 10 05:51:19 PM PDT 24
Peak memory 216036 kb
Host smart-611df54a-e408-41ca-94b2-91722f2aeed2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068159712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.4068159712
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1115779474
Short name T228
Test name
Test status
Simulation time 15750476497 ps
CPU time 28.05 seconds
Started Jul 10 05:49:28 PM PDT 24
Finished Jul 10 05:50:01 PM PDT 24
Peak memory 222476 kb
Host smart-b734e371-6cb1-49c2-b89b-48e99641cf70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115779474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1115779474
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1216740110
Short name T225
Test name
Test status
Simulation time 237391615 ps
CPU time 13.01 seconds
Started Jul 10 05:50:54 PM PDT 24
Finished Jul 10 05:51:09 PM PDT 24
Peak memory 216192 kb
Host smart-159a5522-54e6-4173-8951-ab112137efd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216740110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1216740110
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1487566063
Short name T586
Test name
Test status
Simulation time 86867826 ps
CPU time 2.01 seconds
Started Jul 10 05:50:01 PM PDT 24
Finished Jul 10 05:50:04 PM PDT 24
Peak memory 214264 kb
Host smart-2ee42c5e-ed92-412c-b820-d6fc82e149a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487566063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1487566063
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.425370801
Short name T104
Test name
Test status
Simulation time 113609477 ps
CPU time 4.66 seconds
Started Jul 10 05:48:21 PM PDT 24
Finished Jul 10 05:48:28 PM PDT 24
Peak memory 214316 kb
Host smart-8f0f6be4-74cb-43f3-9f94-5c295e3aa62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425370801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.425370801
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.701491291
Short name T280
Test name
Test status
Simulation time 375262115 ps
CPU time 6.22 seconds
Started Jul 10 05:50:40 PM PDT 24
Finished Jul 10 05:50:48 PM PDT 24
Peak memory 215660 kb
Host smart-7b996a2b-2cc3-4589-96e7-1ed9b0bb3644
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=701491291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.701491291
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1829025053
Short name T310
Test name
Test status
Simulation time 404621669 ps
CPU time 21.67 seconds
Started Jul 10 05:49:32 PM PDT 24
Finished Jul 10 05:49:57 PM PDT 24
Peak memory 216456 kb
Host smart-4a599949-90fc-488d-802c-93161eea59b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829025053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1829025053
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3772600529
Short name T274
Test name
Test status
Simulation time 109451544 ps
CPU time 3.37 seconds
Started Jul 10 05:49:56 PM PDT 24
Finished Jul 10 05:50:01 PM PDT 24
Peak memory 214276 kb
Host smart-aebfd4dc-40b1-4e92-857e-9902e956c0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772600529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3772600529
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.30345076
Short name T171
Test name
Test status
Simulation time 356556812 ps
CPU time 10.35 seconds
Started Jul 10 05:46:58 PM PDT 24
Finished Jul 10 05:47:11 PM PDT 24
Peak memory 213624 kb
Host smart-487df238-8ee0-459f-8805-b19a4c0ea7f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30345076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.30345076
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3602461134
Short name T1069
Test name
Test status
Simulation time 890706996 ps
CPU time 4.06 seconds
Started Jul 10 05:46:57 PM PDT 24
Finished Jul 10 05:47:04 PM PDT 24
Peak memory 220188 kb
Host smart-1d7f2de5-604f-4007-a754-e95e9cbe8bba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602461134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3602461134
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2580725292
Short name T167
Test name
Test status
Simulation time 105246468 ps
CPU time 5.66 seconds
Started Jul 10 05:46:38 PM PDT 24
Finished Jul 10 05:46:45 PM PDT 24
Peak memory 213696 kb
Host smart-5bbb07f8-d00e-4c65-86f3-c1f7f3d5e272
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580725292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2580725292
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3135331913
Short name T65
Test name
Test status
Simulation time 180496760 ps
CPU time 2.66 seconds
Started Jul 10 05:48:25 PM PDT 24
Finished Jul 10 05:48:29 PM PDT 24
Peak memory 217168 kb
Host smart-63412043-5c6e-4146-a761-d6e24a702401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135331913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3135331913
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.529656186
Short name T253
Test name
Test status
Simulation time 1059094697 ps
CPU time 2.82 seconds
Started Jul 10 05:48:49 PM PDT 24
Finished Jul 10 05:48:53 PM PDT 24
Peak memory 214276 kb
Host smart-bfd18849-759c-4214-ac6b-1d87cbd9b617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529656186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.529656186
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1447870117
Short name T296
Test name
Test status
Simulation time 232122749 ps
CPU time 3.55 seconds
Started Jul 10 05:49:11 PM PDT 24
Finished Jul 10 05:49:17 PM PDT 24
Peak memory 220404 kb
Host smart-82c9c063-050c-43fa-bce8-4887427fedfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447870117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1447870117
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2853222798
Short name T351
Test name
Test status
Simulation time 2251287149 ps
CPU time 108.87 seconds
Started Jul 10 05:50:19 PM PDT 24
Finished Jul 10 05:52:11 PM PDT 24
Peak memory 214556 kb
Host smart-82a1e658-9da2-4a5b-80e9-a394faaad7cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853222798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2853222798
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3389338271
Short name T207
Test name
Test status
Simulation time 67437046 ps
CPU time 3.28 seconds
Started Jul 10 05:49:00 PM PDT 24
Finished Jul 10 05:49:04 PM PDT 24
Peak memory 210152 kb
Host smart-b866a9ed-0686-4cee-bd4b-e2012e09a4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389338271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3389338271
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1310772801
Short name T172
Test name
Test status
Simulation time 126329789 ps
CPU time 5.85 seconds
Started Jul 10 05:46:33 PM PDT 24
Finished Jul 10 05:46:41 PM PDT 24
Peak memory 205560 kb
Host smart-b99d5d68-b281-46c8-825d-4233aa5838e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310772801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1310772801
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2862872621
Short name T182
Test name
Test status
Simulation time 209422094 ps
CPU time 8.73 seconds
Started Jul 10 05:46:44 PM PDT 24
Finished Jul 10 05:46:54 PM PDT 24
Peak memory 205504 kb
Host smart-37e728d3-c588-4529-95ef-d84da80b80a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862872621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2862872621
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1551224311
Short name T178
Test name
Test status
Simulation time 3250148616 ps
CPU time 5.83 seconds
Started Jul 10 05:46:50 PM PDT 24
Finished Jul 10 05:46:58 PM PDT 24
Peak memory 213840 kb
Host smart-75fec5f8-32fa-40d8-b10c-1326cf3fcc1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551224311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1551224311
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2086752220
Short name T164
Test name
Test status
Simulation time 261593517 ps
CPU time 3.77 seconds
Started Jul 10 05:48:33 PM PDT 24
Finished Jul 10 05:48:39 PM PDT 24
Peak memory 218320 kb
Host smart-006e49f0-bd6a-4e56-a845-279744b6d3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086752220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2086752220
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1684878892
Short name T757
Test name
Test status
Simulation time 186220432 ps
CPU time 4.54 seconds
Started Jul 10 05:49:15 PM PDT 24
Finished Jul 10 05:49:23 PM PDT 24
Peak memory 222444 kb
Host smart-5bb572d8-0c54-4880-973d-627e930eabb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684878892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1684878892
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3937631554
Short name T285
Test name
Test status
Simulation time 138528336 ps
CPU time 2.72 seconds
Started Jul 10 05:50:33 PM PDT 24
Finished Jul 10 05:50:37 PM PDT 24
Peak memory 214240 kb
Host smart-289eb888-6b07-48a3-bc48-38c55c0dfb5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3937631554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3937631554
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1711517632
Short name T168
Test name
Test status
Simulation time 316000739 ps
CPU time 7.73 seconds
Started Jul 10 05:47:09 PM PDT 24
Finished Jul 10 05:47:18 PM PDT 24
Peak memory 213704 kb
Host smart-9a5a5ad3-541d-403a-ab2c-9ea4a991bfe8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711517632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1711517632
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2651730112
Short name T244
Test name
Test status
Simulation time 152920231 ps
CPU time 3.47 seconds
Started Jul 10 05:49:59 PM PDT 24
Finished Jul 10 05:50:03 PM PDT 24
Peak memory 217628 kb
Host smart-9f4b5960-f436-4617-abfe-0dbbac9a63a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651730112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2651730112
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3219237175
Short name T113
Test name
Test status
Simulation time 72349067 ps
CPU time 2.72 seconds
Started Jul 10 05:49:59 PM PDT 24
Finished Jul 10 05:50:03 PM PDT 24
Peak memory 222692 kb
Host smart-df2d90c4-e400-4ab0-a670-fa478df195d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219237175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3219237175
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.306539371
Short name T391
Test name
Test status
Simulation time 402238411 ps
CPU time 4.51 seconds
Started Jul 10 05:48:14 PM PDT 24
Finished Jul 10 05:48:21 PM PDT 24
Peak memory 214340 kb
Host smart-ff324a6b-0099-40cf-8342-2c8648d979a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306539371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.306539371
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3123894528
Short name T270
Test name
Test status
Simulation time 2746460491 ps
CPU time 4.4 seconds
Started Jul 10 05:48:04 PM PDT 24
Finished Jul 10 05:48:10 PM PDT 24
Peak memory 208784 kb
Host smart-6688ee89-2d7e-45fd-88f3-8759be9e29df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123894528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3123894528
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1521291189
Short name T607
Test name
Test status
Simulation time 1204237536 ps
CPU time 16.55 seconds
Started Jul 10 05:48:06 PM PDT 24
Finished Jul 10 05:48:25 PM PDT 24
Peak memory 208952 kb
Host smart-042f422d-58a2-4e19-bcaa-1c2996ad8516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521291189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1521291189
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.115652956
Short name T389
Test name
Test status
Simulation time 865059688 ps
CPU time 3.59 seconds
Started Jul 10 05:48:36 PM PDT 24
Finished Jul 10 05:48:42 PM PDT 24
Peak memory 221328 kb
Host smart-f6b4fa0c-112a-4d5a-ab47-d9177572b7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115652956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.115652956
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.4275473794
Short name T89
Test name
Test status
Simulation time 119546197 ps
CPU time 1.97 seconds
Started Jul 10 05:48:40 PM PDT 24
Finished Jul 10 05:48:44 PM PDT 24
Peak memory 206112 kb
Host smart-0ef15b71-850c-4530-8cb4-4e3e33570cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275473794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.4275473794
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2467942041
Short name T277
Test name
Test status
Simulation time 204449507 ps
CPU time 4.76 seconds
Started Jul 10 05:48:44 PM PDT 24
Finished Jul 10 05:48:51 PM PDT 24
Peak memory 218476 kb
Host smart-5729fbe1-1751-4b9a-84aa-7e5ab989c83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467942041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2467942041
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.311785302
Short name T346
Test name
Test status
Simulation time 147584656 ps
CPU time 8.03 seconds
Started Jul 10 05:48:56 PM PDT 24
Finished Jul 10 05:49:05 PM PDT 24
Peak memory 214416 kb
Host smart-7155bac6-cffd-45ab-835a-24995302e9fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311785302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.311785302
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.372835045
Short name T107
Test name
Test status
Simulation time 756512447 ps
CPU time 5.62 seconds
Started Jul 10 05:49:00 PM PDT 24
Finished Jul 10 05:49:07 PM PDT 24
Peak memory 208584 kb
Host smart-323b852e-e22e-4547-b9ec-d0b3df047d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372835045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.372835045
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1028472232
Short name T235
Test name
Test status
Simulation time 76074234 ps
CPU time 3.47 seconds
Started Jul 10 05:48:25 PM PDT 24
Finished Jul 10 05:48:30 PM PDT 24
Peak memory 222516 kb
Host smart-3130a80e-e4d8-4873-a914-32c897b5e0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028472232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1028472232
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.4054477096
Short name T174
Test name
Test status
Simulation time 171821532 ps
CPU time 9.18 seconds
Started Jul 10 05:49:23 PM PDT 24
Finished Jul 10 05:49:36 PM PDT 24
Peak memory 222632 kb
Host smart-67efad64-ab18-498d-a491-dbe06bfbcaf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054477096 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.4054477096
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3270484813
Short name T308
Test name
Test status
Simulation time 11358456315 ps
CPU time 30.3 seconds
Started Jul 10 05:49:30 PM PDT 24
Finished Jul 10 05:50:05 PM PDT 24
Peak memory 218076 kb
Host smart-9eb5e37a-3e43-4ed3-8c41-697096246a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270484813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3270484813
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2805345897
Short name T262
Test name
Test status
Simulation time 228389984 ps
CPU time 3.6 seconds
Started Jul 10 05:49:24 PM PDT 24
Finished Jul 10 05:49:31 PM PDT 24
Peak memory 221460 kb
Host smart-d427aa0d-0820-450b-a852-57d2ab1353c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805345897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2805345897
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.4056959451
Short name T373
Test name
Test status
Simulation time 132780407 ps
CPU time 6.61 seconds
Started Jul 10 05:49:55 PM PDT 24
Finished Jul 10 05:50:03 PM PDT 24
Peak memory 215680 kb
Host smart-7e4ecde0-9272-46d7-9044-f66bb1b5fd26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056959451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.4056959451
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1598086058
Short name T199
Test name
Test status
Simulation time 597281919 ps
CPU time 6.61 seconds
Started Jul 10 05:50:03 PM PDT 24
Finished Jul 10 05:50:12 PM PDT 24
Peak memory 215132 kb
Host smart-548d3e83-2e9e-40b1-a26d-d67f2da676d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598086058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1598086058
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2333733540
Short name T869
Test name
Test status
Simulation time 938220203 ps
CPU time 38.88 seconds
Started Jul 10 05:50:13 PM PDT 24
Finished Jul 10 05:50:56 PM PDT 24
Peak memory 221872 kb
Host smart-03c8490b-2668-44e4-bc8b-0cc80dc2843b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333733540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2333733540
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1961756076
Short name T22
Test name
Test status
Simulation time 360911799 ps
CPU time 2.1 seconds
Started Jul 10 05:48:32 PM PDT 24
Finished Jul 10 05:48:36 PM PDT 24
Peak memory 216652 kb
Host smart-bb245a65-1123-4725-a313-f45543143baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961756076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1961756076
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3465429440
Short name T177
Test name
Test status
Simulation time 144129574 ps
CPU time 5.1 seconds
Started Jul 10 05:46:44 PM PDT 24
Finished Jul 10 05:46:50 PM PDT 24
Peak memory 213732 kb
Host smart-ea2336e3-a970-468c-92b5-1a8b1bfa02b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465429440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3465429440
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.526765101
Short name T179
Test name
Test status
Simulation time 629016794 ps
CPU time 6.18 seconds
Started Jul 10 05:46:48 PM PDT 24
Finished Jul 10 05:46:56 PM PDT 24
Peak memory 213700 kb
Host smart-5821d7f2-ecc9-4f07-9700-cb6bbd48a538
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526765101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
526765101
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1651434833
Short name T13
Test name
Test status
Simulation time 2013667313 ps
CPU time 13.17 seconds
Started Jul 10 05:48:22 PM PDT 24
Finished Jul 10 05:48:37 PM PDT 24
Peak memory 234716 kb
Host smart-22589dd9-b471-4286-9935-5882677bb203
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651434833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1651434833
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.53692560
Short name T103
Test name
Test status
Simulation time 132012861 ps
CPU time 2.71 seconds
Started Jul 10 05:48:32 PM PDT 24
Finished Jul 10 05:48:37 PM PDT 24
Peak memory 219532 kb
Host smart-15db0f5d-7bd4-4126-a75f-13d531275e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53692560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.53692560
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2535918781
Short name T160
Test name
Test status
Simulation time 159976259 ps
CPU time 7.37 seconds
Started Jul 10 05:49:48 PM PDT 24
Finished Jul 10 05:49:56 PM PDT 24
Peak memory 218036 kb
Host smart-6bdb2f60-0551-46ff-abe7-28b085c51220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535918781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2535918781
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1214748578
Short name T162
Test name
Test status
Simulation time 44039423 ps
CPU time 2.84 seconds
Started Jul 10 05:49:12 PM PDT 24
Finished Jul 10 05:49:17 PM PDT 24
Peak memory 217700 kb
Host smart-f3bf7ea8-101f-4464-b68c-1cd0852eecfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214748578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1214748578
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3956532334
Short name T827
Test name
Test status
Simulation time 230236176 ps
CPU time 4.53 seconds
Started Jul 10 05:48:02 PM PDT 24
Finished Jul 10 05:48:08 PM PDT 24
Peak memory 208904 kb
Host smart-5059b89b-261a-4c39-a1ad-6a9a087da232
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956532334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3956532334
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2808432932
Short name T276
Test name
Test status
Simulation time 83255986 ps
CPU time 3.36 seconds
Started Jul 10 05:48:14 PM PDT 24
Finished Jul 10 05:48:20 PM PDT 24
Peak memory 215312 kb
Host smart-ac779e5d-e533-4eae-a27a-c3cad45fde92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2808432932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2808432932
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_random.2263990244
Short name T271
Test name
Test status
Simulation time 2233480708 ps
CPU time 10.27 seconds
Started Jul 10 05:48:39 PM PDT 24
Finished Jul 10 05:48:51 PM PDT 24
Peak memory 218624 kb
Host smart-eb41cde1-f367-4003-adbb-0184001a5e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263990244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2263990244
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2195228242
Short name T507
Test name
Test status
Simulation time 1536622922 ps
CPU time 37.35 seconds
Started Jul 10 05:48:44 PM PDT 24
Finished Jul 10 05:49:23 PM PDT 24
Peak memory 209096 kb
Host smart-f620a6a4-ee10-424d-b6a3-ffb3ac084fc2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195228242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2195228242
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.848522629
Short name T284
Test name
Test status
Simulation time 126967909 ps
CPU time 4.51 seconds
Started Jul 10 05:48:48 PM PDT 24
Finished Jul 10 05:48:54 PM PDT 24
Peak memory 218308 kb
Host smart-feb94159-1dd7-4934-9f9e-cf21f6fbb7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848522629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.848522629
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.5148998
Short name T359
Test name
Test status
Simulation time 733376342 ps
CPU time 2.41 seconds
Started Jul 10 05:48:53 PM PDT 24
Finished Jul 10 05:48:57 PM PDT 24
Peak memory 214212 kb
Host smart-27d03590-5cc8-46ef-8cbf-285af47fa696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5148998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.5148998
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2057557467
Short name T238
Test name
Test status
Simulation time 4725609209 ps
CPU time 46.42 seconds
Started Jul 10 05:48:57 PM PDT 24
Finished Jul 10 05:49:45 PM PDT 24
Peak memory 216236 kb
Host smart-772c6c63-793e-4a0a-a10f-7c558b165e61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057557467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2057557467
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.288587488
Short name T198
Test name
Test status
Simulation time 64865913 ps
CPU time 3.93 seconds
Started Jul 10 05:49:15 PM PDT 24
Finished Jul 10 05:49:21 PM PDT 24
Peak memory 207716 kb
Host smart-b31ac1d3-3ed4-40fd-9adf-b85ed3da8645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288587488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.288587488
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3117255272
Short name T327
Test name
Test status
Simulation time 44185293 ps
CPU time 3.15 seconds
Started Jul 10 05:49:18 PM PDT 24
Finished Jul 10 05:49:24 PM PDT 24
Peak memory 214352 kb
Host smart-1a4a9b4f-92f6-46af-8826-bd4043898cf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117255272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3117255272
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.4194363574
Short name T100
Test name
Test status
Simulation time 2328233937 ps
CPU time 8.69 seconds
Started Jul 10 05:49:27 PM PDT 24
Finished Jul 10 05:49:40 PM PDT 24
Peak memory 214384 kb
Host smart-34826a5b-1ceb-4fd3-b371-0fe256eb890d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194363574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.4194363574
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1112123513
Short name T273
Test name
Test status
Simulation time 101911409 ps
CPU time 2.46 seconds
Started Jul 10 05:49:34 PM PDT 24
Finished Jul 10 05:49:38 PM PDT 24
Peak memory 214172 kb
Host smart-a98aefd8-cbea-4903-94ea-4fe97a1a5d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112123513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1112123513
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2540890509
Short name T363
Test name
Test status
Simulation time 263807341 ps
CPU time 3.71 seconds
Started Jul 10 05:49:43 PM PDT 24
Finished Jul 10 05:49:47 PM PDT 24
Peak memory 207896 kb
Host smart-1cb85c7f-9670-48e7-8403-e70c18a94b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540890509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2540890509
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2225166039
Short name T278
Test name
Test status
Simulation time 4457962829 ps
CPU time 8.78 seconds
Started Jul 10 05:49:39 PM PDT 24
Finished Jul 10 05:49:49 PM PDT 24
Peak memory 218320 kb
Host smart-2df342cf-338e-4da6-b535-63c8b3b36740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225166039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2225166039
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2562987981
Short name T314
Test name
Test status
Simulation time 211650223 ps
CPU time 5.27 seconds
Started Jul 10 05:48:18 PM PDT 24
Finished Jul 10 05:48:25 PM PDT 24
Peak memory 222444 kb
Host smart-053fded0-542d-4a8a-afae-c340a750fe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562987981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2562987981
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3424843418
Short name T368
Test name
Test status
Simulation time 535464363 ps
CPU time 6.34 seconds
Started Jul 10 05:49:54 PM PDT 24
Finished Jul 10 05:50:02 PM PDT 24
Peak memory 214636 kb
Host smart-3d247963-fa9d-44ea-a215-4efac918a773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424843418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3424843418
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2887395517
Short name T78
Test name
Test status
Simulation time 47666239662 ps
CPU time 298.34 seconds
Started Jul 10 05:50:15 PM PDT 24
Finished Jul 10 05:55:18 PM PDT 24
Peak memory 221672 kb
Host smart-2bc3bec2-617d-40aa-b50a-c968a2e77459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887395517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2887395517
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2098409510
Short name T264
Test name
Test status
Simulation time 184829135 ps
CPU time 3.55 seconds
Started Jul 10 05:50:23 PM PDT 24
Finished Jul 10 05:50:29 PM PDT 24
Peak memory 215056 kb
Host smart-db578eeb-fa8a-4e93-a9b4-d7179739a2e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2098409510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2098409510
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2887620196
Short name T42
Test name
Test status
Simulation time 104474901 ps
CPU time 2.13 seconds
Started Jul 10 05:50:22 PM PDT 24
Finished Jul 10 05:50:26 PM PDT 24
Peak memory 206064 kb
Host smart-13e7fd16-94e0-4c03-a9bc-4af512bf6065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887620196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2887620196
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3799522676
Short name T243
Test name
Test status
Simulation time 327735861 ps
CPU time 7.77 seconds
Started Jul 10 05:50:22 PM PDT 24
Finished Jul 10 05:50:32 PM PDT 24
Peak memory 220592 kb
Host smart-8a28968c-6c55-4491-9102-0bda318595ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799522676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3799522676
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.998032936
Short name T1009
Test name
Test status
Simulation time 4946269906 ps
CPU time 14.98 seconds
Started Jul 10 05:46:30 PM PDT 24
Finished Jul 10 05:46:46 PM PDT 24
Peak memory 205404 kb
Host smart-2ee25f03-19e8-41eb-b62a-32c2f8326d4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998032936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.998032936
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2424419810
Short name T1051
Test name
Test status
Simulation time 44064756 ps
CPU time 0.96 seconds
Started Jul 10 05:46:32 PM PDT 24
Finished Jul 10 05:46:34 PM PDT 24
Peak memory 205384 kb
Host smart-32cd105d-1c7e-4043-a94b-11803956803b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424419810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
424419810
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.4286435104
Short name T1065
Test name
Test status
Simulation time 74986345 ps
CPU time 1.45 seconds
Started Jul 10 05:46:34 PM PDT 24
Finished Jul 10 05:46:37 PM PDT 24
Peak memory 213776 kb
Host smart-263da753-3888-46be-a07d-3fff0aad367f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286435104 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.4286435104
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2460103744
Short name T934
Test name
Test status
Simulation time 152708715 ps
CPU time 1.19 seconds
Started Jul 10 05:46:33 PM PDT 24
Finished Jul 10 05:46:35 PM PDT 24
Peak memory 205524 kb
Host smart-a0ec8e74-bf43-4379-8ba4-2793f35692e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460103744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2460103744
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1549422298
Short name T976
Test name
Test status
Simulation time 16165263 ps
CPU time 0.73 seconds
Started Jul 10 05:46:30 PM PDT 24
Finished Jul 10 05:46:32 PM PDT 24
Peak memory 205552 kb
Host smart-8e138c80-1c36-4173-9452-58446fab5c27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549422298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1549422298
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4159341362
Short name T1081
Test name
Test status
Simulation time 35068001 ps
CPU time 1.95 seconds
Started Jul 10 05:46:29 PM PDT 24
Finished Jul 10 05:46:32 PM PDT 24
Peak memory 205464 kb
Host smart-0e472c3f-13aa-40d2-913b-e034d2074db7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159341362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.4159341362
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.997091509
Short name T971
Test name
Test status
Simulation time 528649396 ps
CPU time 3.33 seconds
Started Jul 10 05:46:27 PM PDT 24
Finished Jul 10 05:46:32 PM PDT 24
Peak memory 214068 kb
Host smart-1aee5443-ffc9-4805-8917-1874f722cf34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997091509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.997091509
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.228231538
Short name T1084
Test name
Test status
Simulation time 175919744 ps
CPU time 3.81 seconds
Started Jul 10 05:46:26 PM PDT 24
Finished Jul 10 05:46:31 PM PDT 24
Peak memory 213892 kb
Host smart-412af666-8aa3-4644-994f-626e6cfaea03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228231538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.228231538
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3584249806
Short name T1067
Test name
Test status
Simulation time 85126953 ps
CPU time 1.75 seconds
Started Jul 10 05:46:26 PM PDT 24
Finished Jul 10 05:46:29 PM PDT 24
Peak memory 213716 kb
Host smart-2873e346-24bf-4f5c-8db3-c6f9107a8a85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584249806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3584249806
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1706112145
Short name T150
Test name
Test status
Simulation time 132892131 ps
CPU time 3.99 seconds
Started Jul 10 05:46:33 PM PDT 24
Finished Jul 10 05:46:38 PM PDT 24
Peak memory 205592 kb
Host smart-e355a3e8-6461-4fbe-9631-4f9ddf0ceb7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706112145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
706112145
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3266258142
Short name T1072
Test name
Test status
Simulation time 1951810563 ps
CPU time 24.16 seconds
Started Jul 10 05:46:31 PM PDT 24
Finished Jul 10 05:46:57 PM PDT 24
Peak memory 205452 kb
Host smart-0f7673ff-64f6-400e-90e4-3dacb101dfc9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266258142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
266258142
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2126576430
Short name T1050
Test name
Test status
Simulation time 190979871 ps
CPU time 1.24 seconds
Started Jul 10 05:46:31 PM PDT 24
Finished Jul 10 05:46:34 PM PDT 24
Peak memory 205476 kb
Host smart-3d34b14b-75d1-4e70-8e48-e5c775404c78
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126576430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
126576430
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2045619671
Short name T1063
Test name
Test status
Simulation time 125390618 ps
CPU time 2.22 seconds
Started Jul 10 05:46:31 PM PDT 24
Finished Jul 10 05:46:35 PM PDT 24
Peak memory 213860 kb
Host smart-20e96349-f8ea-4141-b6cd-dc5d8a96b9da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045619671 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2045619671
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1021468655
Short name T155
Test name
Test status
Simulation time 180080473 ps
CPU time 1.36 seconds
Started Jul 10 05:46:30 PM PDT 24
Finished Jul 10 05:46:33 PM PDT 24
Peak memory 205520 kb
Host smart-3a21e106-5702-4dab-9894-e52e97cdc346
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021468655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1021468655
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.366558083
Short name T1022
Test name
Test status
Simulation time 116277318 ps
CPU time 0.69 seconds
Started Jul 10 05:46:31 PM PDT 24
Finished Jul 10 05:46:33 PM PDT 24
Peak memory 205324 kb
Host smart-1bca9a84-9ae3-42a2-baeb-8f635dbd5910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366558083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.366558083
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1196410014
Short name T986
Test name
Test status
Simulation time 118113259 ps
CPU time 2.86 seconds
Started Jul 10 05:46:31 PM PDT 24
Finished Jul 10 05:46:35 PM PDT 24
Peak memory 205552 kb
Host smart-f14a2029-1bf0-4ba7-a685-8545946d1060
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196410014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1196410014
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2632351455
Short name T120
Test name
Test status
Simulation time 547449668 ps
CPU time 2.11 seconds
Started Jul 10 05:46:30 PM PDT 24
Finished Jul 10 05:46:33 PM PDT 24
Peak memory 214032 kb
Host smart-b020caf0-e65c-496a-ae29-6f9cb20d176a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632351455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2632351455
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2901312754
Short name T977
Test name
Test status
Simulation time 496790061 ps
CPU time 4.92 seconds
Started Jul 10 05:46:35 PM PDT 24
Finished Jul 10 05:46:41 PM PDT 24
Peak memory 214000 kb
Host smart-c9cb2e4d-5a6f-4981-b840-19dc14e69121
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901312754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2901312754
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2041644224
Short name T966
Test name
Test status
Simulation time 113739287 ps
CPU time 1.98 seconds
Started Jul 10 05:46:31 PM PDT 24
Finished Jul 10 05:46:35 PM PDT 24
Peak memory 213684 kb
Host smart-e59c67d6-0285-413f-8ab8-f603aa0b69b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041644224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2041644224
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3352301476
Short name T1031
Test name
Test status
Simulation time 99768677 ps
CPU time 1.36 seconds
Started Jul 10 05:46:58 PM PDT 24
Finished Jul 10 05:47:02 PM PDT 24
Peak memory 205812 kb
Host smart-dcd42170-0370-41ec-90bd-9209a55e4b2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352301476 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3352301476
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4238340155
Short name T938
Test name
Test status
Simulation time 131442215 ps
CPU time 0.98 seconds
Started Jul 10 05:46:57 PM PDT 24
Finished Jul 10 05:47:01 PM PDT 24
Peak memory 205432 kb
Host smart-b7a5ca54-15b9-465d-a9ee-1ca4df9e4d92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238340155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.4238340155
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2064683070
Short name T1002
Test name
Test status
Simulation time 14420945 ps
CPU time 0.72 seconds
Started Jul 10 05:46:56 PM PDT 24
Finished Jul 10 05:47:00 PM PDT 24
Peak memory 205284 kb
Host smart-a420a753-bbae-4b08-8e47-ceda2b2311b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064683070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2064683070
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2884831811
Short name T1004
Test name
Test status
Simulation time 124174996 ps
CPU time 2.36 seconds
Started Jul 10 05:46:58 PM PDT 24
Finished Jul 10 05:47:03 PM PDT 24
Peak memory 205488 kb
Host smart-8c726e59-e0ad-494f-87ef-7479294b7d96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884831811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2884831811
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.239431150
Short name T1027
Test name
Test status
Simulation time 1130084567 ps
CPU time 5.45 seconds
Started Jul 10 05:46:51 PM PDT 24
Finished Jul 10 05:46:58 PM PDT 24
Peak memory 214012 kb
Host smart-2754d035-fcc2-45f5-9c39-1a3f7b0973f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239431150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.239431150
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.692655114
Short name T1083
Test name
Test status
Simulation time 877054195 ps
CPU time 15.85 seconds
Started Jul 10 05:46:58 PM PDT 24
Finished Jul 10 05:47:17 PM PDT 24
Peak memory 214012 kb
Host smart-ed9f547f-15d9-4a66-82a7-bace1ee46208
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692655114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.692655114
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1880554199
Short name T1012
Test name
Test status
Simulation time 82764765 ps
CPU time 2.66 seconds
Started Jul 10 05:46:59 PM PDT 24
Finished Jul 10 05:47:05 PM PDT 24
Peak memory 213676 kb
Host smart-6a842788-bec4-4a53-ab95-631303fff218
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880554199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1880554199
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1666188686
Short name T1082
Test name
Test status
Simulation time 102579110 ps
CPU time 2.13 seconds
Started Jul 10 05:46:57 PM PDT 24
Finished Jul 10 05:47:02 PM PDT 24
Peak memory 219152 kb
Host smart-ce3e4229-0d42-41be-a59a-c828723a099b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666188686 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1666188686
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.483154182
Short name T1023
Test name
Test status
Simulation time 27598375 ps
CPU time 1.61 seconds
Started Jul 10 05:47:00 PM PDT 24
Finished Jul 10 05:47:04 PM PDT 24
Peak memory 205504 kb
Host smart-5885eca0-7ca4-4801-bd6e-5dd955de7ac5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483154182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.483154182
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.81357536
Short name T1036
Test name
Test status
Simulation time 10543065 ps
CPU time 0.85 seconds
Started Jul 10 05:46:56 PM PDT 24
Finished Jul 10 05:47:00 PM PDT 24
Peak memory 205320 kb
Host smart-10952738-56a1-46cb-b8ef-eb1980091f04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81357536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.81357536
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3116923549
Short name T1039
Test name
Test status
Simulation time 29416125 ps
CPU time 1.42 seconds
Started Jul 10 05:46:57 PM PDT 24
Finished Jul 10 05:47:01 PM PDT 24
Peak memory 205488 kb
Host smart-bb37d8a7-6842-4374-b31e-50b92e3094a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116923549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3116923549
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1044501612
Short name T119
Test name
Test status
Simulation time 84142165 ps
CPU time 1.41 seconds
Started Jul 10 05:46:58 PM PDT 24
Finished Jul 10 05:47:02 PM PDT 24
Peak memory 213956 kb
Host smart-a0f1bc15-b6be-41a3-bc8b-58ff78589f15
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044501612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1044501612
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1846906721
Short name T996
Test name
Test status
Simulation time 1317267189 ps
CPU time 3.25 seconds
Started Jul 10 05:46:58 PM PDT 24
Finished Jul 10 05:47:04 PM PDT 24
Peak memory 216012 kb
Host smart-230329a5-c40c-4a47-a5f4-1fdd8d020090
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846906721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1846906721
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2605828387
Short name T974
Test name
Test status
Simulation time 188999779 ps
CPU time 1.73 seconds
Started Jul 10 05:46:59 PM PDT 24
Finished Jul 10 05:47:03 PM PDT 24
Peak memory 213788 kb
Host smart-3dc2c035-955b-479d-8606-911326d59790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605828387 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2605828387
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1798090599
Short name T932
Test name
Test status
Simulation time 21859133 ps
CPU time 0.99 seconds
Started Jul 10 05:46:57 PM PDT 24
Finished Jul 10 05:47:01 PM PDT 24
Peak memory 205372 kb
Host smart-13bf8d55-894d-48de-9433-8d1483831120
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798090599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1798090599
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.4241319099
Short name T1016
Test name
Test status
Simulation time 42416795 ps
CPU time 0.87 seconds
Started Jul 10 05:46:56 PM PDT 24
Finished Jul 10 05:47:00 PM PDT 24
Peak memory 205360 kb
Host smart-c43ce2b6-d0ce-4cea-8701-bd40740684ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241319099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.4241319099
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.74720581
Short name T999
Test name
Test status
Simulation time 103342053 ps
CPU time 2.45 seconds
Started Jul 10 05:46:59 PM PDT 24
Finished Jul 10 05:47:04 PM PDT 24
Peak memory 205456 kb
Host smart-37a57977-1118-41fd-9a85-0f3693bd49f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74720581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sam
e_csr_outstanding.74720581
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3895418774
Short name T125
Test name
Test status
Simulation time 104590849 ps
CPU time 2.49 seconds
Started Jul 10 05:46:56 PM PDT 24
Finished Jul 10 05:47:02 PM PDT 24
Peak memory 214096 kb
Host smart-f03f364d-1477-4acd-a439-45182a228e91
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895418774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3895418774
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3393136315
Short name T984
Test name
Test status
Simulation time 232900752 ps
CPU time 5.75 seconds
Started Jul 10 05:46:58 PM PDT 24
Finished Jul 10 05:47:07 PM PDT 24
Peak memory 220040 kb
Host smart-17f19f56-102b-45b9-a83c-871f826ee63f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393136315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3393136315
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.4150785069
Short name T953
Test name
Test status
Simulation time 691573971 ps
CPU time 5.91 seconds
Started Jul 10 05:46:57 PM PDT 24
Finished Jul 10 05:47:06 PM PDT 24
Peak memory 216852 kb
Host smart-c6ef2e92-0613-45ca-93cb-8966b038e2ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150785069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.4150785069
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1901142066
Short name T397
Test name
Test status
Simulation time 919394806 ps
CPU time 2.53 seconds
Started Jul 10 05:47:00 PM PDT 24
Finished Jul 10 05:47:05 PM PDT 24
Peak memory 205508 kb
Host smart-a4c3fe97-6076-4bb5-ab89-396c88821562
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901142066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1901142066
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2851019520
Short name T927
Test name
Test status
Simulation time 24763444 ps
CPU time 1.41 seconds
Started Jul 10 05:47:03 PM PDT 24
Finished Jul 10 05:47:06 PM PDT 24
Peak memory 205668 kb
Host smart-2e56e7be-ed9a-407d-a7a5-661416c317d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851019520 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2851019520
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2222814532
Short name T1014
Test name
Test status
Simulation time 34960702 ps
CPU time 0.98 seconds
Started Jul 10 05:47:05 PM PDT 24
Finished Jul 10 05:47:07 PM PDT 24
Peak memory 205316 kb
Host smart-fde5c9bb-7984-4749-aaf7-b2a5f99ccb79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222814532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2222814532
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3053466076
Short name T1071
Test name
Test status
Simulation time 19606604 ps
CPU time 0.74 seconds
Started Jul 10 05:47:04 PM PDT 24
Finished Jul 10 05:47:06 PM PDT 24
Peak memory 205272 kb
Host smart-71232b26-3112-41af-8fec-3e8d7f35344b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053466076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3053466076
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4270389901
Short name T148
Test name
Test status
Simulation time 575226740 ps
CPU time 3.96 seconds
Started Jul 10 05:47:03 PM PDT 24
Finished Jul 10 05:47:09 PM PDT 24
Peak memory 205596 kb
Host smart-d46aa147-30bd-4e9b-9da4-4fcde251969a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270389901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.4270389901
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2017560309
Short name T1079
Test name
Test status
Simulation time 543348146 ps
CPU time 2.71 seconds
Started Jul 10 05:46:58 PM PDT 24
Finished Jul 10 05:47:04 PM PDT 24
Peak memory 214068 kb
Host smart-99d7fab5-56ff-4d67-b092-8be17eab0f51
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017560309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2017560309
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3030887752
Short name T124
Test name
Test status
Simulation time 445703478 ps
CPU time 9.29 seconds
Started Jul 10 05:47:04 PM PDT 24
Finished Jul 10 05:47:14 PM PDT 24
Peak memory 219772 kb
Host smart-aceed96f-891a-417b-9efd-ccd37c3d0172
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030887752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3030887752
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3186072337
Short name T1076
Test name
Test status
Simulation time 201963574 ps
CPU time 3.43 seconds
Started Jul 10 05:47:06 PM PDT 24
Finished Jul 10 05:47:11 PM PDT 24
Peak memory 213552 kb
Host smart-11d20292-51cd-471e-a257-4763bc10b47e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186072337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3186072337
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.897243744
Short name T166
Test name
Test status
Simulation time 90604403 ps
CPU time 2.98 seconds
Started Jul 10 05:47:04 PM PDT 24
Finished Jul 10 05:47:09 PM PDT 24
Peak memory 213644 kb
Host smart-5173dccd-3482-4e17-9122-e352f0c1b805
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897243744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.897243744
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2878586026
Short name T967
Test name
Test status
Simulation time 122866796 ps
CPU time 2.45 seconds
Started Jul 10 05:47:06 PM PDT 24
Finished Jul 10 05:47:10 PM PDT 24
Peak memory 213664 kb
Host smart-7860c9ab-7f1a-4a28-8064-f1cf9d5e29e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878586026 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2878586026
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1893907058
Short name T1045
Test name
Test status
Simulation time 31196774 ps
CPU time 1.11 seconds
Started Jul 10 05:47:04 PM PDT 24
Finished Jul 10 05:47:07 PM PDT 24
Peak memory 205544 kb
Host smart-05b86936-2fc7-4647-8dd2-18f859ba3e02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893907058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1893907058
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2705948325
Short name T1055
Test name
Test status
Simulation time 38925480 ps
CPU time 0.88 seconds
Started Jul 10 05:47:04 PM PDT 24
Finished Jul 10 05:47:06 PM PDT 24
Peak memory 205324 kb
Host smart-16e79ec7-4a8d-4c61-b5b4-a9ac4ed4ee43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705948325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2705948325
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.4183287773
Short name T969
Test name
Test status
Simulation time 46831544 ps
CPU time 2.12 seconds
Started Jul 10 05:47:01 PM PDT 24
Finished Jul 10 05:47:05 PM PDT 24
Peak memory 205500 kb
Host smart-fc946abe-9935-4ddb-a580-206080a994ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183287773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.4183287773
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.523492766
Short name T973
Test name
Test status
Simulation time 1315207715 ps
CPU time 8.37 seconds
Started Jul 10 05:47:03 PM PDT 24
Finished Jul 10 05:47:13 PM PDT 24
Peak memory 214076 kb
Host smart-4990693f-9f8a-4dca-a6f7-7a7369de0958
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523492766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.523492766
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1924489231
Short name T1003
Test name
Test status
Simulation time 51237606 ps
CPU time 1.8 seconds
Started Jul 10 05:47:04 PM PDT 24
Finished Jul 10 05:47:07 PM PDT 24
Peak memory 213728 kb
Host smart-4a60dc36-af03-4a6e-a2d5-e269c7347a58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924489231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1924489231
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2960951867
Short name T180
Test name
Test status
Simulation time 205801233 ps
CPU time 2.69 seconds
Started Jul 10 05:47:06 PM PDT 24
Finished Jul 10 05:47:09 PM PDT 24
Peak memory 213692 kb
Host smart-1ad4eed8-c278-4bd7-92d3-7ad787400b16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960951867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2960951867
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1129417176
Short name T943
Test name
Test status
Simulation time 42095602 ps
CPU time 1.51 seconds
Started Jul 10 05:47:11 PM PDT 24
Finished Jul 10 05:47:14 PM PDT 24
Peak memory 205636 kb
Host smart-7b940e32-d4d8-4a66-9051-75cfee55730b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129417176 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1129417176
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1748164114
Short name T404
Test name
Test status
Simulation time 44916959 ps
CPU time 0.94 seconds
Started Jul 10 05:47:09 PM PDT 24
Finished Jul 10 05:47:12 PM PDT 24
Peak memory 205440 kb
Host smart-2e0fea17-f22b-4ad7-b905-87bd034e9033
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748164114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1748164114
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3629205484
Short name T946
Test name
Test status
Simulation time 26972951 ps
CPU time 0.76 seconds
Started Jul 10 05:47:11 PM PDT 24
Finished Jul 10 05:47:13 PM PDT 24
Peak memory 205324 kb
Host smart-53505c8b-4e91-43aa-8fe6-c39554f3ac4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629205484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3629205484
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.698043372
Short name T154
Test name
Test status
Simulation time 359517316 ps
CPU time 3.79 seconds
Started Jul 10 05:47:11 PM PDT 24
Finished Jul 10 05:47:16 PM PDT 24
Peak memory 205468 kb
Host smart-40f0b549-c003-4131-a343-5f195592fb20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698043372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.698043372
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3527354938
Short name T941
Test name
Test status
Simulation time 65388187 ps
CPU time 1.45 seconds
Started Jul 10 05:47:11 PM PDT 24
Finished Jul 10 05:47:13 PM PDT 24
Peak memory 214036 kb
Host smart-ef681feb-f24a-4c32-a34d-1de0378af210
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527354938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3527354938
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2305581818
Short name T950
Test name
Test status
Simulation time 533749925 ps
CPU time 7.17 seconds
Started Jul 10 05:47:09 PM PDT 24
Finished Jul 10 05:47:18 PM PDT 24
Peak memory 214012 kb
Host smart-25e59f1a-a470-4438-90aa-8a3dc7514e34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305581818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2305581818
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.298843796
Short name T1011
Test name
Test status
Simulation time 39886776 ps
CPU time 1.45 seconds
Started Jul 10 05:47:12 PM PDT 24
Finished Jul 10 05:47:14 PM PDT 24
Peak memory 213812 kb
Host smart-eedcb9d3-c968-4cea-b400-c8f9b4634c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298843796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.298843796
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1028605452
Short name T185
Test name
Test status
Simulation time 516169652 ps
CPU time 7.13 seconds
Started Jul 10 05:47:08 PM PDT 24
Finished Jul 10 05:47:16 PM PDT 24
Peak memory 213644 kb
Host smart-274952f5-92e8-4369-bd84-29030e58d3d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028605452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1028605452
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.12541676
Short name T979
Test name
Test status
Simulation time 377723500 ps
CPU time 2.2 seconds
Started Jul 10 05:47:09 PM PDT 24
Finished Jul 10 05:47:12 PM PDT 24
Peak memory 213688 kb
Host smart-f8b47b3b-d6e2-47b9-943e-29ad06b0d3f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12541676 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.12541676
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2413241886
Short name T152
Test name
Test status
Simulation time 14011890 ps
CPU time 1.13 seconds
Started Jul 10 05:47:08 PM PDT 24
Finished Jul 10 05:47:10 PM PDT 24
Peak memory 205504 kb
Host smart-2a731d65-068c-44d3-9fb8-51ed6f51e47f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413241886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2413241886
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.760779866
Short name T990
Test name
Test status
Simulation time 44744495 ps
CPU time 0.86 seconds
Started Jul 10 05:47:09 PM PDT 24
Finished Jul 10 05:47:12 PM PDT 24
Peak memory 205328 kb
Host smart-47cc71c1-5405-4302-ac6b-7e43624d6c18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760779866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.760779866
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3560724831
Short name T147
Test name
Test status
Simulation time 324671455 ps
CPU time 3.05 seconds
Started Jul 10 05:47:09 PM PDT 24
Finished Jul 10 05:47:14 PM PDT 24
Peak memory 205388 kb
Host smart-5b60a8ca-7615-4b13-ad39-d86410ec3f7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560724831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3560724831
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.653796968
Short name T998
Test name
Test status
Simulation time 204140560 ps
CPU time 5.24 seconds
Started Jul 10 05:47:07 PM PDT 24
Finished Jul 10 05:47:13 PM PDT 24
Peak memory 214052 kb
Host smart-5b5ffe57-bece-48be-a8e2-074c0eb6afd9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653796968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.653796968
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.202885340
Short name T978
Test name
Test status
Simulation time 377974128 ps
CPU time 5.16 seconds
Started Jul 10 05:47:07 PM PDT 24
Finished Jul 10 05:47:13 PM PDT 24
Peak memory 214036 kb
Host smart-530df771-e491-4ca7-ba68-ad20afdabf0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202885340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.202885340
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.476255017
Short name T955
Test name
Test status
Simulation time 451244651 ps
CPU time 2.47 seconds
Started Jul 10 05:47:12 PM PDT 24
Finished Jul 10 05:47:15 PM PDT 24
Peak memory 213744 kb
Host smart-acfb26d6-31c6-439e-8836-87001e54960b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476255017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.476255017
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2209326837
Short name T1025
Test name
Test status
Simulation time 133411582 ps
CPU time 4.77 seconds
Started Jul 10 05:47:08 PM PDT 24
Finished Jul 10 05:47:14 PM PDT 24
Peak memory 213612 kb
Host smart-e1322685-88b7-4174-b712-11f6540aa5db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209326837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2209326837
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2886524210
Short name T924
Test name
Test status
Simulation time 131622335 ps
CPU time 1.27 seconds
Started Jul 10 05:47:19 PM PDT 24
Finished Jul 10 05:47:21 PM PDT 24
Peak memory 205548 kb
Host smart-af76aaac-060a-4793-b061-d813d0bcb405
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886524210 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2886524210
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.355769958
Short name T939
Test name
Test status
Simulation time 146178215 ps
CPU time 1.49 seconds
Started Jul 10 05:47:10 PM PDT 24
Finished Jul 10 05:47:13 PM PDT 24
Peak memory 205524 kb
Host smart-2f18b896-74af-4362-9805-d222dea8cd9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355769958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.355769958
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3587206185
Short name T923
Test name
Test status
Simulation time 55306597 ps
CPU time 0.85 seconds
Started Jul 10 05:47:09 PM PDT 24
Finished Jul 10 05:47:12 PM PDT 24
Peak memory 205288 kb
Host smart-db9c99e9-cf03-4311-85e0-58faba5b3667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587206185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3587206185
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2481577267
Short name T1080
Test name
Test status
Simulation time 36923806 ps
CPU time 2.54 seconds
Started Jul 10 05:47:09 PM PDT 24
Finished Jul 10 05:47:13 PM PDT 24
Peak memory 205460 kb
Host smart-885b1f4f-4ded-412c-a6be-404326122be3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481577267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2481577267
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.289074587
Short name T121
Test name
Test status
Simulation time 218597374 ps
CPU time 1.93 seconds
Started Jul 10 05:47:12 PM PDT 24
Finished Jul 10 05:47:15 PM PDT 24
Peak memory 214004 kb
Host smart-1d003313-bef4-40dd-83ca-059aa40fa489
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289074587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.289074587
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.108877766
Short name T118
Test name
Test status
Simulation time 277094705 ps
CPU time 8.01 seconds
Started Jul 10 05:47:09 PM PDT 24
Finished Jul 10 05:47:18 PM PDT 24
Peak memory 220244 kb
Host smart-ffc3951b-3140-41bf-a0f1-5f8effaa521b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108877766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.108877766
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3002251680
Short name T968
Test name
Test status
Simulation time 41870427 ps
CPU time 2.9 seconds
Started Jul 10 05:47:10 PM PDT 24
Finished Jul 10 05:47:14 PM PDT 24
Peak memory 213740 kb
Host smart-92c50df5-a996-4013-bbcd-296b856dd09c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002251680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3002251680
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3511689792
Short name T1064
Test name
Test status
Simulation time 34345270 ps
CPU time 1.61 seconds
Started Jul 10 05:47:15 PM PDT 24
Finished Jul 10 05:47:18 PM PDT 24
Peak memory 213696 kb
Host smart-9447dc1a-c972-4613-917b-a5db08b2d44f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511689792 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3511689792
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3985119081
Short name T985
Test name
Test status
Simulation time 59233868 ps
CPU time 1.1 seconds
Started Jul 10 05:47:15 PM PDT 24
Finished Jul 10 05:47:17 PM PDT 24
Peak memory 205440 kb
Host smart-f95242da-aee2-4fe6-b577-7e18ca21cd3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985119081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3985119081
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2999651093
Short name T1070
Test name
Test status
Simulation time 14594442 ps
CPU time 0.77 seconds
Started Jul 10 05:47:15 PM PDT 24
Finished Jul 10 05:47:16 PM PDT 24
Peak memory 205332 kb
Host smart-91e5964f-ece3-4a39-82b8-48f2da5eb45a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999651093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2999651093
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2669547911
Short name T1075
Test name
Test status
Simulation time 61900853 ps
CPU time 1.9 seconds
Started Jul 10 05:47:18 PM PDT 24
Finished Jul 10 05:47:21 PM PDT 24
Peak memory 205500 kb
Host smart-646ea9b2-96a1-49c0-9991-e4234c53ba0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669547911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2669547911
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2875268040
Short name T997
Test name
Test status
Simulation time 219373069 ps
CPU time 3.23 seconds
Started Jul 10 05:47:15 PM PDT 24
Finished Jul 10 05:47:19 PM PDT 24
Peak memory 213940 kb
Host smart-a3c67150-c2b0-4091-aa2b-73d2a4e73e73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875268040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2875268040
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4273501949
Short name T972
Test name
Test status
Simulation time 1321402480 ps
CPU time 9.93 seconds
Started Jul 10 05:47:18 PM PDT 24
Finished Jul 10 05:47:29 PM PDT 24
Peak memory 214032 kb
Host smart-fcb6db50-9d1a-4d7e-a0d8-2fdf8c35b4c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273501949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.4273501949
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2896882750
Short name T1073
Test name
Test status
Simulation time 123838074 ps
CPU time 2.39 seconds
Started Jul 10 05:47:20 PM PDT 24
Finished Jul 10 05:47:23 PM PDT 24
Peak memory 213748 kb
Host smart-3268a2ad-65a9-4e8f-a6e7-56aa870ab0fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896882750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2896882750
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1547714440
Short name T175
Test name
Test status
Simulation time 219108437 ps
CPU time 9.37 seconds
Started Jul 10 05:47:18 PM PDT 24
Finished Jul 10 05:47:28 PM PDT 24
Peak memory 213724 kb
Host smart-8ee5072b-feb4-4087-9523-fa9b3fdb7624
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547714440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1547714440
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2067744344
Short name T933
Test name
Test status
Simulation time 63254543 ps
CPU time 1.25 seconds
Started Jul 10 05:47:17 PM PDT 24
Finished Jul 10 05:47:19 PM PDT 24
Peak memory 205496 kb
Host smart-c004dd14-4f23-4a87-a90e-ea17a5433b1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067744344 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2067744344
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3484533778
Short name T1020
Test name
Test status
Simulation time 122730437 ps
CPU time 1.23 seconds
Started Jul 10 05:47:15 PM PDT 24
Finished Jul 10 05:47:18 PM PDT 24
Peak memory 205528 kb
Host smart-dbb629ff-9239-450a-99ba-d40f9b5c3610
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484533778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3484533778
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2465528845
Short name T965
Test name
Test status
Simulation time 15042505 ps
CPU time 0.9 seconds
Started Jul 10 05:47:14 PM PDT 24
Finished Jul 10 05:47:16 PM PDT 24
Peak memory 205328 kb
Host smart-85dd79c5-efa0-4749-bd59-72134c21872f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465528845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2465528845
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3315959161
Short name T151
Test name
Test status
Simulation time 91744949 ps
CPU time 1.43 seconds
Started Jul 10 05:47:18 PM PDT 24
Finished Jul 10 05:47:21 PM PDT 24
Peak memory 205528 kb
Host smart-a27cc0c1-aeb5-49b4-ba6e-d81f909061c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315959161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3315959161
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.4265846566
Short name T1001
Test name
Test status
Simulation time 315530669 ps
CPU time 1.89 seconds
Started Jul 10 05:47:17 PM PDT 24
Finished Jul 10 05:47:20 PM PDT 24
Peak memory 214248 kb
Host smart-2dcb1988-13c3-49c0-92db-22fd7df95155
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265846566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.4265846566
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1290404083
Short name T1048
Test name
Test status
Simulation time 205206790 ps
CPU time 5.28 seconds
Started Jul 10 05:47:17 PM PDT 24
Finished Jul 10 05:47:24 PM PDT 24
Peak memory 219764 kb
Host smart-a2efe140-7535-49c7-a224-40d97a2583b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290404083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1290404083
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.984716625
Short name T1060
Test name
Test status
Simulation time 141758676 ps
CPU time 2.07 seconds
Started Jul 10 05:47:16 PM PDT 24
Finished Jul 10 05:47:19 PM PDT 24
Peak memory 213980 kb
Host smart-06d2dfa2-4a17-4b84-9aa6-6aa112a9d136
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984716625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.984716625
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1519207811
Short name T960
Test name
Test status
Simulation time 533441547 ps
CPU time 3.75 seconds
Started Jul 10 05:47:17 PM PDT 24
Finished Jul 10 05:47:22 PM PDT 24
Peak memory 213684 kb
Host smart-54a25849-742a-4d14-a58f-fc43037d3095
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519207811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1519207811
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2664038741
Short name T1059
Test name
Test status
Simulation time 242629055 ps
CPU time 8.02 seconds
Started Jul 10 05:46:40 PM PDT 24
Finished Jul 10 05:46:49 PM PDT 24
Peak memory 205380 kb
Host smart-9f07b890-b883-4004-9ecd-144900acec12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664038741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
664038741
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3497484279
Short name T1062
Test name
Test status
Simulation time 4748032590 ps
CPU time 16.12 seconds
Started Jul 10 05:46:37 PM PDT 24
Finished Jul 10 05:46:54 PM PDT 24
Peak memory 205604 kb
Host smart-80b9bce6-5fe5-4f3f-ace7-e4dc223ae083
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497484279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
497484279
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.296316060
Short name T1013
Test name
Test status
Simulation time 22827523 ps
CPU time 0.98 seconds
Started Jul 10 05:46:40 PM PDT 24
Finished Jul 10 05:46:42 PM PDT 24
Peak memory 205380 kb
Host smart-c56b6c3d-86fa-4b2d-9a45-67c4c7f3b258
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296316060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.296316060
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2111910117
Short name T169
Test name
Test status
Simulation time 23982849 ps
CPU time 1.73 seconds
Started Jul 10 05:46:40 PM PDT 24
Finished Jul 10 05:46:43 PM PDT 24
Peak memory 213824 kb
Host smart-11ff7be9-2e1a-4100-8a36-7cad2681f878
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111910117 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2111910117
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3411318834
Short name T994
Test name
Test status
Simulation time 22649867 ps
CPU time 0.95 seconds
Started Jul 10 05:46:38 PM PDT 24
Finished Jul 10 05:46:40 PM PDT 24
Peak memory 205352 kb
Host smart-f6f5ce71-3d49-470b-9c5b-6e2eb80dd036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411318834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3411318834
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.664862765
Short name T959
Test name
Test status
Simulation time 27541061 ps
CPU time 0.71 seconds
Started Jul 10 05:46:39 PM PDT 24
Finished Jul 10 05:46:41 PM PDT 24
Peak memory 205264 kb
Host smart-e78e3b88-08e2-48f1-8d50-6be9c1dc97eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664862765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.664862765
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1316066560
Short name T1034
Test name
Test status
Simulation time 67130846 ps
CPU time 1.96 seconds
Started Jul 10 05:46:39 PM PDT 24
Finished Jul 10 05:46:42 PM PDT 24
Peak memory 213712 kb
Host smart-bee29ba1-fc1d-4df0-8957-e9ee84c54d4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316066560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1316066560
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2367409757
Short name T1046
Test name
Test status
Simulation time 302222447 ps
CPU time 4.46 seconds
Started Jul 10 05:46:31 PM PDT 24
Finished Jul 10 05:46:37 PM PDT 24
Peak memory 218456 kb
Host smart-7e323642-9480-4c5e-9168-a520b05a9fbf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367409757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2367409757
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2616085162
Short name T117
Test name
Test status
Simulation time 2009714750 ps
CPU time 7.7 seconds
Started Jul 10 05:46:30 PM PDT 24
Finished Jul 10 05:46:39 PM PDT 24
Peak memory 222168 kb
Host smart-d544f1f1-0a0a-4b2e-b6f6-948842145c18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616085162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2616085162
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1960445030
Short name T1049
Test name
Test status
Simulation time 128053363 ps
CPU time 4.44 seconds
Started Jul 10 05:46:38 PM PDT 24
Finished Jul 10 05:46:44 PM PDT 24
Peak memory 213728 kb
Host smart-5c327385-0ea4-4c6d-834d-374ce628d38b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960445030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1960445030
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1589585183
Short name T183
Test name
Test status
Simulation time 215382491 ps
CPU time 3.09 seconds
Started Jul 10 05:46:38 PM PDT 24
Finished Jul 10 05:46:42 PM PDT 24
Peak memory 213624 kb
Host smart-379a3165-ff54-4030-b84d-07898ee3573c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589585183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1589585183
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1241482547
Short name T1038
Test name
Test status
Simulation time 29888478 ps
CPU time 0.73 seconds
Started Jul 10 05:47:16 PM PDT 24
Finished Jul 10 05:47:18 PM PDT 24
Peak memory 205300 kb
Host smart-b05d4d37-3e4b-42fb-9b6d-e55517f43486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241482547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1241482547
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1408879871
Short name T1032
Test name
Test status
Simulation time 20776127 ps
CPU time 0.88 seconds
Started Jul 10 05:47:17 PM PDT 24
Finished Jul 10 05:47:19 PM PDT 24
Peak memory 205344 kb
Host smart-03bcf345-68f5-45b4-ad36-a9a6a81d7596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408879871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1408879871
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.348684534
Short name T1040
Test name
Test status
Simulation time 10280868 ps
CPU time 0.81 seconds
Started Jul 10 05:47:18 PM PDT 24
Finished Jul 10 05:47:20 PM PDT 24
Peak memory 205328 kb
Host smart-6db3da0f-1c0c-4854-89bf-5b41f973e867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348684534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.348684534
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.4089994055
Short name T1057
Test name
Test status
Simulation time 81269071 ps
CPU time 0.72 seconds
Started Jul 10 05:47:16 PM PDT 24
Finished Jul 10 05:47:17 PM PDT 24
Peak memory 205328 kb
Host smart-97f50c9a-330c-4fe8-8e73-3dfe4e54e438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089994055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.4089994055
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1023423465
Short name T936
Test name
Test status
Simulation time 27678821 ps
CPU time 0.68 seconds
Started Jul 10 05:47:17 PM PDT 24
Finished Jul 10 05:47:18 PM PDT 24
Peak memory 205340 kb
Host smart-ad5adb96-a475-4d9a-8ced-434cd7c67301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023423465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1023423465
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.271517874
Short name T1010
Test name
Test status
Simulation time 28963815 ps
CPU time 0.7 seconds
Started Jul 10 05:47:15 PM PDT 24
Finished Jul 10 05:47:17 PM PDT 24
Peak memory 205348 kb
Host smart-251a530d-2488-4351-b2c4-3e03bef2972f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271517874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.271517874
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.914594124
Short name T961
Test name
Test status
Simulation time 43175160 ps
CPU time 0.79 seconds
Started Jul 10 05:47:17 PM PDT 24
Finished Jul 10 05:47:19 PM PDT 24
Peak memory 205268 kb
Host smart-b6052995-3709-47f3-b0cd-a7345c6f7139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914594124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.914594124
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2625750040
Short name T1056
Test name
Test status
Simulation time 31972633 ps
CPU time 0.72 seconds
Started Jul 10 05:47:16 PM PDT 24
Finished Jul 10 05:47:17 PM PDT 24
Peak memory 205328 kb
Host smart-4dc2d12a-84e7-432a-bd8d-589f0104a07b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625750040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2625750040
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2586967033
Short name T1006
Test name
Test status
Simulation time 20139713 ps
CPU time 0.73 seconds
Started Jul 10 05:47:14 PM PDT 24
Finished Jul 10 05:47:15 PM PDT 24
Peak memory 205168 kb
Host smart-e238cf26-ddbe-4117-a4ef-12133b9942e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586967033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2586967033
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.11080328
Short name T1007
Test name
Test status
Simulation time 11954365 ps
CPU time 0.92 seconds
Started Jul 10 05:47:25 PM PDT 24
Finished Jul 10 05:47:29 PM PDT 24
Peak memory 205372 kb
Host smart-962a310f-55e8-45fd-ac9b-fc3a1acd483f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11080328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.11080328
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2233521782
Short name T1035
Test name
Test status
Simulation time 272186288 ps
CPU time 3.83 seconds
Started Jul 10 05:46:45 PM PDT 24
Finished Jul 10 05:46:50 PM PDT 24
Peak memory 205508 kb
Host smart-a8c67f5d-1619-4671-b773-3d6bc0d52885
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233521782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
233521782
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.570140340
Short name T958
Test name
Test status
Simulation time 259636814 ps
CPU time 8.16 seconds
Started Jul 10 05:46:38 PM PDT 24
Finished Jul 10 05:46:47 PM PDT 24
Peak memory 205424 kb
Host smart-055032d2-6a3d-4611-b2dd-5fae0616bc27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570140340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.570140340
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2479649859
Short name T982
Test name
Test status
Simulation time 33908476 ps
CPU time 0.96 seconds
Started Jul 10 05:46:38 PM PDT 24
Finished Jul 10 05:46:40 PM PDT 24
Peak memory 205436 kb
Host smart-d9b2801f-372d-4719-8f53-25b382e868c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479649859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
479649859
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1005977341
Short name T1061
Test name
Test status
Simulation time 25876617 ps
CPU time 1.62 seconds
Started Jul 10 05:46:47 PM PDT 24
Finished Jul 10 05:46:51 PM PDT 24
Peak memory 213856 kb
Host smart-694996a2-a760-42f4-a164-fac37ff18183
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005977341 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1005977341
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3538786444
Short name T1008
Test name
Test status
Simulation time 28204911 ps
CPU time 1.04 seconds
Started Jul 10 05:46:38 PM PDT 24
Finished Jul 10 05:46:40 PM PDT 24
Peak memory 205516 kb
Host smart-c27aaf6f-97fb-42d3-8272-257d3b53fb8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538786444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3538786444
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1607390287
Short name T921
Test name
Test status
Simulation time 90866087 ps
CPU time 0.74 seconds
Started Jul 10 05:46:40 PM PDT 24
Finished Jul 10 05:46:42 PM PDT 24
Peak memory 205264 kb
Host smart-0a74c9a3-987a-4555-b1da-93800a77dc52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607390287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1607390287
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1996193800
Short name T957
Test name
Test status
Simulation time 109741222 ps
CPU time 4.47 seconds
Started Jul 10 05:46:45 PM PDT 24
Finished Jul 10 05:46:51 PM PDT 24
Peak memory 205484 kb
Host smart-844bbb45-fd0e-44dc-b741-9e70f349142a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996193800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1996193800
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2232833065
Short name T1043
Test name
Test status
Simulation time 875466008 ps
CPU time 2.43 seconds
Started Jul 10 05:46:39 PM PDT 24
Finished Jul 10 05:46:43 PM PDT 24
Peak memory 214052 kb
Host smart-2823c03a-4a09-43b1-a9b8-e51770908f40
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232833065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2232833065
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1898917107
Short name T970
Test name
Test status
Simulation time 385964832 ps
CPU time 7.15 seconds
Started Jul 10 05:46:40 PM PDT 24
Finished Jul 10 05:46:49 PM PDT 24
Peak memory 219892 kb
Host smart-d273812d-6e78-4885-96f5-0beb58c177b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898917107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1898917107
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.12710655
Short name T991
Test name
Test status
Simulation time 559558571 ps
CPU time 5.54 seconds
Started Jul 10 05:46:40 PM PDT 24
Finished Jul 10 05:46:47 PM PDT 24
Peak memory 213712 kb
Host smart-27fe6f04-2c8e-4e23-9a52-562538ad2ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12710655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.12710655
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3262388560
Short name T940
Test name
Test status
Simulation time 8658723 ps
CPU time 0.68 seconds
Started Jul 10 05:47:24 PM PDT 24
Finished Jul 10 05:47:27 PM PDT 24
Peak memory 205324 kb
Host smart-def3b2f5-6e04-4e8e-956a-fbbc1e0d394e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262388560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3262388560
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1348765197
Short name T1078
Test name
Test status
Simulation time 10376877 ps
CPU time 0.85 seconds
Started Jul 10 05:47:25 PM PDT 24
Finished Jul 10 05:47:29 PM PDT 24
Peak memory 205320 kb
Host smart-f91f4dc2-bc69-4e05-a166-57cf04c6d0c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348765197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1348765197
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1182769129
Short name T1017
Test name
Test status
Simulation time 10616995 ps
CPU time 0.71 seconds
Started Jul 10 05:47:24 PM PDT 24
Finished Jul 10 05:47:27 PM PDT 24
Peak memory 205220 kb
Host smart-b7d7234a-048d-4aa0-8e92-9f40473b8c20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182769129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1182769129
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.75895224
Short name T992
Test name
Test status
Simulation time 14314281 ps
CPU time 0.78 seconds
Started Jul 10 05:47:22 PM PDT 24
Finished Jul 10 05:47:25 PM PDT 24
Peak memory 205328 kb
Host smart-86da71c9-f2cb-40b2-ab36-701f05b4228f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75895224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.75895224
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1266427861
Short name T1028
Test name
Test status
Simulation time 41053933 ps
CPU time 0.9 seconds
Started Jul 10 05:47:26 PM PDT 24
Finished Jul 10 05:47:30 PM PDT 24
Peak memory 205472 kb
Host smart-7645b87c-2d97-4613-bfca-f10b2fc2ba36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266427861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1266427861
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1190020236
Short name T951
Test name
Test status
Simulation time 46216374 ps
CPU time 0.86 seconds
Started Jul 10 05:47:24 PM PDT 24
Finished Jul 10 05:47:27 PM PDT 24
Peak memory 205192 kb
Host smart-1378ba76-cb38-47dd-8198-c05866f9fb72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190020236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1190020236
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1506380032
Short name T962
Test name
Test status
Simulation time 10144890 ps
CPU time 0.74 seconds
Started Jul 10 05:47:25 PM PDT 24
Finished Jul 10 05:47:29 PM PDT 24
Peak memory 205328 kb
Host smart-1426fc86-6a68-4df9-a5de-60ddca2e4973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506380032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1506380032
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.225950319
Short name T929
Test name
Test status
Simulation time 31336746 ps
CPU time 0.73 seconds
Started Jul 10 05:47:23 PM PDT 24
Finished Jul 10 05:47:25 PM PDT 24
Peak memory 205192 kb
Host smart-e92115db-870f-4fe6-865b-3205d4a4c7ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225950319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.225950319
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.589751120
Short name T980
Test name
Test status
Simulation time 29558340 ps
CPU time 0.76 seconds
Started Jul 10 05:47:22 PM PDT 24
Finished Jul 10 05:47:24 PM PDT 24
Peak memory 205252 kb
Host smart-9dba15af-32c0-43d9-8881-0ea0dcaf78d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589751120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.589751120
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2754392711
Short name T1047
Test name
Test status
Simulation time 20403139 ps
CPU time 0.74 seconds
Started Jul 10 05:47:24 PM PDT 24
Finished Jul 10 05:47:27 PM PDT 24
Peak memory 205328 kb
Host smart-e835b89f-bf80-4cef-be18-df650d4fcd4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754392711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2754392711
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.851582193
Short name T963
Test name
Test status
Simulation time 253858591 ps
CPU time 4.92 seconds
Started Jul 10 05:46:47 PM PDT 24
Finished Jul 10 05:46:54 PM PDT 24
Peak memory 205468 kb
Host smart-2f0daf35-fe7f-4c0c-96c1-c5f32bfa46c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851582193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.851582193
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.814564337
Short name T964
Test name
Test status
Simulation time 305893787 ps
CPU time 11.46 seconds
Started Jul 10 05:46:44 PM PDT 24
Finished Jul 10 05:46:56 PM PDT 24
Peak memory 205416 kb
Host smart-3c4cf48e-57f9-459a-a1b3-82a8fb84f735
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814564337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.814564337
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.219556892
Short name T1041
Test name
Test status
Simulation time 25973377 ps
CPU time 1.04 seconds
Started Jul 10 05:46:45 PM PDT 24
Finished Jul 10 05:46:48 PM PDT 24
Peak memory 205504 kb
Host smart-10dacb8c-343c-4758-b858-f1f37a25f130
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219556892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.219556892
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.485934221
Short name T1077
Test name
Test status
Simulation time 22394779 ps
CPU time 1.43 seconds
Started Jul 10 05:46:48 PM PDT 24
Finished Jul 10 05:46:51 PM PDT 24
Peak memory 213716 kb
Host smart-7e88074e-1600-44c6-8848-e017e664df80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485934221 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.485934221
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1602252612
Short name T1074
Test name
Test status
Simulation time 59905346 ps
CPU time 1.55 seconds
Started Jul 10 05:46:45 PM PDT 24
Finished Jul 10 05:46:48 PM PDT 24
Peak memory 205552 kb
Host smart-5a237b89-aab2-4e5d-ba61-f310db156fd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602252612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1602252612
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1832293123
Short name T944
Test name
Test status
Simulation time 149022558 ps
CPU time 0.74 seconds
Started Jul 10 05:46:45 PM PDT 24
Finished Jul 10 05:46:47 PM PDT 24
Peak memory 205324 kb
Host smart-d8595634-7077-43b0-8106-0b1a9acc34b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832293123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1832293123
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.843040606
Short name T956
Test name
Test status
Simulation time 157799329 ps
CPU time 2.37 seconds
Started Jul 10 05:46:47 PM PDT 24
Finished Jul 10 05:46:52 PM PDT 24
Peak memory 205440 kb
Host smart-b51846fa-18e4-43e0-be12-89450a051f81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843040606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.843040606
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1155952208
Short name T1026
Test name
Test status
Simulation time 57267022 ps
CPU time 2.14 seconds
Started Jul 10 05:46:45 PM PDT 24
Finished Jul 10 05:46:49 PM PDT 24
Peak memory 213980 kb
Host smart-ceabd559-94ce-4849-83c8-c3e4307b115e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155952208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1155952208
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.4289423335
Short name T123
Test name
Test status
Simulation time 160143212 ps
CPU time 8.65 seconds
Started Jul 10 05:46:44 PM PDT 24
Finished Jul 10 05:46:54 PM PDT 24
Peak memory 214044 kb
Host smart-944a93d6-e46b-48d5-b878-393b6eb5d76a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289423335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.4289423335
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2477107221
Short name T975
Test name
Test status
Simulation time 62871037 ps
CPU time 2.01 seconds
Started Jul 10 05:46:45 PM PDT 24
Finished Jul 10 05:46:48 PM PDT 24
Peak memory 216652 kb
Host smart-a09ee391-0519-49b3-9480-b2bdd7b1a729
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477107221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2477107221
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1902573413
Short name T983
Test name
Test status
Simulation time 8261003 ps
CPU time 0.73 seconds
Started Jul 10 05:47:24 PM PDT 24
Finished Jul 10 05:47:27 PM PDT 24
Peak memory 205312 kb
Host smart-49c49276-9a8c-4aa7-bdbd-07edc4ef2c35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902573413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1902573413
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.81214525
Short name T926
Test name
Test status
Simulation time 20431428 ps
CPU time 0.72 seconds
Started Jul 10 05:47:22 PM PDT 24
Finished Jul 10 05:47:24 PM PDT 24
Peak memory 205328 kb
Host smart-87d2d07b-93bf-417d-bdb6-5fe5535653cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81214525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.81214525
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2372892440
Short name T981
Test name
Test status
Simulation time 29732196 ps
CPU time 0.7 seconds
Started Jul 10 05:47:23 PM PDT 24
Finished Jul 10 05:47:27 PM PDT 24
Peak memory 205328 kb
Host smart-1189d151-a8ed-418d-b7e4-b2948c14dabf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372892440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2372892440
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1659528778
Short name T935
Test name
Test status
Simulation time 29704240 ps
CPU time 0.71 seconds
Started Jul 10 05:47:24 PM PDT 24
Finished Jul 10 05:47:27 PM PDT 24
Peak memory 205272 kb
Host smart-fb8e7fd1-a838-4004-8f15-6639b22384ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659528778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1659528778
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3645465374
Short name T1019
Test name
Test status
Simulation time 12658181 ps
CPU time 0.72 seconds
Started Jul 10 05:47:24 PM PDT 24
Finished Jul 10 05:47:27 PM PDT 24
Peak memory 205252 kb
Host smart-c5668e5a-1248-4b02-9eeb-6136450bd9ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645465374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3645465374
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1447214193
Short name T987
Test name
Test status
Simulation time 37946443 ps
CPU time 0.73 seconds
Started Jul 10 05:47:23 PM PDT 24
Finished Jul 10 05:47:25 PM PDT 24
Peak memory 205264 kb
Host smart-dd84e6d0-562d-4757-88d5-6ad49c04cfb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447214193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1447214193
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.540905771
Short name T1052
Test name
Test status
Simulation time 7596579 ps
CPU time 0.72 seconds
Started Jul 10 05:47:22 PM PDT 24
Finished Jul 10 05:47:23 PM PDT 24
Peak memory 205324 kb
Host smart-53e1f4d0-3985-4f29-bf4b-7e6c87d834ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540905771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.540905771
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1119054427
Short name T947
Test name
Test status
Simulation time 10958991 ps
CPU time 0.8 seconds
Started Jul 10 05:47:24 PM PDT 24
Finished Jul 10 05:47:28 PM PDT 24
Peak memory 205328 kb
Host smart-7015df0d-2d9d-4e3a-9084-35ff0b26e60e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119054427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1119054427
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1353703035
Short name T1044
Test name
Test status
Simulation time 10006189 ps
CPU time 0.85 seconds
Started Jul 10 05:47:23 PM PDT 24
Finished Jul 10 05:47:26 PM PDT 24
Peak memory 205252 kb
Host smart-70bf4de5-9b07-4021-b330-2b530039fcb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353703035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1353703035
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3059119664
Short name T954
Test name
Test status
Simulation time 21752150 ps
CPU time 0.7 seconds
Started Jul 10 05:47:25 PM PDT 24
Finished Jul 10 05:47:29 PM PDT 24
Peak memory 205192 kb
Host smart-16acceb6-8bda-4068-b761-7b290b980147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059119664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3059119664
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.253711175
Short name T930
Test name
Test status
Simulation time 54775570 ps
CPU time 1.51 seconds
Started Jul 10 05:46:43 PM PDT 24
Finished Jul 10 05:46:46 PM PDT 24
Peak memory 205560 kb
Host smart-c672e7e9-4d90-4a30-98da-ae5fdb78c3db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253711175 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.253711175
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3068876832
Short name T153
Test name
Test status
Simulation time 94267570 ps
CPU time 1.18 seconds
Started Jul 10 05:46:45 PM PDT 24
Finished Jul 10 05:46:48 PM PDT 24
Peak memory 205528 kb
Host smart-a6615553-0143-42ce-ab66-6a6ca10655fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068876832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3068876832
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.4129241807
Short name T922
Test name
Test status
Simulation time 136778935 ps
CPU time 0.88 seconds
Started Jul 10 05:46:46 PM PDT 24
Finished Jul 10 05:46:48 PM PDT 24
Peak memory 205320 kb
Host smart-7e411668-e2aa-48d1-8c2a-499879811941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129241807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.4129241807
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4045426842
Short name T949
Test name
Test status
Simulation time 160722893 ps
CPU time 1.7 seconds
Started Jul 10 05:46:47 PM PDT 24
Finished Jul 10 05:46:50 PM PDT 24
Peak memory 205428 kb
Host smart-8a07fe71-f0e4-4d4d-ad86-d7652fd6f9c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045426842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.4045426842
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3260584398
Short name T1033
Test name
Test status
Simulation time 55433766 ps
CPU time 1.71 seconds
Started Jul 10 05:46:46 PM PDT 24
Finished Jul 10 05:46:50 PM PDT 24
Peak memory 214020 kb
Host smart-02ab92cd-621e-46aa-8c0f-0160c192bcc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260584398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3260584398
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3674155681
Short name T989
Test name
Test status
Simulation time 215297108 ps
CPU time 5.2 seconds
Started Jul 10 05:46:47 PM PDT 24
Finished Jul 10 05:46:54 PM PDT 24
Peak memory 214108 kb
Host smart-6caf2795-4c34-4924-801e-980d0a3c3cd9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674155681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3674155681
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.4220870065
Short name T925
Test name
Test status
Simulation time 45820352 ps
CPU time 1.67 seconds
Started Jul 10 05:46:48 PM PDT 24
Finished Jul 10 05:46:51 PM PDT 24
Peak memory 213812 kb
Host smart-2dd2e903-2eac-476d-b5ad-df11a1adfccc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220870065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.4220870065
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3456470964
Short name T1068
Test name
Test status
Simulation time 80869427 ps
CPU time 1.6 seconds
Started Jul 10 05:46:52 PM PDT 24
Finished Jul 10 05:46:56 PM PDT 24
Peak memory 205580 kb
Host smart-91e4e03d-e5fd-4730-b563-2294fc600729
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456470964 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3456470964
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2623661314
Short name T937
Test name
Test status
Simulation time 36577220 ps
CPU time 0.87 seconds
Started Jul 10 05:46:47 PM PDT 24
Finished Jul 10 05:46:49 PM PDT 24
Peak memory 205328 kb
Host smart-1c4b9896-f663-4e29-b12d-6cea0f83088b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623661314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2623661314
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3827708465
Short name T931
Test name
Test status
Simulation time 9124309 ps
CPU time 0.78 seconds
Started Jul 10 05:46:44 PM PDT 24
Finished Jul 10 05:46:46 PM PDT 24
Peak memory 205252 kb
Host smart-2f3a7b43-ddfe-4eef-a6fa-11275b95482b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827708465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3827708465
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.31015735
Short name T156
Test name
Test status
Simulation time 90146366 ps
CPU time 1.58 seconds
Started Jul 10 05:46:43 PM PDT 24
Finished Jul 10 05:46:45 PM PDT 24
Peak memory 205460 kb
Host smart-f6e5c66c-a182-4677-9ade-10147551192e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31015735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same
_csr_outstanding.31015735
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1644594764
Short name T1029
Test name
Test status
Simulation time 184767096 ps
CPU time 2.51 seconds
Started Jul 10 05:46:47 PM PDT 24
Finished Jul 10 05:46:51 PM PDT 24
Peak memory 213936 kb
Host smart-fb84e76e-b24a-4842-9cf3-80392fb36fa8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644594764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1644594764
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1849430715
Short name T126
Test name
Test status
Simulation time 652576200 ps
CPU time 6.94 seconds
Started Jul 10 05:46:46 PM PDT 24
Finished Jul 10 05:46:55 PM PDT 24
Peak memory 214012 kb
Host smart-7d12d666-21cd-4c09-902b-2381497d4c7c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849430715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1849430715
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2023822231
Short name T1030
Test name
Test status
Simulation time 486504078 ps
CPU time 3.92 seconds
Started Jul 10 05:46:47 PM PDT 24
Finished Jul 10 05:46:53 PM PDT 24
Peak memory 213712 kb
Host smart-ac990128-90d3-4d50-a7f4-bd925ab85ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023822231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2023822231
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4231997402
Short name T1042
Test name
Test status
Simulation time 89618794 ps
CPU time 1.55 seconds
Started Jul 10 05:46:50 PM PDT 24
Finished Jul 10 05:46:54 PM PDT 24
Peak memory 213740 kb
Host smart-57e9227a-a222-433a-a159-a4570b0f6f12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231997402 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.4231997402
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3195047769
Short name T1037
Test name
Test status
Simulation time 51239422 ps
CPU time 1.45 seconds
Started Jul 10 05:46:51 PM PDT 24
Finished Jul 10 05:46:54 PM PDT 24
Peak memory 205412 kb
Host smart-7ce23df7-e52a-4efb-883d-3598ebea066d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195047769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3195047769
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1801188578
Short name T1054
Test name
Test status
Simulation time 35839979 ps
CPU time 0.73 seconds
Started Jul 10 05:46:51 PM PDT 24
Finished Jul 10 05:46:54 PM PDT 24
Peak memory 205264 kb
Host smart-23361d4e-8f60-4ffd-afeb-d735bab830d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801188578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1801188578
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2818103572
Short name T1015
Test name
Test status
Simulation time 156305845 ps
CPU time 1.8 seconds
Started Jul 10 05:46:51 PM PDT 24
Finished Jul 10 05:46:55 PM PDT 24
Peak memory 205508 kb
Host smart-cb85ad70-96c7-41a0-9d5a-bf6714a61f8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818103572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2818103572
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.90587640
Short name T952
Test name
Test status
Simulation time 166547397 ps
CPU time 2.29 seconds
Started Jul 10 05:46:53 PM PDT 24
Finished Jul 10 05:46:58 PM PDT 24
Peak memory 214080 kb
Host smart-cb525a2c-923c-485d-ad4c-92f9efa810bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90587640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_
reg_errors.90587640
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3446417358
Short name T1021
Test name
Test status
Simulation time 243788491 ps
CPU time 7.91 seconds
Started Jul 10 05:46:50 PM PDT 24
Finished Jul 10 05:47:00 PM PDT 24
Peak memory 220088 kb
Host smart-042b7101-3b2a-4a0d-9f7b-492d2c81cd5d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446417358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3446417358
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2516962223
Short name T928
Test name
Test status
Simulation time 230020257 ps
CPU time 5.05 seconds
Started Jul 10 05:46:51 PM PDT 24
Finished Jul 10 05:46:58 PM PDT 24
Peak memory 213744 kb
Host smart-d357ddf5-6a29-497c-a18e-7814059b97a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516962223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2516962223
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.4190776649
Short name T181
Test name
Test status
Simulation time 78291443 ps
CPU time 2.67 seconds
Started Jul 10 05:46:52 PM PDT 24
Finished Jul 10 05:46:57 PM PDT 24
Peak memory 205524 kb
Host smart-f3a50c92-69b8-408f-8217-c04213117aee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190776649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.4190776649
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3645619653
Short name T1058
Test name
Test status
Simulation time 111657298 ps
CPU time 1.19 seconds
Started Jul 10 05:46:53 PM PDT 24
Finished Jul 10 05:46:57 PM PDT 24
Peak memory 205568 kb
Host smart-7946eea4-2ae6-4392-9a5e-8778a27aa71d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645619653 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3645619653
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1624048980
Short name T945
Test name
Test status
Simulation time 63521963 ps
CPU time 1.18 seconds
Started Jul 10 05:46:51 PM PDT 24
Finished Jul 10 05:46:55 PM PDT 24
Peak memory 205440 kb
Host smart-699798a0-e4cc-4f60-b410-e3844c51f82c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624048980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1624048980
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4073509304
Short name T988
Test name
Test status
Simulation time 40118776 ps
CPU time 0.81 seconds
Started Jul 10 05:46:50 PM PDT 24
Finished Jul 10 05:46:52 PM PDT 24
Peak memory 205248 kb
Host smart-dbddf867-1c19-4e1e-a474-6f3b3528d82a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073509304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.4073509304
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.582417287
Short name T1066
Test name
Test status
Simulation time 631519072 ps
CPU time 2.65 seconds
Started Jul 10 05:46:51 PM PDT 24
Finished Jul 10 05:46:56 PM PDT 24
Peak memory 205484 kb
Host smart-c39e6145-4ef5-447e-a670-b1fa7ac5f1e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582417287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.582417287
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1331184719
Short name T948
Test name
Test status
Simulation time 372497341 ps
CPU time 2.17 seconds
Started Jul 10 05:46:50 PM PDT 24
Finished Jul 10 05:46:55 PM PDT 24
Peak memory 214016 kb
Host smart-76afe751-5db1-428b-812b-bf02b597b2f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331184719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1331184719
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1803691383
Short name T1053
Test name
Test status
Simulation time 363288415 ps
CPU time 12.44 seconds
Started Jul 10 05:46:49 PM PDT 24
Finished Jul 10 05:47:03 PM PDT 24
Peak memory 213948 kb
Host smart-3cf6edbf-068b-47fa-82a5-9c618a0e1759
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803691383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1803691383
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3782693637
Short name T920
Test name
Test status
Simulation time 20291453 ps
CPU time 1.44 seconds
Started Jul 10 05:46:50 PM PDT 24
Finished Jul 10 05:46:53 PM PDT 24
Peak memory 213708 kb
Host smart-8c4d143b-a33b-4a49-b39a-78b347409c41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782693637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3782693637
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.910352137
Short name T184
Test name
Test status
Simulation time 114098386 ps
CPU time 3.68 seconds
Started Jul 10 05:46:52 PM PDT 24
Finished Jul 10 05:46:58 PM PDT 24
Peak memory 213720 kb
Host smart-656acf21-9128-4ac1-902b-3638801b1674
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910352137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
910352137
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2104759712
Short name T1024
Test name
Test status
Simulation time 77749560 ps
CPU time 1.32 seconds
Started Jul 10 05:46:54 PM PDT 24
Finished Jul 10 05:46:58 PM PDT 24
Peak memory 213772 kb
Host smart-1b52db61-27a3-46a4-8c89-16ca4b84b9b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104759712 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2104759712
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2615665131
Short name T1000
Test name
Test status
Simulation time 20040722 ps
CPU time 1.26 seconds
Started Jul 10 05:46:53 PM PDT 24
Finished Jul 10 05:46:57 PM PDT 24
Peak memory 205576 kb
Host smart-b9430d27-223e-4e4b-bd1c-b853cc5d26eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615665131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2615665131
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.228471604
Short name T993
Test name
Test status
Simulation time 14518187 ps
CPU time 0.78 seconds
Started Jul 10 05:46:50 PM PDT 24
Finished Jul 10 05:46:53 PM PDT 24
Peak memory 205248 kb
Host smart-e0680631-5c3e-497b-bd9b-4ae09ef6b8a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228471604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.228471604
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4270371571
Short name T942
Test name
Test status
Simulation time 184945659 ps
CPU time 2.4 seconds
Started Jul 10 05:46:50 PM PDT 24
Finished Jul 10 05:46:55 PM PDT 24
Peak memory 205468 kb
Host smart-6caa037c-6e5f-4b8c-83ec-6bce3650a42b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270371571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.4270371571
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1208238962
Short name T1005
Test name
Test status
Simulation time 88653121 ps
CPU time 2.67 seconds
Started Jul 10 05:46:51 PM PDT 24
Finished Jul 10 05:46:56 PM PDT 24
Peak memory 218544 kb
Host smart-daf9c0a2-ae62-4c06-af35-19bcb56d4ec2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208238962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1208238962
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.30817758
Short name T995
Test name
Test status
Simulation time 237601851 ps
CPU time 8.5 seconds
Started Jul 10 05:46:53 PM PDT 24
Finished Jul 10 05:47:04 PM PDT 24
Peak memory 213988 kb
Host smart-22adb41a-bb40-4bdf-a119-235b29ee6e2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30817758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.ke
ymgr_shadow_reg_errors_with_csr_rw.30817758
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1889235419
Short name T1018
Test name
Test status
Simulation time 95895611 ps
CPU time 1.7 seconds
Started Jul 10 05:46:51 PM PDT 24
Finished Jul 10 05:46:55 PM PDT 24
Peak memory 213804 kb
Host smart-4795e09e-c9dc-41a2-a210-20e1ccf19d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889235419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1889235419
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2435180509
Short name T630
Test name
Test status
Simulation time 10342598 ps
CPU time 0.72 seconds
Started Jul 10 05:48:14 PM PDT 24
Finished Jul 10 05:48:17 PM PDT 24
Peak memory 205980 kb
Host smart-4990a11f-1ff4-4e27-b827-797ad14ca64e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435180509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2435180509
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3553592977
Short name T405
Test name
Test status
Simulation time 2572183319 ps
CPU time 13.21 seconds
Started Jul 10 05:48:07 PM PDT 24
Finished Jul 10 05:48:22 PM PDT 24
Peak memory 222544 kb
Host smart-61ee3dfe-f60c-46bd-b6c6-71b1002a7938
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3553592977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3553592977
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1982467280
Short name T54
Test name
Test status
Simulation time 163523326 ps
CPU time 3.85 seconds
Started Jul 10 05:48:14 PM PDT 24
Finished Jul 10 05:48:20 PM PDT 24
Peak memory 214328 kb
Host smart-a365d6c7-e4b4-464f-a9ae-584545438612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982467280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1982467280
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3916623746
Short name T99
Test name
Test status
Simulation time 534193624 ps
CPU time 5.16 seconds
Started Jul 10 05:48:13 PM PDT 24
Finished Jul 10 05:48:20 PM PDT 24
Peak memory 208572 kb
Host smart-3d8b25d1-45fc-4410-8396-7e27c6e208f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916623746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3916623746
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1266780573
Short name T682
Test name
Test status
Simulation time 99051320 ps
CPU time 3.26 seconds
Started Jul 10 05:48:13 PM PDT 24
Finished Jul 10 05:48:18 PM PDT 24
Peak memory 208260 kb
Host smart-463d8399-ce4d-4c66-8247-26a4297a4eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266780573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1266780573
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2493003470
Short name T473
Test name
Test status
Simulation time 468826267 ps
CPU time 11.68 seconds
Started Jul 10 05:48:04 PM PDT 24
Finished Jul 10 05:48:18 PM PDT 24
Peak memory 208876 kb
Host smart-da40999e-2297-4d64-8875-aa68b174394c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493003470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2493003470
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1727361231
Short name T37
Test name
Test status
Simulation time 9058765434 ps
CPU time 13.39 seconds
Started Jul 10 05:48:13 PM PDT 24
Finished Jul 10 05:48:29 PM PDT 24
Peak memory 235660 kb
Host smart-24f6d498-7dd9-4d22-b7aa-31c3229085c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727361231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1727361231
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1934160904
Short name T642
Test name
Test status
Simulation time 133070235 ps
CPU time 4.53 seconds
Started Jul 10 05:48:05 PM PDT 24
Finished Jul 10 05:48:11 PM PDT 24
Peak memory 206824 kb
Host smart-583dd436-f10f-4aea-9069-32119f4ef7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934160904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1934160904
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.992583037
Short name T289
Test name
Test status
Simulation time 24248155 ps
CPU time 1.95 seconds
Started Jul 10 05:48:02 PM PDT 24
Finished Jul 10 05:48:06 PM PDT 24
Peak memory 206852 kb
Host smart-734d3548-9a01-4ee9-bb44-f5edd6aa42e7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992583037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.992583037
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3676779639
Short name T583
Test name
Test status
Simulation time 1096849687 ps
CPU time 6.89 seconds
Started Jul 10 05:48:13 PM PDT 24
Finished Jul 10 05:48:21 PM PDT 24
Peak memory 208500 kb
Host smart-8cd55ee6-8c0b-4705-ad9b-ee5ac2224c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676779639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3676779639
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3945138815
Short name T796
Test name
Test status
Simulation time 5309627957 ps
CPU time 19.51 seconds
Started Jul 10 05:48:03 PM PDT 24
Finished Jul 10 05:48:25 PM PDT 24
Peak memory 217380 kb
Host smart-395e2238-fc68-4034-ae8b-6f0af459731d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945138815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3945138815
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.563050828
Short name T306
Test name
Test status
Simulation time 1017449989 ps
CPU time 10.61 seconds
Started Jul 10 05:48:05 PM PDT 24
Finished Jul 10 05:48:18 PM PDT 24
Peak memory 214224 kb
Host smart-132c7fac-d4bb-47d7-b53f-fe7ee6fd6098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563050828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.563050828
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.4226284509
Short name T739
Test name
Test status
Simulation time 2518899709 ps
CPU time 12.83 seconds
Started Jul 10 05:48:14 PM PDT 24
Finished Jul 10 05:48:29 PM PDT 24
Peak memory 211184 kb
Host smart-61f0e68c-109f-458a-ad9f-2d394f323410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226284509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.4226284509
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.4259738743
Short name T613
Test name
Test status
Simulation time 41550984 ps
CPU time 0.77 seconds
Started Jul 10 05:48:14 PM PDT 24
Finished Jul 10 05:48:16 PM PDT 24
Peak memory 205996 kb
Host smart-7d73f5da-ae0d-40b9-8eb8-b4e6f900f4a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259738743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.4259738743
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.551442846
Short name T223
Test name
Test status
Simulation time 169789289 ps
CPU time 1.72 seconds
Started Jul 10 05:48:10 PM PDT 24
Finished Jul 10 05:48:13 PM PDT 24
Peak memory 222820 kb
Host smart-e69585ab-11ec-498c-95a8-8b46784c6110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551442846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.551442846
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3962162578
Short name T608
Test name
Test status
Simulation time 215207454 ps
CPU time 1.55 seconds
Started Jul 10 05:48:08 PM PDT 24
Finished Jul 10 05:48:12 PM PDT 24
Peak memory 207464 kb
Host smart-ec1c1a01-deb4-44ab-a4dc-f59709b02692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962162578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3962162578
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2223638669
Short name T340
Test name
Test status
Simulation time 136442517 ps
CPU time 5.04 seconds
Started Jul 10 05:48:10 PM PDT 24
Finished Jul 10 05:48:17 PM PDT 24
Peak memory 214176 kb
Host smart-1544c9e8-592d-4146-8aee-3673085f79b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223638669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2223638669
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3110626188
Short name T145
Test name
Test status
Simulation time 79586564 ps
CPU time 2.61 seconds
Started Jul 10 05:48:12 PM PDT 24
Finished Jul 10 05:48:16 PM PDT 24
Peak memory 207224 kb
Host smart-de944ecb-82f4-43ba-93e1-db54b60f9f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110626188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3110626188
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.456834507
Short name T801
Test name
Test status
Simulation time 874746410 ps
CPU time 6.33 seconds
Started Jul 10 05:48:08 PM PDT 24
Finished Jul 10 05:48:16 PM PDT 24
Peak memory 207128 kb
Host smart-0d6034ee-484e-486d-991f-45378d712a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456834507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.456834507
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.381261858
Short name T347
Test name
Test status
Simulation time 215489716 ps
CPU time 4.51 seconds
Started Jul 10 05:48:08 PM PDT 24
Finished Jul 10 05:48:14 PM PDT 24
Peak memory 207824 kb
Host smart-195d4883-8efa-4fdd-b7b0-2295f2da2c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381261858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.381261858
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2011775152
Short name T87
Test name
Test status
Simulation time 835986563 ps
CPU time 8.83 seconds
Started Jul 10 05:48:07 PM PDT 24
Finished Jul 10 05:48:18 PM PDT 24
Peak memory 208768 kb
Host smart-af6cbd64-5329-442b-809b-3c3563d2bc23
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011775152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2011775152
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.89550236
Short name T509
Test name
Test status
Simulation time 124656693 ps
CPU time 2.71 seconds
Started Jul 10 05:48:08 PM PDT 24
Finished Jul 10 05:48:12 PM PDT 24
Peak memory 208696 kb
Host smart-2eaed21f-9197-4d1c-80eb-498c4b2fe2f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89550236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.89550236
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3542020979
Short name T92
Test name
Test status
Simulation time 97192113 ps
CPU time 2.64 seconds
Started Jul 10 05:48:09 PM PDT 24
Finished Jul 10 05:48:14 PM PDT 24
Peak memory 206908 kb
Host smart-eb8e11ea-1474-446d-9fa4-30492ae0caf4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542020979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3542020979
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.4248388382
Short name T814
Test name
Test status
Simulation time 176865166 ps
CPU time 3.03 seconds
Started Jul 10 05:48:09 PM PDT 24
Finished Jul 10 05:48:14 PM PDT 24
Peak memory 214388 kb
Host smart-c0b6e962-5b4c-4631-bcf4-e6de2ac4a9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248388382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.4248388382
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1869698716
Short name T540
Test name
Test status
Simulation time 2110795800 ps
CPU time 4.81 seconds
Started Jul 10 05:48:10 PM PDT 24
Finished Jul 10 05:48:17 PM PDT 24
Peak memory 207860 kb
Host smart-cab44942-4451-4ef8-bf26-052ff00eb1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869698716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1869698716
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.4147389421
Short name T232
Test name
Test status
Simulation time 1466073552 ps
CPU time 35.68 seconds
Started Jul 10 05:48:11 PM PDT 24
Finished Jul 10 05:48:48 PM PDT 24
Peak memory 215548 kb
Host smart-7dc17889-0bec-42fe-9517-9a6701b83456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147389421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.4147389421
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2796407551
Short name T188
Test name
Test status
Simulation time 597031896 ps
CPU time 12.46 seconds
Started Jul 10 05:48:08 PM PDT 24
Finished Jul 10 05:48:22 PM PDT 24
Peak memory 220180 kb
Host smart-f7a8b2df-e9c8-4ded-8f94-5b9d22a85805
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796407551 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2796407551
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2214712028
Short name T321
Test name
Test status
Simulation time 102167201 ps
CPU time 5.07 seconds
Started Jul 10 05:48:07 PM PDT 24
Finished Jul 10 05:48:14 PM PDT 24
Peak memory 218268 kb
Host smart-5c83ab06-9a23-481e-993c-dfb3a45e0550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214712028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2214712028
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.4219201206
Short name T43
Test name
Test status
Simulation time 51187893 ps
CPU time 2.71 seconds
Started Jul 10 05:48:12 PM PDT 24
Finished Jul 10 05:48:16 PM PDT 24
Peak memory 209944 kb
Host smart-509ba405-14ba-4715-9a24-bb3ea875ab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219201206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.4219201206
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2378663807
Short name T246
Test name
Test status
Simulation time 45933240 ps
CPU time 3 seconds
Started Jul 10 05:48:37 PM PDT 24
Finished Jul 10 05:48:42 PM PDT 24
Peak memory 214328 kb
Host smart-07e905bc-6f24-4dad-ad81-3cb7164f74ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2378663807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2378663807
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.402545168
Short name T664
Test name
Test status
Simulation time 963953937 ps
CPU time 3.18 seconds
Started Jul 10 05:48:44 PM PDT 24
Finished Jul 10 05:48:49 PM PDT 24
Peak memory 219400 kb
Host smart-7b414fcc-2253-4397-925f-8c1dbcb53d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402545168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.402545168
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3807801471
Short name T762
Test name
Test status
Simulation time 25675131 ps
CPU time 2.11 seconds
Started Jul 10 05:48:39 PM PDT 24
Finished Jul 10 05:48:43 PM PDT 24
Peak memory 214348 kb
Host smart-af3ec59a-fd30-4d62-a942-ac7bb144b7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807801471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3807801471
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.619770405
Short name T802
Test name
Test status
Simulation time 89600310 ps
CPU time 3.13 seconds
Started Jul 10 05:48:37 PM PDT 24
Finished Jul 10 05:48:42 PM PDT 24
Peak memory 222528 kb
Host smart-153ed2c9-da22-4b3a-b432-712da7380815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619770405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.619770405
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2874779893
Short name T138
Test name
Test status
Simulation time 258010380 ps
CPU time 3.31 seconds
Started Jul 10 05:48:40 PM PDT 24
Finished Jul 10 05:48:45 PM PDT 24
Peak memory 208272 kb
Host smart-f1adf9d4-570c-44b1-a395-68205c553228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874779893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2874779893
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.396035518
Short name T779
Test name
Test status
Simulation time 729368819 ps
CPU time 5.9 seconds
Started Jul 10 05:48:39 PM PDT 24
Finished Jul 10 05:48:47 PM PDT 24
Peak memory 208588 kb
Host smart-41021327-5f0e-4211-a244-39116809660a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396035518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.396035518
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2161294679
Short name T656
Test name
Test status
Simulation time 2729480314 ps
CPU time 30.8 seconds
Started Jul 10 05:48:36 PM PDT 24
Finished Jul 10 05:49:09 PM PDT 24
Peak memory 208504 kb
Host smart-b1c238ff-ab91-4067-9261-91e48ae636a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161294679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2161294679
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2598653400
Short name T504
Test name
Test status
Simulation time 1023177811 ps
CPU time 26.07 seconds
Started Jul 10 05:48:39 PM PDT 24
Finished Jul 10 05:49:07 PM PDT 24
Peak memory 209228 kb
Host smart-a6bea304-094d-445f-af15-1c3a34941513
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598653400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2598653400
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2275155124
Short name T350
Test name
Test status
Simulation time 472295713 ps
CPU time 4.77 seconds
Started Jul 10 05:48:44 PM PDT 24
Finished Jul 10 05:48:50 PM PDT 24
Peak memory 209996 kb
Host smart-8f688b39-8978-4676-950e-b24f4a282ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275155124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2275155124
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3184785566
Short name T412
Test name
Test status
Simulation time 61627222 ps
CPU time 2.88 seconds
Started Jul 10 05:48:36 PM PDT 24
Finished Jul 10 05:48:41 PM PDT 24
Peak memory 207828 kb
Host smart-04f8bb6b-390f-44f4-b73a-3095e63cabd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184785566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3184785566
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3783083873
Short name T515
Test name
Test status
Simulation time 450021949 ps
CPU time 8.1 seconds
Started Jul 10 05:48:44 PM PDT 24
Finished Jul 10 05:48:53 PM PDT 24
Peak memory 210052 kb
Host smart-44d1e125-6979-46ef-af00-f103aea86e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783083873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3783083873
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2290578096
Short name T129
Test name
Test status
Simulation time 176756012 ps
CPU time 7.61 seconds
Started Jul 10 05:48:46 PM PDT 24
Finished Jul 10 05:48:55 PM PDT 24
Peak memory 222540 kb
Host smart-1d64ffd8-4605-4bfd-aaf9-0ebbe1c0188a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290578096 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2290578096
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3714847797
Short name T318
Test name
Test status
Simulation time 125288254 ps
CPU time 6.07 seconds
Started Jul 10 05:48:40 PM PDT 24
Finished Jul 10 05:48:48 PM PDT 24
Peak memory 210572 kb
Host smart-4a49724c-7647-4a39-b18f-3fa435cac7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714847797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3714847797
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2661751442
Short name T819
Test name
Test status
Simulation time 2651453070 ps
CPU time 24.21 seconds
Started Jul 10 05:48:43 PM PDT 24
Finished Jul 10 05:49:08 PM PDT 24
Peak memory 210620 kb
Host smart-63494dfa-6cb4-4cd1-9264-c33506c84003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661751442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2661751442
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.4246741849
Short name T632
Test name
Test status
Simulation time 9290409 ps
CPU time 0.71 seconds
Started Jul 10 05:48:44 PM PDT 24
Finished Jul 10 05:48:46 PM PDT 24
Peak memory 205836 kb
Host smart-3c258874-b99f-495d-8943-b514f25e4121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246741849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.4246741849
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1224964932
Short name T432
Test name
Test status
Simulation time 68972692 ps
CPU time 4.73 seconds
Started Jul 10 05:48:45 PM PDT 24
Finished Jul 10 05:48:51 PM PDT 24
Peak memory 215368 kb
Host smart-e33498ee-5602-4123-8213-52e81f30034f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1224964932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1224964932
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2143448182
Short name T34
Test name
Test status
Simulation time 51094837 ps
CPU time 2.81 seconds
Started Jul 10 05:48:43 PM PDT 24
Finished Jul 10 05:48:47 PM PDT 24
Peak memory 217976 kb
Host smart-c441d00a-3d08-4a88-8f14-dfb3e550eb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143448182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2143448182
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1819061213
Short name T493
Test name
Test status
Simulation time 419747839 ps
CPU time 4.05 seconds
Started Jul 10 05:48:43 PM PDT 24
Finished Jul 10 05:48:49 PM PDT 24
Peak memory 209584 kb
Host smart-8feae707-e6c8-447b-b6bb-385341fc3bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819061213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1819061213
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3015622557
Short name T909
Test name
Test status
Simulation time 64993104 ps
CPU time 2.39 seconds
Started Jul 10 05:48:45 PM PDT 24
Finished Jul 10 05:48:49 PM PDT 24
Peak memory 214336 kb
Host smart-a3716384-f72c-4b3e-bc59-eda809f3655e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015622557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3015622557
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.379264156
Short name T372
Test name
Test status
Simulation time 365760676 ps
CPU time 4.9 seconds
Started Jul 10 05:48:43 PM PDT 24
Finished Jul 10 05:48:49 PM PDT 24
Peak memory 220544 kb
Host smart-9cd62d03-f9a1-4648-8ad4-8081de416469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379264156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.379264156
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.148922634
Short name T425
Test name
Test status
Simulation time 179326576 ps
CPU time 4.4 seconds
Started Jul 10 05:48:44 PM PDT 24
Finished Jul 10 05:48:50 PM PDT 24
Peak memory 209956 kb
Host smart-d2995913-8687-4f40-85c5-6f181d79d9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148922634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.148922634
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1165847743
Short name T449
Test name
Test status
Simulation time 408778800 ps
CPU time 5.75 seconds
Started Jul 10 05:48:44 PM PDT 24
Finished Jul 10 05:48:52 PM PDT 24
Peak memory 214384 kb
Host smart-4e66e156-3f49-4257-9858-700f95436d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165847743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1165847743
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.468309187
Short name T213
Test name
Test status
Simulation time 68886585 ps
CPU time 1.92 seconds
Started Jul 10 05:48:45 PM PDT 24
Finished Jul 10 05:48:49 PM PDT 24
Peak memory 206624 kb
Host smart-0d3c01e6-0479-4e5a-84b5-91abe5370a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468309187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.468309187
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3490586536
Short name T568
Test name
Test status
Simulation time 57083357 ps
CPU time 2.82 seconds
Started Jul 10 05:48:43 PM PDT 24
Finished Jul 10 05:48:46 PM PDT 24
Peak memory 207260 kb
Host smart-a9411ca7-4cfb-48a6-a954-e8a9e239a865
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490586536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3490586536
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3330493814
Short name T878
Test name
Test status
Simulation time 128883788 ps
CPU time 2.46 seconds
Started Jul 10 05:48:45 PM PDT 24
Finished Jul 10 05:48:49 PM PDT 24
Peak memory 206776 kb
Host smart-5d7ea66f-af68-478e-bbc9-0490b228a7a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330493814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3330493814
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.4024136714
Short name T552
Test name
Test status
Simulation time 89061468 ps
CPU time 3.55 seconds
Started Jul 10 05:48:45 PM PDT 24
Finished Jul 10 05:48:51 PM PDT 24
Peak memory 218388 kb
Host smart-05ad383a-d4ca-46fd-9c97-b6065b04ca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024136714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.4024136714
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.552340314
Short name T686
Test name
Test status
Simulation time 45778712 ps
CPU time 2.47 seconds
Started Jul 10 05:48:45 PM PDT 24
Finished Jul 10 05:48:49 PM PDT 24
Peak memory 207088 kb
Host smart-b15a1ed9-9cf1-431a-b8a2-bda83c28d3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552340314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.552340314
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.889127106
Short name T203
Test name
Test status
Simulation time 1445847001 ps
CPU time 13 seconds
Started Jul 10 05:48:41 PM PDT 24
Finished Jul 10 05:48:55 PM PDT 24
Peak memory 219920 kb
Host smart-d95e03eb-fe99-4dce-a624-988fc10193bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889127106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.889127106
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3213798430
Short name T640
Test name
Test status
Simulation time 662339415 ps
CPU time 9.79 seconds
Started Jul 10 05:48:45 PM PDT 24
Finished Jul 10 05:48:56 PM PDT 24
Peak memory 222516 kb
Host smart-dda168a0-fbb5-4f56-906a-1b654091bfc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213798430 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3213798430
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1604919434
Short name T845
Test name
Test status
Simulation time 68428597 ps
CPU time 2.22 seconds
Started Jul 10 05:48:42 PM PDT 24
Finished Jul 10 05:48:45 PM PDT 24
Peak memory 209760 kb
Host smart-63e6910b-a113-46d0-bebd-60f59f9596e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604919434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1604919434
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1704511773
Short name T450
Test name
Test status
Simulation time 12444615 ps
CPU time 0.78 seconds
Started Jul 10 05:48:50 PM PDT 24
Finished Jul 10 05:48:52 PM PDT 24
Peak memory 206000 kb
Host smart-182e523f-b8e8-4cb9-8b91-8c9be5c402ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704511773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1704511773
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3135479309
Short name T394
Test name
Test status
Simulation time 1064928547 ps
CPU time 4.26 seconds
Started Jul 10 05:48:43 PM PDT 24
Finished Jul 10 05:48:48 PM PDT 24
Peak memory 214964 kb
Host smart-44b85eab-5e77-4aa2-9150-d82692649169
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3135479309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3135479309
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1851974569
Short name T910
Test name
Test status
Simulation time 166806845 ps
CPU time 4.69 seconds
Started Jul 10 05:48:43 PM PDT 24
Finished Jul 10 05:48:48 PM PDT 24
Peak memory 209632 kb
Host smart-f355d978-41d0-4703-926b-bdd049df5bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851974569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1851974569
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.496702063
Short name T105
Test name
Test status
Simulation time 379604471 ps
CPU time 4.81 seconds
Started Jul 10 05:48:43 PM PDT 24
Finished Jul 10 05:48:50 PM PDT 24
Peak memory 209808 kb
Host smart-600fbf45-d82a-4de4-8573-272d77a2247b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496702063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.496702063
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3954508975
Short name T500
Test name
Test status
Simulation time 622079329 ps
CPU time 4.86 seconds
Started Jul 10 05:48:51 PM PDT 24
Finished Jul 10 05:48:57 PM PDT 24
Peak memory 222436 kb
Host smart-ddfdf418-20eb-4c8f-950a-c429be35d29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954508975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3954508975
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1218347715
Short name T133
Test name
Test status
Simulation time 70549026 ps
CPU time 2.48 seconds
Started Jul 10 05:48:45 PM PDT 24
Finished Jul 10 05:48:49 PM PDT 24
Peak memory 214232 kb
Host smart-147e86d4-f96d-4d0e-9760-c499f50f5673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218347715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1218347715
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3306923547
Short name T598
Test name
Test status
Simulation time 1028281981 ps
CPU time 10.46 seconds
Started Jul 10 05:48:44 PM PDT 24
Finished Jul 10 05:48:56 PM PDT 24
Peak memory 207812 kb
Host smart-d103439e-a89d-4531-a611-507596fe54d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306923547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3306923547
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1064044228
Short name T714
Test name
Test status
Simulation time 90580212 ps
CPU time 3.98 seconds
Started Jul 10 05:48:44 PM PDT 24
Finished Jul 10 05:48:50 PM PDT 24
Peak memory 208436 kb
Host smart-cf4434f1-c74e-47ca-9dc0-91a40be00f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064044228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1064044228
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2738715528
Short name T463
Test name
Test status
Simulation time 152559304 ps
CPU time 4.57 seconds
Started Jul 10 05:48:46 PM PDT 24
Finished Jul 10 05:48:52 PM PDT 24
Peak memory 208804 kb
Host smart-164f16dc-f852-4726-888e-29d369337373
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738715528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2738715528
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1676242246
Short name T811
Test name
Test status
Simulation time 2875082144 ps
CPU time 7.56 seconds
Started Jul 10 05:48:45 PM PDT 24
Finished Jul 10 05:48:54 PM PDT 24
Peak memory 208788 kb
Host smart-78617be6-f71d-4ff8-8d16-bd609264ac2c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676242246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1676242246
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.244923648
Short name T446
Test name
Test status
Simulation time 722748337 ps
CPU time 2.9 seconds
Started Jul 10 05:48:44 PM PDT 24
Finished Jul 10 05:48:49 PM PDT 24
Peak memory 207036 kb
Host smart-21f40133-a67e-46e7-a784-abb9c3f27d08
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244923648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.244923648
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2711714753
Short name T513
Test name
Test status
Simulation time 315936227 ps
CPU time 2.15 seconds
Started Jul 10 05:48:49 PM PDT 24
Finished Jul 10 05:48:53 PM PDT 24
Peak memory 207648 kb
Host smart-8fcb9c84-fbf9-423d-8dd5-68e0c05154b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711714753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2711714753
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.833462918
Short name T210
Test name
Test status
Simulation time 47873796 ps
CPU time 2.33 seconds
Started Jul 10 05:48:44 PM PDT 24
Finished Jul 10 05:48:48 PM PDT 24
Peak memory 206788 kb
Host smart-da11b3aa-fce7-4359-84c1-54937abb8cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833462918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.833462918
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1929359315
Short name T876
Test name
Test status
Simulation time 4038917355 ps
CPU time 25.21 seconds
Started Jul 10 05:48:49 PM PDT 24
Finished Jul 10 05:49:15 PM PDT 24
Peak memory 222512 kb
Host smart-47c63083-feed-4820-9c04-3b4b266c6168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929359315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1929359315
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.4293693581
Short name T339
Test name
Test status
Simulation time 103587997 ps
CPU time 4.24 seconds
Started Jul 10 05:48:46 PM PDT 24
Finished Jul 10 05:48:51 PM PDT 24
Peak memory 214320 kb
Host smart-2c423155-c9ff-4d38-9e34-dbd75266e1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293693581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.4293693581
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.12579391
Short name T732
Test name
Test status
Simulation time 1475307929 ps
CPU time 22.79 seconds
Started Jul 10 05:48:48 PM PDT 24
Finished Jul 10 05:49:12 PM PDT 24
Peak memory 210612 kb
Host smart-49ff271a-1e40-460d-9e45-68f28566ed6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12579391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.12579391
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1604884102
Short name T462
Test name
Test status
Simulation time 22586389 ps
CPU time 0.95 seconds
Started Jul 10 05:48:57 PM PDT 24
Finished Jul 10 05:48:59 PM PDT 24
Peak memory 206104 kb
Host smart-8cb18512-7006-401b-b1a7-b1a3950e76d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604884102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1604884102
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.4267403450
Short name T428
Test name
Test status
Simulation time 148773906 ps
CPU time 3.15 seconds
Started Jul 10 05:48:50 PM PDT 24
Finished Jul 10 05:48:55 PM PDT 24
Peak memory 214236 kb
Host smart-b3438cd7-4cf2-481c-884e-2785ec4a39c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4267403450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.4267403450
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3726728391
Short name T907
Test name
Test status
Simulation time 518457630 ps
CPU time 6.87 seconds
Started Jul 10 05:48:53 PM PDT 24
Finished Jul 10 05:49:01 PM PDT 24
Peak memory 214600 kb
Host smart-c8b50e41-d863-4e96-b453-f2dbacbed86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726728391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3726728391
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1072826994
Short name T617
Test name
Test status
Simulation time 61338776 ps
CPU time 2.46 seconds
Started Jul 10 05:48:49 PM PDT 24
Finished Jul 10 05:48:53 PM PDT 24
Peak memory 207656 kb
Host smart-6d0181e9-48f7-421b-afe1-fd6f87ca4795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072826994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1072826994
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3717242073
Short name T102
Test name
Test status
Simulation time 185613402 ps
CPU time 4.73 seconds
Started Jul 10 05:48:48 PM PDT 24
Finished Jul 10 05:48:53 PM PDT 24
Peak memory 214332 kb
Host smart-825fb38c-f0c1-44b3-b8f3-3a163121c540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717242073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3717242073
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.326162307
Short name T573
Test name
Test status
Simulation time 822618129 ps
CPU time 5.34 seconds
Started Jul 10 05:48:49 PM PDT 24
Finished Jul 10 05:48:56 PM PDT 24
Peak memory 218504 kb
Host smart-14da39dc-a686-4e8a-8e44-1710b9e343e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326162307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.326162307
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1766193833
Short name T27
Test name
Test status
Simulation time 613384359 ps
CPU time 9 seconds
Started Jul 10 05:48:50 PM PDT 24
Finished Jul 10 05:49:00 PM PDT 24
Peak memory 208600 kb
Host smart-d37e0b0e-7b21-4625-9143-cf914eb642a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766193833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1766193833
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.987715740
Short name T871
Test name
Test status
Simulation time 223906074 ps
CPU time 2.91 seconds
Started Jul 10 05:48:48 PM PDT 24
Finished Jul 10 05:48:53 PM PDT 24
Peak memory 206824 kb
Host smart-184da93f-24c2-43bd-b0e0-6166e2103e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987715740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.987715740
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.304468270
Short name T458
Test name
Test status
Simulation time 900676983 ps
CPU time 12.51 seconds
Started Jul 10 05:48:50 PM PDT 24
Finished Jul 10 05:49:04 PM PDT 24
Peak memory 208568 kb
Host smart-585853a2-2711-42e4-9ab2-b72280e4300a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304468270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.304468270
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2478448901
Short name T694
Test name
Test status
Simulation time 961986900 ps
CPU time 6.15 seconds
Started Jul 10 05:48:48 PM PDT 24
Finished Jul 10 05:48:56 PM PDT 24
Peak memory 206912 kb
Host smart-5dcab8f2-c0ad-43e3-8635-3b65d54b62af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478448901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2478448901
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1886848409
Short name T344
Test name
Test status
Simulation time 237132649 ps
CPU time 2.57 seconds
Started Jul 10 05:48:50 PM PDT 24
Finished Jul 10 05:48:54 PM PDT 24
Peak memory 208492 kb
Host smart-42ee77f6-1061-4be2-bc77-b85d12ed67cd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886848409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1886848409
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2072322007
Short name T476
Test name
Test status
Simulation time 226137238 ps
CPU time 3.02 seconds
Started Jul 10 05:48:55 PM PDT 24
Finished Jul 10 05:48:59 PM PDT 24
Peak memory 215648 kb
Host smart-007f9993-f576-4644-932f-b40eac977dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072322007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2072322007
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1874624659
Short name T706
Test name
Test status
Simulation time 198926623 ps
CPU time 4.82 seconds
Started Jul 10 05:48:51 PM PDT 24
Finished Jul 10 05:48:57 PM PDT 24
Peak memory 206828 kb
Host smart-c1b2d116-2a42-4c9c-acde-e565c116ca9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874624659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1874624659
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1393552078
Short name T639
Test name
Test status
Simulation time 232734371 ps
CPU time 7.36 seconds
Started Jul 10 05:48:55 PM PDT 24
Finished Jul 10 05:49:03 PM PDT 24
Peak memory 220028 kb
Host smart-2bd6cbaf-9bcb-4506-96d9-263ac750c514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393552078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1393552078
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.276345853
Short name T312
Test name
Test status
Simulation time 295560618 ps
CPU time 8.12 seconds
Started Jul 10 05:48:52 PM PDT 24
Finished Jul 10 05:49:01 PM PDT 24
Peak memory 218468 kb
Host smart-6e7c60da-1aa6-4626-ac90-7a747e2218d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276345853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.276345853
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1316864682
Short name T142
Test name
Test status
Simulation time 115447456 ps
CPU time 2.24 seconds
Started Jul 10 05:49:07 PM PDT 24
Finished Jul 10 05:49:11 PM PDT 24
Peak memory 210380 kb
Host smart-756cbbf0-63e0-4402-9d81-2f3bc6073326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316864682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1316864682
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.482852812
Short name T780
Test name
Test status
Simulation time 10997615 ps
CPU time 0.77 seconds
Started Jul 10 05:49:03 PM PDT 24
Finished Jul 10 05:49:05 PM PDT 24
Peak memory 205832 kb
Host smart-dc424a65-1b0b-41c8-b823-1666521dc775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482852812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.482852812
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2257385006
Short name T622
Test name
Test status
Simulation time 263786023 ps
CPU time 2.91 seconds
Started Jul 10 05:49:05 PM PDT 24
Finished Jul 10 05:49:08 PM PDT 24
Peak memory 221436 kb
Host smart-1f606587-1adc-4ca4-b700-0c0e7a4d688e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257385006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2257385006
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.4293602474
Short name T74
Test name
Test status
Simulation time 23029193 ps
CPU time 1.82 seconds
Started Jul 10 05:48:59 PM PDT 24
Finished Jul 10 05:49:02 PM PDT 24
Peak memory 209664 kb
Host smart-869967b0-5d3d-4376-bb7e-0cf025a2bfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293602474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.4293602474
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3021306726
Short name T371
Test name
Test status
Simulation time 65035717 ps
CPU time 2.67 seconds
Started Jul 10 05:48:53 PM PDT 24
Finished Jul 10 05:48:57 PM PDT 24
Peak memory 214172 kb
Host smart-1a8cb6c4-e9fe-441f-98c0-c60c5261a594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021306726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3021306726
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1484105474
Short name T781
Test name
Test status
Simulation time 68664695 ps
CPU time 3.55 seconds
Started Jul 10 05:48:55 PM PDT 24
Finished Jul 10 05:48:59 PM PDT 24
Peak memory 209284 kb
Host smart-6f1480fc-3733-4fdd-b906-7b79895537cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484105474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1484105474
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2601036671
Short name T662
Test name
Test status
Simulation time 132951655 ps
CPU time 3.38 seconds
Started Jul 10 05:48:59 PM PDT 24
Finished Jul 10 05:49:04 PM PDT 24
Peak memory 207540 kb
Host smart-40d0711a-01d9-45a2-93e2-3474a207075c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601036671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2601036671
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.362970494
Short name T734
Test name
Test status
Simulation time 1040109952 ps
CPU time 23.12 seconds
Started Jul 10 05:48:56 PM PDT 24
Finished Jul 10 05:49:20 PM PDT 24
Peak memory 208788 kb
Host smart-32ea95d8-f716-464f-8317-ed8d1506d024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362970494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.362970494
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2677314345
Short name T837
Test name
Test status
Simulation time 73554234 ps
CPU time 3.87 seconds
Started Jul 10 05:48:54 PM PDT 24
Finished Jul 10 05:48:59 PM PDT 24
Peak memory 208648 kb
Host smart-b4d173f8-4cc0-4e62-a524-8a105077ce20
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677314345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2677314345
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1530419348
Short name T15
Test name
Test status
Simulation time 58001486 ps
CPU time 2.84 seconds
Started Jul 10 05:48:56 PM PDT 24
Finished Jul 10 05:49:00 PM PDT 24
Peak memory 206772 kb
Host smart-e79210e5-eac1-4d0c-b289-64dcbd967b8c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530419348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1530419348
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2121204036
Short name T723
Test name
Test status
Simulation time 167460724 ps
CPU time 2.89 seconds
Started Jul 10 05:49:07 PM PDT 24
Finished Jul 10 05:49:12 PM PDT 24
Peak memory 208756 kb
Host smart-ca7350b7-004f-4995-b60d-1a02c068dd8b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121204036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2121204036
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1114218187
Short name T86
Test name
Test status
Simulation time 141594998 ps
CPU time 1.61 seconds
Started Jul 10 05:48:59 PM PDT 24
Finished Jul 10 05:49:02 PM PDT 24
Peak memory 216272 kb
Host smart-797fb708-0c3d-408a-ab25-6e3973ba1963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114218187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1114218187
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1545700945
Short name T508
Test name
Test status
Simulation time 291523938 ps
CPU time 3.16 seconds
Started Jul 10 05:49:00 PM PDT 24
Finished Jul 10 05:49:05 PM PDT 24
Peak memory 208548 kb
Host smart-8dac66bc-386d-4463-9d8b-c01e800e7f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545700945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1545700945
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3343367212
Short name T548
Test name
Test status
Simulation time 273970383 ps
CPU time 7.13 seconds
Started Jul 10 05:49:07 PM PDT 24
Finished Jul 10 05:49:16 PM PDT 24
Peak memory 210244 kb
Host smart-04ebcb1b-c585-4a97-8493-820e0475054d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343367212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3343367212
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1589804425
Short name T402
Test name
Test status
Simulation time 165932828 ps
CPU time 1.31 seconds
Started Jul 10 05:48:59 PM PDT 24
Finished Jul 10 05:49:01 PM PDT 24
Peak memory 210312 kb
Host smart-9a1378d5-83ea-42c4-89f0-316a84363463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589804425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1589804425
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.4247170420
Short name T440
Test name
Test status
Simulation time 28865025 ps
CPU time 0.82 seconds
Started Jul 10 05:49:03 PM PDT 24
Finished Jul 10 05:49:04 PM PDT 24
Peak memory 205992 kb
Host smart-e5b6aa5a-b18c-481e-bf1c-5611d0637d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247170420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.4247170420
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3641258580
Short name T427
Test name
Test status
Simulation time 124480770 ps
CPU time 7.43 seconds
Started Jul 10 05:49:02 PM PDT 24
Finished Jul 10 05:49:10 PM PDT 24
Peak memory 214236 kb
Host smart-cf2ab873-5129-4e4c-a9fe-7f822f6f047d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3641258580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3641258580
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3548004283
Short name T7
Test name
Test status
Simulation time 49074653 ps
CPU time 2.3 seconds
Started Jul 10 05:49:00 PM PDT 24
Finished Jul 10 05:49:03 PM PDT 24
Peak memory 220568 kb
Host smart-d611e742-43a5-4e6b-ae04-72bae7a52c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548004283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3548004283
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3237558782
Short name T564
Test name
Test status
Simulation time 21672907 ps
CPU time 1.7 seconds
Started Jul 10 05:49:01 PM PDT 24
Finished Jul 10 05:49:04 PM PDT 24
Peak memory 208288 kb
Host smart-b6004031-ac79-4996-9bf5-a32ba29e70c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237558782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3237558782
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.20663217
Short name T563
Test name
Test status
Simulation time 807025429 ps
CPU time 2.77 seconds
Started Jul 10 05:49:05 PM PDT 24
Finished Jul 10 05:49:08 PM PDT 24
Peak memory 214260 kb
Host smart-8b096bf7-2ce4-4262-b9d7-d11dd6858f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20663217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.20663217
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2675610083
Short name T769
Test name
Test status
Simulation time 596439010 ps
CPU time 4.51 seconds
Started Jul 10 05:49:15 PM PDT 24
Finished Jul 10 05:49:22 PM PDT 24
Peak memory 214356 kb
Host smart-878c839e-90cd-4912-97c5-6b3bfb453a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675610083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2675610083
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.193768000
Short name T858
Test name
Test status
Simulation time 597051367 ps
CPU time 3.63 seconds
Started Jul 10 05:49:01 PM PDT 24
Finished Jul 10 05:49:06 PM PDT 24
Peak memory 207708 kb
Host smart-bf4ce081-6d2e-4868-8f3b-11320727f956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193768000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.193768000
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3932794485
Short name T660
Test name
Test status
Simulation time 75638397 ps
CPU time 1.9 seconds
Started Jul 10 05:49:02 PM PDT 24
Finished Jul 10 05:49:05 PM PDT 24
Peak memory 206952 kb
Host smart-fec968ad-ea50-4ec3-8d58-a398ed652dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932794485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3932794485
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1010084509
Short name T875
Test name
Test status
Simulation time 169195859 ps
CPU time 2.84 seconds
Started Jul 10 05:49:15 PM PDT 24
Finished Jul 10 05:49:19 PM PDT 24
Peak memory 208584 kb
Host smart-440d7b69-e87a-4d59-a151-831df26e82a9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010084509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1010084509
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3962193097
Short name T411
Test name
Test status
Simulation time 287190922 ps
CPU time 2.72 seconds
Started Jul 10 05:49:15 PM PDT 24
Finished Jul 10 05:49:20 PM PDT 24
Peak memory 208164 kb
Host smart-d7f30bc1-d4e6-4bc1-92a4-0923ab2925eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962193097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3962193097
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2486411494
Short name T216
Test name
Test status
Simulation time 211948254 ps
CPU time 6.12 seconds
Started Jul 10 05:49:03 PM PDT 24
Finished Jul 10 05:49:10 PM PDT 24
Peak memory 207864 kb
Host smart-87011056-5314-460f-9afc-da5e0a0e0a29
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486411494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2486411494
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1682537793
Short name T879
Test name
Test status
Simulation time 582806822 ps
CPU time 3.46 seconds
Started Jul 10 05:49:15 PM PDT 24
Finished Jul 10 05:49:20 PM PDT 24
Peak memory 218384 kb
Host smart-1674c761-ba55-4637-a759-792da83bdb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682537793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1682537793
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2966523830
Short name T733
Test name
Test status
Simulation time 287748107 ps
CPU time 2.59 seconds
Started Jul 10 05:49:15 PM PDT 24
Finished Jul 10 05:49:20 PM PDT 24
Peak memory 206668 kb
Host smart-b158bf5d-54a5-4a5c-9406-45f9edf97174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966523830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2966523830
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.4008383075
Short name T272
Test name
Test status
Simulation time 611104441 ps
CPU time 20.74 seconds
Started Jul 10 05:49:01 PM PDT 24
Finished Jul 10 05:49:23 PM PDT 24
Peak memory 216452 kb
Host smart-a05f4fcd-1f49-4c9d-8e3b-e3b7b8a4b4ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008383075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.4008383075
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1588015898
Short name T536
Test name
Test status
Simulation time 633720616 ps
CPU time 5.12 seconds
Started Jul 10 05:49:00 PM PDT 24
Finished Jul 10 05:49:06 PM PDT 24
Peak memory 208700 kb
Host smart-e67cac45-0a68-486e-905c-d3dccc1ef246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588015898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1588015898
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.110143143
Short name T527
Test name
Test status
Simulation time 105843878 ps
CPU time 1.09 seconds
Started Jul 10 05:49:06 PM PDT 24
Finished Jul 10 05:49:08 PM PDT 24
Peak memory 205972 kb
Host smart-59b178db-b944-46c0-bbcc-f950c73ab554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110143143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.110143143
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1918458683
Short name T73
Test name
Test status
Simulation time 98673073 ps
CPU time 3.16 seconds
Started Jul 10 05:49:09 PM PDT 24
Finished Jul 10 05:49:13 PM PDT 24
Peak memory 208940 kb
Host smart-2e0411ac-c101-4cbf-855b-5c005ace7c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918458683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1918458683
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2962306085
Short name T749
Test name
Test status
Simulation time 447570127 ps
CPU time 2.88 seconds
Started Jul 10 05:49:01 PM PDT 24
Finished Jul 10 05:49:05 PM PDT 24
Peak memory 210216 kb
Host smart-51e4c828-a868-43c7-a769-de0e14cb4538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962306085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2962306085
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1042740606
Short name T892
Test name
Test status
Simulation time 375185039 ps
CPU time 4.79 seconds
Started Jul 10 05:49:06 PM PDT 24
Finished Jul 10 05:49:12 PM PDT 24
Peak memory 216764 kb
Host smart-65a53e9c-3176-4a3e-8b78-0f9ee7307414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042740606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1042740606
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2508513293
Short name T499
Test name
Test status
Simulation time 105213013 ps
CPU time 1.62 seconds
Started Jul 10 05:49:11 PM PDT 24
Finished Jul 10 05:49:15 PM PDT 24
Peak memory 206136 kb
Host smart-c8703376-e827-4962-a0e8-434efc03e76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508513293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2508513293
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.634692088
Short name T726
Test name
Test status
Simulation time 596302300 ps
CPU time 2.72 seconds
Started Jul 10 05:49:00 PM PDT 24
Finished Jul 10 05:49:04 PM PDT 24
Peak memory 206920 kb
Host smart-0ae84a82-bb51-4857-be6e-9869a274c3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634692088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.634692088
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2665047187
Short name T901
Test name
Test status
Simulation time 125396182 ps
CPU time 4.38 seconds
Started Jul 10 05:49:07 PM PDT 24
Finished Jul 10 05:49:14 PM PDT 24
Peak memory 208592 kb
Host smart-7d20029c-77c1-41d4-8814-3a3ada1e19b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665047187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2665047187
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.310158577
Short name T386
Test name
Test status
Simulation time 75982084 ps
CPU time 2.94 seconds
Started Jul 10 05:49:15 PM PDT 24
Finished Jul 10 05:49:19 PM PDT 24
Peak memory 206900 kb
Host smart-c75529ca-3cbf-4dfb-af4b-55584b7e663a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310158577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.310158577
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3133023366
Short name T790
Test name
Test status
Simulation time 86358726 ps
CPU time 1.99 seconds
Started Jul 10 05:49:01 PM PDT 24
Finished Jul 10 05:49:04 PM PDT 24
Peak memory 207500 kb
Host smart-68867aba-8a97-4e7f-b98a-be9a8da6ad46
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133023366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3133023366
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.372948247
Short name T498
Test name
Test status
Simulation time 201150707 ps
CPU time 2.64 seconds
Started Jul 10 05:49:03 PM PDT 24
Finished Jul 10 05:49:06 PM PDT 24
Peak memory 206884 kb
Host smart-9b30bd95-dff1-4e6b-b551-6b3472d7f5f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372948247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.372948247
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.4057460677
Short name T916
Test name
Test status
Simulation time 509824806 ps
CPU time 3.5 seconds
Started Jul 10 05:49:07 PM PDT 24
Finished Jul 10 05:49:12 PM PDT 24
Peak memory 207600 kb
Host smart-71af9942-d864-4ea6-9050-9e1ec7bd40a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057460677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.4057460677
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.576159824
Short name T494
Test name
Test status
Simulation time 103954973 ps
CPU time 2.48 seconds
Started Jul 10 05:49:15 PM PDT 24
Finished Jul 10 05:49:19 PM PDT 24
Peak memory 208500 kb
Host smart-b7482a8b-c9c9-4d11-aa6f-f500d1f59320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576159824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.576159824
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3034831372
Short name T788
Test name
Test status
Simulation time 136790244 ps
CPU time 4.32 seconds
Started Jul 10 05:49:05 PM PDT 24
Finished Jul 10 05:49:11 PM PDT 24
Peak memory 214308 kb
Host smart-b4d90eb0-425c-44c6-9955-146c82b5290d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034831372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3034831372
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3986235356
Short name T333
Test name
Test status
Simulation time 158211347 ps
CPU time 6.47 seconds
Started Jul 10 05:49:08 PM PDT 24
Finished Jul 10 05:49:16 PM PDT 24
Peak memory 218672 kb
Host smart-916e99d7-ef5a-4ad5-b3ca-3ba2296a4186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986235356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3986235356
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2255455145
Short name T830
Test name
Test status
Simulation time 97179436 ps
CPU time 2.39 seconds
Started Jul 10 05:49:12 PM PDT 24
Finished Jul 10 05:49:17 PM PDT 24
Peak memory 210168 kb
Host smart-9410d532-daa5-4887-90bc-eef75c1957ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255455145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2255455145
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2416109460
Short name T483
Test name
Test status
Simulation time 10524977 ps
CPU time 0.82 seconds
Started Jul 10 05:49:10 PM PDT 24
Finished Jul 10 05:49:14 PM PDT 24
Peak memory 205976 kb
Host smart-79dafbfd-e2b7-4b88-8a09-000e458c6b6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416109460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2416109460
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2095438451
Short name T418
Test name
Test status
Simulation time 267141535 ps
CPU time 13.18 seconds
Started Jul 10 05:49:06 PM PDT 24
Finished Jul 10 05:49:21 PM PDT 24
Peak memory 214712 kb
Host smart-4bc0cca3-92f5-4db3-a40f-696b32077bef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2095438451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2095438451
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2764411202
Short name T229
Test name
Test status
Simulation time 460670486 ps
CPU time 3.46 seconds
Started Jul 10 05:49:05 PM PDT 24
Finished Jul 10 05:49:10 PM PDT 24
Peak memory 218556 kb
Host smart-d014a806-858d-4936-a908-45a6ee8185a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764411202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2764411202
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2292566483
Short name T60
Test name
Test status
Simulation time 606539761 ps
CPU time 3.63 seconds
Started Jul 10 05:49:07 PM PDT 24
Finished Jul 10 05:49:12 PM PDT 24
Peak memory 209640 kb
Host smart-8b1bfced-647b-45c5-924e-cab1606556a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292566483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2292566483
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.996172427
Short name T390
Test name
Test status
Simulation time 143256070 ps
CPU time 3.78 seconds
Started Jul 10 05:49:07 PM PDT 24
Finished Jul 10 05:49:12 PM PDT 24
Peak memory 214340 kb
Host smart-66b790d5-131e-4ac8-83c7-be47bf6c2002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996172427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.996172427
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.301969547
Short name T606
Test name
Test status
Simulation time 56266521 ps
CPU time 2.76 seconds
Started Jul 10 05:49:08 PM PDT 24
Finished Jul 10 05:49:13 PM PDT 24
Peak memory 214260 kb
Host smart-d360bc72-8939-4634-927b-d35b7e431435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301969547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.301969547
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2174714212
Short name T588
Test name
Test status
Simulation time 52766025 ps
CPU time 3.5 seconds
Started Jul 10 05:49:07 PM PDT 24
Finished Jul 10 05:49:12 PM PDT 24
Peak memory 219920 kb
Host smart-a9044816-9c0a-42f6-b7c1-d84494595002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174714212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2174714212
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2554632412
Short name T307
Test name
Test status
Simulation time 88985685 ps
CPU time 4.5 seconds
Started Jul 10 05:49:06 PM PDT 24
Finished Jul 10 05:49:12 PM PDT 24
Peak memory 214232 kb
Host smart-8c84eb58-7061-42e4-a119-f823ebb0d97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554632412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2554632412
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.112478708
Short name T809
Test name
Test status
Simulation time 429810963 ps
CPU time 3.89 seconds
Started Jul 10 05:49:06 PM PDT 24
Finished Jul 10 05:49:11 PM PDT 24
Peak memory 208596 kb
Host smart-d8b8cc1b-0ada-4ba8-b3a5-3a9b65456369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112478708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.112478708
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3076410761
Short name T533
Test name
Test status
Simulation time 84391630 ps
CPU time 1.78 seconds
Started Jul 10 05:49:06 PM PDT 24
Finished Jul 10 05:49:09 PM PDT 24
Peak memory 206956 kb
Host smart-9e951301-3a5b-4825-aad8-48226abc9091
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076410761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3076410761
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.220887305
Short name T524
Test name
Test status
Simulation time 76317796 ps
CPU time 1.61 seconds
Started Jul 10 05:49:06 PM PDT 24
Finished Jul 10 05:49:09 PM PDT 24
Peak memory 206980 kb
Host smart-78992da9-aafa-459f-9c12-b3ed974bb42a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220887305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.220887305
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2672843967
Short name T643
Test name
Test status
Simulation time 34426517 ps
CPU time 2.18 seconds
Started Jul 10 05:49:12 PM PDT 24
Finished Jul 10 05:49:16 PM PDT 24
Peak memory 207004 kb
Host smart-9fc37a1e-796f-4303-8be9-a6eabd3a796d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672843967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2672843967
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.379487700
Short name T453
Test name
Test status
Simulation time 34706923 ps
CPU time 2.29 seconds
Started Jul 10 05:49:07 PM PDT 24
Finished Jul 10 05:49:11 PM PDT 24
Peak memory 214256 kb
Host smart-c1f34cc0-70cb-403b-8bee-581af50acf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379487700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.379487700
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2574253680
Short name T569
Test name
Test status
Simulation time 749534673 ps
CPU time 7.82 seconds
Started Jul 10 05:49:05 PM PDT 24
Finished Jul 10 05:49:14 PM PDT 24
Peak memory 208068 kb
Host smart-9e2ae232-3b4a-484f-be47-f599ebebeb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574253680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2574253680
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1830247443
Short name T132
Test name
Test status
Simulation time 796365397 ps
CPU time 14.07 seconds
Started Jul 10 05:49:08 PM PDT 24
Finished Jul 10 05:49:24 PM PDT 24
Peak memory 222716 kb
Host smart-40d87920-97f5-4865-8058-5f6379aafa6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830247443 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1830247443
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3754321372
Short name T742
Test name
Test status
Simulation time 317635728 ps
CPU time 8.53 seconds
Started Jul 10 05:49:08 PM PDT 24
Finished Jul 10 05:49:18 PM PDT 24
Peak memory 214320 kb
Host smart-70fb77a4-2de7-4db8-a7bf-72120978ccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754321372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3754321372
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2661725006
Short name T206
Test name
Test status
Simulation time 946212827 ps
CPU time 3.05 seconds
Started Jul 10 05:49:05 PM PDT 24
Finished Jul 10 05:49:10 PM PDT 24
Peak memory 210260 kb
Host smart-1ea10c91-0c3e-48bb-9223-b2b7ceab3335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661725006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2661725006
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2921068834
Short name T839
Test name
Test status
Simulation time 38057814 ps
CPU time 0.78 seconds
Started Jul 10 05:49:11 PM PDT 24
Finished Jul 10 05:49:14 PM PDT 24
Peak memory 205912 kb
Host smart-ee8d1ebf-94ea-4616-9300-4e82f61e0935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921068834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2921068834
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2310318791
Short name T266
Test name
Test status
Simulation time 850925725 ps
CPU time 8.37 seconds
Started Jul 10 05:49:11 PM PDT 24
Finished Jul 10 05:49:22 PM PDT 24
Peak memory 214336 kb
Host smart-c863d3ed-70fe-4867-b676-de82a1c1104f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2310318791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2310318791
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2191562484
Short name T11
Test name
Test status
Simulation time 79314582 ps
CPU time 4.17 seconds
Started Jul 10 05:49:12 PM PDT 24
Finished Jul 10 05:49:18 PM PDT 24
Peak memory 214808 kb
Host smart-1339a0a8-fd5d-4196-8a81-d5187a54bf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191562484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2191562484
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3358894055
Short name T856
Test name
Test status
Simulation time 69863345 ps
CPU time 2.5 seconds
Started Jul 10 05:49:16 PM PDT 24
Finished Jul 10 05:49:21 PM PDT 24
Peak memory 207584 kb
Host smart-9c6d3b92-1de0-40b6-bd7d-4488ead387e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358894055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3358894055
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3650764944
Short name T98
Test name
Test status
Simulation time 117708172 ps
CPU time 3.37 seconds
Started Jul 10 05:49:12 PM PDT 24
Finished Jul 10 05:49:17 PM PDT 24
Peak memory 214328 kb
Host smart-dfa175aa-44b4-4937-b31a-6a7dc6edea19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650764944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3650764944
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3566329215
Short name T610
Test name
Test status
Simulation time 49271798 ps
CPU time 1.91 seconds
Started Jul 10 05:49:16 PM PDT 24
Finished Jul 10 05:49:21 PM PDT 24
Peak memory 214324 kb
Host smart-5275a436-7b06-4648-a15a-4a05bd15c393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566329215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3566329215
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.4212326424
Short name T604
Test name
Test status
Simulation time 207512351 ps
CPU time 2.73 seconds
Started Jul 10 05:49:16 PM PDT 24
Finished Jul 10 05:49:22 PM PDT 24
Peak memory 206576 kb
Host smart-973e07b2-8691-4f46-9cc5-c34657087ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212326424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.4212326424
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2249156749
Short name T582
Test name
Test status
Simulation time 380151201 ps
CPU time 6.26 seconds
Started Jul 10 05:49:05 PM PDT 24
Finished Jul 10 05:49:13 PM PDT 24
Peak memory 209308 kb
Host smart-5c4780ac-b90a-4401-9fb6-be85416bbb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249156749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2249156749
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2932119332
Short name T364
Test name
Test status
Simulation time 32976961 ps
CPU time 2.51 seconds
Started Jul 10 05:49:08 PM PDT 24
Finished Jul 10 05:49:12 PM PDT 24
Peak memory 208628 kb
Host smart-562fb0f4-d1f0-4eec-b9de-81001124f001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932119332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2932119332
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2998355531
Short name T661
Test name
Test status
Simulation time 146737803 ps
CPU time 3.74 seconds
Started Jul 10 05:49:06 PM PDT 24
Finished Jul 10 05:49:12 PM PDT 24
Peak memory 208796 kb
Host smart-a5863ca4-6b85-4ca0-bc42-c4cbf0d4833d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998355531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2998355531
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1489985198
Short name T5
Test name
Test status
Simulation time 299061342 ps
CPU time 2.97 seconds
Started Jul 10 05:49:07 PM PDT 24
Finished Jul 10 05:49:12 PM PDT 24
Peak memory 206844 kb
Host smart-78a158a1-ab17-4411-91bd-fb6c5a60c4a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489985198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1489985198
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3648104777
Short name T741
Test name
Test status
Simulation time 140011035 ps
CPU time 3.53 seconds
Started Jul 10 05:49:07 PM PDT 24
Finished Jul 10 05:49:13 PM PDT 24
Peak memory 208676 kb
Host smart-95b71f0b-4bcf-4611-a8ce-13e2a3dc7dc7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648104777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3648104777
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1294321027
Short name T454
Test name
Test status
Simulation time 1396079884 ps
CPU time 3.62 seconds
Started Jul 10 05:49:11 PM PDT 24
Finished Jul 10 05:49:17 PM PDT 24
Peak memory 209160 kb
Host smart-2a76f99c-39b4-4bc9-9a25-87a9a08e1024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294321027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1294321027
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1435817820
Short name T437
Test name
Test status
Simulation time 67114073 ps
CPU time 2.8 seconds
Started Jul 10 05:49:11 PM PDT 24
Finished Jul 10 05:49:16 PM PDT 24
Peak memory 208328 kb
Host smart-7a7d9473-96a2-4693-96b4-54bc21bcfe8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435817820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1435817820
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1744642077
Short name T62
Test name
Test status
Simulation time 448218371 ps
CPU time 17.89 seconds
Started Jul 10 05:49:12 PM PDT 24
Finished Jul 10 05:49:32 PM PDT 24
Peak memory 220952 kb
Host smart-64a6a5b2-3d32-4609-b6e1-d3fe992fdb3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744642077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1744642077
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.4202845836
Short name T186
Test name
Test status
Simulation time 795029573 ps
CPU time 16.26 seconds
Started Jul 10 05:49:15 PM PDT 24
Finished Jul 10 05:49:34 PM PDT 24
Peak memory 222532 kb
Host smart-ab2b5dbf-db65-4832-8ec6-6b5019d7e589
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202845836 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.4202845836
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1461767631
Short name T380
Test name
Test status
Simulation time 1406592852 ps
CPU time 19.62 seconds
Started Jul 10 05:49:13 PM PDT 24
Finished Jul 10 05:49:34 PM PDT 24
Peak memory 209252 kb
Host smart-7205b56b-64e5-45ff-ba15-60111abf0fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461767631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1461767631
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2659015856
Short name T866
Test name
Test status
Simulation time 89189960 ps
CPU time 3.2 seconds
Started Jul 10 05:49:13 PM PDT 24
Finished Jul 10 05:49:18 PM PDT 24
Peak memory 210400 kb
Host smart-5c712acc-c5bf-4470-8ef3-248858326b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659015856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2659015856
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2189662697
Short name T626
Test name
Test status
Simulation time 11933148 ps
CPU time 0.91 seconds
Started Jul 10 05:49:10 PM PDT 24
Finished Jul 10 05:49:12 PM PDT 24
Peak memory 205992 kb
Host smart-7c662a65-a389-416c-8fe7-66bd527fc93a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189662697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2189662697
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3967109570
Short name T433
Test name
Test status
Simulation time 203140040 ps
CPU time 3.96 seconds
Started Jul 10 05:49:16 PM PDT 24
Finished Jul 10 05:49:22 PM PDT 24
Peak memory 214344 kb
Host smart-d6374d1f-fc2d-4a5d-bc23-bced9f75aada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3967109570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3967109570
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3089762370
Short name T708
Test name
Test status
Simulation time 35933832 ps
CPU time 1.45 seconds
Started Jul 10 05:49:12 PM PDT 24
Finished Jul 10 05:49:16 PM PDT 24
Peak memory 207904 kb
Host smart-aef54aa2-eb90-4c02-859b-a8130b833615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089762370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3089762370
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.4215606905
Short name T700
Test name
Test status
Simulation time 113789374 ps
CPU time 2.08 seconds
Started Jul 10 05:49:11 PM PDT 24
Finished Jul 10 05:49:16 PM PDT 24
Peak memory 214328 kb
Host smart-809111cf-fde4-4984-84ec-5dcb7c514543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215606905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.4215606905
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1625039146
Short name T297
Test name
Test status
Simulation time 87184997 ps
CPU time 3.92 seconds
Started Jul 10 05:49:12 PM PDT 24
Finished Jul 10 05:49:18 PM PDT 24
Peak memory 214280 kb
Host smart-19338f46-b8af-41f1-922e-dd05016a4b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625039146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1625039146
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.221061029
Short name T230
Test name
Test status
Simulation time 108884495 ps
CPU time 3.01 seconds
Started Jul 10 05:49:15 PM PDT 24
Finished Jul 10 05:49:21 PM PDT 24
Peak memory 210320 kb
Host smart-3e3de9b8-39f1-46fb-91fa-8df4573957ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221061029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.221061029
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1768518275
Short name T502
Test name
Test status
Simulation time 21272913049 ps
CPU time 84.49 seconds
Started Jul 10 05:49:13 PM PDT 24
Finished Jul 10 05:50:39 PM PDT 24
Peak memory 209768 kb
Host smart-d02296a7-0f4f-4af8-adde-4bed1b158546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768518275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1768518275
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2349059805
Short name T903
Test name
Test status
Simulation time 21540836 ps
CPU time 1.84 seconds
Started Jul 10 05:49:12 PM PDT 24
Finished Jul 10 05:49:16 PM PDT 24
Peak memory 206896 kb
Host smart-87289cf6-b0f4-4732-a7f0-f5b205d4ebcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349059805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2349059805
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3757948466
Short name T472
Test name
Test status
Simulation time 5177433744 ps
CPU time 21.11 seconds
Started Jul 10 05:49:10 PM PDT 24
Finished Jul 10 05:49:34 PM PDT 24
Peak memory 208300 kb
Host smart-dd2879be-ce3e-4628-926b-a2a9a8e6c4cd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757948466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3757948466
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.416143279
Short name T543
Test name
Test status
Simulation time 297587497 ps
CPU time 6.15 seconds
Started Jul 10 05:49:12 PM PDT 24
Finished Jul 10 05:49:20 PM PDT 24
Peak memory 208072 kb
Host smart-f73b08a2-66dd-442d-a72e-094a241cb8c3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416143279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.416143279
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1715405054
Short name T322
Test name
Test status
Simulation time 86542574 ps
CPU time 2.09 seconds
Started Jul 10 05:49:12 PM PDT 24
Finished Jul 10 05:49:16 PM PDT 24
Peak memory 208892 kb
Host smart-736b31ff-bf81-4091-a2d7-49b979e1e7b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715405054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1715405054
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1852601646
Short name T915
Test name
Test status
Simulation time 67640638 ps
CPU time 2.57 seconds
Started Jul 10 05:49:16 PM PDT 24
Finished Jul 10 05:49:22 PM PDT 24
Peak memory 209580 kb
Host smart-0ceaaa04-fcf3-4eed-b85a-c3164737c3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852601646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1852601646
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2598829447
Short name T896
Test name
Test status
Simulation time 762307648 ps
CPU time 3.62 seconds
Started Jul 10 05:49:10 PM PDT 24
Finished Jul 10 05:49:16 PM PDT 24
Peak memory 208648 kb
Host smart-9df4a166-9989-436b-afd1-a1c7ef32d824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598829447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2598829447
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3125358489
Short name T698
Test name
Test status
Simulation time 2346178786 ps
CPU time 15.72 seconds
Started Jul 10 05:49:15 PM PDT 24
Finished Jul 10 05:49:32 PM PDT 24
Peak memory 214380 kb
Host smart-8d4293ce-18c4-4522-bd58-632f9519cabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125358489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3125358489
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1303053168
Short name T667
Test name
Test status
Simulation time 95122984 ps
CPU time 2.32 seconds
Started Jul 10 05:49:10 PM PDT 24
Finished Jul 10 05:49:14 PM PDT 24
Peak memory 209984 kb
Host smart-e2b16aa2-6c1b-4380-83bf-c91c7b24c505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303053168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1303053168
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.640282420
Short name T456
Test name
Test status
Simulation time 22051352 ps
CPU time 0.86 seconds
Started Jul 10 05:48:17 PM PDT 24
Finished Jul 10 05:48:19 PM PDT 24
Peak memory 205968 kb
Host smart-0b7e0dd0-5ea4-4a28-84f6-6c07f1bc9267
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640282420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.640282420
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1144148900
Short name T93
Test name
Test status
Simulation time 221843506 ps
CPU time 8.54 seconds
Started Jul 10 05:48:17 PM PDT 24
Finished Jul 10 05:48:27 PM PDT 24
Peak memory 215424 kb
Host smart-860d32b3-5818-4eb9-a973-c231a65aba46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1144148900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1144148900
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.311110131
Short name T72
Test name
Test status
Simulation time 217089815 ps
CPU time 2.38 seconds
Started Jul 10 05:48:16 PM PDT 24
Finished Jul 10 05:48:20 PM PDT 24
Peak memory 207340 kb
Host smart-a8f60a25-0223-4131-954f-6974eb1b3210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311110131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.311110131
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.4048200165
Short name T898
Test name
Test status
Simulation time 86386161 ps
CPU time 4.23 seconds
Started Jul 10 05:48:13 PM PDT 24
Finished Jul 10 05:48:19 PM PDT 24
Peak memory 214392 kb
Host smart-b430206a-1770-42d2-be62-1ec4c29e929d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048200165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4048200165
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.305888233
Short name T787
Test name
Test status
Simulation time 226480260 ps
CPU time 5.33 seconds
Started Jul 10 05:48:25 PM PDT 24
Finished Jul 10 05:48:32 PM PDT 24
Peak memory 222388 kb
Host smart-c310a10d-3803-4abb-ba7c-4a0444db9b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305888233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.305888233
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_random.1290570564
Short name T354
Test name
Test status
Simulation time 147237796 ps
CPU time 5.73 seconds
Started Jul 10 05:48:12 PM PDT 24
Finished Jul 10 05:48:20 PM PDT 24
Peak memory 207444 kb
Host smart-171e2f81-e7d5-416e-aae0-f3588ad7819c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290570564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1290570564
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3959211775
Short name T14
Test name
Test status
Simulation time 444294286 ps
CPU time 6.69 seconds
Started Jul 10 05:48:25 PM PDT 24
Finished Jul 10 05:48:34 PM PDT 24
Peak memory 229008 kb
Host smart-aac8a274-8c76-4c5a-be43-cc73b517ce96
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959211775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3959211775
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.857818925
Short name T348
Test name
Test status
Simulation time 118938951 ps
CPU time 4.34 seconds
Started Jul 10 05:48:15 PM PDT 24
Finished Jul 10 05:48:21 PM PDT 24
Peak memory 208720 kb
Host smart-6e9c4c26-b909-4c20-adc0-7b279c589927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857818925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.857818925
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2935786223
Short name T544
Test name
Test status
Simulation time 2450867996 ps
CPU time 41.36 seconds
Started Jul 10 05:48:15 PM PDT 24
Finished Jul 10 05:48:58 PM PDT 24
Peak memory 208016 kb
Host smart-e0eb2f09-7c7b-490a-b2b9-20bdf4c7c5cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935786223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2935786223
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.810648378
Short name T377
Test name
Test status
Simulation time 1193185886 ps
CPU time 13.29 seconds
Started Jul 10 05:48:18 PM PDT 24
Finished Jul 10 05:48:34 PM PDT 24
Peak memory 208460 kb
Host smart-7dca23aa-67f1-40d1-be79-b10498df5417
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810648378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.810648378
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1935309798
Short name T621
Test name
Test status
Simulation time 156110625 ps
CPU time 3.87 seconds
Started Jul 10 05:48:13 PM PDT 24
Finished Jul 10 05:48:19 PM PDT 24
Peak memory 208832 kb
Host smart-31ee47d5-9849-4eca-8825-e42cf20f3a63
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935309798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1935309798
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2707595964
Short name T831
Test name
Test status
Simulation time 56241017 ps
CPU time 2.96 seconds
Started Jul 10 05:48:15 PM PDT 24
Finished Jul 10 05:48:20 PM PDT 24
Peak memory 214352 kb
Host smart-489ec8da-9878-4bc1-b3f2-c4fd7656c6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707595964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2707595964
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3552100596
Short name T415
Test name
Test status
Simulation time 133830239 ps
CPU time 4.49 seconds
Started Jul 10 05:48:15 PM PDT 24
Finished Jul 10 05:48:21 PM PDT 24
Peak memory 206728 kb
Host smart-bdc0c0df-c5d2-499a-9fa0-0f0bc2b14458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552100596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3552100596
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2057995325
Short name T134
Test name
Test status
Simulation time 125647970 ps
CPU time 5.92 seconds
Started Jul 10 05:48:15 PM PDT 24
Finished Jul 10 05:48:23 PM PDT 24
Peak memory 209480 kb
Host smart-146aed8e-eb93-4c3a-8f70-686294ee1d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057995325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2057995325
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.444889794
Short name T173
Test name
Test status
Simulation time 135181521 ps
CPU time 1.46 seconds
Started Jul 10 05:48:24 PM PDT 24
Finished Jul 10 05:48:28 PM PDT 24
Peak memory 209972 kb
Host smart-bd8fa245-9dd4-42f2-beb1-e36453dd32a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444889794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.444889794
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.585442596
Short name T496
Test name
Test status
Simulation time 24224671 ps
CPU time 0.89 seconds
Started Jul 10 05:49:22 PM PDT 24
Finished Jul 10 05:49:26 PM PDT 24
Peak memory 205988 kb
Host smart-39c68211-56aa-42bd-865d-091cea061a79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585442596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.585442596
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.761968498
Short name T430
Test name
Test status
Simulation time 842380872 ps
CPU time 13.69 seconds
Started Jul 10 05:49:16 PM PDT 24
Finished Jul 10 05:49:33 PM PDT 24
Peak memory 215076 kb
Host smart-f51ac400-4a5f-4a60-a445-c3f8f356b6e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=761968498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.761968498
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2488802106
Short name T32
Test name
Test status
Simulation time 91909122 ps
CPU time 3.6 seconds
Started Jul 10 05:49:15 PM PDT 24
Finished Jul 10 05:49:22 PM PDT 24
Peak memory 214228 kb
Host smart-99861825-949a-4a51-936a-a887e97e2b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488802106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2488802106
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1931176264
Short name T512
Test name
Test status
Simulation time 1029576471 ps
CPU time 4.18 seconds
Started Jul 10 05:49:18 PM PDT 24
Finished Jul 10 05:49:26 PM PDT 24
Peak memory 209260 kb
Host smart-0f49494d-a7a2-42eb-930a-1aa1a73f6354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931176264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1931176264
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1478525044
Short name T737
Test name
Test status
Simulation time 77449195 ps
CPU time 2.95 seconds
Started Jul 10 05:49:19 PM PDT 24
Finished Jul 10 05:49:26 PM PDT 24
Peak memory 222568 kb
Host smart-48b8c4df-e2fa-4a54-8c14-c643f27d881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478525044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1478525044
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.212890788
Short name T252
Test name
Test status
Simulation time 242769221 ps
CPU time 3.14 seconds
Started Jul 10 05:49:21 PM PDT 24
Finished Jul 10 05:49:27 PM PDT 24
Peak memory 214264 kb
Host smart-affedff2-c937-4b2c-bdb6-09771005dccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212890788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.212890788
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_random.3805597743
Short name T335
Test name
Test status
Simulation time 546672715 ps
CPU time 4.47 seconds
Started Jul 10 05:49:17 PM PDT 24
Finished Jul 10 05:49:24 PM PDT 24
Peak memory 210148 kb
Host smart-6d39445e-1ea4-451a-a755-fd79307781c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805597743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3805597743
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.741983560
Short name T467
Test name
Test status
Simulation time 189166759 ps
CPU time 6.92 seconds
Started Jul 10 05:49:18 PM PDT 24
Finished Jul 10 05:49:27 PM PDT 24
Peak memory 208868 kb
Host smart-c0356a2b-8cd0-49c3-9286-1c163d72c3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741983560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.741983560
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.131437780
Short name T305
Test name
Test status
Simulation time 839006316 ps
CPU time 9.35 seconds
Started Jul 10 05:49:19 PM PDT 24
Finished Jul 10 05:49:32 PM PDT 24
Peak memory 207252 kb
Host smart-07a5136d-bf69-4c8e-ac80-21fe5c3c78f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131437780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.131437780
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3153253464
Short name T751
Test name
Test status
Simulation time 156980348 ps
CPU time 4.97 seconds
Started Jul 10 05:49:10 PM PDT 24
Finished Jul 10 05:49:16 PM PDT 24
Peak memory 208184 kb
Host smart-a234d5c8-46bc-4aff-9357-19a0dd8b2ad6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153253464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3153253464
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1256606102
Short name T908
Test name
Test status
Simulation time 124292107 ps
CPU time 3.41 seconds
Started Jul 10 05:49:22 PM PDT 24
Finished Jul 10 05:49:29 PM PDT 24
Peak memory 206980 kb
Host smart-58b67093-f052-4a9f-8411-616e5948a564
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256606102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1256606102
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3294474821
Short name T679
Test name
Test status
Simulation time 47812681 ps
CPU time 2.51 seconds
Started Jul 10 05:49:18 PM PDT 24
Finished Jul 10 05:49:24 PM PDT 24
Peak memory 209300 kb
Host smart-8e015602-f970-4c59-abba-3329c38e6c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294474821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3294474821
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3533225164
Short name T560
Test name
Test status
Simulation time 3461213875 ps
CPU time 26.68 seconds
Started Jul 10 05:49:11 PM PDT 24
Finished Jul 10 05:49:40 PM PDT 24
Peak memory 208628 kb
Host smart-b12e37d9-7a0e-46b6-beef-a3ec3f7d345f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533225164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3533225164
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.839900283
Short name T366
Test name
Test status
Simulation time 556472834 ps
CPU time 27.19 seconds
Started Jul 10 05:49:17 PM PDT 24
Finished Jul 10 05:49:47 PM PDT 24
Peak memory 222580 kb
Host smart-82c652ac-9785-4565-8b6e-741673754122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839900283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.839900283
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3600387254
Short name T459
Test name
Test status
Simulation time 54662380 ps
CPU time 3.43 seconds
Started Jul 10 05:49:18 PM PDT 24
Finished Jul 10 05:49:26 PM PDT 24
Peak memory 207392 kb
Host smart-d160f8b7-3192-49e2-944e-a534e1a10305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600387254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3600387254
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.157425988
Short name T895
Test name
Test status
Simulation time 556415827 ps
CPU time 2.86 seconds
Started Jul 10 05:49:29 PM PDT 24
Finished Jul 10 05:49:36 PM PDT 24
Peak memory 209816 kb
Host smart-207175ee-8509-4857-9903-ea35864a63e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157425988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.157425988
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.194774349
Short name T810
Test name
Test status
Simulation time 55233081 ps
CPU time 0.79 seconds
Started Jul 10 05:49:22 PM PDT 24
Finished Jul 10 05:49:26 PM PDT 24
Peak memory 205984 kb
Host smart-f799ce8f-83a5-49d3-8dfe-9d1e7c4cb472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194774349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.194774349
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.677224775
Short name T704
Test name
Test status
Simulation time 123251689 ps
CPU time 4.35 seconds
Started Jul 10 05:49:18 PM PDT 24
Finished Jul 10 05:49:26 PM PDT 24
Peak memory 208348 kb
Host smart-960542a0-ac39-4022-9873-fa6f5636c230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677224775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.677224775
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3839582764
Short name T730
Test name
Test status
Simulation time 111148521 ps
CPU time 2.22 seconds
Started Jul 10 05:49:18 PM PDT 24
Finished Jul 10 05:49:24 PM PDT 24
Peak memory 214360 kb
Host smart-021c14de-34f8-4e8c-8bda-1a1a87f15ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839582764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3839582764
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.169591228
Short name T224
Test name
Test status
Simulation time 580083718 ps
CPU time 5.33 seconds
Started Jul 10 05:49:20 PM PDT 24
Finished Jul 10 05:49:29 PM PDT 24
Peak memory 209852 kb
Host smart-b74fed96-c88b-47a7-93ac-e2edad5c70fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169591228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.169591228
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1178628416
Short name T361
Test name
Test status
Simulation time 272506475 ps
CPU time 3.91 seconds
Started Jul 10 05:49:17 PM PDT 24
Finished Jul 10 05:49:24 PM PDT 24
Peak memory 209580 kb
Host smart-37a38974-d358-4b52-9c48-1cbf8fa26c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178628416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1178628416
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1794684093
Short name T820
Test name
Test status
Simulation time 105685213 ps
CPU time 2.36 seconds
Started Jul 10 05:49:18 PM PDT 24
Finished Jul 10 05:49:24 PM PDT 24
Peak memory 206904 kb
Host smart-ce3de37a-0654-4ef9-98db-bab0fca0371a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794684093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1794684093
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2520581769
Short name T740
Test name
Test status
Simulation time 1992734097 ps
CPU time 33.94 seconds
Started Jul 10 05:49:29 PM PDT 24
Finished Jul 10 05:50:07 PM PDT 24
Peak memory 208656 kb
Host smart-e161dc41-a114-478f-928e-567c62a611a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520581769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2520581769
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.256351630
Short name T718
Test name
Test status
Simulation time 260869305 ps
CPU time 3.51 seconds
Started Jul 10 05:49:21 PM PDT 24
Finished Jul 10 05:49:28 PM PDT 24
Peak memory 207324 kb
Host smart-18a8d786-b3db-4872-8b99-7837f0c47483
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256351630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.256351630
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.206959914
Short name T501
Test name
Test status
Simulation time 289198953 ps
CPU time 3.5 seconds
Started Jul 10 05:49:21 PM PDT 24
Finished Jul 10 05:49:28 PM PDT 24
Peak memory 206900 kb
Host smart-54a71c59-6ec4-4d88-87a0-5705f881ed66
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206959914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.206959914
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2376924954
Short name T888
Test name
Test status
Simulation time 1029014697 ps
CPU time 8.29 seconds
Started Jul 10 05:49:17 PM PDT 24
Finished Jul 10 05:49:28 PM PDT 24
Peak memory 216176 kb
Host smart-2f300a3d-41ca-4862-9aed-be3dca3686d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376924954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2376924954
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.649170384
Short name T727
Test name
Test status
Simulation time 49980484 ps
CPU time 1.76 seconds
Started Jul 10 05:49:19 PM PDT 24
Finished Jul 10 05:49:24 PM PDT 24
Peak memory 206908 kb
Host smart-22067d15-03da-4837-a73c-cb3a0bbc0bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649170384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.649170384
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.241647115
Short name T196
Test name
Test status
Simulation time 2276590018 ps
CPU time 13.73 seconds
Started Jul 10 05:49:19 PM PDT 24
Finished Jul 10 05:49:37 PM PDT 24
Peak memory 218216 kb
Host smart-2c550286-9f34-44ec-94ed-eb36eba1f386
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241647115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.241647115
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.832453090
Short name T684
Test name
Test status
Simulation time 5601446459 ps
CPU time 64.23 seconds
Started Jul 10 05:49:22 PM PDT 24
Finished Jul 10 05:50:30 PM PDT 24
Peak memory 208756 kb
Host smart-a52f6435-65fe-4c39-9cd9-22f602f35034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832453090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.832453090
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2643935377
Short name T66
Test name
Test status
Simulation time 67121238 ps
CPU time 2.65 seconds
Started Jul 10 05:49:19 PM PDT 24
Finished Jul 10 05:49:26 PM PDT 24
Peak memory 210428 kb
Host smart-fe461f6a-cda9-4c04-8f6d-57ada6bcb0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643935377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2643935377
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.2402159395
Short name T1
Test name
Test status
Simulation time 12672334 ps
CPU time 0.75 seconds
Started Jul 10 05:49:22 PM PDT 24
Finished Jul 10 05:49:26 PM PDT 24
Peak memory 205984 kb
Host smart-33b98814-82ea-49ff-8f10-a901a30cbc04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402159395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2402159395
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1636833614
Short name T849
Test name
Test status
Simulation time 30730473 ps
CPU time 1.52 seconds
Started Jul 10 05:49:22 PM PDT 24
Finished Jul 10 05:49:27 PM PDT 24
Peak memory 216388 kb
Host smart-8dd84da0-4a45-4827-b512-f9c964aeb056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636833614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1636833614
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.517963803
Short name T772
Test name
Test status
Simulation time 109021116 ps
CPU time 3.53 seconds
Started Jul 10 05:49:29 PM PDT 24
Finished Jul 10 05:49:37 PM PDT 24
Peak memory 210208 kb
Host smart-dda808e4-05fa-442c-a455-8bedc82f3343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517963803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.517963803
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3716126824
Short name T251
Test name
Test status
Simulation time 53586788 ps
CPU time 2.33 seconds
Started Jul 10 05:49:18 PM PDT 24
Finished Jul 10 05:49:24 PM PDT 24
Peak memory 214324 kb
Host smart-e3cd2d3e-942a-4af8-8800-b4c48674e21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716126824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3716126824
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1470079332
Short name T55
Test name
Test status
Simulation time 876395997 ps
CPU time 4.82 seconds
Started Jul 10 05:49:22 PM PDT 24
Finished Jul 10 05:49:30 PM PDT 24
Peak memory 214280 kb
Host smart-0d4dfd68-77f3-4ed4-850b-0de0c4daa711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470079332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1470079332
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.545243089
Short name T488
Test name
Test status
Simulation time 115239558 ps
CPU time 3.51 seconds
Started Jul 10 05:49:17 PM PDT 24
Finished Jul 10 05:49:24 PM PDT 24
Peak memory 220492 kb
Host smart-60752576-5b27-4229-a4a2-79ca15fe2261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545243089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.545243089
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2954788157
Short name T882
Test name
Test status
Simulation time 126246264 ps
CPU time 4.48 seconds
Started Jul 10 05:49:21 PM PDT 24
Finished Jul 10 05:49:29 PM PDT 24
Peak memory 210036 kb
Host smart-13485872-c129-4b65-93cd-8be795ccf654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954788157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2954788157
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1285312616
Short name T111
Test name
Test status
Simulation time 105361724 ps
CPU time 4.62 seconds
Started Jul 10 05:49:20 PM PDT 24
Finished Jul 10 05:49:28 PM PDT 24
Peak memory 207448 kb
Host smart-e244f940-0b81-4ae5-aaaa-edc0c4a172af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285312616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1285312616
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3705820108
Short name T587
Test name
Test status
Simulation time 1334639573 ps
CPU time 12.97 seconds
Started Jul 10 05:49:29 PM PDT 24
Finished Jul 10 05:49:47 PM PDT 24
Peak memory 208284 kb
Host smart-5d8bf797-0e17-418f-a34d-8626030f7e34
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705820108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3705820108
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1255276264
Short name T480
Test name
Test status
Simulation time 137777502 ps
CPU time 2.61 seconds
Started Jul 10 05:49:21 PM PDT 24
Finished Jul 10 05:49:27 PM PDT 24
Peak memory 208688 kb
Host smart-7636557f-8c8e-42ab-82ae-7a6c0dd7066d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255276264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1255276264
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2349733832
Short name T374
Test name
Test status
Simulation time 68437582 ps
CPU time 3.07 seconds
Started Jul 10 05:49:19 PM PDT 24
Finished Jul 10 05:49:25 PM PDT 24
Peak memory 208524 kb
Host smart-26e8cb95-64df-4a81-811d-e1cb47767f43
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349733832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2349733832
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3001431451
Short name T638
Test name
Test status
Simulation time 2097213723 ps
CPU time 18.98 seconds
Started Jul 10 05:49:28 PM PDT 24
Finished Jul 10 05:49:52 PM PDT 24
Peak memory 208308 kb
Host smart-7b59b576-200a-495c-b0a9-7a9d520abc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001431451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3001431451
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2478243844
Short name T442
Test name
Test status
Simulation time 172886385 ps
CPU time 3.23 seconds
Started Jul 10 05:49:22 PM PDT 24
Finished Jul 10 05:49:29 PM PDT 24
Peak memory 208480 kb
Host smart-7139a25e-8a59-4bd5-ae85-7f3da51656eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478243844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2478243844
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.156731270
Short name T558
Test name
Test status
Simulation time 1217771904 ps
CPU time 28.09 seconds
Started Jul 10 05:49:22 PM PDT 24
Finished Jul 10 05:49:54 PM PDT 24
Peak memory 216504 kb
Host smart-89eae1a2-f7ba-4dee-a068-a6278a7be82c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156731270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.156731270
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2168281484
Short name T623
Test name
Test status
Simulation time 177195914 ps
CPU time 7.04 seconds
Started Jul 10 05:49:29 PM PDT 24
Finished Jul 10 05:49:41 PM PDT 24
Peak memory 218492 kb
Host smart-48a0dac8-3a1e-4b3a-87c4-91460a9043fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168281484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2168281484
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2143888752
Short name T520
Test name
Test status
Simulation time 219798061 ps
CPU time 1.99 seconds
Started Jul 10 05:49:29 PM PDT 24
Finished Jul 10 05:49:35 PM PDT 24
Peak memory 210368 kb
Host smart-1106cf00-83cd-4c18-9c2e-e6acd6eb3e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143888752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2143888752
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.372838889
Short name T575
Test name
Test status
Simulation time 47921674 ps
CPU time 0.86 seconds
Started Jul 10 05:49:23 PM PDT 24
Finished Jul 10 05:49:28 PM PDT 24
Peak memory 205980 kb
Host smart-d4d4d143-c97a-4647-bb5e-c8d3fe3980b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372838889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.372838889
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.808010471
Short name T683
Test name
Test status
Simulation time 1109789515 ps
CPU time 6.64 seconds
Started Jul 10 05:49:22 PM PDT 24
Finished Jul 10 05:49:33 PM PDT 24
Peak memory 209604 kb
Host smart-f2876df1-84e2-44c7-a235-4ab0a31533ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808010471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.808010471
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.795703107
Short name T715
Test name
Test status
Simulation time 31055214 ps
CPU time 2.4 seconds
Started Jul 10 05:49:25 PM PDT 24
Finished Jul 10 05:49:32 PM PDT 24
Peak memory 208048 kb
Host smart-08dcb506-3f6f-436a-ae30-da1d847acadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795703107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.795703107
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3039213211
Short name T572
Test name
Test status
Simulation time 89660973 ps
CPU time 2.9 seconds
Started Jul 10 05:49:25 PM PDT 24
Finished Jul 10 05:49:33 PM PDT 24
Peak memory 214392 kb
Host smart-05224a80-e5c6-41ea-885f-70d50be0085a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039213211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3039213211
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3937014111
Short name T724
Test name
Test status
Simulation time 129514993 ps
CPU time 4.29 seconds
Started Jul 10 05:49:22 PM PDT 24
Finished Jul 10 05:49:30 PM PDT 24
Peak memory 222436 kb
Host smart-2327db20-b74a-46dc-9873-624515cd005f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937014111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3937014111
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.880845168
Short name T63
Test name
Test status
Simulation time 998867072 ps
CPU time 5.09 seconds
Started Jul 10 05:49:23 PM PDT 24
Finished Jul 10 05:49:32 PM PDT 24
Peak memory 209740 kb
Host smart-86f96eee-1e51-4a89-8d39-debb96de9f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880845168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.880845168
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2220574525
Short name T407
Test name
Test status
Simulation time 872884062 ps
CPU time 6.5 seconds
Started Jul 10 05:49:25 PM PDT 24
Finished Jul 10 05:49:36 PM PDT 24
Peak memory 218428 kb
Host smart-b64901b0-96b6-41fa-95d5-3a0d1a81637a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220574525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2220574525
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.264235735
Short name T343
Test name
Test status
Simulation time 545855493 ps
CPU time 4.25 seconds
Started Jul 10 05:49:27 PM PDT 24
Finished Jul 10 05:49:36 PM PDT 24
Peak memory 208556 kb
Host smart-8bcfe014-9649-41a1-8219-795bd63c778c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264235735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.264235735
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.779819727
Short name T192
Test name
Test status
Simulation time 69652296 ps
CPU time 3.13 seconds
Started Jul 10 05:49:23 PM PDT 24
Finished Jul 10 05:49:30 PM PDT 24
Peak memory 208912 kb
Host smart-cbedaae0-2b76-4bd4-9dfc-e5796c7eea23
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779819727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.779819727
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1007923081
Short name T584
Test name
Test status
Simulation time 101233935 ps
CPU time 3.05 seconds
Started Jul 10 05:49:28 PM PDT 24
Finished Jul 10 05:49:35 PM PDT 24
Peak memory 207388 kb
Host smart-f137721c-aa68-4cd9-9f55-dc2744352798
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007923081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1007923081
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.4268501012
Short name T282
Test name
Test status
Simulation time 1651662128 ps
CPU time 3.68 seconds
Started Jul 10 05:49:26 PM PDT 24
Finished Jul 10 05:49:34 PM PDT 24
Peak memory 209016 kb
Host smart-6666dc17-153c-4496-b4ad-cfb38b9cad96
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268501012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.4268501012
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2401274738
Short name T260
Test name
Test status
Simulation time 179120129 ps
CPU time 4.72 seconds
Started Jul 10 05:49:25 PM PDT 24
Finished Jul 10 05:49:34 PM PDT 24
Peak memory 210012 kb
Host smart-78c05ea9-5cb4-4ae9-83d7-304bce94ea3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401274738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2401274738
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.765130536
Short name T465
Test name
Test status
Simulation time 371108796 ps
CPU time 6.02 seconds
Started Jul 10 05:49:23 PM PDT 24
Finished Jul 10 05:49:33 PM PDT 24
Peak memory 208444 kb
Host smart-56828288-2d0d-4ca0-ad72-c25b650a62e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765130536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.765130536
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3486737462
Short name T793
Test name
Test status
Simulation time 11721711949 ps
CPU time 51.5 seconds
Started Jul 10 05:49:24 PM PDT 24
Finished Jul 10 05:50:20 PM PDT 24
Peak memory 217040 kb
Host smart-ce00ca85-d47d-4645-824f-6cb8731ab9b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486737462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3486737462
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2909826943
Short name T805
Test name
Test status
Simulation time 43913565 ps
CPU time 2.19 seconds
Started Jul 10 05:49:24 PM PDT 24
Finished Jul 10 05:49:30 PM PDT 24
Peak memory 209960 kb
Host smart-08ae80d0-c2cb-41ec-99f6-fc2bac82fdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909826943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2909826943
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2880258570
Short name T619
Test name
Test status
Simulation time 33052338 ps
CPU time 0.8 seconds
Started Jul 10 05:49:29 PM PDT 24
Finished Jul 10 05:49:34 PM PDT 24
Peak memory 205984 kb
Host smart-67426e67-b4b1-40f3-b211-58ce6b1206e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880258570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2880258570
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.4171761178
Short name T426
Test name
Test status
Simulation time 49460031 ps
CPU time 3.57 seconds
Started Jul 10 05:49:24 PM PDT 24
Finished Jul 10 05:49:32 PM PDT 24
Peak memory 214444 kb
Host smart-3272e7f9-fa59-49d6-9f7b-8ff1a1b09109
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4171761178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.4171761178
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3030105339
Short name T44
Test name
Test status
Simulation time 56192311 ps
CPU time 1.6 seconds
Started Jul 10 05:49:25 PM PDT 24
Finished Jul 10 05:49:31 PM PDT 24
Peak memory 209368 kb
Host smart-ebe81c99-4869-4c5d-a980-aae8e1c1725b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030105339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3030105339
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3955190695
Short name T522
Test name
Test status
Simulation time 651946948 ps
CPU time 2.82 seconds
Started Jul 10 05:49:23 PM PDT 24
Finished Jul 10 05:49:30 PM PDT 24
Peak memory 220004 kb
Host smart-30a204d5-c932-4e63-880d-6c29e253940f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955190695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3955190695
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.928917928
Short name T738
Test name
Test status
Simulation time 256345476 ps
CPU time 7.11 seconds
Started Jul 10 05:49:24 PM PDT 24
Finished Jul 10 05:49:36 PM PDT 24
Peak memory 209200 kb
Host smart-f87f208a-9ec3-4c27-bb04-475c4e5989ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928917928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.928917928
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_random.4181413380
Short name T701
Test name
Test status
Simulation time 105441935 ps
CPU time 4.97 seconds
Started Jul 10 05:49:22 PM PDT 24
Finished Jul 10 05:49:31 PM PDT 24
Peak memory 209040 kb
Host smart-f75c7959-43af-4746-b00c-53eaa86108d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181413380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.4181413380
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1685784569
Short name T506
Test name
Test status
Simulation time 219717030 ps
CPU time 3.09 seconds
Started Jul 10 05:49:25 PM PDT 24
Finished Jul 10 05:49:33 PM PDT 24
Peak memory 208608 kb
Host smart-48288fc2-a7fc-454c-89d8-af5478ef2ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685784569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1685784569
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.115168343
Short name T220
Test name
Test status
Simulation time 610095457 ps
CPU time 8.2 seconds
Started Jul 10 05:49:24 PM PDT 24
Finished Jul 10 05:49:36 PM PDT 24
Peak memory 208228 kb
Host smart-340604ad-8523-4e31-b7a9-04fe24d05784
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115168343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.115168343
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2748179677
Short name T526
Test name
Test status
Simulation time 76265029 ps
CPU time 3.6 seconds
Started Jul 10 05:49:24 PM PDT 24
Finished Jul 10 05:49:31 PM PDT 24
Peak memory 208832 kb
Host smart-29b03f9a-1db7-43a2-835c-13c2df630455
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748179677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2748179677
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2150393080
Short name T614
Test name
Test status
Simulation time 55737655 ps
CPU time 2.23 seconds
Started Jul 10 05:49:27 PM PDT 24
Finished Jul 10 05:49:33 PM PDT 24
Peak memory 206792 kb
Host smart-c411fcef-2ba4-4083-9cc9-eb1ab5969d19
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150393080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2150393080
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2512779686
Short name T852
Test name
Test status
Simulation time 22652902 ps
CPU time 1.56 seconds
Started Jul 10 05:49:23 PM PDT 24
Finished Jul 10 05:49:29 PM PDT 24
Peak memory 208532 kb
Host smart-14ca561a-5f36-4850-b3d3-8acea23d4801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512779686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2512779686
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3719513184
Short name T6
Test name
Test status
Simulation time 162885626 ps
CPU time 2.57 seconds
Started Jul 10 05:49:25 PM PDT 24
Finished Jul 10 05:49:31 PM PDT 24
Peak memory 208840 kb
Host smart-5fe2c6d1-75fd-43e4-aaf6-f914ffc2cd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719513184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3719513184
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2484385376
Short name T383
Test name
Test status
Simulation time 161799849 ps
CPU time 5.08 seconds
Started Jul 10 05:49:22 PM PDT 24
Finished Jul 10 05:49:31 PM PDT 24
Peak memory 210056 kb
Host smart-a7b192d9-5fe1-4897-9a36-7654bd77e207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484385376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2484385376
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1431402458
Short name T140
Test name
Test status
Simulation time 49411525 ps
CPU time 1.64 seconds
Started Jul 10 05:49:30 PM PDT 24
Finished Jul 10 05:49:36 PM PDT 24
Peak memory 209528 kb
Host smart-c703afc7-5a0c-48d5-be64-1b40ae214743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431402458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1431402458
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1539491825
Short name T452
Test name
Test status
Simulation time 12704151 ps
CPU time 0.92 seconds
Started Jul 10 05:49:29 PM PDT 24
Finished Jul 10 05:49:34 PM PDT 24
Peak memory 205996 kb
Host smart-d4c0e590-783a-49d6-9754-c592fb7ec6f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539491825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1539491825
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.156982797
Short name T868
Test name
Test status
Simulation time 116867262 ps
CPU time 6.49 seconds
Started Jul 10 05:49:28 PM PDT 24
Finished Jul 10 05:49:38 PM PDT 24
Peak memory 222480 kb
Host smart-6e88d7a8-4540-459d-ac84-515c2f6eeded
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=156982797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.156982797
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.523794205
Short name T690
Test name
Test status
Simulation time 148071766 ps
CPU time 5.37 seconds
Started Jul 10 05:49:29 PM PDT 24
Finished Jul 10 05:49:39 PM PDT 24
Peak memory 222964 kb
Host smart-6113321e-cae7-4e5a-9264-9f4a55d5179e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523794205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.523794205
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.857644824
Short name T883
Test name
Test status
Simulation time 40902322 ps
CPU time 2.05 seconds
Started Jul 10 05:49:29 PM PDT 24
Finished Jul 10 05:49:35 PM PDT 24
Peak memory 209108 kb
Host smart-7497d63f-7d98-4493-8e14-f9ce1402fbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857644824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.857644824
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2445512960
Short name T795
Test name
Test status
Simulation time 56623507 ps
CPU time 1.97 seconds
Started Jul 10 05:49:28 PM PDT 24
Finished Jul 10 05:49:34 PM PDT 24
Peak memory 214340 kb
Host smart-94aafbde-201c-48d4-b874-5f528ce3b3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445512960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2445512960
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.138548451
Short name T471
Test name
Test status
Simulation time 158792147 ps
CPU time 5.72 seconds
Started Jul 10 05:49:30 PM PDT 24
Finished Jul 10 05:49:40 PM PDT 24
Peak memory 222460 kb
Host smart-456c657d-4078-4b04-abdf-3006efd6839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138548451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.138548451
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1184143323
Short name T53
Test name
Test status
Simulation time 717279228 ps
CPU time 3.7 seconds
Started Jul 10 05:49:30 PM PDT 24
Finished Jul 10 05:49:38 PM PDT 24
Peak memory 217936 kb
Host smart-65cf41d1-b5f4-41e9-824f-9cdcfc0019c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184143323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1184143323
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.289430749
Short name T288
Test name
Test status
Simulation time 147717675 ps
CPU time 5.55 seconds
Started Jul 10 05:49:28 PM PDT 24
Finished Jul 10 05:49:38 PM PDT 24
Peak memory 218400 kb
Host smart-636a2a4c-6110-4f0a-9b5a-cccd773160d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289430749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.289430749
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.4132089489
Short name T143
Test name
Test status
Simulation time 81533656 ps
CPU time 2.97 seconds
Started Jul 10 05:49:30 PM PDT 24
Finished Jul 10 05:49:37 PM PDT 24
Peak memory 208436 kb
Host smart-38f2cb4d-2c30-43e7-b8a7-359eed7a0cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132089489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.4132089489
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1096309365
Short name T595
Test name
Test status
Simulation time 5163380586 ps
CPU time 36.75 seconds
Started Jul 10 05:49:28 PM PDT 24
Finished Jul 10 05:50:09 PM PDT 24
Peak memory 209252 kb
Host smart-a4d1fd8a-e0fa-4d7c-ae5b-0c7faabc468d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096309365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1096309365
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3610582046
Short name T755
Test name
Test status
Simulation time 37571484 ps
CPU time 2.62 seconds
Started Jul 10 05:49:26 PM PDT 24
Finished Jul 10 05:49:33 PM PDT 24
Peak memory 208688 kb
Host smart-26580bbc-20fe-45a5-82be-d18a6c0a0717
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610582046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3610582046
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3985507798
Short name T717
Test name
Test status
Simulation time 52516047 ps
CPU time 2.87 seconds
Started Jul 10 05:49:29 PM PDT 24
Finished Jul 10 05:49:36 PM PDT 24
Peak memory 207188 kb
Host smart-9ca474b9-2ebd-4c28-af96-cb380b68a5e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985507798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3985507798
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2694944212
Short name T862
Test name
Test status
Simulation time 932204457 ps
CPU time 3.43 seconds
Started Jul 10 05:49:30 PM PDT 24
Finished Jul 10 05:49:38 PM PDT 24
Peak memory 214372 kb
Host smart-35a10fa0-85a3-4206-96f5-147412d5cf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694944212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2694944212
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.507969101
Short name T443
Test name
Test status
Simulation time 92221721 ps
CPU time 3.45 seconds
Started Jul 10 05:49:28 PM PDT 24
Finished Jul 10 05:49:36 PM PDT 24
Peak memory 207924 kb
Host smart-ca6ee343-6509-4389-ae64-0ca67e362cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507969101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.507969101
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2113572676
Short name T913
Test name
Test status
Simulation time 2661107161 ps
CPU time 62.93 seconds
Started Jul 10 05:49:28 PM PDT 24
Finished Jul 10 05:50:35 PM PDT 24
Peak memory 216032 kb
Host smart-fa9dc460-29ba-4f27-bcb2-97120565bb14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113572676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2113572676
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.4039313039
Short name T625
Test name
Test status
Simulation time 822116287 ps
CPU time 14.73 seconds
Started Jul 10 05:49:29 PM PDT 24
Finished Jul 10 05:49:49 PM PDT 24
Peak memory 222604 kb
Host smart-6034c058-698d-41a8-8985-ac895c9cc404
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039313039 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.4039313039
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.769622277
Short name T818
Test name
Test status
Simulation time 322741191 ps
CPU time 3.84 seconds
Started Jul 10 05:49:28 PM PDT 24
Finished Jul 10 05:49:36 PM PDT 24
Peak memory 210444 kb
Host smart-df6ba1be-5037-4fbf-827a-9eb957ea537d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769622277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.769622277
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.600993996
Short name T67
Test name
Test status
Simulation time 158073222 ps
CPU time 2.43 seconds
Started Jul 10 05:49:28 PM PDT 24
Finished Jul 10 05:49:34 PM PDT 24
Peak memory 210568 kb
Host smart-87cbf946-2b8b-4e5b-9b5f-7ee23cf7c747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600993996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.600993996
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2795951338
Short name T441
Test name
Test status
Simulation time 159548825 ps
CPU time 0.72 seconds
Started Jul 10 05:49:38 PM PDT 24
Finished Jul 10 05:49:40 PM PDT 24
Peak memory 205996 kb
Host smart-77f816ea-2964-4705-92b0-6742c6d9817e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795951338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2795951338
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2978294704
Short name T159
Test name
Test status
Simulation time 262468430 ps
CPU time 13.61 seconds
Started Jul 10 05:49:30 PM PDT 24
Finished Jul 10 05:49:48 PM PDT 24
Peak memory 214328 kb
Host smart-c99e63a9-b6bf-4f99-a6dd-3edad2a9822d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2978294704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2978294704
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3408091237
Short name T323
Test name
Test status
Simulation time 138525487 ps
CPU time 3.63 seconds
Started Jul 10 05:49:36 PM PDT 24
Finished Jul 10 05:49:42 PM PDT 24
Peak memory 218364 kb
Host smart-d462c2d1-7d4d-465e-822c-aa964e83a3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408091237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3408091237
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3278692904
Short name T517
Test name
Test status
Simulation time 184269495 ps
CPU time 3.13 seconds
Started Jul 10 05:49:27 PM PDT 24
Finished Jul 10 05:49:34 PM PDT 24
Peak memory 209832 kb
Host smart-778d1b40-6ce2-492a-927a-5753a3531205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278692904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3278692904
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1483169696
Short name T388
Test name
Test status
Simulation time 190601847 ps
CPU time 5.21 seconds
Started Jul 10 05:49:28 PM PDT 24
Finished Jul 10 05:49:38 PM PDT 24
Peak memory 220328 kb
Host smart-2a48a3c2-2f64-413b-b1dc-a92a411db80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483169696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1483169696
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2825239946
Short name T413
Test name
Test status
Simulation time 62477256 ps
CPU time 1.48 seconds
Started Jul 10 05:49:27 PM PDT 24
Finished Jul 10 05:49:33 PM PDT 24
Peak memory 206156 kb
Host smart-fccbe5d1-d4e9-465e-a438-bf7174d9e3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825239946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2825239946
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2158774527
Short name T257
Test name
Test status
Simulation time 403199411 ps
CPU time 4.32 seconds
Started Jul 10 05:49:26 PM PDT 24
Finished Jul 10 05:49:35 PM PDT 24
Peak memory 218456 kb
Host smart-7e0786cf-1332-45f8-8c7f-bea2479351ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158774527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2158774527
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3681980097
Short name T807
Test name
Test status
Simulation time 203953688 ps
CPU time 5.84 seconds
Started Jul 10 05:49:27 PM PDT 24
Finished Jul 10 05:49:37 PM PDT 24
Peak memory 206848 kb
Host smart-84577bfe-02ee-4b95-89dc-d700976fb3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681980097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3681980097
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2629660570
Short name T410
Test name
Test status
Simulation time 295928376 ps
CPU time 3.22 seconds
Started Jul 10 05:49:27 PM PDT 24
Finished Jul 10 05:49:34 PM PDT 24
Peak memory 206940 kb
Host smart-3dfdbd58-5ea5-432b-b4d0-5518a9e27551
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629660570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2629660570
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1866706307
Short name T375
Test name
Test status
Simulation time 31302851 ps
CPU time 2.35 seconds
Started Jul 10 05:49:29 PM PDT 24
Finished Jul 10 05:49:36 PM PDT 24
Peak memory 207496 kb
Host smart-ee3d096a-5f1d-49b6-a80c-484eb039087b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866706307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1866706307
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2640826963
Short name T376
Test name
Test status
Simulation time 212203227 ps
CPU time 7.5 seconds
Started Jul 10 05:49:31 PM PDT 24
Finished Jul 10 05:49:42 PM PDT 24
Peak memory 207056 kb
Host smart-5a79c67b-ee89-4313-a2c3-caaa5267d9e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640826963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2640826963
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1679068571
Short name T791
Test name
Test status
Simulation time 83536164 ps
CPU time 3.91 seconds
Started Jul 10 05:49:32 PM PDT 24
Finished Jul 10 05:49:39 PM PDT 24
Peak memory 209320 kb
Host smart-f09b5b5f-2540-48f4-a0dc-3752900d284b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679068571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1679068571
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.134649672
Short name T477
Test name
Test status
Simulation time 194826454 ps
CPU time 3.84 seconds
Started Jul 10 05:49:28 PM PDT 24
Finished Jul 10 05:49:36 PM PDT 24
Peak memory 208848 kb
Host smart-a85f4a36-1b8e-494a-a42c-99aeb137d41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134649672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.134649672
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.586019138
Short name T767
Test name
Test status
Simulation time 8429683630 ps
CPU time 60.51 seconds
Started Jul 10 05:49:30 PM PDT 24
Finished Jul 10 05:50:35 PM PDT 24
Peak memory 209684 kb
Host smart-b6fda980-8f24-4907-85ad-9b508509e6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586019138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.586019138
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3686679938
Short name T725
Test name
Test status
Simulation time 92840189 ps
CPU time 2.61 seconds
Started Jul 10 05:49:37 PM PDT 24
Finished Jul 10 05:49:41 PM PDT 24
Peak memory 210264 kb
Host smart-adb1a273-b151-4ad0-8bbc-74775acfe967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686679938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3686679938
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3518508491
Short name T577
Test name
Test status
Simulation time 13909840 ps
CPU time 0.81 seconds
Started Jul 10 05:49:35 PM PDT 24
Finished Jul 10 05:49:37 PM PDT 24
Peak memory 206000 kb
Host smart-f7b0e504-5b2b-4add-a479-ce944e855f8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518508491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3518508491
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1597333936
Short name T771
Test name
Test status
Simulation time 160165382 ps
CPU time 2.24 seconds
Started Jul 10 05:49:36 PM PDT 24
Finished Jul 10 05:49:40 PM PDT 24
Peak memory 209364 kb
Host smart-f2928e91-c47d-4611-8fc9-4dd09729ef68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597333936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1597333936
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1050824784
Short name T881
Test name
Test status
Simulation time 90380467 ps
CPU time 3.29 seconds
Started Jul 10 05:49:36 PM PDT 24
Finished Jul 10 05:49:41 PM PDT 24
Peak memory 207324 kb
Host smart-9d6f7926-8f4f-404a-b7d2-2c380ba6ae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050824784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1050824784
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.4011537205
Short name T256
Test name
Test status
Simulation time 448120994 ps
CPU time 2.9 seconds
Started Jul 10 05:49:37 PM PDT 24
Finished Jul 10 05:49:42 PM PDT 24
Peak memory 214392 kb
Host smart-3872a1c1-fab4-41fd-bf7a-a504d41c98f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011537205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.4011537205
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3033384340
Short name T812
Test name
Test status
Simulation time 58242256 ps
CPU time 3.5 seconds
Started Jul 10 05:49:36 PM PDT 24
Finished Jul 10 05:49:42 PM PDT 24
Peak memory 208172 kb
Host smart-f7125e02-92e6-40cd-9099-f2d2aa491c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033384340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3033384340
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2230616378
Short name T620
Test name
Test status
Simulation time 4473259616 ps
CPU time 58.67 seconds
Started Jul 10 05:49:36 PM PDT 24
Finished Jul 10 05:50:37 PM PDT 24
Peak memory 209772 kb
Host smart-dd6a65a5-a356-4829-8413-965d65afa210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230616378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2230616378
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3748948573
Short name T841
Test name
Test status
Simulation time 31002493 ps
CPU time 2.36 seconds
Started Jul 10 05:49:39 PM PDT 24
Finished Jul 10 05:49:43 PM PDT 24
Peak memory 209096 kb
Host smart-15380262-f3c9-4288-8e49-86c87dc8a3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748948573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3748948573
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1804688567
Short name T414
Test name
Test status
Simulation time 162466251 ps
CPU time 4.28 seconds
Started Jul 10 05:49:37 PM PDT 24
Finished Jul 10 05:49:43 PM PDT 24
Peak memory 209240 kb
Host smart-14ffd2d7-75d9-4834-ba5a-2f8ca57c2896
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804688567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1804688567
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3516159881
Short name T602
Test name
Test status
Simulation time 674953109 ps
CPU time 2.71 seconds
Started Jul 10 05:49:37 PM PDT 24
Finished Jul 10 05:49:42 PM PDT 24
Peak memory 206964 kb
Host smart-13b304ed-5f10-40e7-8678-bc0ed36cdc10
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516159881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3516159881
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.49125859
Short name T624
Test name
Test status
Simulation time 1100871336 ps
CPU time 17.46 seconds
Started Jul 10 05:49:36 PM PDT 24
Finished Jul 10 05:49:55 PM PDT 24
Peak memory 208156 kb
Host smart-39de0f74-44f5-47be-99d4-6ec3489b3d8e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49125859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.49125859
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1687223229
Short name T663
Test name
Test status
Simulation time 284257289 ps
CPU time 2.36 seconds
Started Jul 10 05:49:33 PM PDT 24
Finished Jul 10 05:49:38 PM PDT 24
Peak memory 217008 kb
Host smart-29512c85-7ca7-4e7d-8832-16d0efd79c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687223229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1687223229
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.361352589
Short name T902
Test name
Test status
Simulation time 84137851 ps
CPU time 2.88 seconds
Started Jul 10 05:49:35 PM PDT 24
Finished Jul 10 05:49:40 PM PDT 24
Peak memory 208464 kb
Host smart-84c4f27f-7b5c-4548-bc32-acdb18893e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361352589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.361352589
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3086590746
Short name T434
Test name
Test status
Simulation time 73261739 ps
CPU time 4.02 seconds
Started Jul 10 05:49:38 PM PDT 24
Finished Jul 10 05:49:43 PM PDT 24
Peak memory 207460 kb
Host smart-5c075445-a370-4398-92a1-3e65d3a3c3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086590746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3086590746
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1362113713
Short name T530
Test name
Test status
Simulation time 1521429916 ps
CPU time 10.41 seconds
Started Jul 10 05:49:36 PM PDT 24
Finished Jul 10 05:49:49 PM PDT 24
Peak memory 210616 kb
Host smart-dc5104f9-e0e6-4385-88ed-e14e552ee1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362113713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1362113713
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3393804238
Short name T633
Test name
Test status
Simulation time 44541457 ps
CPU time 0.76 seconds
Started Jul 10 05:49:41 PM PDT 24
Finished Jul 10 05:49:43 PM PDT 24
Peak memory 206012 kb
Host smart-66e4f77a-7d29-4b7d-94c4-2c22f652874a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393804238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3393804238
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.218724221
Short name T417
Test name
Test status
Simulation time 241467090 ps
CPU time 2.87 seconds
Started Jul 10 05:49:38 PM PDT 24
Finished Jul 10 05:49:42 PM PDT 24
Peak memory 215360 kb
Host smart-6cfb0716-77af-4e31-a348-99c5781f2def
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=218724221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.218724221
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3272946042
Short name T659
Test name
Test status
Simulation time 4035937503 ps
CPU time 31.91 seconds
Started Jul 10 05:49:41 PM PDT 24
Finished Jul 10 05:50:14 PM PDT 24
Peak memory 209784 kb
Host smart-8fb983f7-4e65-44b2-a1a4-3d4321849f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272946042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3272946042
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_random.1463564119
Short name T349
Test name
Test status
Simulation time 399409427 ps
CPU time 11.14 seconds
Started Jul 10 05:49:42 PM PDT 24
Finished Jul 10 05:49:54 PM PDT 24
Peak memory 208588 kb
Host smart-3668f37a-7c1c-4f8e-86b0-86b76ba45836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463564119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1463564119
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1052957272
Short name T744
Test name
Test status
Simulation time 112145263 ps
CPU time 3.15 seconds
Started Jul 10 05:49:42 PM PDT 24
Finished Jul 10 05:49:46 PM PDT 24
Peak memory 208340 kb
Host smart-dbec0ee2-724c-44bc-9be3-906a4383c669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052957272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1052957272
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.52790256
Short name T636
Test name
Test status
Simulation time 387165867 ps
CPU time 2.34 seconds
Started Jul 10 05:49:40 PM PDT 24
Finished Jul 10 05:49:44 PM PDT 24
Peak memory 206908 kb
Host smart-707a561c-df97-409d-9983-051abaa16d81
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52790256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.52790256
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2349802036
Short name T697
Test name
Test status
Simulation time 585750240 ps
CPU time 4.7 seconds
Started Jul 10 05:49:42 PM PDT 24
Finished Jul 10 05:49:48 PM PDT 24
Peak memory 207944 kb
Host smart-9d01f297-bb43-409a-9152-7e463c7e8b71
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349802036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2349802036
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3636016909
Short name T408
Test name
Test status
Simulation time 44338300 ps
CPU time 2.61 seconds
Started Jul 10 05:49:39 PM PDT 24
Finished Jul 10 05:49:43 PM PDT 24
Peak memory 206976 kb
Host smart-e1a40abf-c6ab-40ae-a630-d8cc06679e06
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636016909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3636016909
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.213850038
Short name T445
Test name
Test status
Simulation time 550204518 ps
CPU time 11.09 seconds
Started Jul 10 05:49:40 PM PDT 24
Finished Jul 10 05:49:53 PM PDT 24
Peak memory 209320 kb
Host smart-736adb83-f1f6-4ddf-a661-a41730055216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213850038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.213850038
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1618995743
Short name T803
Test name
Test status
Simulation time 69586020 ps
CPU time 1.7 seconds
Started Jul 10 05:49:48 PM PDT 24
Finished Jul 10 05:49:51 PM PDT 24
Peak memory 206704 kb
Host smart-c57e9549-ca47-4ebd-abb9-fd90a28c537a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618995743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1618995743
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3759984900
Short name T200
Test name
Test status
Simulation time 3472171140 ps
CPU time 31.71 seconds
Started Jul 10 05:49:41 PM PDT 24
Finished Jul 10 05:50:14 PM PDT 24
Peak memory 216760 kb
Host smart-cb2a218c-2625-469f-a379-5bbb97fc6899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759984900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3759984900
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.443505920
Short name T157
Test name
Test status
Simulation time 725437899 ps
CPU time 6.34 seconds
Started Jul 10 05:49:40 PM PDT 24
Finished Jul 10 05:49:48 PM PDT 24
Peak memory 208656 kb
Host smart-a5fe91e5-4cbf-4449-8b1d-646eaec820e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443505920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.443505920
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.838032666
Short name T616
Test name
Test status
Simulation time 313169533 ps
CPU time 4.78 seconds
Started Jul 10 05:49:40 PM PDT 24
Finished Jul 10 05:49:46 PM PDT 24
Peak memory 210728 kb
Host smart-6b283480-4e61-45be-92f7-1ee96c854b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838032666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.838032666
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3703324800
Short name T562
Test name
Test status
Simulation time 104251348 ps
CPU time 0.86 seconds
Started Jul 10 05:49:54 PM PDT 24
Finished Jul 10 05:49:56 PM PDT 24
Peak memory 205980 kb
Host smart-bc50edbe-0d0a-4e59-bc43-aefae234504d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703324800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3703324800
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2369907195
Short name T421
Test name
Test status
Simulation time 1930739617 ps
CPU time 103.04 seconds
Started Jul 10 05:49:42 PM PDT 24
Finished Jul 10 05:51:27 PM PDT 24
Peak memory 222476 kb
Host smart-e52292a6-d018-4d27-a5be-eb55559762c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369907195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2369907195
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3273749899
Short name T233
Test name
Test status
Simulation time 93086378 ps
CPU time 2.89 seconds
Started Jul 10 05:49:45 PM PDT 24
Finished Jul 10 05:49:49 PM PDT 24
Peak memory 218096 kb
Host smart-0ec8715c-5d88-45c8-bd65-78b58c7ef640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273749899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3273749899
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1447775505
Short name T268
Test name
Test status
Simulation time 214310500 ps
CPU time 2.99 seconds
Started Jul 10 05:49:42 PM PDT 24
Finished Jul 10 05:49:46 PM PDT 24
Peak memory 209448 kb
Host smart-fc198ddc-85df-4baf-a882-0a8cf70a9aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447775505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1447775505
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.206533561
Short name T797
Test name
Test status
Simulation time 130245365 ps
CPU time 4.99 seconds
Started Jul 10 05:49:54 PM PDT 24
Finished Jul 10 05:50:00 PM PDT 24
Peak memory 209668 kb
Host smart-ec83f52a-0553-4cc7-80ca-f38c4a9d54a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206533561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.206533561
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3739802553
Short name T722
Test name
Test status
Simulation time 141456892 ps
CPU time 2.92 seconds
Started Jul 10 05:49:46 PM PDT 24
Finished Jul 10 05:49:50 PM PDT 24
Peak memory 221256 kb
Host smart-529caee3-21c7-486f-9e75-5cae7b0c04a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739802553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3739802553
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3997995115
Short name T475
Test name
Test status
Simulation time 217864137 ps
CPU time 3.16 seconds
Started Jul 10 05:49:45 PM PDT 24
Finished Jul 10 05:49:49 PM PDT 24
Peak memory 209640 kb
Host smart-8f0e8102-b501-4895-b5fb-f5cfed611acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997995115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3997995115
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_sideload.969723333
Short name T567
Test name
Test status
Simulation time 69082421 ps
CPU time 3 seconds
Started Jul 10 05:49:44 PM PDT 24
Finished Jul 10 05:49:47 PM PDT 24
Peak memory 208652 kb
Host smart-34c1e4fb-7130-450c-91e2-af13c5e5eb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969723333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.969723333
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3604438959
Short name T877
Test name
Test status
Simulation time 1615961011 ps
CPU time 3.37 seconds
Started Jul 10 05:49:41 PM PDT 24
Finished Jul 10 05:49:46 PM PDT 24
Peak memory 208580 kb
Host smart-24ebc38a-452f-4da0-94d0-0144f08111c9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604438959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3604438959
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.4063482077
Short name T674
Test name
Test status
Simulation time 2242514581 ps
CPU time 29.41 seconds
Started Jul 10 05:49:43 PM PDT 24
Finished Jul 10 05:50:13 PM PDT 24
Peak memory 208880 kb
Host smart-dcbfde49-5217-4f89-9477-c67735cba5ef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063482077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.4063482077
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1471963386
Short name T528
Test name
Test status
Simulation time 90054616 ps
CPU time 2.96 seconds
Started Jul 10 05:49:40 PM PDT 24
Finished Jul 10 05:49:44 PM PDT 24
Peak memory 206984 kb
Host smart-6a28f37e-3ed9-423c-b7b4-a8330c595166
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471963386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1471963386
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1024110820
Short name T382
Test name
Test status
Simulation time 111518595 ps
CPU time 2.29 seconds
Started Jul 10 05:49:54 PM PDT 24
Finished Jul 10 05:49:57 PM PDT 24
Peak memory 206872 kb
Host smart-b9323599-76eb-4207-a732-0a29129ce10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024110820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1024110820
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3498054025
Short name T665
Test name
Test status
Simulation time 49052689 ps
CPU time 2.52 seconds
Started Jul 10 05:49:41 PM PDT 24
Finished Jul 10 05:49:45 PM PDT 24
Peak memory 206748 kb
Host smart-2ac0952a-9905-43a7-9b60-8a125cb0208b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498054025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3498054025
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3533941075
Short name T218
Test name
Test status
Simulation time 338635831 ps
CPU time 4.3 seconds
Started Jul 10 05:49:46 PM PDT 24
Finished Jul 10 05:49:52 PM PDT 24
Peak memory 218428 kb
Host smart-3ba1b1d8-ff0c-4675-963d-1d0f7fea3292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533941075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3533941075
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1401075121
Short name T561
Test name
Test status
Simulation time 27210172 ps
CPU time 0.94 seconds
Started Jul 10 05:48:27 PM PDT 24
Finished Jul 10 05:48:30 PM PDT 24
Peak memory 205912 kb
Host smart-1b81d401-1fb4-467c-a2e1-39a9f50bc63b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401075121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1401075121
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3078984025
Short name T891
Test name
Test status
Simulation time 470716277 ps
CPU time 13.56 seconds
Started Jul 10 05:48:19 PM PDT 24
Finished Jul 10 05:48:34 PM PDT 24
Peak memory 215596 kb
Host smart-e0042f31-f987-4420-a6be-8342a3de255c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3078984025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3078984025
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1039063624
Short name T21
Test name
Test status
Simulation time 123748424 ps
CPU time 3.96 seconds
Started Jul 10 05:48:21 PM PDT 24
Finished Jul 10 05:48:27 PM PDT 24
Peak memory 222872 kb
Host smart-5436e467-e4d5-48c8-9a80-e5bf60f1a9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039063624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1039063624
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.824568608
Short name T673
Test name
Test status
Simulation time 138299775 ps
CPU time 1.96 seconds
Started Jul 10 05:48:20 PM PDT 24
Finished Jul 10 05:48:24 PM PDT 24
Peak memory 208192 kb
Host smart-cb7af072-c3cd-4bff-9356-d3b006bad325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824568608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.824568608
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.4179023666
Short name T829
Test name
Test status
Simulation time 116165132 ps
CPU time 4.83 seconds
Started Jul 10 05:48:28 PM PDT 24
Finished Jul 10 05:48:35 PM PDT 24
Peak memory 214328 kb
Host smart-4665c4ac-eef0-45c2-88ae-fb1c6c3008fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179023666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.4179023666
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3928810614
Short name T387
Test name
Test status
Simulation time 416873911 ps
CPU time 8.67 seconds
Started Jul 10 05:48:27 PM PDT 24
Finished Jul 10 05:48:37 PM PDT 24
Peak memory 208296 kb
Host smart-6328a64e-e354-4017-80ff-a080ab8df6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928810614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3928810614
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1485748495
Short name T259
Test name
Test status
Simulation time 12777237208 ps
CPU time 45.65 seconds
Started Jul 10 05:48:14 PM PDT 24
Finished Jul 10 05:49:02 PM PDT 24
Peak memory 208896 kb
Host smart-681f31f7-c1a8-488e-afad-8d5b0b1af230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485748495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1485748495
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1656482504
Short name T712
Test name
Test status
Simulation time 346650218 ps
CPU time 3.45 seconds
Started Jul 10 05:48:14 PM PDT 24
Finished Jul 10 05:48:19 PM PDT 24
Peak memory 208172 kb
Host smart-aa78dc01-65af-4c75-b731-908cae2f4ce0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656482504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1656482504
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2245595887
Short name T490
Test name
Test status
Simulation time 302533965 ps
CPU time 6.13 seconds
Started Jul 10 05:48:14 PM PDT 24
Finished Jul 10 05:48:22 PM PDT 24
Peak memory 208840 kb
Host smart-550c82fe-9677-4cd5-8432-6aaa2690a0df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245595887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2245595887
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1111072036
Short name T571
Test name
Test status
Simulation time 341840163 ps
CPU time 6.79 seconds
Started Jul 10 05:48:15 PM PDT 24
Finished Jul 10 05:48:24 PM PDT 24
Peak memory 208760 kb
Host smart-57e3e9ab-d84a-410d-9d47-8ef4f84429ec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111072036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1111072036
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3188334383
Short name T317
Test name
Test status
Simulation time 268861079 ps
CPU time 3.14 seconds
Started Jul 10 05:48:19 PM PDT 24
Finished Jul 10 05:48:24 PM PDT 24
Peak memory 209748 kb
Host smart-61704779-488b-4f87-accc-bb3cd6e20177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188334383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3188334383
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3903309706
Short name T752
Test name
Test status
Simulation time 640785594 ps
CPU time 11.23 seconds
Started Jul 10 05:48:15 PM PDT 24
Finished Jul 10 05:48:28 PM PDT 24
Peak memory 206828 kb
Host smart-70a868d4-607f-4714-869f-b4c70c502c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903309706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3903309706
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2024817221
Short name T81
Test name
Test status
Simulation time 3440154456 ps
CPU time 11.5 seconds
Started Jul 10 05:48:22 PM PDT 24
Finished Jul 10 05:48:35 PM PDT 24
Peak memory 214420 kb
Host smart-f580329a-a1a8-4d04-9436-d3f4d4a81123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024817221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2024817221
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.4187493540
Short name T365
Test name
Test status
Simulation time 5219100240 ps
CPU time 9.66 seconds
Started Jul 10 05:48:21 PM PDT 24
Finished Jul 10 05:48:33 PM PDT 24
Peak memory 206924 kb
Host smart-031cce3d-acc6-4dea-91bc-741cd2e38162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187493540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.4187493540
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.252972940
Short name T205
Test name
Test status
Simulation time 190996837 ps
CPU time 2.66 seconds
Started Jul 10 05:48:27 PM PDT 24
Finished Jul 10 05:48:31 PM PDT 24
Peak memory 210208 kb
Host smart-d735b1cc-9b5f-4039-a4d0-c7d596e918b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252972940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.252972940
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1460354024
Short name T109
Test name
Test status
Simulation time 95074187 ps
CPU time 0.92 seconds
Started Jul 10 05:49:56 PM PDT 24
Finished Jul 10 05:49:58 PM PDT 24
Peak memory 205980 kb
Host smart-a0540a98-7d37-4124-9494-adbda15f8c6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460354024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1460354024
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.445289995
Short name T144
Test name
Test status
Simulation time 210522489 ps
CPU time 4.22 seconds
Started Jul 10 05:49:46 PM PDT 24
Finished Jul 10 05:49:51 PM PDT 24
Peak memory 214228 kb
Host smart-e3d4e614-7514-497c-ac74-da7ea755a02d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=445289995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.445289995
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3964803614
Short name T884
Test name
Test status
Simulation time 185610707 ps
CPU time 5.26 seconds
Started Jul 10 05:49:58 PM PDT 24
Finished Jul 10 05:50:04 PM PDT 24
Peak memory 214320 kb
Host smart-9deadc0f-78a4-417c-a014-51d5f55b1ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964803614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3964803614
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3475102770
Short name T864
Test name
Test status
Simulation time 1172927195 ps
CPU time 15.09 seconds
Started Jul 10 05:49:44 PM PDT 24
Finished Jul 10 05:50:00 PM PDT 24
Peak memory 214328 kb
Host smart-fa250cbd-7f31-4af9-b23e-0fc691879ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475102770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3475102770
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.4259995979
Short name T597
Test name
Test status
Simulation time 36306595 ps
CPU time 2.47 seconds
Started Jul 10 05:49:46 PM PDT 24
Finished Jul 10 05:49:50 PM PDT 24
Peak memory 214540 kb
Host smart-9520fd75-c6de-4442-943a-1750f404b41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259995979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.4259995979
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2440708799
Short name T337
Test name
Test status
Simulation time 51995010 ps
CPU time 2.95 seconds
Started Jul 10 05:49:45 PM PDT 24
Finished Jul 10 05:49:48 PM PDT 24
Peak memory 220496 kb
Host smart-df90b73d-f51c-4452-a10a-147770f5e4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440708799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2440708799
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1258441569
Short name T468
Test name
Test status
Simulation time 112348427 ps
CPU time 4.59 seconds
Started Jul 10 05:49:47 PM PDT 24
Finished Jul 10 05:49:53 PM PDT 24
Peak memory 208884 kb
Host smart-21d70b6a-5f26-46ac-bd7f-2162dfe02816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258441569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1258441569
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.111844873
Short name T332
Test name
Test status
Simulation time 298563277 ps
CPU time 9.32 seconds
Started Jul 10 05:49:44 PM PDT 24
Finished Jul 10 05:49:54 PM PDT 24
Peak memory 209132 kb
Host smart-9cf6d1f3-c5ed-43c1-9e53-b1a177601872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111844873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.111844873
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3855937058
Short name T532
Test name
Test status
Simulation time 137048769 ps
CPU time 4.18 seconds
Started Jul 10 05:49:44 PM PDT 24
Finished Jul 10 05:49:49 PM PDT 24
Peak memory 206732 kb
Host smart-7b534663-c6cb-4ad9-a5bc-56f1cdc8fbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855937058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3855937058
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.4114896036
Short name T645
Test name
Test status
Simulation time 64852727 ps
CPU time 3.36 seconds
Started Jul 10 05:49:45 PM PDT 24
Finished Jul 10 05:49:50 PM PDT 24
Peak memory 208228 kb
Host smart-7ce59cec-04ad-4894-abbc-629789b6d8b8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114896036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.4114896036
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3100775893
Short name T461
Test name
Test status
Simulation time 3917119981 ps
CPU time 40.05 seconds
Started Jul 10 05:49:47 PM PDT 24
Finished Jul 10 05:50:28 PM PDT 24
Peak memory 208148 kb
Host smart-f0a3dce6-2815-4be3-ac45-51d07f5be2c3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100775893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3100775893
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1704276309
Short name T836
Test name
Test status
Simulation time 73575619 ps
CPU time 2.3 seconds
Started Jul 10 05:49:46 PM PDT 24
Finished Jul 10 05:49:49 PM PDT 24
Peak memory 206972 kb
Host smart-7348cc3f-8386-4f60-aeb0-6dfcf611d81b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704276309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1704276309
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.4155309702
Short name T423
Test name
Test status
Simulation time 1494264154 ps
CPU time 6.18 seconds
Started Jul 10 05:49:54 PM PDT 24
Finished Jul 10 05:50:01 PM PDT 24
Peak memory 208572 kb
Host smart-24750644-dff4-4d66-a99a-5fd1798e0d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155309702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.4155309702
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3909741556
Short name T135
Test name
Test status
Simulation time 208021072 ps
CPU time 2.57 seconds
Started Jul 10 05:49:46 PM PDT 24
Finished Jul 10 05:49:49 PM PDT 24
Peak memory 206868 kb
Host smart-3f4856b7-149e-4be6-a8db-12626145c987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909741556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3909741556
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2800722625
Short name T29
Test name
Test status
Simulation time 759759955 ps
CPU time 7.92 seconds
Started Jul 10 05:49:47 PM PDT 24
Finished Jul 10 05:49:56 PM PDT 24
Peak memory 214420 kb
Host smart-43d92549-b2d8-4128-84b7-5dd9494e0553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800722625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2800722625
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2426074512
Short name T69
Test name
Test status
Simulation time 1524350520 ps
CPU time 7.64 seconds
Started Jul 10 05:49:55 PM PDT 24
Finished Jul 10 05:50:04 PM PDT 24
Peak memory 210784 kb
Host smart-bdde35bb-7b5e-4bed-9be8-94604bda863f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426074512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2426074512
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2432481274
Short name T628
Test name
Test status
Simulation time 12781837 ps
CPU time 0.85 seconds
Started Jul 10 05:50:01 PM PDT 24
Finished Jul 10 05:50:03 PM PDT 24
Peak memory 205996 kb
Host smart-9d805e0e-e1d5-489f-839a-43fcfc1ad395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432481274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2432481274
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3544470936
Short name T899
Test name
Test status
Simulation time 521044970 ps
CPU time 4.2 seconds
Started Jul 10 05:49:55 PM PDT 24
Finished Jul 10 05:50:00 PM PDT 24
Peak memory 214696 kb
Host smart-2785facb-ead4-4bab-b12a-28422d7d90ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544470936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3544470936
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2237264862
Short name T194
Test name
Test status
Simulation time 107068022 ps
CPU time 2.62 seconds
Started Jul 10 05:50:01 PM PDT 24
Finished Jul 10 05:50:05 PM PDT 24
Peak memory 209028 kb
Host smart-1812dbe0-a749-42f2-b761-95adf61395dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237264862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2237264862
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2751469622
Short name T534
Test name
Test status
Simulation time 316200348 ps
CPU time 3.61 seconds
Started Jul 10 05:49:58 PM PDT 24
Finished Jul 10 05:50:02 PM PDT 24
Peak memory 209708 kb
Host smart-e513c8f2-0302-4ee0-aa93-680598cbccd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751469622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2751469622
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2034514231
Short name T356
Test name
Test status
Simulation time 116999731 ps
CPU time 5.31 seconds
Started Jul 10 05:49:55 PM PDT 24
Finished Jul 10 05:50:02 PM PDT 24
Peak memory 207796 kb
Host smart-c19dbedd-7c3e-46d2-82c5-c2a458fa8786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034514231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2034514231
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2359831127
Short name T279
Test name
Test status
Simulation time 339011742 ps
CPU time 3.8 seconds
Started Jul 10 05:49:54 PM PDT 24
Finished Jul 10 05:49:59 PM PDT 24
Peak memory 208604 kb
Host smart-f51bdc77-4e1b-458d-b5a0-3686f40bd1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359831127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2359831127
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2350501969
Short name T750
Test name
Test status
Simulation time 135803928 ps
CPU time 2.73 seconds
Started Jul 10 05:49:54 PM PDT 24
Finished Jul 10 05:49:58 PM PDT 24
Peak memory 206996 kb
Host smart-819dbe7c-989a-4e5f-9bd3-7f9fdb55f8be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350501969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2350501969
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2062672033
Short name T886
Test name
Test status
Simulation time 220918277 ps
CPU time 3.81 seconds
Started Jul 10 05:50:00 PM PDT 24
Finished Jul 10 05:50:05 PM PDT 24
Peak memory 208036 kb
Host smart-eae25cc1-eab0-4557-821d-a35b661a6ba0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062672033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2062672033
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.4266937592
Short name T707
Test name
Test status
Simulation time 206941455 ps
CPU time 3.03 seconds
Started Jul 10 05:49:55 PM PDT 24
Finished Jul 10 05:50:00 PM PDT 24
Peak memory 206876 kb
Host smart-83713cff-6cab-4a2d-9644-bcd2c26bd144
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266937592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.4266937592
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.410754993
Short name T211
Test name
Test status
Simulation time 226666912 ps
CPU time 5.32 seconds
Started Jul 10 05:49:56 PM PDT 24
Finished Jul 10 05:50:03 PM PDT 24
Peak memory 214328 kb
Host smart-bcc86869-32d9-42cf-afa7-58f0eb43553c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410754993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.410754993
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3421534252
Short name T778
Test name
Test status
Simulation time 711984855 ps
CPU time 7.27 seconds
Started Jul 10 05:49:55 PM PDT 24
Finished Jul 10 05:50:04 PM PDT 24
Peak memory 208420 kb
Host smart-9915c661-c5d8-48eb-a1da-975b2381cf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421534252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3421534252
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.776298896
Short name T631
Test name
Test status
Simulation time 1217463182 ps
CPU time 8.47 seconds
Started Jul 10 05:49:57 PM PDT 24
Finished Jul 10 05:50:06 PM PDT 24
Peak memory 219984 kb
Host smart-095f1b85-d429-4924-9740-241dc7efcd0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776298896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.776298896
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3374447347
Short name T825
Test name
Test status
Simulation time 680189711 ps
CPU time 15.32 seconds
Started Jul 10 05:49:55 PM PDT 24
Finished Jul 10 05:50:11 PM PDT 24
Peak memory 220480 kb
Host smart-49c79e59-30e7-4386-ac65-ae55fd1ab98e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374447347 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3374447347
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3285848956
Short name T195
Test name
Test status
Simulation time 155347609 ps
CPU time 2.84 seconds
Started Jul 10 05:49:53 PM PDT 24
Finished Jul 10 05:49:57 PM PDT 24
Peak memory 208208 kb
Host smart-576c5eec-2993-4bff-b9e8-00dd988260e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285848956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3285848956
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.605479284
Short name T141
Test name
Test status
Simulation time 133418626 ps
CPU time 1.92 seconds
Started Jul 10 05:49:55 PM PDT 24
Finished Jul 10 05:49:58 PM PDT 24
Peak memory 210196 kb
Host smart-70193dd2-19af-4e70-86dd-39e4f68069e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605479284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.605479284
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.43607226
Short name T731
Test name
Test status
Simulation time 19828227 ps
CPU time 0.91 seconds
Started Jul 10 05:50:06 PM PDT 24
Finished Jul 10 05:50:10 PM PDT 24
Peak memory 205988 kb
Host smart-467e95c4-4093-4b41-b9fc-b2785a1f48aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43607226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.43607226
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3881894107
Short name T846
Test name
Test status
Simulation time 175418589 ps
CPU time 2.81 seconds
Started Jul 10 05:49:55 PM PDT 24
Finished Jul 10 05:49:59 PM PDT 24
Peak memory 214896 kb
Host smart-3c29489b-7b4b-48b5-a700-07cc28b29c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3881894107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3881894107
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.746203358
Short name T31
Test name
Test status
Simulation time 300138984 ps
CPU time 6.39 seconds
Started Jul 10 05:50:02 PM PDT 24
Finished Jul 10 05:50:10 PM PDT 24
Peak memory 221592 kb
Host smart-5ee6e195-c082-47e5-8d98-a2da948e06b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746203358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.746203358
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.4122746469
Short name T393
Test name
Test status
Simulation time 90071026 ps
CPU time 3.74 seconds
Started Jul 10 05:49:53 PM PDT 24
Finished Jul 10 05:49:57 PM PDT 24
Peak memory 210168 kb
Host smart-62849300-b628-4e1f-a296-48b67efdff32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122746469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.4122746469
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.4164368940
Short name T594
Test name
Test status
Simulation time 355953424 ps
CPU time 3.9 seconds
Started Jul 10 05:49:59 PM PDT 24
Finished Jul 10 05:50:04 PM PDT 24
Peak memory 209728 kb
Host smart-714f50b4-f14a-4e8a-bd01-91ec1de3f218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164368940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.4164368940
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2803558329
Short name T384
Test name
Test status
Simulation time 248437683 ps
CPU time 10.11 seconds
Started Jul 10 05:49:55 PM PDT 24
Finished Jul 10 05:50:07 PM PDT 24
Peak memory 207584 kb
Host smart-c563f585-5873-4953-ae30-63e7e6161c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803558329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2803558329
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3510982818
Short name T554
Test name
Test status
Simulation time 66376121 ps
CPU time 2.78 seconds
Started Jul 10 05:49:55 PM PDT 24
Finished Jul 10 05:50:00 PM PDT 24
Peak memory 206840 kb
Host smart-89f02c8c-d972-4db2-b395-98200be4d2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510982818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3510982818
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1138704792
Short name T537
Test name
Test status
Simulation time 251885819 ps
CPU time 3.85 seconds
Started Jul 10 05:49:54 PM PDT 24
Finished Jul 10 05:49:59 PM PDT 24
Peak memory 208580 kb
Host smart-56ab35bc-61de-408a-b686-5b88e2e48edc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138704792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1138704792
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.930086790
Short name T481
Test name
Test status
Simulation time 35499643 ps
CPU time 2.58 seconds
Started Jul 10 05:49:55 PM PDT 24
Finished Jul 10 05:50:00 PM PDT 24
Peak memory 206848 kb
Host smart-01d06fc4-8760-43c4-bee8-84582c1cf278
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930086790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.930086790
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3119045265
Short name T17
Test name
Test status
Simulation time 231964365 ps
CPU time 2.72 seconds
Started Jul 10 05:50:03 PM PDT 24
Finished Jul 10 05:50:08 PM PDT 24
Peak memory 207988 kb
Host smart-278a39f5-c5ff-49f6-b50e-76d91501a5fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119045265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3119045265
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1443507625
Short name T38
Test name
Test status
Simulation time 31269426 ps
CPU time 1.73 seconds
Started Jul 10 05:50:03 PM PDT 24
Finished Jul 10 05:50:07 PM PDT 24
Peak memory 207648 kb
Host smart-45d17e8b-a12a-4dc9-a128-88e6da472d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443507625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1443507625
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.336416047
Short name T693
Test name
Test status
Simulation time 396845268 ps
CPU time 2.75 seconds
Started Jul 10 05:49:52 PM PDT 24
Finished Jul 10 05:49:56 PM PDT 24
Peak memory 206628 kb
Host smart-3587e844-f469-4ef0-a3e7-e02feedd677d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336416047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.336416047
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2381713256
Short name T201
Test name
Test status
Simulation time 1635323166 ps
CPU time 31.42 seconds
Started Jul 10 05:49:59 PM PDT 24
Finished Jul 10 05:50:32 PM PDT 24
Peak memory 215680 kb
Host smart-9a046a72-6a09-4a17-8f92-8c543a8591c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381713256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2381713256
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.18356326
Short name T189
Test name
Test status
Simulation time 287534665 ps
CPU time 9.66 seconds
Started Jul 10 05:50:01 PM PDT 24
Finished Jul 10 05:50:12 PM PDT 24
Peak memory 222540 kb
Host smart-eb57797d-13db-496b-83a9-877a25f2db89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18356326 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.18356326
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3017303720
Short name T880
Test name
Test status
Simulation time 2912760230 ps
CPU time 13.62 seconds
Started Jul 10 05:49:55 PM PDT 24
Finished Jul 10 05:50:11 PM PDT 24
Peak memory 207792 kb
Host smart-333b54d4-b9a5-4883-aa8c-606e673c6f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017303720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3017303720
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3386359808
Short name T170
Test name
Test status
Simulation time 130056695 ps
CPU time 2.72 seconds
Started Jul 10 05:50:01 PM PDT 24
Finished Jul 10 05:50:05 PM PDT 24
Peak memory 210044 kb
Host smart-8546ca90-0766-458f-b851-5de6cb847c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386359808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3386359808
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.997411615
Short name T479
Test name
Test status
Simulation time 37709626 ps
CPU time 0.84 seconds
Started Jul 10 05:50:05 PM PDT 24
Finished Jul 10 05:50:08 PM PDT 24
Peak memory 205984 kb
Host smart-9ff7df7b-3466-421f-b598-3f92c30d0ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997411615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.997411615
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1485277051
Short name T320
Test name
Test status
Simulation time 455231327 ps
CPU time 4.73 seconds
Started Jul 10 05:50:02 PM PDT 24
Finished Jul 10 05:50:08 PM PDT 24
Peak memory 215704 kb
Host smart-3cb8a386-5be1-4f8d-807c-f0744143f018
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485277051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1485277051
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2008585372
Short name T112
Test name
Test status
Simulation time 290341801 ps
CPU time 8.54 seconds
Started Jul 10 05:50:00 PM PDT 24
Finished Jul 10 05:50:09 PM PDT 24
Peak memory 214700 kb
Host smart-5a64ebfb-4719-422a-b32c-6a1fb169df1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008585372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2008585372
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.954998716
Short name T291
Test name
Test status
Simulation time 92202771 ps
CPU time 1.82 seconds
Started Jul 10 05:50:00 PM PDT 24
Finished Jul 10 05:50:03 PM PDT 24
Peak memory 208136 kb
Host smart-421bd991-43aa-44d7-8baa-8119866a02ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954998716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.954998716
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.277358982
Short name T295
Test name
Test status
Simulation time 78684667 ps
CPU time 3.72 seconds
Started Jul 10 05:50:02 PM PDT 24
Finished Jul 10 05:50:07 PM PDT 24
Peak memory 214372 kb
Host smart-1f0931ac-b178-4756-af34-903dbccb1d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277358982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.277358982
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.498325208
Short name T281
Test name
Test status
Simulation time 856738663 ps
CPU time 4.92 seconds
Started Jul 10 05:50:08 PM PDT 24
Finished Jul 10 05:50:17 PM PDT 24
Peak memory 214152 kb
Host smart-69cf67ac-b5b0-4c97-aaa9-15fe5fbc1e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498325208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.498325208
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.45149669
Short name T58
Test name
Test status
Simulation time 56094021 ps
CPU time 2.69 seconds
Started Jul 10 05:50:02 PM PDT 24
Finished Jul 10 05:50:06 PM PDT 24
Peak memory 222504 kb
Host smart-061e05c1-3e56-4b61-9628-5f096174b19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45149669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.45149669
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3137794275
Short name T754
Test name
Test status
Simulation time 179850979 ps
CPU time 3.74 seconds
Started Jul 10 05:50:08 PM PDT 24
Finished Jul 10 05:50:15 PM PDT 24
Peak memory 214248 kb
Host smart-520e8db3-b142-4361-8402-db0f85db8632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137794275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3137794275
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1847337538
Short name T800
Test name
Test status
Simulation time 55707848 ps
CPU time 2.35 seconds
Started Jul 10 05:50:04 PM PDT 24
Finished Jul 10 05:50:09 PM PDT 24
Peak memory 208928 kb
Host smart-2bd53756-7c6f-4643-bfe8-38098fa2ad98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847337538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1847337538
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1427190864
Short name T474
Test name
Test status
Simulation time 335586965 ps
CPU time 2.99 seconds
Started Jul 10 05:50:03 PM PDT 24
Finished Jul 10 05:50:08 PM PDT 24
Peak memory 208512 kb
Host smart-f8b02776-b896-4be1-af42-96dfb2e9a50b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427190864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1427190864
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3721961332
Short name T4
Test name
Test status
Simulation time 77916054 ps
CPU time 2.79 seconds
Started Jul 10 05:50:00 PM PDT 24
Finished Jul 10 05:50:04 PM PDT 24
Peak memory 208280 kb
Host smart-b4175d6d-56ea-4489-b0a4-b137ce04b7a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721961332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3721961332
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2865806990
Short name T593
Test name
Test status
Simulation time 23175365 ps
CPU time 1.89 seconds
Started Jul 10 05:50:01 PM PDT 24
Finished Jul 10 05:50:04 PM PDT 24
Peak memory 206864 kb
Host smart-28fa9dde-e2b1-483f-9838-4b4c9d6da6c5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865806990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2865806990
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.844601491
Short name T758
Test name
Test status
Simulation time 250404514 ps
CPU time 2.25 seconds
Started Jul 10 05:50:04 PM PDT 24
Finished Jul 10 05:50:09 PM PDT 24
Peak memory 208160 kb
Host smart-a595b1ca-ca26-41f7-b4a2-e81c58a742e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844601491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.844601491
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3039760121
Short name T88
Test name
Test status
Simulation time 60904222 ps
CPU time 2.68 seconds
Started Jul 10 05:50:00 PM PDT 24
Finished Jul 10 05:50:04 PM PDT 24
Peak memory 208484 kb
Host smart-14a23361-d2ed-4eb0-af59-efc836e0e990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039760121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3039760121
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2398455442
Short name T326
Test name
Test status
Simulation time 179537138 ps
CPU time 3.96 seconds
Started Jul 10 05:50:02 PM PDT 24
Finished Jul 10 05:50:08 PM PDT 24
Peak memory 207408 kb
Host smart-c14028e0-ee54-4e67-a9ff-dd9e9ad71dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398455442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2398455442
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.325881248
Short name T535
Test name
Test status
Simulation time 455198168 ps
CPU time 7.8 seconds
Started Jul 10 05:50:03 PM PDT 24
Finished Jul 10 05:50:13 PM PDT 24
Peak memory 210484 kb
Host smart-eb2961df-e89a-4d82-afe1-7c6eb08cba26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325881248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.325881248
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3516032708
Short name T444
Test name
Test status
Simulation time 27754187 ps
CPU time 0.92 seconds
Started Jul 10 05:50:03 PM PDT 24
Finished Jul 10 05:50:06 PM PDT 24
Peak memory 205904 kb
Host smart-a14a3a6c-6b8b-4623-9c4b-1aae2c658487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516032708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3516032708
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1049623793
Short name T85
Test name
Test status
Simulation time 778510261 ps
CPU time 10.21 seconds
Started Jul 10 05:50:05 PM PDT 24
Finished Jul 10 05:50:18 PM PDT 24
Peak memory 214340 kb
Host smart-1865e0de-292f-4e2d-956e-758170f718d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049623793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1049623793
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.86688997
Short name T94
Test name
Test status
Simulation time 3846076001 ps
CPU time 48.03 seconds
Started Jul 10 05:50:05 PM PDT 24
Finished Jul 10 05:50:55 PM PDT 24
Peak memory 222660 kb
Host smart-1b450f7e-e2e8-4f08-ad1a-f807bae4aec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86688997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.86688997
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2242434200
Short name T316
Test name
Test status
Simulation time 1454402892 ps
CPU time 4.58 seconds
Started Jul 10 05:50:02 PM PDT 24
Finished Jul 10 05:50:08 PM PDT 24
Peak memory 206360 kb
Host smart-07c15402-173c-4a8a-8184-c89af9049e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242434200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2242434200
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1964759715
Short name T234
Test name
Test status
Simulation time 327875772 ps
CPU time 4.14 seconds
Started Jul 10 05:50:03 PM PDT 24
Finished Jul 10 05:50:10 PM PDT 24
Peak memory 220608 kb
Host smart-7cfc0603-cb9e-4e16-b35b-fe1129bc01d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964759715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1964759715
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.849281344
Short name T197
Test name
Test status
Simulation time 317838523 ps
CPU time 3.9 seconds
Started Jul 10 05:50:01 PM PDT 24
Finished Jul 10 05:50:06 PM PDT 24
Peak memory 209160 kb
Host smart-1a420475-4347-4d6e-9d82-271deca9187e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849281344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.849281344
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.4290922456
Short name T328
Test name
Test status
Simulation time 83004226 ps
CPU time 1.88 seconds
Started Jul 10 05:49:59 PM PDT 24
Finished Jul 10 05:50:02 PM PDT 24
Peak memory 206848 kb
Host smart-c9529324-90ca-4d67-8f81-dc60de85218e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290922456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.4290922456
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3721115778
Short name T409
Test name
Test status
Simulation time 172298055 ps
CPU time 5.79 seconds
Started Jul 10 05:50:03 PM PDT 24
Finished Jul 10 05:50:11 PM PDT 24
Peak memory 207832 kb
Host smart-747d4fb0-78ba-4b4d-865c-b8d0a48a1896
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721115778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3721115778
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2867198201
Short name T832
Test name
Test status
Simulation time 195754811 ps
CPU time 2.42 seconds
Started Jul 10 05:50:03 PM PDT 24
Finished Jul 10 05:50:08 PM PDT 24
Peak memory 206984 kb
Host smart-04d856f8-8cb0-4265-8d5e-691ef23f1e24
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867198201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2867198201
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3953403046
Short name T897
Test name
Test status
Simulation time 230013846 ps
CPU time 4.14 seconds
Started Jul 10 05:50:04 PM PDT 24
Finished Jul 10 05:50:11 PM PDT 24
Peak memory 208676 kb
Host smart-64b6bc31-a034-4c80-ad88-6b280034edac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953403046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3953403046
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2767723134
Short name T591
Test name
Test status
Simulation time 170488671 ps
CPU time 2.24 seconds
Started Jul 10 05:50:05 PM PDT 24
Finished Jul 10 05:50:10 PM PDT 24
Peak memory 207504 kb
Host smart-6f7734f1-76f1-47a6-b0af-f8e681f34458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767723134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2767723134
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1366090916
Short name T765
Test name
Test status
Simulation time 46108449 ps
CPU time 2.73 seconds
Started Jul 10 05:50:01 PM PDT 24
Finished Jul 10 05:50:05 PM PDT 24
Peak memory 208664 kb
Host smart-7d4472d2-96ce-4653-9c9e-1053059b97b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366090916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1366090916
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1624398378
Short name T187
Test name
Test status
Simulation time 1242434493 ps
CPU time 12 seconds
Started Jul 10 05:50:02 PM PDT 24
Finished Jul 10 05:50:16 PM PDT 24
Peak memory 219896 kb
Host smart-cc6bf2bd-eb3c-4797-962f-e311c7ebd316
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624398378 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1624398378
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.501549452
Short name T309
Test name
Test status
Simulation time 99407618 ps
CPU time 4.6 seconds
Started Jul 10 05:50:03 PM PDT 24
Finished Jul 10 05:50:09 PM PDT 24
Peak memory 209876 kb
Host smart-856beb0a-1242-49df-a279-9883a6691211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501549452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.501549452
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3380448543
Short name T821
Test name
Test status
Simulation time 621386467 ps
CPU time 2.28 seconds
Started Jul 10 05:50:04 PM PDT 24
Finished Jul 10 05:50:09 PM PDT 24
Peak memory 209928 kb
Host smart-00ce8560-aac3-40c8-a9b4-c3f23cf58e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380448543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3380448543
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1255358437
Short name T439
Test name
Test status
Simulation time 46007591 ps
CPU time 0.77 seconds
Started Jul 10 05:50:07 PM PDT 24
Finished Jul 10 05:50:11 PM PDT 24
Peak memory 205984 kb
Host smart-4259cdc8-8c8b-494f-a47e-e828a8e48080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255358437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1255358437
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.502816644
Short name T355
Test name
Test status
Simulation time 397948035 ps
CPU time 4 seconds
Started Jul 10 05:50:08 PM PDT 24
Finished Jul 10 05:50:16 PM PDT 24
Peak memory 215092 kb
Host smart-c6852f68-c9b4-49a0-bca5-e7b202a75c72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=502816644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.502816644
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1333135469
Short name T2
Test name
Test status
Simulation time 491311944 ps
CPU time 5.01 seconds
Started Jul 10 05:50:10 PM PDT 24
Finished Jul 10 05:50:19 PM PDT 24
Peak memory 222612 kb
Host smart-68048373-609c-4a86-86ce-e11420c1e09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333135469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1333135469
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2530101176
Short name T672
Test name
Test status
Simulation time 658296762 ps
CPU time 6.15 seconds
Started Jul 10 05:50:08 PM PDT 24
Finished Jul 10 05:50:18 PM PDT 24
Peak memory 219404 kb
Host smart-39b1b1cb-c67d-47bc-b0c0-e2f2162a2d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530101176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2530101176
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1947736750
Short name T338
Test name
Test status
Simulation time 376337309 ps
CPU time 3.76 seconds
Started Jul 10 05:50:07 PM PDT 24
Finished Jul 10 05:50:14 PM PDT 24
Peak memory 214576 kb
Host smart-3c5437ba-c915-472f-84b4-0b0000036ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947736750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1947736750
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3570340242
Short name T557
Test name
Test status
Simulation time 204766137 ps
CPU time 3.2 seconds
Started Jul 10 05:50:07 PM PDT 24
Finished Jul 10 05:50:13 PM PDT 24
Peak memory 213696 kb
Host smart-0dc96513-1990-4756-a17e-b1797950d4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570340242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3570340242
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.577595108
Short name T236
Test name
Test status
Simulation time 173502775 ps
CPU time 4.83 seconds
Started Jul 10 05:50:07 PM PDT 24
Finished Jul 10 05:50:15 PM PDT 24
Peak memory 213828 kb
Host smart-eb0ecbb5-a66e-4410-9e81-b95ad339134e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577595108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.577595108
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2631650409
Short name T495
Test name
Test status
Simulation time 207812242 ps
CPU time 6.22 seconds
Started Jul 10 05:50:07 PM PDT 24
Finished Jul 10 05:50:17 PM PDT 24
Peak memory 207172 kb
Host smart-126b6b8b-a35b-43f4-9df5-169a2f8881d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631650409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2631650409
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3788553080
Short name T680
Test name
Test status
Simulation time 1325323482 ps
CPU time 9.66 seconds
Started Jul 10 05:50:03 PM PDT 24
Finished Jul 10 05:50:15 PM PDT 24
Peak memory 208168 kb
Host smart-98120cab-044a-4525-b5d4-c64780c7e9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788553080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3788553080
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.815134892
Short name T523
Test name
Test status
Simulation time 56689858 ps
CPU time 3.08 seconds
Started Jul 10 05:50:02 PM PDT 24
Finished Jul 10 05:50:08 PM PDT 24
Peak memory 208756 kb
Host smart-a03c2a2c-d421-4948-8b2b-3bdc8514083a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815134892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.815134892
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3590917125
Short name T635
Test name
Test status
Simulation time 130147657 ps
CPU time 2.54 seconds
Started Jul 10 05:50:01 PM PDT 24
Finished Jul 10 05:50:06 PM PDT 24
Peak memory 206972 kb
Host smart-de328f29-3af5-48e7-8dae-2cd3b6bd35bc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590917125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3590917125
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1821011212
Short name T485
Test name
Test status
Simulation time 232938735 ps
CPU time 3.03 seconds
Started Jul 10 05:50:03 PM PDT 24
Finished Jul 10 05:50:09 PM PDT 24
Peak memory 207040 kb
Host smart-3b0402d3-7695-4eec-a540-ee16e13cc899
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821011212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1821011212
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.701243228
Short name T519
Test name
Test status
Simulation time 27627032 ps
CPU time 1.88 seconds
Started Jul 10 05:50:07 PM PDT 24
Finished Jul 10 05:50:13 PM PDT 24
Peak memory 207684 kb
Host smart-1c0da347-538b-4716-9b9c-e7b18cd483a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701243228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.701243228
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2286114105
Short name T514
Test name
Test status
Simulation time 268430758 ps
CPU time 3.25 seconds
Started Jul 10 05:50:04 PM PDT 24
Finished Jul 10 05:50:09 PM PDT 24
Peak memory 208268 kb
Host smart-f296d327-4f9d-41c6-b7a4-406db0547900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286114105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2286114105
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.304148619
Short name T57
Test name
Test status
Simulation time 549818427 ps
CPU time 19.89 seconds
Started Jul 10 05:50:09 PM PDT 24
Finished Jul 10 05:50:33 PM PDT 24
Peak memory 220676 kb
Host smart-d0eb773f-9963-4697-8445-546738fe317c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304148619 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.304148619
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3368914162
Short name T283
Test name
Test status
Simulation time 289747074 ps
CPU time 5.48 seconds
Started Jul 10 05:50:07 PM PDT 24
Finished Jul 10 05:50:15 PM PDT 24
Peak memory 210008 kb
Host smart-8bfc0ef8-7a0a-429c-8eb1-2f28df48d39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368914162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3368914162
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2637820065
Short name T685
Test name
Test status
Simulation time 1355675530 ps
CPU time 4.71 seconds
Started Jul 10 05:50:11 PM PDT 24
Finished Jul 10 05:50:20 PM PDT 24
Peak memory 210164 kb
Host smart-e465c3b0-2f2b-4d25-baf7-097afdd1cc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637820065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2637820065
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2231125964
Short name T436
Test name
Test status
Simulation time 15981757 ps
CPU time 0.8 seconds
Started Jul 10 05:50:15 PM PDT 24
Finished Jul 10 05:50:20 PM PDT 24
Peak memory 205936 kb
Host smart-a508a4f9-c23e-4c4e-993a-862a2cf027af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231125964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2231125964
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1229527666
Short name T753
Test name
Test status
Simulation time 3939236653 ps
CPU time 31.66 seconds
Started Jul 10 05:50:09 PM PDT 24
Finished Jul 10 05:50:45 PM PDT 24
Peak memory 214404 kb
Host smart-af69cf3e-f9d3-4b5a-a501-f9d475993c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229527666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1229527666
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3703529403
Short name T292
Test name
Test status
Simulation time 31161556 ps
CPU time 2.17 seconds
Started Jul 10 05:50:08 PM PDT 24
Finished Jul 10 05:50:13 PM PDT 24
Peak memory 214304 kb
Host smart-093ed65a-b79f-453a-9e58-3fd1a31085b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703529403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3703529403
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2848049804
Short name T24
Test name
Test status
Simulation time 493234334 ps
CPU time 4.22 seconds
Started Jul 10 05:50:07 PM PDT 24
Finished Jul 10 05:50:15 PM PDT 24
Peak memory 221772 kb
Host smart-572be685-bff1-482e-b2cb-66e3c54fd307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848049804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2848049804
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1582663545
Short name T255
Test name
Test status
Simulation time 137210896 ps
CPU time 3.35 seconds
Started Jul 10 05:50:07 PM PDT 24
Finished Jul 10 05:50:13 PM PDT 24
Peak memory 214280 kb
Host smart-b7beb4fb-91b3-4b06-a563-1e7f4b82a048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582663545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1582663545
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2733756771
Short name T804
Test name
Test status
Simulation time 114189171 ps
CPU time 2.78 seconds
Started Jul 10 05:50:06 PM PDT 24
Finished Jul 10 05:50:11 PM PDT 24
Peak memory 214600 kb
Host smart-af308188-d210-4747-bd37-c895feee3043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733756771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2733756771
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1694999952
Short name T555
Test name
Test status
Simulation time 83436851 ps
CPU time 5.4 seconds
Started Jul 10 05:50:12 PM PDT 24
Finished Jul 10 05:50:22 PM PDT 24
Peak memory 219628 kb
Host smart-2a6df3d5-9f5b-4701-8d61-dae2c2acbb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694999952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1694999952
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1682386743
Short name T324
Test name
Test status
Simulation time 152193705 ps
CPU time 5.68 seconds
Started Jul 10 05:50:10 PM PDT 24
Finished Jul 10 05:50:20 PM PDT 24
Peak memory 208472 kb
Host smart-532225c2-c1dc-4453-8c92-1ce4760964a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682386743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1682386743
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1897379520
Short name T646
Test name
Test status
Simulation time 525516716 ps
CPU time 4.36 seconds
Started Jul 10 05:50:11 PM PDT 24
Finished Jul 10 05:50:20 PM PDT 24
Peak memory 208388 kb
Host smart-6d7324d4-6b27-41e1-b354-6c1c8862528e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897379520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1897379520
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.174739814
Short name T578
Test name
Test status
Simulation time 1161006007 ps
CPU time 34.55 seconds
Started Jul 10 05:50:05 PM PDT 24
Finished Jul 10 05:50:42 PM PDT 24
Peak memory 208028 kb
Host smart-b783e40c-7099-4416-a76e-f80c9402ffac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174739814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.174739814
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2057814129
Short name T709
Test name
Test status
Simulation time 814671139 ps
CPU time 5.77 seconds
Started Jul 10 05:50:06 PM PDT 24
Finished Jul 10 05:50:15 PM PDT 24
Peak memory 207956 kb
Host smart-c93a9cd5-d7e4-451f-8666-a5cf28a81bee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057814129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2057814129
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.795216826
Short name T556
Test name
Test status
Simulation time 61345722 ps
CPU time 2.97 seconds
Started Jul 10 05:50:15 PM PDT 24
Finished Jul 10 05:50:22 PM PDT 24
Peak memory 214272 kb
Host smart-d687ee28-8003-408c-ae91-7cf67cdadab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795216826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.795216826
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1724464562
Short name T489
Test name
Test status
Simulation time 109776686 ps
CPU time 3.22 seconds
Started Jul 10 05:50:04 PM PDT 24
Finished Jul 10 05:50:10 PM PDT 24
Peak memory 208896 kb
Host smart-7d9a3afb-8f01-4e4e-98b6-5fbde6d9a465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724464562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1724464562
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.827297536
Short name T385
Test name
Test status
Simulation time 19326553852 ps
CPU time 446.04 seconds
Started Jul 10 05:50:07 PM PDT 24
Finished Jul 10 05:57:37 PM PDT 24
Peak memory 218052 kb
Host smart-26dfc29f-7d9b-4057-b945-cc7296f7fb12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827297536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.827297536
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1771997935
Short name T743
Test name
Test status
Simulation time 1693643242 ps
CPU time 22.68 seconds
Started Jul 10 05:50:08 PM PDT 24
Finished Jul 10 05:50:35 PM PDT 24
Peak memory 222428 kb
Host smart-5d99101d-f51e-4a66-9db1-dd2c94031d47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771997935 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1771997935
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2723062742
Short name T678
Test name
Test status
Simulation time 598868655 ps
CPU time 5.4 seconds
Started Jul 10 05:50:15 PM PDT 24
Finished Jul 10 05:50:25 PM PDT 24
Peak memory 213716 kb
Host smart-9c092610-f59e-4db3-b571-719d654218a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723062742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2723062742
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2852985292
Short name T766
Test name
Test status
Simulation time 210190173 ps
CPU time 2.21 seconds
Started Jul 10 05:50:06 PM PDT 24
Finished Jul 10 05:50:12 PM PDT 24
Peak memory 210048 kb
Host smart-6bb90eff-1f39-4b83-a0c0-b39269449e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852985292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2852985292
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1238496208
Short name T457
Test name
Test status
Simulation time 41470825 ps
CPU time 0.76 seconds
Started Jul 10 05:50:16 PM PDT 24
Finished Jul 10 05:50:21 PM PDT 24
Peak memory 205872 kb
Host smart-df26237f-6908-476e-97c6-c351ab9fa320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238496208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1238496208
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2324518631
Short name T692
Test name
Test status
Simulation time 76518038 ps
CPU time 3.27 seconds
Started Jul 10 05:50:06 PM PDT 24
Finished Jul 10 05:50:13 PM PDT 24
Peak memory 214356 kb
Host smart-079cac5e-e866-4dca-ab28-d6aefef56fbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2324518631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2324518631
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2522007520
Short name T784
Test name
Test status
Simulation time 445196250 ps
CPU time 2.76 seconds
Started Jul 10 05:50:11 PM PDT 24
Finished Jul 10 05:50:17 PM PDT 24
Peak memory 214336 kb
Host smart-85afaae8-c1c1-4ea7-8641-1504ff44aa67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522007520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2522007520
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.478194497
Short name T650
Test name
Test status
Simulation time 58867886 ps
CPU time 3.29 seconds
Started Jul 10 05:50:06 PM PDT 24
Finished Jul 10 05:50:13 PM PDT 24
Peak memory 207696 kb
Host smart-bbb1cebf-9c75-4bef-9b27-b1f9156862c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478194497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.478194497
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.893549155
Short name T529
Test name
Test status
Simulation time 446091367 ps
CPU time 3.49 seconds
Started Jul 10 05:50:06 PM PDT 24
Finished Jul 10 05:50:12 PM PDT 24
Peak memory 214416 kb
Host smart-b34b5fde-b1aa-4ac8-9d20-550cabe5aa64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893549155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.893549155
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.672371848
Short name T254
Test name
Test status
Simulation time 248563004 ps
CPU time 2.98 seconds
Started Jul 10 05:50:15 PM PDT 24
Finished Jul 10 05:50:22 PM PDT 24
Peak memory 220780 kb
Host smart-e56a41f9-cf24-476d-84fd-3364cfd4f811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672371848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.672371848
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3147591555
Short name T833
Test name
Test status
Simulation time 360268726 ps
CPU time 3.68 seconds
Started Jul 10 05:50:06 PM PDT 24
Finished Jul 10 05:50:12 PM PDT 24
Peak memory 222576 kb
Host smart-7bab8f01-455b-4d37-afc2-31a31cc8bf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147591555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3147591555
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1671187508
Short name T491
Test name
Test status
Simulation time 90591518 ps
CPU time 4.08 seconds
Started Jul 10 05:50:06 PM PDT 24
Finished Jul 10 05:50:13 PM PDT 24
Peak memory 218432 kb
Host smart-d3298b59-a5e8-49f7-bd59-3fd6c1b2a025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671187508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1671187508
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1119777242
Short name T263
Test name
Test status
Simulation time 931551509 ps
CPU time 6.86 seconds
Started Jul 10 05:50:05 PM PDT 24
Finished Jul 10 05:50:14 PM PDT 24
Peak memory 208440 kb
Host smart-74dc3ace-71ee-4423-9609-7332135da97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119777242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1119777242
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1386026016
Short name T695
Test name
Test status
Simulation time 658402638 ps
CPU time 5.93 seconds
Started Jul 10 05:50:09 PM PDT 24
Finished Jul 10 05:50:19 PM PDT 24
Peak memory 208356 kb
Host smart-72b5455c-2fd2-4184-9b88-1aedaec24ee5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386026016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1386026016
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.820652561
Short name T720
Test name
Test status
Simulation time 84326161 ps
CPU time 1.76 seconds
Started Jul 10 05:50:08 PM PDT 24
Finished Jul 10 05:50:13 PM PDT 24
Peak memory 206840 kb
Host smart-6d6e5778-3e95-4c2b-ab34-af9bbdf70000
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820652561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.820652561
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.4267533363
Short name T615
Test name
Test status
Simulation time 214199329 ps
CPU time 3.23 seconds
Started Jul 10 05:50:07 PM PDT 24
Finished Jul 10 05:50:14 PM PDT 24
Peak memory 206980 kb
Host smart-e33ca652-cd6e-477b-a83e-995aae5b532a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267533363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.4267533363
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1458348323
Short name T905
Test name
Test status
Simulation time 152823291 ps
CPU time 2.34 seconds
Started Jul 10 05:50:15 PM PDT 24
Finished Jul 10 05:50:22 PM PDT 24
Peak memory 208968 kb
Host smart-3c4141da-af3f-4466-a5fd-77c6669032e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458348323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1458348323
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.4034906832
Short name T711
Test name
Test status
Simulation time 58784325 ps
CPU time 2.27 seconds
Started Jul 10 05:50:14 PM PDT 24
Finished Jul 10 05:50:21 PM PDT 24
Peak memory 207376 kb
Host smart-5e87f715-801a-4f57-ad58-7d1a07bc4656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034906832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.4034906832
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3237448002
Short name T367
Test name
Test status
Simulation time 1953705519 ps
CPU time 23.63 seconds
Started Jul 10 05:50:11 PM PDT 24
Finished Jul 10 05:50:40 PM PDT 24
Peak memory 216584 kb
Host smart-3e800f62-66a6-4efa-844a-9a8d5a8a0aed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237448002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3237448002
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1520050692
Short name T789
Test name
Test status
Simulation time 339286345 ps
CPU time 9.18 seconds
Started Jul 10 05:50:14 PM PDT 24
Finished Jul 10 05:50:28 PM PDT 24
Peak memory 222560 kb
Host smart-1f6c0ff5-3d93-4e4a-80bc-6858f52cd0a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520050692 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1520050692
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.61990361
Short name T301
Test name
Test status
Simulation time 287974215 ps
CPU time 3.86 seconds
Started Jul 10 05:50:06 PM PDT 24
Finished Jul 10 05:50:13 PM PDT 24
Peak memory 222476 kb
Host smart-2b72320e-4d8d-4fd8-a1bc-26f2a5c284f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61990361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.61990361
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3952065358
Short name T49
Test name
Test status
Simulation time 284254875 ps
CPU time 2.48 seconds
Started Jul 10 05:50:11 PM PDT 24
Finished Jul 10 05:50:17 PM PDT 24
Peak memory 210660 kb
Host smart-3b56f9de-db01-4b22-be59-7126ee140d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952065358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3952065358
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1760848188
Short name T861
Test name
Test status
Simulation time 15812070 ps
CPU time 0.79 seconds
Started Jul 10 05:50:10 PM PDT 24
Finished Jul 10 05:50:15 PM PDT 24
Peak memory 205984 kb
Host smart-cec0cee5-ca7a-4145-8252-654aa0b8e3f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760848188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1760848188
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.4160144629
Short name T914
Test name
Test status
Simulation time 51575060 ps
CPU time 3.82 seconds
Started Jul 10 05:50:11 PM PDT 24
Finished Jul 10 05:50:19 PM PDT 24
Peak memory 214340 kb
Host smart-28779029-e4e9-41ad-9756-8cff9a6198aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4160144629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.4160144629
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2302957678
Short name T851
Test name
Test status
Simulation time 112238966 ps
CPU time 5.02 seconds
Started Jul 10 05:50:13 PM PDT 24
Finished Jul 10 05:50:22 PM PDT 24
Peak memory 218808 kb
Host smart-f068bd66-7a09-4223-8446-dc7d35a57389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302957678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2302957678
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1871021142
Short name T705
Test name
Test status
Simulation time 75735361 ps
CPU time 3.48 seconds
Started Jul 10 05:50:11 PM PDT 24
Finished Jul 10 05:50:18 PM PDT 24
Peak memory 209856 kb
Host smart-d1db5dd0-5aa3-4db1-889f-d2629683d282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871021142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1871021142
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.42600992
Short name T96
Test name
Test status
Simulation time 167718776 ps
CPU time 3.56 seconds
Started Jul 10 05:50:15 PM PDT 24
Finished Jul 10 05:50:23 PM PDT 24
Peak memory 222508 kb
Host smart-e3823b46-7b12-44f3-acf1-cd96a744ce38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42600992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.42600992
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3219765291
Short name T681
Test name
Test status
Simulation time 37908196 ps
CPU time 2.37 seconds
Started Jul 10 05:50:12 PM PDT 24
Finished Jul 10 05:50:19 PM PDT 24
Peak memory 214280 kb
Host smart-3335bb18-76f5-48a8-8b99-07c23d3c0a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219765291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3219765291
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2317420011
Short name T341
Test name
Test status
Simulation time 94810653 ps
CPU time 4.52 seconds
Started Jul 10 05:50:10 PM PDT 24
Finished Jul 10 05:50:19 PM PDT 24
Peak memory 220064 kb
Host smart-fbd3c3ee-9d1e-4b34-a059-f799677300dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317420011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2317420011
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2665026996
Short name T843
Test name
Test status
Simulation time 429237218 ps
CPU time 5.59 seconds
Started Jul 10 05:50:14 PM PDT 24
Finished Jul 10 05:50:24 PM PDT 24
Peak memory 209260 kb
Host smart-676e6db4-74d1-41a5-b757-b69298b47b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665026996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2665026996
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1801923389
Short name T330
Test name
Test status
Simulation time 227457280 ps
CPU time 3.04 seconds
Started Jul 10 05:50:15 PM PDT 24
Finished Jul 10 05:50:23 PM PDT 24
Peak memory 207068 kb
Host smart-4e39e64d-7386-4329-b9f2-e2bff6ea1111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801923389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1801923389
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1215029823
Short name T817
Test name
Test status
Simulation time 1148242458 ps
CPU time 7.69 seconds
Started Jul 10 05:50:15 PM PDT 24
Finished Jul 10 05:50:27 PM PDT 24
Peak memory 209168 kb
Host smart-b08832b5-7f88-42c0-b08e-035b28bd3fa1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215029823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1215029823
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.4119711831
Short name T497
Test name
Test status
Simulation time 26345032 ps
CPU time 1.91 seconds
Started Jul 10 05:50:10 PM PDT 24
Finished Jul 10 05:50:16 PM PDT 24
Peak memory 207204 kb
Host smart-04dadcec-ce65-490a-b990-c109b55e0a76
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119711831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.4119711831
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3234652162
Short name T19
Test name
Test status
Simulation time 95683764 ps
CPU time 3.11 seconds
Started Jul 10 05:50:09 PM PDT 24
Finished Jul 10 05:50:16 PM PDT 24
Peak memory 206808 kb
Host smart-34ef4e2d-32f3-42ca-b554-499830ff5fa6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234652162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3234652162
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.516462311
Short name T838
Test name
Test status
Simulation time 77228599 ps
CPU time 2.99 seconds
Started Jul 10 05:50:13 PM PDT 24
Finished Jul 10 05:50:21 PM PDT 24
Peak memory 209928 kb
Host smart-cd4e26fb-bbc3-4523-b696-c5a024eeed14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516462311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.516462311
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2955443975
Short name T918
Test name
Test status
Simulation time 352085543 ps
CPU time 2.72 seconds
Started Jul 10 05:50:11 PM PDT 24
Finished Jul 10 05:50:18 PM PDT 24
Peak memory 206832 kb
Host smart-9703fd5c-19c9-4e79-820c-d7b8fd782af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955443975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2955443975
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.4289678971
Short name T191
Test name
Test status
Simulation time 572907235 ps
CPU time 20.22 seconds
Started Jul 10 05:50:13 PM PDT 24
Finished Jul 10 05:50:38 PM PDT 24
Peak memory 222444 kb
Host smart-5cbd9f34-f564-4be9-8ae1-84d179b9fff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289678971 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.4289678971
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.127196640
Short name T629
Test name
Test status
Simulation time 404481349 ps
CPU time 11.01 seconds
Started Jul 10 05:50:12 PM PDT 24
Finished Jul 10 05:50:27 PM PDT 24
Peak memory 218048 kb
Host smart-dd6136fa-6d22-461e-9595-f028bacc386c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127196640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.127196640
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1957833978
Short name T904
Test name
Test status
Simulation time 136123714 ps
CPU time 3.02 seconds
Started Jul 10 05:50:16 PM PDT 24
Finished Jul 10 05:50:23 PM PDT 24
Peak memory 210544 kb
Host smart-2bd543c2-e53e-4c09-b3ae-eb9d36e5c362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957833978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1957833978
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1468184415
Short name T590
Test name
Test status
Simulation time 67339143 ps
CPU time 0.99 seconds
Started Jul 10 05:50:12 PM PDT 24
Finished Jul 10 05:50:18 PM PDT 24
Peak memory 206116 kb
Host smart-b7cf1c7d-4ef6-44b3-a9b8-7d2f9adbb650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468184415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1468184415
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1583516358
Short name T267
Test name
Test status
Simulation time 113986020 ps
CPU time 6.68 seconds
Started Jul 10 05:50:11 PM PDT 24
Finished Jul 10 05:50:21 PM PDT 24
Peak memory 214324 kb
Host smart-c9a48576-a58a-4d3b-8479-9117d6268158
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583516358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1583516358
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2075565392
Short name T703
Test name
Test status
Simulation time 473841652 ps
CPU time 6.55 seconds
Started Jul 10 05:50:15 PM PDT 24
Finished Jul 10 05:50:26 PM PDT 24
Peak memory 214704 kb
Host smart-e9b014d0-42c5-4fc5-945c-5006ecb15c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075565392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2075565392
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1379949971
Short name T576
Test name
Test status
Simulation time 216056651 ps
CPU time 4.37 seconds
Started Jul 10 05:50:11 PM PDT 24
Finished Jul 10 05:50:20 PM PDT 24
Peak memory 208648 kb
Host smart-6babc1a3-9c90-4b85-bb53-c18babe02527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379949971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1379949971
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.4191737870
Short name T644
Test name
Test status
Simulation time 473048986 ps
CPU time 3.82 seconds
Started Jul 10 05:50:11 PM PDT 24
Finished Jul 10 05:50:18 PM PDT 24
Peak memory 214328 kb
Host smart-e0a8ed2a-6165-4a15-9f54-0ae13d71a607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191737870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.4191737870
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3623940704
Short name T294
Test name
Test status
Simulation time 57672782 ps
CPU time 2.86 seconds
Started Jul 10 05:50:12 PM PDT 24
Finished Jul 10 05:50:19 PM PDT 24
Peak memory 214236 kb
Host smart-47a8416f-4b4e-4f8c-9204-faea0c03c480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623940704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3623940704
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1486185068
Short name T64
Test name
Test status
Simulation time 1491868485 ps
CPU time 3.44 seconds
Started Jul 10 05:50:10 PM PDT 24
Finished Jul 10 05:50:18 PM PDT 24
Peak memory 210204 kb
Host smart-97fb2473-45dc-4b3e-8e5d-70d4b1de2b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486185068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1486185068
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1325527084
Short name T842
Test name
Test status
Simulation time 1910767477 ps
CPU time 4.55 seconds
Started Jul 10 05:50:12 PM PDT 24
Finished Jul 10 05:50:21 PM PDT 24
Peak memory 208096 kb
Host smart-f1a8b8e2-68e7-45d0-a223-a17c6f4d827d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325527084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1325527084
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3043649245
Short name T828
Test name
Test status
Simulation time 202937841 ps
CPU time 4.19 seconds
Started Jul 10 05:50:12 PM PDT 24
Finished Jul 10 05:50:21 PM PDT 24
Peak memory 208408 kb
Host smart-148af0fd-d85c-43c5-aaf4-b40cfe088a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043649245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3043649245
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.868274979
Short name T885
Test name
Test status
Simulation time 259133756 ps
CPU time 2.58 seconds
Started Jul 10 05:50:10 PM PDT 24
Finished Jul 10 05:50:17 PM PDT 24
Peak memory 206984 kb
Host smart-5de0c769-594b-4e82-871c-3b016078c8b5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868274979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.868274979
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1472903784
Short name T455
Test name
Test status
Simulation time 130660355 ps
CPU time 2.58 seconds
Started Jul 10 05:50:13 PM PDT 24
Finished Jul 10 05:50:20 PM PDT 24
Peak memory 206804 kb
Host smart-88e26150-e504-4658-84dd-49aff567b164
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472903784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1472903784
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1228874972
Short name T736
Test name
Test status
Simulation time 275907702 ps
CPU time 3.79 seconds
Started Jul 10 05:50:13 PM PDT 24
Finished Jul 10 05:50:21 PM PDT 24
Peak memory 208704 kb
Host smart-7646c56f-1b33-4b84-a663-b0736b3bd3a5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228874972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1228874972
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2079027169
Short name T581
Test name
Test status
Simulation time 175791168 ps
CPU time 2.63 seconds
Started Jul 10 05:50:13 PM PDT 24
Finished Jul 10 05:50:20 PM PDT 24
Peak memory 214372 kb
Host smart-c8fedac1-404d-4ecf-a931-5086c43cfadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079027169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2079027169
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3865909974
Short name T776
Test name
Test status
Simulation time 6053148689 ps
CPU time 45.47 seconds
Started Jul 10 05:50:12 PM PDT 24
Finished Jul 10 05:51:02 PM PDT 24
Peak memory 208496 kb
Host smart-c56cc268-1ed0-4125-98cf-eae727284596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865909974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3865909974
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3474086889
Short name T56
Test name
Test status
Simulation time 537643800 ps
CPU time 18.23 seconds
Started Jul 10 05:50:12 PM PDT 24
Finished Jul 10 05:50:35 PM PDT 24
Peak memory 215168 kb
Host smart-e5c2cfe0-5426-4f72-8e9f-3b3f1606be96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474086889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3474086889
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.988079625
Short name T190
Test name
Test status
Simulation time 2576698000 ps
CPU time 22.37 seconds
Started Jul 10 05:50:12 PM PDT 24
Finished Jul 10 05:50:39 PM PDT 24
Peak memory 222680 kb
Host smart-8526871c-a3fe-45b1-9a95-ba083c16205d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988079625 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.988079625
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2065867201
Short name T671
Test name
Test status
Simulation time 3350741171 ps
CPU time 42.01 seconds
Started Jul 10 05:50:09 PM PDT 24
Finished Jul 10 05:50:55 PM PDT 24
Peak memory 209096 kb
Host smart-c7649335-6a1f-4cae-8d2d-ffc55dd4d528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065867201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2065867201
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1944107294
Short name T110
Test name
Test status
Simulation time 125044697 ps
CPU time 2.17 seconds
Started Jul 10 05:50:12 PM PDT 24
Finished Jul 10 05:50:18 PM PDT 24
Peak memory 210084 kb
Host smart-6fbf09f8-b82c-4648-8432-3fb577806a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944107294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1944107294
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3328945231
Short name T516
Test name
Test status
Simulation time 53039767 ps
CPU time 0.78 seconds
Started Jul 10 05:48:17 PM PDT 24
Finished Jul 10 05:48:19 PM PDT 24
Peak memory 205840 kb
Host smart-2047040d-92b9-493c-9add-6fd5ca620dbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328945231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3328945231
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2956948019
Short name T420
Test name
Test status
Simulation time 50191593 ps
CPU time 3.26 seconds
Started Jul 10 05:48:24 PM PDT 24
Finished Jul 10 05:48:29 PM PDT 24
Peak memory 214332 kb
Host smart-75f57a86-9b7c-46ee-b525-540e155f0145
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2956948019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2956948019
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1038880838
Short name T35
Test name
Test status
Simulation time 279772405 ps
CPU time 2.57 seconds
Started Jul 10 05:48:20 PM PDT 24
Finished Jul 10 05:48:25 PM PDT 24
Peak memory 210372 kb
Host smart-f6faa073-ca15-4cf9-bf05-3f8cacf900ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038880838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1038880838
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.255293417
Short name T300
Test name
Test status
Simulation time 557116347 ps
CPU time 6.9 seconds
Started Jul 10 05:48:21 PM PDT 24
Finished Jul 10 05:48:30 PM PDT 24
Peak memory 219868 kb
Host smart-54a178cd-815e-4884-8fbc-472c4c4f0a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255293417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.255293417
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.889094194
Short name T275
Test name
Test status
Simulation time 29002974 ps
CPU time 2.07 seconds
Started Jul 10 05:48:21 PM PDT 24
Finished Jul 10 05:48:25 PM PDT 24
Peak memory 214644 kb
Host smart-b7bec175-5b87-4441-9d19-5b063dce5a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889094194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.889094194
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3603790841
Short name T369
Test name
Test status
Simulation time 182569033 ps
CPU time 3.09 seconds
Started Jul 10 05:48:23 PM PDT 24
Finished Jul 10 05:48:28 PM PDT 24
Peak memory 214356 kb
Host smart-3096ccac-2e55-481d-ac69-350e3b453bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603790841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3603790841
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3542734822
Short name T541
Test name
Test status
Simulation time 226448428 ps
CPU time 3.48 seconds
Started Jul 10 05:48:23 PM PDT 24
Finished Jul 10 05:48:29 PM PDT 24
Peak memory 215824 kb
Host smart-b4b2ff4c-6af7-4275-a5ec-5e31d365ee01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542734822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3542734822
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1163785463
Short name T579
Test name
Test status
Simulation time 124751166 ps
CPU time 5.73 seconds
Started Jul 10 05:48:28 PM PDT 24
Finished Jul 10 05:48:36 PM PDT 24
Peak memory 208900 kb
Host smart-5c9e74e7-455b-4e71-8265-d50da1cc55e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163785463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1163785463
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3881296930
Short name T40
Test name
Test status
Simulation time 343361503 ps
CPU time 11.04 seconds
Started Jul 10 05:48:28 PM PDT 24
Finished Jul 10 05:48:41 PM PDT 24
Peak memory 230500 kb
Host smart-af7c1ba2-277b-4db3-823d-7e4da9fba8bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881296930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3881296930
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2535423577
Short name T570
Test name
Test status
Simulation time 514178593 ps
CPU time 4.87 seconds
Started Jul 10 05:48:19 PM PDT 24
Finished Jul 10 05:48:26 PM PDT 24
Peak memory 208544 kb
Host smart-c703a006-05d9-43bc-b194-6b75d6220789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535423577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2535423577
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1746641984
Short name T854
Test name
Test status
Simulation time 612573769 ps
CPU time 7.43 seconds
Started Jul 10 05:48:21 PM PDT 24
Finished Jul 10 05:48:30 PM PDT 24
Peak memory 208144 kb
Host smart-c3a33ba2-a711-4c0c-9bc2-a1fab8a6c2f1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746641984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1746641984
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3000020656
Short name T782
Test name
Test status
Simulation time 476818869 ps
CPU time 6.15 seconds
Started Jul 10 05:48:23 PM PDT 24
Finished Jul 10 05:48:31 PM PDT 24
Peak memory 208192 kb
Host smart-6c7f4293-3243-4f83-a33b-43f6d3277328
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000020656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3000020656
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1589387685
Short name T248
Test name
Test status
Simulation time 201803924 ps
CPU time 5.05 seconds
Started Jul 10 05:48:28 PM PDT 24
Finished Jul 10 05:48:35 PM PDT 24
Peak memory 208744 kb
Host smart-666e1ec3-d051-440e-9c95-2d901b402353
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589387685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1589387685
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1624751860
Short name T334
Test name
Test status
Simulation time 2453594167 ps
CPU time 14.21 seconds
Started Jul 10 05:48:19 PM PDT 24
Finished Jul 10 05:48:35 PM PDT 24
Peak memory 214568 kb
Host smart-625e1d8c-b7d0-4849-bf8f-56f17a9adc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624751860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1624751860
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.463511081
Short name T813
Test name
Test status
Simulation time 1629464120 ps
CPU time 15.4 seconds
Started Jul 10 05:48:18 PM PDT 24
Finished Jul 10 05:48:35 PM PDT 24
Peak memory 208484 kb
Host smart-1dcb3305-412e-4316-bb09-77a09fa075b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463511081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.463511081
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3427964574
Short name T403
Test name
Test status
Simulation time 55678584 ps
CPU time 0.9 seconds
Started Jul 10 05:48:20 PM PDT 24
Finished Jul 10 05:48:23 PM PDT 24
Peak memory 206056 kb
Host smart-b3ecfd72-0370-4387-9c2a-45d6d4e1f588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427964574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3427964574
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1409900179
Short name T241
Test name
Test status
Simulation time 290274855 ps
CPU time 17 seconds
Started Jul 10 05:48:22 PM PDT 24
Finished Jul 10 05:48:41 PM PDT 24
Peak memory 222540 kb
Host smart-d2d2e663-8bf8-4b58-bdbd-2f1042a7914d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409900179 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1409900179
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.250411097
Short name T269
Test name
Test status
Simulation time 227360552 ps
CPU time 7.24 seconds
Started Jul 10 05:48:20 PM PDT 24
Finished Jul 10 05:48:29 PM PDT 24
Peak memory 218276 kb
Host smart-a07651b2-9bfd-4301-a272-4eb21c64a257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250411097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.250411097
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2511887319
Short name T395
Test name
Test status
Simulation time 517561380 ps
CPU time 5.83 seconds
Started Jul 10 05:48:21 PM PDT 24
Finished Jul 10 05:48:29 PM PDT 24
Peak memory 211036 kb
Host smart-cd3f6fc6-e54f-457c-8467-19a9e5d1c5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511887319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2511887319
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2238842553
Short name T764
Test name
Test status
Simulation time 33854650 ps
CPU time 0.77 seconds
Started Jul 10 05:50:17 PM PDT 24
Finished Jul 10 05:50:22 PM PDT 24
Peak memory 205984 kb
Host smart-ffd9d37f-916a-46ed-a1cd-36afebbb62d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238842553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2238842553
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.4201547586
Short name T873
Test name
Test status
Simulation time 288075729 ps
CPU time 8.57 seconds
Started Jul 10 05:50:20 PM PDT 24
Finished Jul 10 05:50:32 PM PDT 24
Peak memory 221996 kb
Host smart-cf124e1b-df10-4573-8333-40ed48ee1920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201547586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.4201547586
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3064911900
Short name T71
Test name
Test status
Simulation time 137702561 ps
CPU time 3.18 seconds
Started Jul 10 05:50:17 PM PDT 24
Finished Jul 10 05:50:24 PM PDT 24
Peak memory 209328 kb
Host smart-c801ecdd-9961-421f-b911-4456bfedba24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064911900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3064911900
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1334813133
Short name T687
Test name
Test status
Simulation time 120092731 ps
CPU time 3.2 seconds
Started Jul 10 05:50:19 PM PDT 24
Finished Jul 10 05:50:26 PM PDT 24
Peak memory 207280 kb
Host smart-044976f5-3e29-4d01-ae75-ec24638f8195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334813133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1334813133
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3169756342
Short name T25
Test name
Test status
Simulation time 478672663 ps
CPU time 5.37 seconds
Started Jul 10 05:50:20 PM PDT 24
Finished Jul 10 05:50:29 PM PDT 24
Peak memory 214184 kb
Host smart-24531c64-1c07-4257-8bcc-ccce5354b405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169756342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3169756342
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2825747218
Short name T215
Test name
Test status
Simulation time 59424386 ps
CPU time 4.44 seconds
Started Jul 10 05:50:16 PM PDT 24
Finished Jul 10 05:50:24 PM PDT 24
Peak memory 222632 kb
Host smart-20ebf7ce-0233-40f5-9f8e-052b311b061b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825747218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2825747218
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3786438572
Short name T91
Test name
Test status
Simulation time 1297486890 ps
CPU time 30.22 seconds
Started Jul 10 05:50:18 PM PDT 24
Finished Jul 10 05:50:52 PM PDT 24
Peak memory 214336 kb
Host smart-0f2f09f3-4a41-43da-a97d-1370f5bfb8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786438572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3786438572
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2834932694
Short name T870
Test name
Test status
Simulation time 30437571 ps
CPU time 2.28 seconds
Started Jul 10 05:50:17 PM PDT 24
Finished Jul 10 05:50:23 PM PDT 24
Peak memory 206904 kb
Host smart-decca603-592f-4b4a-aed8-ff5a2ffbcd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834932694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2834932694
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2391610140
Short name T815
Test name
Test status
Simulation time 1144152984 ps
CPU time 5.05 seconds
Started Jul 10 05:50:17 PM PDT 24
Finished Jul 10 05:50:26 PM PDT 24
Peak memory 208540 kb
Host smart-8f1876e5-5149-4ccd-aa25-6fca176cea35
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391610140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2391610140
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.56036004
Short name T716
Test name
Test status
Simulation time 638808784 ps
CPU time 15.8 seconds
Started Jul 10 05:50:19 PM PDT 24
Finished Jul 10 05:50:39 PM PDT 24
Peak memory 208100 kb
Host smart-29bc4524-b96e-4e9c-b624-0743da6509d8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56036004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.56036004
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2952832797
Short name T600
Test name
Test status
Simulation time 765737809 ps
CPU time 10.75 seconds
Started Jul 10 05:50:20 PM PDT 24
Finished Jul 10 05:50:34 PM PDT 24
Peak memory 207960 kb
Host smart-8a159049-3f12-4f71-b6af-7276a394046b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952832797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2952832797
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1296743593
Short name T653
Test name
Test status
Simulation time 35439029 ps
CPU time 2.2 seconds
Started Jul 10 05:50:18 PM PDT 24
Finished Jul 10 05:50:24 PM PDT 24
Peak memory 207872 kb
Host smart-e11e138e-e44b-4e5d-8aa5-e0423ab595ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296743593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1296743593
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3311948111
Short name T208
Test name
Test status
Simulation time 130434253 ps
CPU time 2.85 seconds
Started Jul 10 05:50:10 PM PDT 24
Finished Jul 10 05:50:17 PM PDT 24
Peak memory 206896 kb
Host smart-03c043df-0de2-412a-b1e9-7137c587f959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311948111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3311948111
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1839506134
Short name T79
Test name
Test status
Simulation time 644363465 ps
CPU time 24.6 seconds
Started Jul 10 05:50:19 PM PDT 24
Finished Jul 10 05:50:47 PM PDT 24
Peak memory 220384 kb
Host smart-cf862c64-7e6c-4239-b6aa-05317b884507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839506134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1839506134
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1380307332
Short name T770
Test name
Test status
Simulation time 402328307 ps
CPU time 4.62 seconds
Started Jul 10 05:50:17 PM PDT 24
Finished Jul 10 05:50:26 PM PDT 24
Peak memory 208696 kb
Host smart-c98657d6-d3b0-4d8d-b0af-985a388d89d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380307332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1380307332
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2043165969
Short name T48
Test name
Test status
Simulation time 258820144 ps
CPU time 2.01 seconds
Started Jul 10 05:50:17 PM PDT 24
Finished Jul 10 05:50:23 PM PDT 24
Peak memory 210208 kb
Host smart-28aee28f-e7a0-4b47-a2a1-ec16c0751a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043165969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2043165969
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1275415195
Short name T746
Test name
Test status
Simulation time 47310468 ps
CPU time 0.74 seconds
Started Jul 10 05:50:19 PM PDT 24
Finished Jul 10 05:50:23 PM PDT 24
Peak memory 205976 kb
Host smart-e7010bfe-408f-4972-a349-196323c3de48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275415195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1275415195
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2347378842
Short name T431
Test name
Test status
Simulation time 151216743 ps
CPU time 4.26 seconds
Started Jul 10 05:50:17 PM PDT 24
Finished Jul 10 05:50:25 PM PDT 24
Peak memory 215876 kb
Host smart-fd52d121-31d6-4ef7-900e-415408a9b7eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2347378842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2347378842
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1502931556
Short name T611
Test name
Test status
Simulation time 417019564 ps
CPU time 11.76 seconds
Started Jul 10 05:50:17 PM PDT 24
Finished Jul 10 05:50:32 PM PDT 24
Peak memory 222768 kb
Host smart-33948507-bb13-4234-be23-c92f9064ffbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502931556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1502931556
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2680596126
Short name T763
Test name
Test status
Simulation time 96082299 ps
CPU time 3.52 seconds
Started Jul 10 05:50:18 PM PDT 24
Finished Jul 10 05:50:25 PM PDT 24
Peak memory 210072 kb
Host smart-dff6d14e-e931-48f7-8193-6afc173a07d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680596126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2680596126
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3424561841
Short name T860
Test name
Test status
Simulation time 176140189 ps
CPU time 5.82 seconds
Started Jul 10 05:50:20 PM PDT 24
Finished Jul 10 05:50:29 PM PDT 24
Peak memory 209068 kb
Host smart-8da16180-78cd-43bc-b9ca-2ea2b13a4480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424561841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3424561841
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1170325225
Short name T293
Test name
Test status
Simulation time 58751048 ps
CPU time 2.91 seconds
Started Jul 10 05:50:18 PM PDT 24
Finished Jul 10 05:50:25 PM PDT 24
Peak memory 214348 kb
Host smart-1fd7ae45-490e-472b-a6c3-dec4e43edccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170325225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1170325225
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3986201666
Short name T469
Test name
Test status
Simulation time 90003040 ps
CPU time 2.68 seconds
Started Jul 10 05:50:17 PM PDT 24
Finished Jul 10 05:50:24 PM PDT 24
Peak memory 209784 kb
Host smart-0a1493de-084b-4d1b-85d7-e7074ca88905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986201666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3986201666
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3101762186
Short name T487
Test name
Test status
Simulation time 404301055 ps
CPU time 6.68 seconds
Started Jul 10 05:50:21 PM PDT 24
Finished Jul 10 05:50:30 PM PDT 24
Peak memory 207736 kb
Host smart-5c486722-b933-4781-943a-a79a39d314d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101762186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3101762186
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3716535017
Short name T894
Test name
Test status
Simulation time 63369706 ps
CPU time 2.36 seconds
Started Jul 10 05:50:15 PM PDT 24
Finished Jul 10 05:50:22 PM PDT 24
Peak memory 206928 kb
Host smart-9a938b11-52d8-41c2-aded-a8dabcaded5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716535017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3716535017
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1842248274
Short name T761
Test name
Test status
Simulation time 369578360 ps
CPU time 7.42 seconds
Started Jul 10 05:50:21 PM PDT 24
Finished Jul 10 05:50:31 PM PDT 24
Peak memory 208516 kb
Host smart-d2fdc2a5-d78d-4b0b-803a-514555086e3c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842248274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1842248274
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.4157093656
Short name T826
Test name
Test status
Simulation time 306076555 ps
CPU time 4.13 seconds
Started Jul 10 05:50:20 PM PDT 24
Finished Jul 10 05:50:27 PM PDT 24
Peak memory 209136 kb
Host smart-e1e83d5b-1d24-4dc4-ad8a-50ee85acec3f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157093656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.4157093656
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2454812141
Short name T798
Test name
Test status
Simulation time 216691333 ps
CPU time 2.31 seconds
Started Jul 10 05:50:17 PM PDT 24
Finished Jul 10 05:50:23 PM PDT 24
Peak memory 206956 kb
Host smart-f284f4f1-307a-4b00-9cd3-5292f6aa91ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454812141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2454812141
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.204750835
Short name T214
Test name
Test status
Simulation time 1365494977 ps
CPU time 24.45 seconds
Started Jul 10 05:50:16 PM PDT 24
Finished Jul 10 05:50:45 PM PDT 24
Peak memory 209776 kb
Host smart-a2952915-3162-4ab1-90aa-a394e85aba7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204750835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.204750835
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1221037963
Short name T470
Test name
Test status
Simulation time 149977776 ps
CPU time 3.35 seconds
Started Jul 10 05:50:18 PM PDT 24
Finished Jul 10 05:50:25 PM PDT 24
Peak memory 208680 kb
Host smart-d7f242f7-8246-4302-89da-e4f0bd83b048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221037963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1221037963
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.747182908
Short name T863
Test name
Test status
Simulation time 1449540658 ps
CPU time 15.11 seconds
Started Jul 10 05:50:18 PM PDT 24
Finished Jul 10 05:50:37 PM PDT 24
Peak memory 215848 kb
Host smart-9152507a-da91-437b-8da2-44ec2ce9de2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747182908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.747182908
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3693197400
Short name T128
Test name
Test status
Simulation time 2368712983 ps
CPU time 22.82 seconds
Started Jul 10 05:50:18 PM PDT 24
Finished Jul 10 05:50:44 PM PDT 24
Peak memory 221008 kb
Host smart-ca52c6eb-4779-4674-beca-d691b340bc17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693197400 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3693197400
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1553068365
Short name T265
Test name
Test status
Simulation time 48260447 ps
CPU time 3.49 seconds
Started Jul 10 05:50:21 PM PDT 24
Finished Jul 10 05:50:28 PM PDT 24
Peak memory 209936 kb
Host smart-91799e52-8f7f-4983-85ad-014c4bc967cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553068365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1553068365
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.707032267
Short name T675
Test name
Test status
Simulation time 132134017 ps
CPU time 2.36 seconds
Started Jul 10 05:50:21 PM PDT 24
Finished Jul 10 05:50:26 PM PDT 24
Peak memory 210580 kb
Host smart-4b47752b-6158-4c6b-a645-1c70316e0922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707032267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.707032267
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2070698337
Short name T658
Test name
Test status
Simulation time 29189723 ps
CPU time 0.92 seconds
Started Jul 10 05:50:26 PM PDT 24
Finished Jul 10 05:50:29 PM PDT 24
Peak memory 206116 kb
Host smart-37841d81-e0e0-45c2-8ceb-f0f194745377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070698337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2070698337
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3448017373
Short name T792
Test name
Test status
Simulation time 49850544 ps
CPU time 2.6 seconds
Started Jul 10 05:50:21 PM PDT 24
Finished Jul 10 05:50:27 PM PDT 24
Peak memory 210132 kb
Host smart-2dce1e87-3ba8-49e6-9d27-4df849df873f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448017373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3448017373
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3439996946
Short name T242
Test name
Test status
Simulation time 78598549 ps
CPU time 3.43 seconds
Started Jul 10 05:50:27 PM PDT 24
Finished Jul 10 05:50:33 PM PDT 24
Peak memory 209648 kb
Host smart-64639200-4647-4299-985b-ac712ae9ffc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439996946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3439996946
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1939111068
Short name T637
Test name
Test status
Simulation time 3629143015 ps
CPU time 5.89 seconds
Started Jul 10 05:50:21 PM PDT 24
Finished Jul 10 05:50:30 PM PDT 24
Peak memory 214964 kb
Host smart-cf8e8bc0-6747-4b6c-ad10-3b3ff7f3dc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939111068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1939111068
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2368900923
Short name T747
Test name
Test status
Simulation time 2632204703 ps
CPU time 26.74 seconds
Started Jul 10 05:50:24 PM PDT 24
Finished Jul 10 05:50:53 PM PDT 24
Peak memory 218568 kb
Host smart-62a4b3b8-2984-4cce-8d17-a85e109c30fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368900923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2368900923
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2210115227
Short name T756
Test name
Test status
Simulation time 89713637 ps
CPU time 3.13 seconds
Started Jul 10 05:50:17 PM PDT 24
Finished Jul 10 05:50:24 PM PDT 24
Peak memory 208464 kb
Host smart-245765f6-f4ad-4b96-b1e3-dd78f4d7574c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210115227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2210115227
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.521605350
Short name T538
Test name
Test status
Simulation time 82072473 ps
CPU time 1.83 seconds
Started Jul 10 05:50:26 PM PDT 24
Finished Jul 10 05:50:30 PM PDT 24
Peak memory 206956 kb
Host smart-06bfd489-cfc3-4a4f-af02-0c68875d2c0f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521605350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.521605350
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.640778895
Short name T729
Test name
Test status
Simulation time 157638815 ps
CPU time 2.68 seconds
Started Jul 10 05:50:22 PM PDT 24
Finished Jul 10 05:50:28 PM PDT 24
Peak memory 206988 kb
Host smart-82013194-64eb-4ea1-bdb8-15b009490542
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640778895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.640778895
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1476304498
Short name T139
Test name
Test status
Simulation time 152284861 ps
CPU time 5.43 seconds
Started Jul 10 05:50:23 PM PDT 24
Finished Jul 10 05:50:31 PM PDT 24
Peak memory 208756 kb
Host smart-8f9cdccb-09fe-4ea6-84ae-c945b02ed83a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476304498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1476304498
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.934945370
Short name T696
Test name
Test status
Simulation time 49510065 ps
CPU time 1.52 seconds
Started Jul 10 05:50:22 PM PDT 24
Finished Jul 10 05:50:26 PM PDT 24
Peak memory 207592 kb
Host smart-8034927a-7b6c-4972-8a9d-f3b8160d58db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934945370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.934945370
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1243045346
Short name T677
Test name
Test status
Simulation time 146728587 ps
CPU time 2.95 seconds
Started Jul 10 05:50:18 PM PDT 24
Finished Jul 10 05:50:25 PM PDT 24
Peak memory 208404 kb
Host smart-bd8911fa-58fa-4d66-a210-86cdbbd8889a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243045346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1243045346
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2174106840
Short name T227
Test name
Test status
Simulation time 3679448032 ps
CPU time 87.41 seconds
Started Jul 10 05:50:22 PM PDT 24
Finished Jul 10 05:51:52 PM PDT 24
Peak memory 215248 kb
Host smart-a9624051-d866-4b78-8b67-5c73e510cf53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174106840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2174106840
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2829608166
Short name T287
Test name
Test status
Simulation time 242863233 ps
CPU time 5.62 seconds
Started Jul 10 05:50:27 PM PDT 24
Finished Jul 10 05:50:35 PM PDT 24
Peak memory 218212 kb
Host smart-086a846b-fbfc-4995-916d-1e436f7afbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829608166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2829608166
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.506361284
Short name T396
Test name
Test status
Simulation time 72951655 ps
CPU time 2.06 seconds
Started Jul 10 05:50:26 PM PDT 24
Finished Jul 10 05:50:30 PM PDT 24
Peak memory 210564 kb
Host smart-7807ae29-5609-4d5c-a846-c67384f31bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506361284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.506361284
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2213600531
Short name T657
Test name
Test status
Simulation time 201493173 ps
CPU time 0.79 seconds
Started Jul 10 05:50:30 PM PDT 24
Finished Jul 10 05:50:33 PM PDT 24
Peak memory 205976 kb
Host smart-172e2c52-a1f3-4ea0-a15f-2333504d033f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213600531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2213600531
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1846614337
Short name T247
Test name
Test status
Simulation time 1910935172 ps
CPU time 40.22 seconds
Started Jul 10 05:50:25 PM PDT 24
Finished Jul 10 05:51:08 PM PDT 24
Peak memory 214328 kb
Host smart-aef1f4c9-3bc7-456e-9765-1f5e8ca4fb0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1846614337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1846614337
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3302367301
Short name T163
Test name
Test status
Simulation time 384478913 ps
CPU time 3.37 seconds
Started Jul 10 05:50:26 PM PDT 24
Finished Jul 10 05:50:31 PM PDT 24
Peak memory 222620 kb
Host smart-1340fa8e-66cb-4455-8f5f-d92d59dceea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302367301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3302367301
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2444306540
Short name T872
Test name
Test status
Simulation time 449735988 ps
CPU time 6.31 seconds
Started Jul 10 05:50:25 PM PDT 24
Finished Jul 10 05:50:34 PM PDT 24
Peak memory 214320 kb
Host smart-248e4173-0b29-4721-8259-bef9eb6d4b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444306540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2444306540
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1891379696
Short name T336
Test name
Test status
Simulation time 77298101 ps
CPU time 2.17 seconds
Started Jul 10 05:50:22 PM PDT 24
Finished Jul 10 05:50:27 PM PDT 24
Peak memory 221712 kb
Host smart-f236c5aa-baf8-48b5-8768-0fe0289916f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891379696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1891379696
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.4048415844
Short name T68
Test name
Test status
Simulation time 75986827 ps
CPU time 3.91 seconds
Started Jul 10 05:50:22 PM PDT 24
Finished Jul 10 05:50:28 PM PDT 24
Peak memory 207976 kb
Host smart-2ca96b17-cb92-457e-b513-57e16fc9716d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048415844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.4048415844
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2111288297
Short name T546
Test name
Test status
Simulation time 90565701 ps
CPU time 4.47 seconds
Started Jul 10 05:50:23 PM PDT 24
Finished Jul 10 05:50:30 PM PDT 24
Peak memory 208820 kb
Host smart-837650d2-8917-4fdc-acc3-8f6bfe1815a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111288297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2111288297
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.230174754
Short name T641
Test name
Test status
Simulation time 81024756 ps
CPU time 3.31 seconds
Started Jul 10 05:50:24 PM PDT 24
Finished Jul 10 05:50:30 PM PDT 24
Peak memory 208340 kb
Host smart-b1061151-2ceb-4b8f-8bc7-084c8dc908b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230174754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.230174754
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1985497233
Short name T539
Test name
Test status
Simulation time 559270889 ps
CPU time 2.48 seconds
Started Jul 10 05:50:28 PM PDT 24
Finished Jul 10 05:50:33 PM PDT 24
Peak memory 206956 kb
Host smart-7e247104-cdf6-4256-930f-563e30d0aff0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985497233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1985497233
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3610782908
Short name T816
Test name
Test status
Simulation time 105659501 ps
CPU time 2.86 seconds
Started Jul 10 05:50:25 PM PDT 24
Finished Jul 10 05:50:30 PM PDT 24
Peak memory 209044 kb
Host smart-345e103f-ed87-4e0b-beff-6ee05ba75637
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610782908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3610782908
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3439223219
Short name T357
Test name
Test status
Simulation time 877059777 ps
CPU time 7.57 seconds
Started Jul 10 05:50:24 PM PDT 24
Finished Jul 10 05:50:34 PM PDT 24
Peak memory 208712 kb
Host smart-7af89c04-d592-4ccb-b137-8322040c8d41
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439223219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3439223219
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2224586909
Short name T834
Test name
Test status
Simulation time 98778840 ps
CPU time 4.45 seconds
Started Jul 10 05:50:23 PM PDT 24
Finished Jul 10 05:50:30 PM PDT 24
Peak memory 209820 kb
Host smart-3e6d2baf-fe7d-4708-a8b3-026165373277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224586909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2224586909
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2904933421
Short name T719
Test name
Test status
Simulation time 20083067 ps
CPU time 1.7 seconds
Started Jul 10 05:50:23 PM PDT 24
Finished Jul 10 05:50:27 PM PDT 24
Peak memory 206848 kb
Host smart-2e71faeb-315c-4fa9-bf2b-ba197f028527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904933421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2904933421
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1118515011
Short name T358
Test name
Test status
Simulation time 974891775 ps
CPU time 39.23 seconds
Started Jul 10 05:50:30 PM PDT 24
Finished Jul 10 05:51:11 PM PDT 24
Peak memory 222416 kb
Host smart-1609dc98-277e-47da-9b38-5783003ebb94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118515011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1118515011
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3689611282
Short name T648
Test name
Test status
Simulation time 153480684 ps
CPU time 5.43 seconds
Started Jul 10 05:50:23 PM PDT 24
Finished Jul 10 05:50:31 PM PDT 24
Peak memory 219600 kb
Host smart-5c107761-fc21-468a-8a21-478c219b5e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689611282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3689611282
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2214326660
Short name T400
Test name
Test status
Simulation time 117872531 ps
CPU time 2.09 seconds
Started Jul 10 05:50:29 PM PDT 24
Finished Jul 10 05:50:34 PM PDT 24
Peak memory 209996 kb
Host smart-ed980bcd-0c7c-41ad-99a7-9c3fa40918fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214326660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2214326660
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.479837261
Short name T919
Test name
Test status
Simulation time 58270319 ps
CPU time 0.98 seconds
Started Jul 10 05:50:27 PM PDT 24
Finished Jul 10 05:50:30 PM PDT 24
Peak memory 206128 kb
Host smart-270f1055-7c34-438a-9b48-bc9e3d3ec14f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479837261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.479837261
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.325581959
Short name T759
Test name
Test status
Simulation time 210829840 ps
CPU time 3.12 seconds
Started Jul 10 05:50:31 PM PDT 24
Finished Jul 10 05:50:36 PM PDT 24
Peak memory 208100 kb
Host smart-d2efaa18-d8e8-4707-bf65-010cce1f20fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325581959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.325581959
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3935881934
Short name T676
Test name
Test status
Simulation time 77849648 ps
CPU time 1.98 seconds
Started Jul 10 05:50:30 PM PDT 24
Finished Jul 10 05:50:34 PM PDT 24
Peak memory 214336 kb
Host smart-991db149-85e7-45d4-8f7a-e24207a2b9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935881934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3935881934
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3716464403
Short name T559
Test name
Test status
Simulation time 141532337 ps
CPU time 2.93 seconds
Started Jul 10 05:50:28 PM PDT 24
Finished Jul 10 05:50:33 PM PDT 24
Peak memory 214264 kb
Host smart-46be43f4-0908-4f5f-9b1b-658be1c3f952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716464403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3716464403
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3901621944
Short name T585
Test name
Test status
Simulation time 1307111532 ps
CPU time 2.43 seconds
Started Jul 10 05:50:28 PM PDT 24
Finished Jul 10 05:50:33 PM PDT 24
Peak memory 216216 kb
Host smart-ce5ea753-e9d5-4816-a8a4-4480c873692b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901621944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3901621944
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.4283940319
Short name T261
Test name
Test status
Simulation time 36246105 ps
CPU time 2.61 seconds
Started Jul 10 05:50:28 PM PDT 24
Finished Jul 10 05:50:33 PM PDT 24
Peak memory 218076 kb
Host smart-41a8ea48-09c2-4457-94b0-c5c2c4fcf36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283940319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.4283940319
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2049345885
Short name T550
Test name
Test status
Simulation time 235532865 ps
CPU time 4.06 seconds
Started Jul 10 05:50:27 PM PDT 24
Finished Jul 10 05:50:33 PM PDT 24
Peak memory 208964 kb
Host smart-2ecb2c79-c6ac-48df-956f-9e231419d8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049345885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2049345885
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.375532511
Short name T478
Test name
Test status
Simulation time 118923060 ps
CPU time 2.08 seconds
Started Jul 10 05:50:30 PM PDT 24
Finished Jul 10 05:50:35 PM PDT 24
Peak memory 208924 kb
Host smart-f53b21a0-1f98-43de-afea-dd66b411d37f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375532511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.375532511
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3940396280
Short name T331
Test name
Test status
Simulation time 454571291 ps
CPU time 6.39 seconds
Started Jul 10 05:50:29 PM PDT 24
Finished Jul 10 05:50:38 PM PDT 24
Peak memory 207992 kb
Host smart-ffef8acc-3ec5-45fa-bdc1-c55b754d3cd9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940396280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3940396280
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3393522098
Short name T669
Test name
Test status
Simulation time 433813525 ps
CPU time 6.05 seconds
Started Jul 10 05:50:29 PM PDT 24
Finished Jul 10 05:50:38 PM PDT 24
Peak memory 208728 kb
Host smart-cf16fb30-2d30-4b65-b17f-bb4f41f1f218
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393522098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3393522098
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.47962066
Short name T303
Test name
Test status
Simulation time 115622947 ps
CPU time 2.92 seconds
Started Jul 10 05:50:31 PM PDT 24
Finished Jul 10 05:50:36 PM PDT 24
Peak memory 207380 kb
Host smart-0c0d7e76-2526-4c69-a60d-fae67dc79b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47962066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.47962066
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1140234561
Short name T768
Test name
Test status
Simulation time 226100871 ps
CPU time 3.92 seconds
Started Jul 10 05:50:33 PM PDT 24
Finished Jul 10 05:50:39 PM PDT 24
Peak memory 208680 kb
Host smart-2f5e2ab7-67fe-4cba-a26e-6bb3c965d73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140234561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1140234561
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2862625468
Short name T547
Test name
Test status
Simulation time 444550672 ps
CPU time 15.63 seconds
Started Jul 10 05:50:29 PM PDT 24
Finished Jul 10 05:50:47 PM PDT 24
Peak memory 216596 kb
Host smart-4800c47f-3187-4cb9-bf11-e43b3b6ba870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862625468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2862625468
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.4029626152
Short name T353
Test name
Test status
Simulation time 365295390 ps
CPU time 13.64 seconds
Started Jul 10 05:50:29 PM PDT 24
Finished Jul 10 05:50:45 PM PDT 24
Peak memory 220656 kb
Host smart-3f05c111-266f-43b0-9a77-08473f21b60c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029626152 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.4029626152
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3496592557
Short name T424
Test name
Test status
Simulation time 627186189 ps
CPU time 20.27 seconds
Started Jul 10 05:50:29 PM PDT 24
Finished Jul 10 05:50:52 PM PDT 24
Peak memory 209448 kb
Host smart-385a8d24-48a1-4550-9244-d0d1b5cb8b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496592557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3496592557
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.591029188
Short name T823
Test name
Test status
Simulation time 19987202 ps
CPU time 0.74 seconds
Started Jul 10 05:50:32 PM PDT 24
Finished Jul 10 05:50:35 PM PDT 24
Peak memory 205988 kb
Host smart-21eb7289-41be-425d-aab9-8a6509d949e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591029188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.591029188
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2971832967
Short name T245
Test name
Test status
Simulation time 748222275 ps
CPU time 10.36 seconds
Started Jul 10 05:50:36 PM PDT 24
Finished Jul 10 05:50:48 PM PDT 24
Peak memory 215280 kb
Host smart-a80857fa-8459-4018-8257-21fdda28c4e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2971832967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2971832967
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2354917730
Short name T865
Test name
Test status
Simulation time 324997613 ps
CPU time 6.28 seconds
Started Jul 10 05:50:35 PM PDT 24
Finished Jul 10 05:50:42 PM PDT 24
Peak memory 207604 kb
Host smart-74c4ebf1-ecef-4aff-b9ca-e9318b89afb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354917730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2354917730
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3438134672
Short name T101
Test name
Test status
Simulation time 234949609 ps
CPU time 3.73 seconds
Started Jul 10 05:50:34 PM PDT 24
Finished Jul 10 05:50:39 PM PDT 24
Peak memory 214204 kb
Host smart-e9ce834f-e5b4-4a5a-99bd-946fae447afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438134672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3438134672
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.968480558
Short name T794
Test name
Test status
Simulation time 34242767 ps
CPU time 1.78 seconds
Started Jul 10 05:50:34 PM PDT 24
Finished Jul 10 05:50:37 PM PDT 24
Peak memory 214228 kb
Host smart-64914c42-678d-4aa4-b1c7-ae7afc7e8f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968480558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.968480558
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.477971650
Short name T808
Test name
Test status
Simulation time 119345833 ps
CPU time 2.5 seconds
Started Jul 10 05:50:37 PM PDT 24
Finished Jul 10 05:50:41 PM PDT 24
Peak memory 208336 kb
Host smart-cfb2869d-48ad-4623-aad5-d9e64796eb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477971650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.477971650
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2321241490
Short name T521
Test name
Test status
Simulation time 603144212 ps
CPU time 5.67 seconds
Started Jul 10 05:50:33 PM PDT 24
Finished Jul 10 05:50:40 PM PDT 24
Peak memory 207468 kb
Host smart-c0914488-6425-4c23-8725-adb7c697202b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321241490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2321241490
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1078342103
Short name T311
Test name
Test status
Simulation time 152969139 ps
CPU time 2.58 seconds
Started Jul 10 05:50:28 PM PDT 24
Finished Jul 10 05:50:33 PM PDT 24
Peak memory 206856 kb
Host smart-8bd99b04-8ee2-4b2c-8335-4ca236ea42ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078342103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1078342103
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3211486689
Short name T221
Test name
Test status
Simulation time 1465730909 ps
CPU time 37.6 seconds
Started Jul 10 05:50:28 PM PDT 24
Finished Jul 10 05:51:08 PM PDT 24
Peak memory 208316 kb
Host smart-908ed47c-82a3-4cb7-a607-33ff5f98b37d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211486689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3211486689
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3213871959
Short name T651
Test name
Test status
Simulation time 2045622735 ps
CPU time 22.55 seconds
Started Jul 10 05:50:30 PM PDT 24
Finished Jul 10 05:50:55 PM PDT 24
Peak memory 208080 kb
Host smart-841416ac-c432-40eb-8ee5-c00840577cd8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213871959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3213871959
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1023011482
Short name T799
Test name
Test status
Simulation time 156196367 ps
CPU time 3.08 seconds
Started Jul 10 05:50:36 PM PDT 24
Finished Jul 10 05:50:41 PM PDT 24
Peak memory 207064 kb
Host smart-0fc079ca-9802-4271-aa88-3d0491ad3b0d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023011482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1023011482
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3294867245
Short name T302
Test name
Test status
Simulation time 58156349 ps
CPU time 2.31 seconds
Started Jul 10 05:50:47 PM PDT 24
Finished Jul 10 05:50:50 PM PDT 24
Peak memory 214224 kb
Host smart-e984817d-4a0f-4b77-9f3e-e244e20a20e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294867245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3294867245
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3145681514
Short name T466
Test name
Test status
Simulation time 69854029 ps
CPU time 2.74 seconds
Started Jul 10 05:50:29 PM PDT 24
Finished Jul 10 05:50:35 PM PDT 24
Peak memory 206856 kb
Host smart-d7c027cc-984d-4ae2-9f08-3aa7efb15c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145681514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3145681514
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3304282002
Short name T239
Test name
Test status
Simulation time 5282529797 ps
CPU time 171.11 seconds
Started Jul 10 05:50:36 PM PDT 24
Finished Jul 10 05:53:29 PM PDT 24
Peak memory 222576 kb
Host smart-6b81ce16-3f19-44b7-8765-d72212fd824a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304282002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3304282002
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3005827693
Short name T130
Test name
Test status
Simulation time 2633254357 ps
CPU time 14.38 seconds
Started Jul 10 05:50:34 PM PDT 24
Finished Jul 10 05:50:50 PM PDT 24
Peak memory 222692 kb
Host smart-cff6ab4b-a8ea-4bc4-95b7-58597d9ffa4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005827693 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3005827693
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.4032407813
Short name T298
Test name
Test status
Simulation time 262956288 ps
CPU time 7.74 seconds
Started Jul 10 05:50:36 PM PDT 24
Finished Jul 10 05:50:45 PM PDT 24
Peak memory 209784 kb
Host smart-84e56d6d-4b30-425c-8b36-965e9b2d08e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032407813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.4032407813
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.906046647
Short name T399
Test name
Test status
Simulation time 114533723 ps
CPU time 1.96 seconds
Started Jul 10 05:50:37 PM PDT 24
Finished Jul 10 05:50:40 PM PDT 24
Peak memory 209812 kb
Host smart-fb58cf53-7bcb-49fb-8c7f-50ce4af6cbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906046647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.906046647
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3737692182
Short name T721
Test name
Test status
Simulation time 16359967 ps
CPU time 0.75 seconds
Started Jul 10 05:50:39 PM PDT 24
Finished Jul 10 05:50:41 PM PDT 24
Peak memory 206012 kb
Host smart-703f3999-c655-4a8d-9351-b8bd2376fb92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737692182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3737692182
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3067160394
Short name T30
Test name
Test status
Simulation time 89010023 ps
CPU time 4.04 seconds
Started Jul 10 05:50:40 PM PDT 24
Finished Jul 10 05:50:46 PM PDT 24
Peak memory 210928 kb
Host smart-09382dc4-8afb-4635-b8eb-db10a8538b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067160394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3067160394
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3737770958
Short name T592
Test name
Test status
Simulation time 147228067 ps
CPU time 2.46 seconds
Started Jul 10 05:50:36 PM PDT 24
Finished Jul 10 05:50:40 PM PDT 24
Peak memory 218476 kb
Host smart-067796df-7cd0-45ec-b89c-dffed4c08b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737770958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3737770958
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.4275846857
Short name T392
Test name
Test status
Simulation time 104272932 ps
CPU time 4.72 seconds
Started Jul 10 05:50:43 PM PDT 24
Finished Jul 10 05:50:49 PM PDT 24
Peak memory 222412 kb
Host smart-f53f8e99-c978-4618-b892-3dcf8b8705d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275846857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.4275846857
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3804256623
Short name T231
Test name
Test status
Simulation time 72326263 ps
CPU time 4.43 seconds
Started Jul 10 05:50:35 PM PDT 24
Finished Jul 10 05:50:40 PM PDT 24
Peak memory 217860 kb
Host smart-2d1b5459-3bfa-4281-ae71-9441906eb059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804256623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3804256623
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3265098566
Short name T209
Test name
Test status
Simulation time 1024125678 ps
CPU time 25.2 seconds
Started Jul 10 05:50:34 PM PDT 24
Finished Jul 10 05:51:00 PM PDT 24
Peak memory 208508 kb
Host smart-9aa26e76-9fcc-430e-a1eb-27d807a00c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265098566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3265098566
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1765213053
Short name T219
Test name
Test status
Simulation time 511638315 ps
CPU time 4.42 seconds
Started Jul 10 05:50:37 PM PDT 24
Finished Jul 10 05:50:43 PM PDT 24
Peak memory 206684 kb
Host smart-a0199bbe-8e38-4da9-aa9a-02bb80388a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765213053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1765213053
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2941791252
Short name T605
Test name
Test status
Simulation time 518897987 ps
CPU time 4.57 seconds
Started Jul 10 05:50:36 PM PDT 24
Finished Jul 10 05:50:42 PM PDT 24
Peak memory 208680 kb
Host smart-fdc2f05c-2ac5-436a-b079-e1c55df23618
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941791252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2941791252
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2910006714
Short name T136
Test name
Test status
Simulation time 49351126 ps
CPU time 2.73 seconds
Started Jul 10 05:50:35 PM PDT 24
Finished Jul 10 05:50:39 PM PDT 24
Peak memory 206980 kb
Host smart-a36bcb5f-219f-4dad-b244-0241c7868e47
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910006714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2910006714
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.811516109
Short name T115
Test name
Test status
Simulation time 120385209 ps
CPU time 4.99 seconds
Started Jul 10 05:50:35 PM PDT 24
Finished Jul 10 05:50:41 PM PDT 24
Peak memory 208004 kb
Host smart-3195c067-2ca4-44ba-a1ee-9a08763dd211
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811516109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.811516109
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.18821419
Short name T286
Test name
Test status
Simulation time 377642466 ps
CPU time 3.64 seconds
Started Jul 10 05:50:40 PM PDT 24
Finished Jul 10 05:50:45 PM PDT 24
Peak memory 209568 kb
Host smart-bc17e7d9-6b70-4aff-81bf-c7d6b7de42f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18821419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.18821419
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2019002924
Short name T460
Test name
Test status
Simulation time 84364437 ps
CPU time 2.49 seconds
Started Jul 10 05:50:35 PM PDT 24
Finished Jul 10 05:50:38 PM PDT 24
Peak memory 208576 kb
Host smart-7f0a4cd7-7db9-40d9-b0ff-5dde2b127770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019002924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2019002924
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2527808244
Short name T80
Test name
Test status
Simulation time 5520365650 ps
CPU time 38.49 seconds
Started Jul 10 05:50:47 PM PDT 24
Finished Jul 10 05:51:27 PM PDT 24
Peak memory 222152 kb
Host smart-1b39c44e-3b3f-4966-95eb-95867926476e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527808244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2527808244
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2012019785
Short name T688
Test name
Test status
Simulation time 192583720 ps
CPU time 12.49 seconds
Started Jul 10 05:50:47 PM PDT 24
Finished Jul 10 05:51:01 PM PDT 24
Peak memory 222488 kb
Host smart-dcf10710-e43b-4e72-a75d-7719639a1691
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012019785 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2012019785
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1263237601
Short name T874
Test name
Test status
Simulation time 420018754 ps
CPU time 4.89 seconds
Started Jul 10 05:50:40 PM PDT 24
Finished Jul 10 05:50:46 PM PDT 24
Peak memory 218424 kb
Host smart-2a7751c7-c72e-400e-af23-e68a62c95450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263237601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1263237601
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.4073960228
Short name T917
Test name
Test status
Simulation time 55910793 ps
CPU time 2.46 seconds
Started Jul 10 05:50:45 PM PDT 24
Finished Jul 10 05:50:49 PM PDT 24
Peak memory 210056 kb
Host smart-fcd3ac69-3b6e-4570-900b-7e9417a66dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073960228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.4073960228
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3456819288
Short name T774
Test name
Test status
Simulation time 25257274 ps
CPU time 0.91 seconds
Started Jul 10 05:50:43 PM PDT 24
Finished Jul 10 05:50:45 PM PDT 24
Peak memory 206092 kb
Host smart-6e7a421c-ce1f-4152-bdf0-bd8dc55fba3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456819288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3456819288
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1818817262
Short name T45
Test name
Test status
Simulation time 138044852 ps
CPU time 3 seconds
Started Jul 10 05:50:42 PM PDT 24
Finished Jul 10 05:50:46 PM PDT 24
Peak memory 209832 kb
Host smart-d345a318-5662-40fb-ab12-759672ae131d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818817262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1818817262
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.797065909
Short name T83
Test name
Test status
Simulation time 246948223 ps
CPU time 2.55 seconds
Started Jul 10 05:50:43 PM PDT 24
Finished Jul 10 05:50:46 PM PDT 24
Peak memory 207156 kb
Host smart-ec0568ba-2a68-4921-b027-1288e1ae642f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797065909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.797065909
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2474804633
Short name T95
Test name
Test status
Simulation time 68874788 ps
CPU time 2.65 seconds
Started Jul 10 05:50:39 PM PDT 24
Finished Jul 10 05:50:42 PM PDT 24
Peak memory 214328 kb
Host smart-4d5f75ec-448b-488f-92f1-a35d0e4abd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474804633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2474804633
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.952087082
Short name T370
Test name
Test status
Simulation time 306736638 ps
CPU time 4.1 seconds
Started Jul 10 05:50:43 PM PDT 24
Finished Jul 10 05:50:49 PM PDT 24
Peak memory 222004 kb
Host smart-a7ce0850-1cab-477e-a8b4-cb820e81b943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952087082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.952087082
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.4080229716
Short name T217
Test name
Test status
Simulation time 105279984 ps
CPU time 5.3 seconds
Started Jul 10 05:50:43 PM PDT 24
Finished Jul 10 05:50:49 PM PDT 24
Peak memory 214328 kb
Host smart-e0d0580e-903f-4624-afa8-c0ff81b0f17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080229716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.4080229716
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3557085398
Short name T691
Test name
Test status
Simulation time 593229133 ps
CPU time 6.16 seconds
Started Jul 10 05:50:42 PM PDT 24
Finished Jul 10 05:50:50 PM PDT 24
Peak memory 209316 kb
Host smart-e28de928-bf3e-4259-87a2-66f7144170fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557085398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3557085398
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3483642154
Short name T250
Test name
Test status
Simulation time 115643445 ps
CPU time 2.8 seconds
Started Jul 10 05:50:40 PM PDT 24
Finished Jul 10 05:50:44 PM PDT 24
Peak memory 208292 kb
Host smart-80dcb359-4345-4878-a0a8-f7bcfd68dd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483642154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3483642154
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.522634141
Short name T352
Test name
Test status
Simulation time 155712846 ps
CPU time 2.42 seconds
Started Jul 10 05:50:41 PM PDT 24
Finished Jul 10 05:50:45 PM PDT 24
Peak memory 208592 kb
Host smart-96739f89-c459-4fa4-bc6f-d772f58d892e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522634141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.522634141
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2194485640
Short name T859
Test name
Test status
Simulation time 58894575 ps
CPU time 3.15 seconds
Started Jul 10 05:50:41 PM PDT 24
Finished Jul 10 05:50:45 PM PDT 24
Peak memory 208056 kb
Host smart-657f5ff3-d481-4091-a2b2-5e696aaf38c3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194485640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2194485640
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.651318516
Short name T710
Test name
Test status
Simulation time 5075162170 ps
CPU time 34.13 seconds
Started Jul 10 05:50:39 PM PDT 24
Finished Jul 10 05:51:15 PM PDT 24
Peak memory 207516 kb
Host smart-1990b14a-e72e-4917-ae7c-1c287a105660
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651318516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.651318516
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.841008890
Short name T212
Test name
Test status
Simulation time 414041247 ps
CPU time 3.1 seconds
Started Jul 10 05:50:40 PM PDT 24
Finished Jul 10 05:50:45 PM PDT 24
Peak memory 209336 kb
Host smart-7705c6f5-dcdd-4dbf-97d6-6aef708b05a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841008890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.841008890
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1434296164
Short name T486
Test name
Test status
Simulation time 72789589 ps
CPU time 2.69 seconds
Started Jul 10 05:50:39 PM PDT 24
Finished Jul 10 05:50:44 PM PDT 24
Peak memory 206848 kb
Host smart-41476dc9-07a2-408b-85e4-1a245230179f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434296164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1434296164
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3164442062
Short name T226
Test name
Test status
Simulation time 1663031433 ps
CPU time 48.27 seconds
Started Jul 10 05:50:39 PM PDT 24
Finished Jul 10 05:51:29 PM PDT 24
Peak memory 222080 kb
Host smart-090635ad-5fe0-4db0-84c0-72a8a6adaa61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164442062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3164442062
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.933533281
Short name T378
Test name
Test status
Simulation time 1065878960 ps
CPU time 16.32 seconds
Started Jul 10 05:50:42 PM PDT 24
Finished Jul 10 05:51:00 PM PDT 24
Peak memory 222692 kb
Host smart-d9678fac-0d37-477a-8176-3efc05ae91f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933533281 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.933533281
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.609318142
Short name T853
Test name
Test status
Simulation time 150932055 ps
CPU time 3.86 seconds
Started Jul 10 05:50:40 PM PDT 24
Finished Jul 10 05:50:45 PM PDT 24
Peak memory 209120 kb
Host smart-0ae0d618-8c56-43b7-b65c-1bd589dd73cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609318142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.609318142
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2242381591
Short name T857
Test name
Test status
Simulation time 250822168 ps
CPU time 3.34 seconds
Started Jul 10 05:50:40 PM PDT 24
Finished Jul 10 05:50:45 PM PDT 24
Peak memory 210468 kb
Host smart-c3a91fe2-0ead-4840-a437-7774f69084a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242381591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2242381591
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3317079693
Short name T108
Test name
Test status
Simulation time 11269282 ps
CPU time 0.88 seconds
Started Jul 10 05:50:50 PM PDT 24
Finished Jul 10 05:50:52 PM PDT 24
Peak memory 205892 kb
Host smart-b1ff81e2-28ae-4e93-8a3b-3e705bd2b9c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317079693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3317079693
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2708166493
Short name T222
Test name
Test status
Simulation time 205689905 ps
CPU time 5.39 seconds
Started Jul 10 05:50:45 PM PDT 24
Finished Jul 10 05:50:52 PM PDT 24
Peak memory 214696 kb
Host smart-aacdfcdc-7353-4709-bfeb-d89d855e4d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708166493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2708166493
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1336228711
Short name T855
Test name
Test status
Simulation time 59415316 ps
CPU time 2.23 seconds
Started Jul 10 05:50:51 PM PDT 24
Finished Jul 10 05:50:55 PM PDT 24
Peak memory 214380 kb
Host smart-16bc04d2-03f6-4a82-8d69-2b539a6a4438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336228711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1336228711
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1811409745
Short name T574
Test name
Test status
Simulation time 950556751 ps
CPU time 3.9 seconds
Started Jul 10 05:50:45 PM PDT 24
Finished Jul 10 05:50:50 PM PDT 24
Peak memory 214324 kb
Host smart-4e5608ed-2023-4548-becc-a3d4e45754de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811409745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1811409745
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.4277436598
Short name T890
Test name
Test status
Simulation time 169740596 ps
CPU time 3.05 seconds
Started Jul 10 05:50:53 PM PDT 24
Finished Jul 10 05:50:58 PM PDT 24
Peak memory 222364 kb
Host smart-1c7f2af9-205b-4f3a-9ad6-f96752e5fc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277436598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.4277436598
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1781176267
Short name T850
Test name
Test status
Simulation time 58947817 ps
CPU time 2.5 seconds
Started Jul 10 05:50:44 PM PDT 24
Finished Jul 10 05:50:48 PM PDT 24
Peak memory 217660 kb
Host smart-fd6a8cfd-6dd8-4821-8c90-89932e9e2964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781176267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1781176267
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2079358174
Short name T806
Test name
Test status
Simulation time 141124512 ps
CPU time 2.71 seconds
Started Jul 10 05:50:41 PM PDT 24
Finished Jul 10 05:50:45 PM PDT 24
Peak memory 207976 kb
Host smart-daac135b-5752-4ff8-8d34-578ba4d0731e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079358174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2079358174
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.600381746
Short name T666
Test name
Test status
Simulation time 282477402 ps
CPU time 4.18 seconds
Started Jul 10 05:50:39 PM PDT 24
Finished Jul 10 05:50:45 PM PDT 24
Peak memory 208796 kb
Host smart-931ca938-72a3-4266-afe7-4c1aaee242d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600381746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.600381746
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1011441085
Short name T760
Test name
Test status
Simulation time 56104950 ps
CPU time 2.88 seconds
Started Jul 10 05:50:48 PM PDT 24
Finished Jul 10 05:50:52 PM PDT 24
Peak memory 207100 kb
Host smart-937cf170-6fb8-4028-b52f-4e8793221445
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011441085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1011441085
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2987748897
Short name T773
Test name
Test status
Simulation time 270316442 ps
CPU time 3.45 seconds
Started Jul 10 05:50:39 PM PDT 24
Finished Jul 10 05:50:44 PM PDT 24
Peak memory 206948 kb
Host smart-feced31b-d75c-4599-b36d-6205862506a8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987748897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2987748897
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.672224185
Short name T887
Test name
Test status
Simulation time 18877383 ps
CPU time 1.9 seconds
Started Jul 10 05:50:41 PM PDT 24
Finished Jul 10 05:50:44 PM PDT 24
Peak memory 206956 kb
Host smart-505d00f9-903d-4b34-9e89-1e515d94b0b3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672224185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.672224185
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1624772059
Short name T448
Test name
Test status
Simulation time 49892638 ps
CPU time 2.57 seconds
Started Jul 10 05:50:44 PM PDT 24
Finished Jul 10 05:50:49 PM PDT 24
Peak memory 207248 kb
Host smart-75ef9272-a74e-42fd-9d22-0b098f4220e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624772059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1624772059
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3295875102
Short name T505
Test name
Test status
Simulation time 38322126 ps
CPU time 2.55 seconds
Started Jul 10 05:50:47 PM PDT 24
Finished Jul 10 05:50:51 PM PDT 24
Peak memory 208528 kb
Host smart-b44f501a-c4e1-4978-a174-313e609b2686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295875102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3295875102
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.487924449
Short name T237
Test name
Test status
Simulation time 212208329 ps
CPU time 14.47 seconds
Started Jul 10 05:50:49 PM PDT 24
Finished Jul 10 05:51:05 PM PDT 24
Peak memory 222692 kb
Host smart-65c8d13e-abf6-4fa2-adc1-468eeb7cda17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487924449 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.487924449
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2931577608
Short name T342
Test name
Test status
Simulation time 132188879 ps
CPU time 5.96 seconds
Started Jul 10 05:50:47 PM PDT 24
Finished Jul 10 05:50:54 PM PDT 24
Peak memory 209668 kb
Host smart-4becc593-b88e-4043-a83f-7ec6e33c68ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931577608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2931577608
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.233687179
Short name T531
Test name
Test status
Simulation time 54144755 ps
CPU time 2.44 seconds
Started Jul 10 05:50:54 PM PDT 24
Finished Jul 10 05:50:59 PM PDT 24
Peak memory 209984 kb
Host smart-9e09d398-e0b2-4e4d-a591-5ec6a1f9a471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233687179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.233687179
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2468321480
Short name T699
Test name
Test status
Simulation time 22332293 ps
CPU time 0.87 seconds
Started Jul 10 05:50:58 PM PDT 24
Finished Jul 10 05:51:04 PM PDT 24
Peak memory 205992 kb
Host smart-117a0e38-8ca3-436f-8932-0e308d6d5f8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468321480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2468321480
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1912471562
Short name T406
Test name
Test status
Simulation time 187862160 ps
CPU time 3.48 seconds
Started Jul 10 05:50:45 PM PDT 24
Finished Jul 10 05:50:50 PM PDT 24
Peak memory 214536 kb
Host smart-96bccb66-8907-4d56-b2ba-81d7e2c5bf30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1912471562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1912471562
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.4197860417
Short name T906
Test name
Test status
Simulation time 190248876 ps
CPU time 6.51 seconds
Started Jul 10 05:50:55 PM PDT 24
Finished Jul 10 05:51:04 PM PDT 24
Peak memory 208828 kb
Host smart-cacc0af6-850c-4ff0-8c6d-070ccafc3817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197860417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.4197860417
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.477562352
Short name T652
Test name
Test status
Simulation time 817056936 ps
CPU time 5.33 seconds
Started Jul 10 05:50:49 PM PDT 24
Finished Jul 10 05:50:56 PM PDT 24
Peak memory 214324 kb
Host smart-8285848b-6b6a-4410-9064-ea30888bf493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477562352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.477562352
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3566141194
Short name T654
Test name
Test status
Simulation time 31095454 ps
CPU time 2.39 seconds
Started Jul 10 05:50:54 PM PDT 24
Finished Jul 10 05:50:58 PM PDT 24
Peak memory 214484 kb
Host smart-a103be56-046c-40aa-a696-a4ff4280d486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566141194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3566141194
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.541781467
Short name T313
Test name
Test status
Simulation time 99866988 ps
CPU time 3.03 seconds
Started Jul 10 05:50:54 PM PDT 24
Finished Jul 10 05:50:59 PM PDT 24
Peak memory 214332 kb
Host smart-ed4221ef-a599-4ebf-9d73-86856fbca0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541781467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.541781467
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3405069292
Short name T785
Test name
Test status
Simulation time 51925627 ps
CPU time 3.09 seconds
Started Jul 10 05:50:52 PM PDT 24
Finished Jul 10 05:50:56 PM PDT 24
Peak memory 219928 kb
Host smart-492c7e28-00e6-47e2-91c6-09a32fd60a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405069292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3405069292
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2700503187
Short name T580
Test name
Test status
Simulation time 2257521861 ps
CPU time 40.61 seconds
Started Jul 10 05:50:46 PM PDT 24
Finished Jul 10 05:51:27 PM PDT 24
Peak memory 209404 kb
Host smart-906fb08b-6f1a-4263-ba6a-61da4ac5f5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700503187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2700503187
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1433971187
Short name T545
Test name
Test status
Simulation time 334169242 ps
CPU time 3.23 seconds
Started Jul 10 05:50:53 PM PDT 24
Finished Jul 10 05:50:58 PM PDT 24
Peak memory 206912 kb
Host smart-6ac35488-5db6-4b2f-be49-8b212b26ff0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433971187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1433971187
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1895703189
Short name T204
Test name
Test status
Simulation time 197124966 ps
CPU time 7.46 seconds
Started Jul 10 05:50:53 PM PDT 24
Finished Jul 10 05:51:03 PM PDT 24
Peak memory 208932 kb
Host smart-dee049be-5e46-43ac-a649-d252002974d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895703189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1895703189
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1938406842
Short name T16
Test name
Test status
Simulation time 37487329 ps
CPU time 2.63 seconds
Started Jul 10 05:50:52 PM PDT 24
Finished Jul 10 05:50:56 PM PDT 24
Peak memory 208764 kb
Host smart-dd29192b-a5d8-4f8e-a8d8-d53494e997e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938406842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1938406842
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2908814525
Short name T702
Test name
Test status
Simulation time 3398381082 ps
CPU time 38.33 seconds
Started Jul 10 05:50:52 PM PDT 24
Finished Jul 10 05:51:32 PM PDT 24
Peak memory 208432 kb
Host smart-2478decb-2d93-4d48-970b-1cd9176bf571
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908814525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2908814525
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3133235328
Short name T137
Test name
Test status
Simulation time 559425740 ps
CPU time 2.9 seconds
Started Jul 10 05:50:48 PM PDT 24
Finished Jul 10 05:50:52 PM PDT 24
Peak memory 208700 kb
Host smart-22d7835f-6882-4b62-9170-cc5312c99f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133235328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3133235328
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2252587310
Short name T745
Test name
Test status
Simulation time 214033649 ps
CPU time 6.81 seconds
Started Jul 10 05:50:46 PM PDT 24
Finished Jul 10 05:50:54 PM PDT 24
Peak memory 208832 kb
Host smart-c9df95d9-5fb1-4940-857e-aa9edc4dd6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252587310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2252587310
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1619409299
Short name T618
Test name
Test status
Simulation time 483420788 ps
CPU time 8.46 seconds
Started Jul 10 05:50:58 PM PDT 24
Finished Jul 10 05:51:11 PM PDT 24
Peak memory 208344 kb
Host smart-b360f4ee-85d3-4fed-a6f7-6623e29e57d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619409299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1619409299
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1118449397
Short name T193
Test name
Test status
Simulation time 82333300 ps
CPU time 2.7 seconds
Started Jul 10 05:50:45 PM PDT 24
Finished Jul 10 05:50:49 PM PDT 24
Peak memory 210596 kb
Host smart-0aa7ea59-f0aa-4330-909d-4271ec31af30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118449397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1118449397
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.431050045
Short name T668
Test name
Test status
Simulation time 32956463 ps
CPU time 0.83 seconds
Started Jul 10 05:48:27 PM PDT 24
Finished Jul 10 05:48:30 PM PDT 24
Peak memory 205980 kb
Host smart-a167d299-f54b-400b-ad5c-db6ee2ea7e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431050045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.431050045
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2506410541
Short name T90
Test name
Test status
Simulation time 175087681 ps
CPU time 4.02 seconds
Started Jul 10 05:48:22 PM PDT 24
Finished Jul 10 05:48:28 PM PDT 24
Peak memory 214352 kb
Host smart-d73a39fe-77cb-4bf0-b7f6-d41cda518c6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2506410541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2506410541
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3404910618
Short name T822
Test name
Test status
Simulation time 411750605 ps
CPU time 4.24 seconds
Started Jul 10 05:48:25 PM PDT 24
Finished Jul 10 05:48:31 PM PDT 24
Peak memory 218468 kb
Host smart-f807b595-6309-4c88-9038-73ce1315b626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404910618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3404910618
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3104790736
Short name T596
Test name
Test status
Simulation time 643332294 ps
CPU time 4.21 seconds
Started Jul 10 05:48:23 PM PDT 24
Finished Jul 10 05:48:30 PM PDT 24
Peak memory 207696 kb
Host smart-a53e53b4-04b7-4362-8999-82bf83d25fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104790736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3104790736
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3023372267
Short name T566
Test name
Test status
Simulation time 2576908399 ps
CPU time 28.05 seconds
Started Jul 10 05:48:24 PM PDT 24
Finished Jul 10 05:48:54 PM PDT 24
Peak memory 209816 kb
Host smart-aa05b271-d6f4-4310-979d-0b5a37c11d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023372267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3023372267
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3302206115
Short name T911
Test name
Test status
Simulation time 140994655 ps
CPU time 2.94 seconds
Started Jul 10 05:48:24 PM PDT 24
Finished Jul 10 05:48:29 PM PDT 24
Peak memory 221432 kb
Host smart-8cd385f2-263c-4c97-a4e7-4705d23295ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302206115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3302206115
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3893301896
Short name T240
Test name
Test status
Simulation time 94555300 ps
CPU time 3.53 seconds
Started Jul 10 05:48:27 PM PDT 24
Finished Jul 10 05:48:32 PM PDT 24
Peak memory 210148 kb
Host smart-22e1ecee-87b9-4df5-863b-90e3216c8ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893301896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3893301896
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2769731978
Short name T304
Test name
Test status
Simulation time 240928090 ps
CPU time 6.74 seconds
Started Jul 10 05:48:22 PM PDT 24
Finished Jul 10 05:48:31 PM PDT 24
Peak memory 210468 kb
Host smart-409cf43a-b698-4a92-9e21-270b621191a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769731978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2769731978
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3145984538
Short name T670
Test name
Test status
Simulation time 607002137 ps
CPU time 22.77 seconds
Started Jul 10 05:48:22 PM PDT 24
Finished Jul 10 05:48:46 PM PDT 24
Peak memory 208320 kb
Host smart-e7ae2a6c-1a47-4e2c-b33e-abaef2572b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145984538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3145984538
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3434591052
Short name T447
Test name
Test status
Simulation time 209123193 ps
CPU time 5.62 seconds
Started Jul 10 05:48:20 PM PDT 24
Finished Jul 10 05:48:28 PM PDT 24
Peak memory 208528 kb
Host smart-3d56b0cb-ebc2-4369-b79c-760819e46645
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434591052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3434591052
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1107966216
Short name T551
Test name
Test status
Simulation time 1312140848 ps
CPU time 5.94 seconds
Started Jul 10 05:48:23 PM PDT 24
Finished Jul 10 05:48:31 PM PDT 24
Peak memory 207880 kb
Host smart-bde41669-d1a5-4530-b28e-095df48e4d6d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107966216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1107966216
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1767648707
Short name T511
Test name
Test status
Simulation time 804297534 ps
CPU time 6.23 seconds
Started Jul 10 05:48:21 PM PDT 24
Finished Jul 10 05:48:29 PM PDT 24
Peak memory 208444 kb
Host smart-670fef66-759f-452c-baa1-2ef8c28f89ad
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767648707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1767648707
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1068277705
Short name T824
Test name
Test status
Simulation time 227551351 ps
CPU time 4.33 seconds
Started Jul 10 05:48:26 PM PDT 24
Finished Jul 10 05:48:31 PM PDT 24
Peak memory 209928 kb
Host smart-29855177-0bb6-4d5d-a408-1ff973b8411d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068277705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1068277705
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.402952272
Short name T589
Test name
Test status
Simulation time 126497461 ps
CPU time 2.43 seconds
Started Jul 10 05:48:20 PM PDT 24
Finished Jul 10 05:48:25 PM PDT 24
Peak memory 207384 kb
Host smart-ba4a0e24-e711-4639-b9f5-2fca8fbfb446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402952272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.402952272
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1428016961
Short name T379
Test name
Test status
Simulation time 1631575044 ps
CPU time 41.07 seconds
Started Jul 10 05:48:27 PM PDT 24
Finished Jul 10 05:49:10 PM PDT 24
Peak memory 222376 kb
Host smart-4005d9fa-7259-47c1-95b9-ca0a795c06df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428016961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1428016961
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.535296488
Short name T131
Test name
Test status
Simulation time 754471247 ps
CPU time 13.35 seconds
Started Jul 10 05:48:27 PM PDT 24
Finished Jul 10 05:48:43 PM PDT 24
Peak memory 222576 kb
Host smart-d497cf9d-e553-40e6-bef0-347baad65804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535296488 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.535296488
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1935454114
Short name T329
Test name
Test status
Simulation time 634761801 ps
CPU time 16.18 seconds
Started Jul 10 05:48:27 PM PDT 24
Finished Jul 10 05:48:44 PM PDT 24
Peak memory 209552 kb
Host smart-3ce22e40-81dd-481b-83b6-3b95ccf0c2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935454114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1935454114
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.4008195954
Short name T503
Test name
Test status
Simulation time 37056044 ps
CPU time 2.2 seconds
Started Jul 10 05:48:27 PM PDT 24
Finished Jul 10 05:48:31 PM PDT 24
Peak memory 210232 kb
Host smart-50c51154-7cf5-4694-8bf9-2ec6d22fbcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008195954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.4008195954
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1740747738
Short name T603
Test name
Test status
Simulation time 42944089 ps
CPU time 0.8 seconds
Started Jul 10 05:48:33 PM PDT 24
Finished Jul 10 05:48:37 PM PDT 24
Peak memory 205984 kb
Host smart-053bc71f-6766-4f4f-9e28-5d23601451e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740747738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1740747738
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.4204274263
Short name T419
Test name
Test status
Simulation time 226138286 ps
CPU time 6.46 seconds
Started Jul 10 05:48:26 PM PDT 24
Finished Jul 10 05:48:34 PM PDT 24
Peak memory 214340 kb
Host smart-ba1c2287-a146-49bc-87c1-dbdd0b6b5dd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4204274263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.4204274263
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1563067307
Short name T76
Test name
Test status
Simulation time 280779362 ps
CPU time 2.51 seconds
Started Jul 10 05:48:27 PM PDT 24
Finished Jul 10 05:48:32 PM PDT 24
Peak memory 209320 kb
Host smart-fea5313b-efa6-474d-ab38-50113fe01bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563067307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1563067307
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2245901928
Short name T106
Test name
Test status
Simulation time 8052718298 ps
CPU time 46.26 seconds
Started Jul 10 05:48:29 PM PDT 24
Finished Jul 10 05:49:17 PM PDT 24
Peak memory 214416 kb
Host smart-b04b4542-618f-4e60-9cc4-693c5988d448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245901928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2245901928
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1896617490
Short name T315
Test name
Test status
Simulation time 434488958 ps
CPU time 5.39 seconds
Started Jul 10 05:48:28 PM PDT 24
Finished Jul 10 05:48:35 PM PDT 24
Peak memory 222520 kb
Host smart-09a4e30f-1e8b-469d-80d8-fde929be1182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896617490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1896617490
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2140399164
Short name T647
Test name
Test status
Simulation time 70934957 ps
CPU time 3.16 seconds
Started Jul 10 05:48:27 PM PDT 24
Finished Jul 10 05:48:32 PM PDT 24
Peak memory 209452 kb
Host smart-59c9ed0f-07f2-4d8c-b71e-dd4f8eb3eab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140399164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2140399164
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3136155291
Short name T518
Test name
Test status
Simulation time 64202199 ps
CPU time 3.49 seconds
Started Jul 10 05:48:27 PM PDT 24
Finished Jul 10 05:48:33 PM PDT 24
Peak memory 207044 kb
Host smart-efa3ccfb-a125-4762-b9a5-b74bcdfcbafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136155291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3136155291
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.559480015
Short name T748
Test name
Test status
Simulation time 49168164 ps
CPU time 2.61 seconds
Started Jul 10 05:48:27 PM PDT 24
Finished Jul 10 05:48:32 PM PDT 24
Peak memory 206916 kb
Host smart-de62f5fa-5ff1-4ded-a3c4-30ef4b61f735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559480015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.559480015
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.312563012
Short name T893
Test name
Test status
Simulation time 222657668 ps
CPU time 6.81 seconds
Started Jul 10 05:48:26 PM PDT 24
Finished Jul 10 05:48:34 PM PDT 24
Peak memory 209032 kb
Host smart-17c87f32-c068-4aa2-9629-1551830f5ed4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312563012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.312563012
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2494835278
Short name T713
Test name
Test status
Simulation time 434369489 ps
CPU time 5.58 seconds
Started Jul 10 05:48:30 PM PDT 24
Finished Jul 10 05:48:37 PM PDT 24
Peak memory 208136 kb
Host smart-4acde739-c88e-4edd-86a6-c46e3b31b97d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494835278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2494835278
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.4077631895
Short name T482
Test name
Test status
Simulation time 1582630051 ps
CPU time 47.72 seconds
Started Jul 10 05:48:27 PM PDT 24
Finished Jul 10 05:49:16 PM PDT 24
Peak memory 208444 kb
Host smart-ab7faaa8-c578-49d3-887d-86b89ad7f299
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077631895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.4077631895
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3707319641
Short name T609
Test name
Test status
Simulation time 1298807639 ps
CPU time 3.42 seconds
Started Jul 10 05:48:25 PM PDT 24
Finished Jul 10 05:48:30 PM PDT 24
Peak memory 218352 kb
Host smart-7c80658c-6920-456b-bc75-9fec058522ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707319641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3707319641
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2718063479
Short name T464
Test name
Test status
Simulation time 199938814 ps
CPU time 2.62 seconds
Started Jul 10 05:48:27 PM PDT 24
Finished Jul 10 05:48:31 PM PDT 24
Peak memory 206848 kb
Host smart-50c87f9b-c150-4e40-8a2a-e6fad6dfe8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718063479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2718063479
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1005718554
Short name T82
Test name
Test status
Simulation time 2290313887 ps
CPU time 46.82 seconds
Started Jul 10 05:48:31 PM PDT 24
Finished Jul 10 05:49:20 PM PDT 24
Peak memory 222552 kb
Host smart-18ebe9bc-a58d-4b10-b842-e99357b1781a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005718554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1005718554
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3057485117
Short name T777
Test name
Test status
Simulation time 578011386 ps
CPU time 5.61 seconds
Started Jul 10 05:48:27 PM PDT 24
Finished Jul 10 05:48:35 PM PDT 24
Peak memory 218408 kb
Host smart-f61befd8-187c-495a-8eb3-e0579329f6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057485117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3057485117
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2120221360
Short name T398
Test name
Test status
Simulation time 324543370 ps
CPU time 1.86 seconds
Started Jul 10 05:48:25 PM PDT 24
Finished Jul 10 05:48:28 PM PDT 24
Peak memory 210300 kb
Host smart-9c04b7b2-0f0f-4b50-b86b-a1eaa353090f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120221360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2120221360
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.83381023
Short name T549
Test name
Test status
Simulation time 29004943 ps
CPU time 0.75 seconds
Started Jul 10 05:48:33 PM PDT 24
Finished Jul 10 05:48:36 PM PDT 24
Peak memory 205932 kb
Host smart-70d479bf-0fd9-4bf7-834e-b6acbaa2a05f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83381023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.83381023
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.834833241
Short name T867
Test name
Test status
Simulation time 37511764 ps
CPU time 3.27 seconds
Started Jul 10 05:48:33 PM PDT 24
Finished Jul 10 05:48:38 PM PDT 24
Peak memory 214364 kb
Host smart-c01ea371-1406-4620-8348-fb3989f8f551
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=834833241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.834833241
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1796269020
Short name T735
Test name
Test status
Simulation time 437250934 ps
CPU time 10.7 seconds
Started Jul 10 05:48:32 PM PDT 24
Finished Jul 10 05:48:45 PM PDT 24
Peak memory 218160 kb
Host smart-a587d6c5-533e-44bd-90a3-1935a730211e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796269020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1796269020
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1700962723
Short name T599
Test name
Test status
Simulation time 489917872 ps
CPU time 3.8 seconds
Started Jul 10 05:48:33 PM PDT 24
Finished Jul 10 05:48:40 PM PDT 24
Peak memory 215108 kb
Host smart-80de43ba-0ecd-4ddf-9b11-8f6788a8ea34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700962723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1700962723
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3340290207
Short name T484
Test name
Test status
Simulation time 92177110 ps
CPU time 2.16 seconds
Started Jul 10 05:48:36 PM PDT 24
Finished Jul 10 05:48:40 PM PDT 24
Peak memory 216116 kb
Host smart-fea5dbab-7f9c-4eef-9034-3bb05aa2f53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340290207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3340290207
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.4052578173
Short name T912
Test name
Test status
Simulation time 1832069214 ps
CPU time 32.72 seconds
Started Jul 10 05:48:31 PM PDT 24
Finished Jul 10 05:49:06 PM PDT 24
Peak memory 208968 kb
Host smart-ca4a295a-b0a7-4426-92cc-b1da01c1a43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052578173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.4052578173
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.659887868
Short name T840
Test name
Test status
Simulation time 602963101 ps
CPU time 4.93 seconds
Started Jul 10 05:48:33 PM PDT 24
Finished Jul 10 05:48:40 PM PDT 24
Peak memory 208600 kb
Host smart-f1111719-ef08-439c-b1b0-0a40ae78441b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659887868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.659887868
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2632584475
Short name T889
Test name
Test status
Simulation time 279610745 ps
CPU time 6.57 seconds
Started Jul 10 05:48:34 PM PDT 24
Finished Jul 10 05:48:43 PM PDT 24
Peak memory 208528 kb
Host smart-eaca6399-dc68-4401-84c0-636d8326589e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632584475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2632584475
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1398210432
Short name T249
Test name
Test status
Simulation time 183579318 ps
CPU time 2.67 seconds
Started Jul 10 05:48:35 PM PDT 24
Finished Jul 10 05:48:40 PM PDT 24
Peak memory 207012 kb
Host smart-ac04c362-86ac-40fe-8eff-eb00221521a7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398210432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1398210432
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.96547770
Short name T601
Test name
Test status
Simulation time 833802539 ps
CPU time 6.37 seconds
Started Jul 10 05:48:33 PM PDT 24
Finished Jul 10 05:48:41 PM PDT 24
Peak memory 208128 kb
Host smart-e433f5ec-bf12-41e2-9f58-117a167764e9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96547770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.96547770
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.4204684623
Short name T510
Test name
Test status
Simulation time 176603970 ps
CPU time 2.3 seconds
Started Jul 10 05:48:35 PM PDT 24
Finished Jul 10 05:48:39 PM PDT 24
Peak memory 207152 kb
Host smart-78636c5e-d0e1-42d5-9836-e82df608d20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204684623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4204684623
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1897256194
Short name T775
Test name
Test status
Simulation time 423517605 ps
CPU time 3.27 seconds
Started Jul 10 05:48:35 PM PDT 24
Finished Jul 10 05:48:40 PM PDT 24
Peak memory 207200 kb
Host smart-b2a138c1-e8c0-4ddb-8665-47e8bd63152c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897256194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1897256194
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3137428803
Short name T84
Test name
Test status
Simulation time 8789083686 ps
CPU time 54.73 seconds
Started Jul 10 05:48:31 PM PDT 24
Finished Jul 10 05:49:28 PM PDT 24
Peak memory 216360 kb
Host smart-629d9262-f2bb-4c3b-9d98-e3fb0c728e10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137428803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3137428803
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3101132401
Short name T783
Test name
Test status
Simulation time 385240757 ps
CPU time 5.18 seconds
Started Jul 10 05:48:32 PM PDT 24
Finished Jul 10 05:48:39 PM PDT 24
Peak memory 209408 kb
Host smart-b0c5c354-c73f-49d9-85ee-14773cee8bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101132401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3101132401
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2905541201
Short name T47
Test name
Test status
Simulation time 243046294 ps
CPU time 5.64 seconds
Started Jul 10 05:48:31 PM PDT 24
Finished Jul 10 05:48:39 PM PDT 24
Peak memory 210436 kb
Host smart-0a79d300-b910-4678-b0bf-80bb7d933f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905541201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2905541201
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2899544547
Short name T435
Test name
Test status
Simulation time 11841048 ps
CPU time 0.73 seconds
Started Jul 10 05:48:40 PM PDT 24
Finished Jul 10 05:48:43 PM PDT 24
Peak memory 205904 kb
Host smart-433230b4-3cd8-4516-86ad-bcb16f6109a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899544547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2899544547
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2157391617
Short name T75
Test name
Test status
Simulation time 168232876 ps
CPU time 2.6 seconds
Started Jul 10 05:48:33 PM PDT 24
Finished Jul 10 05:48:38 PM PDT 24
Peak memory 207768 kb
Host smart-7f4bf991-fee7-4bd6-b1a6-25b631f8a64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157391617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2157391617
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.4284297384
Short name T634
Test name
Test status
Simulation time 35797645 ps
CPU time 2.69 seconds
Started Jul 10 05:48:32 PM PDT 24
Finished Jul 10 05:48:37 PM PDT 24
Peak memory 214356 kb
Host smart-d38fb96a-9914-41f2-858c-0173291ebbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284297384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.4284297384
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1397242598
Short name T28
Test name
Test status
Simulation time 268855083 ps
CPU time 4.33 seconds
Started Jul 10 05:48:32 PM PDT 24
Finished Jul 10 05:48:39 PM PDT 24
Peak memory 222536 kb
Host smart-b8c7a8c1-389a-4bb6-a1d1-d9c8cc1cfaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397242598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1397242598
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.4042993700
Short name T847
Test name
Test status
Simulation time 206163608 ps
CPU time 4.39 seconds
Started Jul 10 05:48:35 PM PDT 24
Finished Jul 10 05:48:41 PM PDT 24
Peak memory 209680 kb
Host smart-90b96246-4be2-4185-8470-a0e691de9b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042993700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.4042993700
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3336856097
Short name T655
Test name
Test status
Simulation time 1092840415 ps
CPU time 41.33 seconds
Started Jul 10 05:48:32 PM PDT 24
Finished Jul 10 05:49:15 PM PDT 24
Peak memory 209040 kb
Host smart-95ddd980-cc56-4033-921d-6c82559db087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336856097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3336856097
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.909056457
Short name T381
Test name
Test status
Simulation time 21545162 ps
CPU time 1.88 seconds
Started Jul 10 05:48:32 PM PDT 24
Finished Jul 10 05:48:36 PM PDT 24
Peak memory 206956 kb
Host smart-60777d5b-0a50-4bb9-98d0-0c010511c925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909056457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.909056457
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.4223081186
Short name T848
Test name
Test status
Simulation time 55945062 ps
CPU time 2.58 seconds
Started Jul 10 05:48:33 PM PDT 24
Finished Jul 10 05:48:38 PM PDT 24
Peak memory 207212 kb
Host smart-03d59e43-ec11-4d71-bd74-fa17d62e400a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223081186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.4223081186
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3551278399
Short name T451
Test name
Test status
Simulation time 133123928 ps
CPU time 3.8 seconds
Started Jul 10 05:48:33 PM PDT 24
Finished Jul 10 05:48:39 PM PDT 24
Peak memory 208124 kb
Host smart-b3bb6ecc-4731-4bb3-b7ec-83feb96ba8b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551278399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3551278399
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2640350507
Short name T345
Test name
Test status
Simulation time 307973647 ps
CPU time 3.63 seconds
Started Jul 10 05:48:32 PM PDT 24
Finished Jul 10 05:48:39 PM PDT 24
Peak memory 209040 kb
Host smart-b0c09f2f-fac5-4958-88d3-e57aa94407bc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640350507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2640350507
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1588579656
Short name T525
Test name
Test status
Simulation time 70419095 ps
CPU time 2.72 seconds
Started Jul 10 05:48:34 PM PDT 24
Finished Jul 10 05:48:39 PM PDT 24
Peak memory 215556 kb
Host smart-6b58c0c0-01e3-47f8-8230-08e8197a1b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588579656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1588579656
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3059617476
Short name T844
Test name
Test status
Simulation time 151285429 ps
CPU time 4.28 seconds
Started Jul 10 05:48:35 PM PDT 24
Finished Jul 10 05:48:41 PM PDT 24
Peak memory 207272 kb
Host smart-7383520c-b01e-4053-843b-fad9c56a689d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059617476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3059617476
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.823685105
Short name T565
Test name
Test status
Simulation time 163312774 ps
CPU time 8.84 seconds
Started Jul 10 05:48:37 PM PDT 24
Finished Jul 10 05:48:48 PM PDT 24
Peak memory 220472 kb
Host smart-d7e11967-31aa-4a8d-88f4-5202be7d33ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823685105 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.823685105
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2145027198
Short name T542
Test name
Test status
Simulation time 281783310 ps
CPU time 3.96 seconds
Started Jul 10 05:48:32 PM PDT 24
Finished Jul 10 05:48:38 PM PDT 24
Peak memory 207084 kb
Host smart-fccd7e02-82f9-4855-be0c-916562e0b122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145027198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2145027198
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.4100256067
Short name T612
Test name
Test status
Simulation time 96271728 ps
CPU time 3.46 seconds
Started Jul 10 05:48:32 PM PDT 24
Finished Jul 10 05:48:38 PM PDT 24
Peak memory 210956 kb
Host smart-74482e3b-63de-43c0-8bce-4f19ee4f0310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100256067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.4100256067
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.334930580
Short name T728
Test name
Test status
Simulation time 14235080 ps
CPU time 0.78 seconds
Started Jul 10 05:48:39 PM PDT 24
Finished Jul 10 05:48:42 PM PDT 24
Peak memory 205904 kb
Host smart-a0357a12-c2c4-46d9-873c-57e7596437c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334930580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.334930580
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1485169065
Short name T290
Test name
Test status
Simulation time 60280431 ps
CPU time 4.17 seconds
Started Jul 10 05:48:38 PM PDT 24
Finished Jul 10 05:48:45 PM PDT 24
Peak memory 214244 kb
Host smart-f8fa2534-95d9-459f-900c-b599f1f7d743
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485169065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1485169065
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.545770148
Short name T627
Test name
Test status
Simulation time 169796587 ps
CPU time 3.98 seconds
Started Jul 10 05:48:39 PM PDT 24
Finished Jul 10 05:48:45 PM PDT 24
Peak memory 209312 kb
Host smart-fcee9757-68e8-43e3-8e3c-b0536f1b0cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545770148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.545770148
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2753609786
Short name T97
Test name
Test status
Simulation time 61791754 ps
CPU time 2.52 seconds
Started Jul 10 05:48:40 PM PDT 24
Finished Jul 10 05:48:44 PM PDT 24
Peak memory 214340 kb
Host smart-756428da-9959-494e-bb8a-07adfd7a9283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753609786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2753609786
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.641755772
Short name T786
Test name
Test status
Simulation time 289309320 ps
CPU time 8.34 seconds
Started Jul 10 05:48:40 PM PDT 24
Finished Jul 10 05:48:50 PM PDT 24
Peak memory 214256 kb
Host smart-39e8ab1e-8d5b-48bf-a960-63e8581ba39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641755772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.641755772
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2861774447
Short name T553
Test name
Test status
Simulation time 282083318 ps
CPU time 4.87 seconds
Started Jul 10 05:48:38 PM PDT 24
Finished Jul 10 05:48:44 PM PDT 24
Peak memory 222584 kb
Host smart-e2164d6b-129a-4b84-a680-a87fc63bb58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861774447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2861774447
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1171851474
Short name T325
Test name
Test status
Simulation time 117379598 ps
CPU time 4.27 seconds
Started Jul 10 05:48:36 PM PDT 24
Finished Jul 10 05:48:42 PM PDT 24
Peak memory 209948 kb
Host smart-3ed9b593-5d54-4940-ae16-6b1f60e9edb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171851474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1171851474
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1465123605
Short name T36
Test name
Test status
Simulation time 623911246 ps
CPU time 5.55 seconds
Started Jul 10 05:48:37 PM PDT 24
Finished Jul 10 05:48:44 PM PDT 24
Peak memory 208468 kb
Host smart-16be69c9-6d71-45fb-ac18-9318ad508055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465123605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1465123605
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3738159079
Short name T649
Test name
Test status
Simulation time 649258834 ps
CPU time 3.28 seconds
Started Jul 10 05:48:35 PM PDT 24
Finished Jul 10 05:48:41 PM PDT 24
Peak memory 208728 kb
Host smart-f367476a-4e3c-4eca-8069-2b9c440f6651
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738159079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3738159079
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3012653322
Short name T114
Test name
Test status
Simulation time 493885427 ps
CPU time 3.71 seconds
Started Jul 10 05:48:40 PM PDT 24
Finished Jul 10 05:48:45 PM PDT 24
Peak memory 206956 kb
Host smart-3e76548a-a139-4650-b056-ff4345179ed4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012653322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3012653322
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2460478957
Short name T492
Test name
Test status
Simulation time 148844976 ps
CPU time 3.11 seconds
Started Jul 10 05:48:37 PM PDT 24
Finished Jul 10 05:48:41 PM PDT 24
Peak memory 206872 kb
Host smart-db26d2ce-6d07-47ea-ad3d-c58824aead89
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460478957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2460478957
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3813997341
Short name T900
Test name
Test status
Simulation time 399007533 ps
CPU time 2.51 seconds
Started Jul 10 05:48:40 PM PDT 24
Finished Jul 10 05:48:45 PM PDT 24
Peak memory 216068 kb
Host smart-f98cb3d7-a01a-47e1-97bf-10f46e87fade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813997341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3813997341
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1315774405
Short name T689
Test name
Test status
Simulation time 64877718 ps
CPU time 2.73 seconds
Started Jul 10 05:48:37 PM PDT 24
Finished Jul 10 05:48:42 PM PDT 24
Peak memory 208360 kb
Host smart-3e6a7053-b5eb-4ca5-af5e-1d9817c34a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315774405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1315774405
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2019168015
Short name T202
Test name
Test status
Simulation time 253243076 ps
CPU time 9.81 seconds
Started Jul 10 05:48:38 PM PDT 24
Finished Jul 10 05:48:50 PM PDT 24
Peak memory 215248 kb
Host smart-36d97721-100c-42a1-a3db-51e7f9b3dea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019168015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2019168015
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1119333245
Short name T835
Test name
Test status
Simulation time 75003568 ps
CPU time 3.55 seconds
Started Jul 10 05:48:37 PM PDT 24
Finished Jul 10 05:48:42 PM PDT 24
Peak memory 214364 kb
Host smart-e9db70cb-6f7d-4ebd-82d8-04e772ea50ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119333245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1119333245
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2069246277
Short name T401
Test name
Test status
Simulation time 92936339 ps
CPU time 1.52 seconds
Started Jul 10 05:48:37 PM PDT 24
Finished Jul 10 05:48:40 PM PDT 24
Peak memory 209860 kb
Host smart-f8e201c6-0ec4-45ac-ae08-da2aa3ae96c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069246277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2069246277
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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