Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	17	32	65.31

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	16	19	54.29	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	63	1			T30	1		T32	1		T45	2
auto[OpGenId]	10	1			T70	1		T223	1		T60	1
auto[OpGenSwOut]	22	1			T55	1		T45	1		T57	1
auto[OpGenHwOut]	12	1			T3	1		T4	1		T5	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1642	1			T30	3		T54	1		T55	4
auto[StInit]	84	1			T3	1		T30	1		T32	1
auto[StCreatorRootKey]	57	1			T55	1		T45	3		T4	1
auto[StOwnerIntKey]	42	1			T31	1		T54	1		T62	1
auto[StOwnerKey]	47	1			T30	1		T39	1		T45	1
auto[StDisabled]	529	1			T30	10		T54	1		T21	1
auto[StInvalid]	50	1			T29	1		T37	1		T38	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3433

1

T1

1

T2

1

T3

1

auto[1]

107

1

T3

1

T30

1

T32

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1632	1			T30	3		T54	1		T55	4
auto[StReset]	auto[1]	10	1			T51	1		T127	1		T52	1
auto[StInit]	auto[0]	38	1			T54	2		T56	1		T33	1
auto[StInit]	auto[1]	46	1			T3	1		T30	1		T32	1
auto[StCreatorRootKey]	auto[0]	40	1			T55	1		T45	1		T59	1
auto[StCreatorRootKey]	auto[1]	17	1			T45	2		T4	1		T150	1
auto[StOwnerIntKey]	auto[0]	30	1			T31	1		T54	1		T62	1
auto[StOwnerIntKey]	auto[1]	12	1			T65	1		T66	1		T224	1
auto[StOwnerKey]	auto[0]	37	1			T30	1		T39	1		T69	1
auto[StOwnerKey]	auto[1]	10	1			T45	1		T70	1		T223	1
auto[StDisabled]	auto[0]	517	1			T30	10		T54	1		T21	1
auto[StDisabled]	auto[1]	12	1			T55	1		T5	1		T225	1
auto[StInvalid]	auto[0]	50	1			T29	1		T37	1		T38	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	16	19	54.29	16

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	3
[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[StCreatorRootKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StDisabled]]	[auto[OpGenId]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	9	1			T51	1		T127	1		T52	1
auto[StReset]	auto[OpGenId]	1	1			T226	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	24	1			T30	1		T32	1		T46	1
auto[StInit]	auto[OpGenId]	3	1			T227	1		T228	1		T229	1
auto[StInit]	auto[OpGenSwOut]	15	1			T57	1		T147	1		T7	1
auto[StInit]	auto[OpGenHwOut]	4	1			T3	1		T152	1		T230	1
auto[StCreatorRootKey]	auto[OpAdvance]	12	1			T45	2		T150	1		T231	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T60	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenHwOut]	4	1			T4	1		T6	1		T232	1
auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T65	1		T66	1		T224	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T233	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T234	1		T235	1		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	1	1			T236	1		-	-		-	-
auto[StOwnerKey]	auto[OpAdvance]	4	1			T237	1		T34	1		T238	1
auto[StOwnerKey]	auto[OpGenId]	4	1			T70	1		T223	1		T239	1
auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T45	1		T240	1		-	-
auto[StDisabled]	auto[OpAdvance]	6	1			T225	1		T241	1		T242	1
auto[StDisabled]	auto[OpGenSwOut]	3	1			T55	1		T243	1		T244	1
auto[StDisabled]	auto[OpGenHwOut]	3	1			T5	1		T245	1		T235	1