Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11779

1

T1

6

T2

4

T3

12

auto[Attestation]

8367

1

T1

5

T2

4

T3

2

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2936	1			T1	3		T3	4		T14	6
auto[Aes]	3667	1			T1	3		T2	3		T3	2
auto[Kmac]	3484	1			T1	1		T2	1		T3	4
auto[Otbn]	3563	1			T1	1		T2	1		T3	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8141	1			T1	4		T2	8		T3	1
auto[OpGenId]	6496	1			T1	3		T2	3		T3	3
auto[OpGenSwOut]	6368	1			T1	3		T2	4		T3	6
auto[OpGenHwOut]	7282	1			T1	5		T2	1		T3	5
auto[OpDisable]	158	1			T1	1		T16	1		T47	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11323

1

T1

10

T2

8

T3

1

auto[OpDoneFail]

17122

1

T1

6

T2

8

T3

14

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6954	1			T1	1		T2	1		T3	10
auto[StInit]	4044	1			T1	4		T2	2		T3	5
auto[StCreatorRootKey]	3391	1			T1	5		T2	2		T13	2
auto[StOwnerIntKey]	2935	1			T1	3		T2	2		T13	2
auto[StOwnerKey]	2649	1			T2	2		T13	2		T14	4
auto[StDisabled]	8472	1			T1	3		T2	7		T13	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	359	1			T3	2		T14	2		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	113	1			T30	2		T54	2		T55	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	89	1			T61	1		T209	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	81	1			T30	2		T4	1		T78	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	77	1			T14	1		T45	2		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	221	1			T20	2		T30	3		T210	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	361	1			T14	1		T17	1		T29	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	110	1			T3	1		T20	1		T210	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	88	1			T1	1		T18	1		T89	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	79	1			T15	1		T61	1		T30	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	73	1			T30	1		T211	1		T212	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	241	1			T2	1		T13	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	327	1			T3	1		T14	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	103	1			T18	1		T30	2		T122	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	72	1			T20	1		T47	1		T128	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	64	1			T21	1		T4	2		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	79	1			T89	1		T30	2		T68	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	241	1			T2	1		T14	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	347	1			T3	1		T14	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	103	1			T15	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	91	1			T13	1		T31	1		T121	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	80	1			T211	1		T84	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	70	1			T30	1		T21	1		T213	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	222	1			T17	1		T89	1		T30	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	81	1			T37	1		T30	1		T55	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	104	1			T47	1		T30	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	95	1			T1	1		T15	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	81	1			T18	1		T62	1		T144	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	70	1			T89	1		T4	2		T78	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	232	1			T14	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	112	1			T30	2		T55	3		T45	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	128	1			T30	2		T121	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	92	1			T1	1		T15	1		T128	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	64	1			T15	1		T17	1		T128	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	75	1			T17	1		T20	1		T30	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	217	1			T2	1		T15	2		T20	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	91	1			T30	3		T55	2		T4	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	108	1			T3	1		T39	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	80	1			T17	1		T47	1		T89	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	86	1			T13	1		T15	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	66	1			T20	1		T30	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	224	1			T18	1		T61	1		T89	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	96	1			T30	4		T55	3		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	118	1			T37	1		T31	1		T30	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	81	1			T30	1		T45	3		T145	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T18	1		T89	1		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	74	1			T15	1		T30	1		T214	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	237	1			T2	1		T15	2		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	282	1			T3	1		T18	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	88	1			T20	1		T30	1		T122	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	77	1			T16	1		T128	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	59	1			T30	1		T124	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	63	1			T30	1		T122	1		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	183	1			T1	1		T30	2		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	489	1			T3	1		T29	1		T128	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	136	1			T18	1		T61	1		T90	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	122	1			T14	1		T19	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	99	1			T19	1		T30	1		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	80	1			T2	1		T15	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	320	1			T19	2		T30	3		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	465	1			T3	2		T20	1		T29	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	120	1			T1	1		T18	1		T31	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	111	1			T14	1		T16	2		T30	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	105	1			T61	1		T216	1		T144	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	94	1			T20	1		T30	1		T217	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	282	1			T20	2		T47	1		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	447	1			T29	4		T128	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	139	1			T15	2		T20	1		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T29	1		T30	1		T218	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	114	1			T128	1		T215	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	81	1			T120	1		T78	1		T219	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	293	1			T1	1		T13	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	67	1			T30	3		T4	4		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	103	1			T1	1		T3	1		T128	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	86	1			T14	1		T68	1		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	77	1			T20	1		T45	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	61	1			T21	1		T55	1		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	187	1			T14	1		T15	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	77	1			T37	3		T30	5		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	130	1			T19	1		T128	2		T89	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	108	1			T15	2		T90	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	76	1			T1	1		T14	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	97	1			T14	1		T15	1		T89	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	293	1			T19	2		T90	4		T30	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	67	1			T37	1		T4	4		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	111	1			T30	2		T39	1		T210	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	108	1			T61	1		T30	1		T122	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	95	1			T14	1		T30	1		T209	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	86	1			T210	1		T216	1		T220	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	299	1			T18	1		T30	3		T209	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	68	1			T37	1		T30	5		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	127	1			T15	1		T18	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	120	1			T54	1		T120	1		T221	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	86	1			T14	1		T128	1		T30	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	103	1			T30	1		T219	1		T222	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	288	1			T15	1		T18	1		T89	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	227	1			T14	1		T61	1		T30	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	713	1			T3	2		T14	2		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	229	1			T1	1		T15	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	723	1			T2	1		T3	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	193	1			T20	1		T47	1		T128	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	693	1			T2	1		T3	1		T14	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	219	1			T13	1		T31	1		T30	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	694	1			T3	1		T14	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	230	1			T1	1		T15	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	433	1			T14	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	217	1			T1	1		T15	2		T17	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	471	1			T2	1		T15	2		T20	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	222	1			T13	1		T15	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	433	1			T3	1		T18	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	205	1			T15	1		T18	1		T89	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	466	1			T2	1		T15	2		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	180	1			T16	1		T128	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	572	1			T1	1		T3	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	283	1			T2	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	963	1			T3	1		T18	1		T19	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	298	1			T14	1		T16	2		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	879	1			T1	1		T3	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	284	1			T128	1		T30	1		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	903	1			T1	1		T13	1		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	197	1			T14	1		T20	1		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	384	1			T1	1		T3	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	271	1			T1	1		T14	1		T15	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	510	1			T14	1		T19	3		T128	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	279	1			T61	1		T30	2		T210	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	487	1			T14	1		T18	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	291	1			T14	1		T128	1		T30	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	501	1			T15	2		T18	2		T29	1