Unified Coverage Report :: Group Instance : salt_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3073

1

T1

2

T14

5

T15

5

auto[1]

259

1

T20

13

T110

2

T144

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	117	1			T209	1		T54	1		T68	1
auto[134217728:268435455]	106	1			T29	1		T37	1		T31	1
auto[268435456:402653183]	106	1			T14	1		T20	1		T29	1
auto[402653184:536870911]	98	1			T31	1		T54	1		T38	1
auto[536870912:671088639]	102	1			T20	3		T30	1		T32	1
auto[671088640:805306367]	107	1			T16	1		T20	1		T29	1
auto[805306368:939524095]	119	1			T29	1		T54	1		T68	1
auto[939524096:1073741823]	110	1			T29	1		T37	1		T30	1
auto[1073741824:1207959551]	106	1			T37	1		T89	1		T30	1
auto[1207959552:1342177279]	102	1			T37	1		T122	1		T21	1
auto[1342177280:1476395007]	89	1			T29	1		T47	1		T30	1
auto[1476395008:1610612735]	118	1			T30	1		T218	1		T33	1
auto[1610612736:1744830463]	100	1			T15	1		T20	1		T30	3
auto[1744830464:1879048191]	115	1			T1	1		T37	1		T30	2
auto[1879048192:2013265919]	104	1			T14	2		T89	1		T32	1
auto[2013265920:2147483647]	99	1			T89	1		T32	1		T210	2
auto[2147483648:2281701375]	99	1			T210	1		T55	1		T4	1
auto[2281701376:2415919103]	105	1			T18	1		T20	1		T61	1
auto[2415919104:2550136831]	100	1			T15	1		T30	3		T38	1
auto[2550136832:2684354559]	98	1			T16	1		T18	1		T20	1
auto[2684354560:2818572287]	112	1			T32	1		T209	1		T122	1
auto[2818572288:2952790015]	102	1			T18	1		T20	1		T30	1
auto[2952790016:3087007743]	106	1			T20	1		T30	2		T68	1
auto[3087007744:3221225471]	100	1			T15	1		T20	1		T29	1
auto[3221225472:3355443199]	113	1			T20	1		T29	1		T37	1
auto[3355443200:3489660927]	90	1			T20	3		T38	1		T144	2
auto[3489660928:3623878655]	106	1			T14	1		T15	1		T18	1
auto[3623878656:3758096383]	104	1			T1	1		T20	1		T29	1
auto[3758096384:3892314111]	93	1			T29	1		T128	1		T209	1
auto[3892314112:4026531839]	97	1			T29	1		T30	1		T54	1
auto[4026531840:4160749567]	105	1			T20	2		T61	2		T58	1
auto[4160749568:4294967295]	104	1			T14	1		T15	1		T89	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	110	1			T209	1		T54	1		T68	1
auto[0:134217727]	auto[1]	7	1			T416	1		T255	1		T326	1
auto[134217728:268435455]	auto[0]	96	1			T29	1		T37	1		T31	1
auto[134217728:268435455]	auto[1]	10	1			T246	2		T324	2		T136	1
auto[268435456:402653183]	auto[0]	97	1			T14	1		T29	1		T128	1
auto[268435456:402653183]	auto[1]	9	1			T20	1		T144	1		T146	1
auto[402653184:536870911]	auto[0]	91	1			T31	1		T54	1		T38	1
auto[402653184:536870911]	auto[1]	7	1			T273	1		T136	2		T330	2
auto[536870912:671088639]	auto[0]	92	1			T20	1		T30	1		T32	1
auto[536870912:671088639]	auto[1]	10	1			T20	2		T136	1		T247	1
auto[671088640:805306367]	auto[0]	100	1			T16	1		T29	1		T89	1
auto[671088640:805306367]	auto[1]	7	1			T20	1		T412	2		T409	1
auto[805306368:939524095]	auto[0]	112	1			T29	1		T54	1		T68	1
auto[805306368:939524095]	auto[1]	7	1			T273	1		T136	1		T330	1
auto[939524096:1073741823]	auto[0]	103	1			T29	1		T37	1		T30	1
auto[939524096:1073741823]	auto[1]	7	1			T135	1		T247	1		T365	1
auto[1073741824:1207959551]	auto[0]	97	1			T37	1		T89	1		T30	1
auto[1073741824:1207959551]	auto[1]	9	1			T145	1		T330	1		T408	1
auto[1207959552:1342177279]	auto[0]	96	1			T37	1		T122	1		T21	1
auto[1207959552:1342177279]	auto[1]	6	1			T264	1		T247	1		T410	1
auto[1342177280:1476395007]	auto[0]	83	1			T29	1		T47	1		T30	1
auto[1342177280:1476395007]	auto[1]	6	1			T246	1		T330	1		T247	1
auto[1476395008:1610612735]	auto[0]	104	1			T30	1		T218	1		T33	1
auto[1476395008:1610612735]	auto[1]	14	1			T144	1		T129	2		T132	1
auto[1610612736:1744830463]	auto[0]	92	1			T15	1		T30	3		T55	1
auto[1610612736:1744830463]	auto[1]	8	1			T20	1		T135	1		T409	1
auto[1744830464:1879048191]	auto[0]	108	1			T1	1		T37	1		T30	2
auto[1744830464:1879048191]	auto[1]	7	1			T144	1		T422	1		T287	1
auto[1879048192:2013265919]	auto[0]	99	1			T14	2		T89	1		T32	1
auto[1879048192:2013265919]	auto[1]	5	1			T136	1		T330	1		T412	1
auto[2013265920:2147483647]	auto[0]	91	1			T89	1		T32	1		T210	2
auto[2013265920:2147483647]	auto[1]	8	1			T246	2		T330	1		T408	1
auto[2147483648:2281701375]	auto[0]	87	1			T210	1		T55	1		T4	1
auto[2147483648:2281701375]	auto[1]	12	1			T146	1		T264	1		T330	1
auto[2281701376:2415919103]	auto[0]	97	1			T18	1		T20	1		T61	1
auto[2281701376:2415919103]	auto[1]	8	1			T146	1		T136	2		T255	1
auto[2415919104:2550136831]	auto[0]	98	1			T15	1		T30	3		T38	1
auto[2415919104:2550136831]	auto[1]	2	1			T273	1		T428	1		-	-
auto[2550136832:2684354559]	auto[0]	85	1			T16	1		T18	1		T29	1
auto[2550136832:2684354559]	auto[1]	13	1			T20	1		T146	2		T273	1
auto[2684354560:2818572287]	auto[0]	102	1			T32	1		T209	1		T122	1
auto[2684354560:2818572287]	auto[1]	10	1			T129	1		T408	1		T365	1
auto[2818572288:2952790015]	auto[0]	94	1			T18	1		T30	1		T215	1
auto[2818572288:2952790015]	auto[1]	8	1			T20	1		T144	1		T134	1
auto[2952790016:3087007743]	auto[0]	97	1			T30	2		T68	1		T21	1
auto[2952790016:3087007743]	auto[1]	9	1			T20	1		T110	1		T146	1
auto[3087007744:3221225471]	auto[0]	92	1			T15	1		T29	1		T32	1
auto[3087007744:3221225471]	auto[1]	8	1			T20	1		T146	1		T264	1
auto[3221225472:3355443199]	auto[0]	107	1			T29	1		T37	1		T30	1
auto[3221225472:3355443199]	auto[1]	6	1			T20	1		T409	1		T429	1
auto[3355443200:3489660927]	auto[0]	79	1			T20	2		T38	1		T144	1
auto[3355443200:3489660927]	auto[1]	11	1			T20	1		T144	1		T132	1
auto[3489660928:3623878655]	auto[0]	100	1			T14	1		T15	1		T18	1
auto[3489660928:3623878655]	auto[1]	6	1			T146	1		T273	1		T324	1
auto[3623878656:3758096383]	auto[0]	96	1			T1	1		T29	1		T128	1
auto[3623878656:3758096383]	auto[1]	8	1			T20	1		T324	1		T304	1
auto[3758096384:3892314111]	auto[0]	85	1			T29	1		T128	1		T209	1
auto[3758096384:3892314111]	auto[1]	8	1			T129	2		T146	1		T134	1
auto[3892314112:4026531839]	auto[0]	93	1			T29	1		T30	1		T54	1
auto[3892314112:4026531839]	auto[1]	4	1			T110	1		T410	1		T414	1
auto[4026531840:4160749567]	auto[0]	94	1			T20	1		T61	2		T58	1
auto[4026531840:4160749567]	auto[1]	11	1			T20	1		T144	1		T145	1
auto[4160749568:4294967295]	auto[0]	96	1			T14	1		T15	1		T89	1
auto[4160749568:4294967295]	auto[1]	8	1			T129	1		T136	1		T408	1