Unified Coverage Report :: Group Instance : sealing_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1662

1

T1

1

T14

2

T15

1

auto[1]

1850

1

T1

1

T3

1

T14

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	110	1			T4	1		T78	1		T130	1
auto[134217728:268435455]	127	1			T14	1		T15	1		T18	1
auto[268435456:402653183]	115	1			T1	1		T14	1		T37	3
auto[402653184:536870911]	122	1			T18	1		T30	3		T58	1
auto[536870912:671088639]	120	1			T29	2		T47	1		T61	1
auto[671088640:805306367]	128	1			T16	1		T30	1		T54	1
auto[805306368:939524095]	90	1			T37	2		T30	1		T215	1
auto[939524096:1073741823]	101	1			T30	2		T38	1		T33	1
auto[1073741824:1207959551]	118	1			T16	1		T20	1		T29	2
auto[1207959552:1342177279]	93	1			T37	1		T30	2		T122	1
auto[1342177280:1476395007]	95	1			T20	2		T30	1		T32	1
auto[1476395008:1610612735]	116	1			T29	2		T89	1		T32	1
auto[1610612736:1744830463]	95	1			T14	1		T89	1		T30	1
auto[1744830464:1879048191]	99	1			T210	1		T209	1		T54	1
auto[1879048192:2013265919]	99	1			T29	1		T37	1		T30	1
auto[2013265920:2147483647]	102	1			T30	1		T32	1		T38	1
auto[2147483648:2281701375]	116	1			T30	1		T38	1		T218	1
auto[2281701376:2415919103]	112	1			T30	2		T32	1		T54	3
auto[2415919104:2550136831]	115	1			T15	1		T29	1		T30	1
auto[2550136832:2684354559]	107	1			T89	1		T54	1		T218	1
auto[2684354560:2818572287]	111	1			T3	1		T18	1		T30	1
auto[2818572288:2952790015]	102	1			T20	1		T61	1		T89	2
auto[2952790016:3087007743]	110	1			T128	1		T89	1		T32	1
auto[3087007744:3221225471]	109	1			T1	1		T30	2		T54	2
auto[3221225472:3355443199]	102	1			T14	2		T89	1		T30	1
auto[3355443200:3489660927]	117	1			T29	1		T30	3		T58	1
auto[3489660928:3623878655]	112	1			T15	1		T55	1		T45	2
auto[3623878656:3758096383]	114	1			T31	1		T68	1		T144	1
auto[3758096384:3892314111]	110	1			T15	1		T18	1		T20	1
auto[3892314112:4026531839]	114	1			T15	1		T29	2		T61	1
auto[4026531840:4160749567]	115	1			T128	1		T30	1		T38	2
auto[4160749568:4294967295]	116	1			T30	1		T55	1		T43	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T4	1		T130	1		T50	1
auto[0:134217727]	auto[1]	59	1			T78	1		T403	1		T46	1
auto[134217728:268435455]	auto[0]	63	1			T18	1		T32	1		T4	1
auto[134217728:268435455]	auto[1]	64	1			T14	1		T15	1		T29	1
auto[268435456:402653183]	auto[0]	62	1			T37	2		T43	1		T4	1
auto[268435456:402653183]	auto[1]	53	1			T1	1		T14	1		T37	1
auto[402653184:536870911]	auto[0]	64	1			T18	1		T58	1		T78	1
auto[402653184:536870911]	auto[1]	58	1			T30	3		T78	2		T70	1
auto[536870912:671088639]	auto[0]	63	1			T29	2		T54	1		T55	1
auto[536870912:671088639]	auto[1]	57	1			T47	1		T61	1		T211	1
auto[671088640:805306367]	auto[0]	58	1			T68	2		T38	1		T21	1
auto[671088640:805306367]	auto[1]	70	1			T16	1		T30	1		T54	1
auto[805306368:939524095]	auto[0]	31	1			T37	2		T30	1		T45	1
auto[805306368:939524095]	auto[1]	59	1			T215	1		T122	1		T21	1
auto[939524096:1073741823]	auto[0]	42	1			T38	1		T33	1		T110	1
auto[939524096:1073741823]	auto[1]	59	1			T30	2		T55	1		T84	1
auto[1073741824:1207959551]	auto[0]	49	1			T20	1		T29	2		T30	1
auto[1073741824:1207959551]	auto[1]	69	1			T16	1		T128	1		T31	1
auto[1207959552:1342177279]	auto[0]	48	1			T37	1		T38	1		T297	1
auto[1207959552:1342177279]	auto[1]	45	1			T30	2		T122	1		T21	1
auto[1342177280:1476395007]	auto[0]	44	1			T20	2		T55	1		T45	2
auto[1342177280:1476395007]	auto[1]	51	1			T30	1		T32	1		T4	1
auto[1476395008:1610612735]	auto[0]	59	1			T29	2		T89	1		T32	1
auto[1476395008:1610612735]	auto[1]	57	1			T210	1		T55	1		T78	1
auto[1610612736:1744830463]	auto[0]	41	1			T14	1		T89	1		T78	1
auto[1610612736:1744830463]	auto[1]	54	1			T30	1		T210	1		T45	2
auto[1744830464:1879048191]	auto[0]	42	1			T210	1		T4	1		T251	1
auto[1744830464:1879048191]	auto[1]	57	1			T209	1		T54	1		T144	1
auto[1879048192:2013265919]	auto[0]	46	1			T29	1		T210	1		T297	1
auto[1879048192:2013265919]	auto[1]	53	1			T37	1		T30	1		T209	1
auto[2013265920:2147483647]	auto[0]	59	1			T30	1		T38	1		T48	1
auto[2013265920:2147483647]	auto[1]	43	1			T32	1		T21	1		T45	2
auto[2147483648:2281701375]	auto[0]	59	1			T30	1		T38	1		T218	1
auto[2147483648:2281701375]	auto[1]	57	1			T21	1		T144	1		T71	1
auto[2281701376:2415919103]	auto[0]	68	1			T30	2		T32	1		T68	1
auto[2281701376:2415919103]	auto[1]	44	1			T54	3		T68	1		T55	1
auto[2415919104:2550136831]	auto[0]	48	1			T15	1		T43	1		T4	1
auto[2415919104:2550136831]	auto[1]	67	1			T29	1		T30	1		T110	1
auto[2550136832:2684354559]	auto[0]	53	1			T54	1		T218	1		T222	1
auto[2550136832:2684354559]	auto[1]	54	1			T89	1		T84	1		T4	2
auto[2684354560:2818572287]	auto[0]	53	1			T30	1		T100	1		T50	1
auto[2684354560:2818572287]	auto[1]	58	1			T3	1		T18	1		T215	1
auto[2818572288:2952790015]	auto[0]	46	1			T57	1		T334	1		T71	1
auto[2818572288:2952790015]	auto[1]	56	1			T20	1		T61	1		T89	2
auto[2952790016:3087007743]	auto[0]	49	1			T32	1		T68	1		T4	3
auto[2952790016:3087007743]	auto[1]	61	1			T128	1		T89	1		T122	1
auto[3087007744:3221225471]	auto[0]	55	1			T1	1		T30	2		T218	1
auto[3087007744:3221225471]	auto[1]	54	1			T54	2		T122	1		T55	1
auto[3221225472:3355443199]	auto[0]	41	1			T14	1		T122	1		T38	1
auto[3221225472:3355443199]	auto[1]	61	1			T14	1		T89	1		T30	1
auto[3355443200:3489660927]	auto[0]	46	1			T29	1		T30	2		T58	1
auto[3355443200:3489660927]	auto[1]	71	1			T30	1		T84	1		T70	1
auto[3489660928:3623878655]	auto[0]	57	1			T55	1		T45	1		T26	1
auto[3489660928:3623878655]	auto[1]	55	1			T15	1		T45	1		T4	1
auto[3623878656:3758096383]	auto[0]	53	1			T219	1		T130	1		T46	1
auto[3623878656:3758096383]	auto[1]	61	1			T31	1		T68	1		T144	1
auto[3758096384:3892314111]	auto[0]	56	1			T18	1		T20	1		T30	1
auto[3758096384:3892314111]	auto[1]	54	1			T15	1		T55	2		T212	1
auto[3892314112:4026531839]	auto[0]	51	1			T209	1		T70	1		T100	1
auto[3892314112:4026531839]	auto[1]	63	1			T15	1		T29	2		T61	1
auto[4026531840:4160749567]	auto[0]	53	1			T30	1		T38	1		T70	1
auto[4026531840:4160749567]	auto[1]	62	1			T128	1		T38	1		T45	1
auto[4160749568:4294967295]	auto[0]	52	1			T30	1		T55	1		T43	1
auto[4160749568:4294967295]	auto[1]	64	1			T257	1		T297	1		T219	1