Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7304

1

T1

3

T14

17

T15

11

auto[1]

261

1

T20

11

T110

2

T144

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	3091	1			T1	1		T14	7		T15	5
auto[134217728:268435455]	170	1			T20	1		T128	1		T37	1
auto[268435456:402653183]	174	1			T14	1		T16	1		T29	1
auto[402653184:536870911]	159	1			T15	1		T209	1		T21	1
auto[536870912:671088639]	148	1			T14	1		T15	2		T37	1
auto[671088640:805306367]	151	1			T18	1		T29	1		T47	1
auto[805306368:939524095]	140	1			T20	1		T29	1		T61	1
auto[939524096:1073741823]	140	1			T18	1		T29	1		T128	1
auto[1073741824:1207959551]	152	1			T1	1		T37	2		T89	1
auto[1207959552:1342177279]	161	1			T20	2		T29	1		T37	2
auto[1342177280:1476395007]	138	1			T20	1		T89	1		T30	1
auto[1476395008:1610612735]	130	1			T29	1		T30	1		T210	1
auto[1610612736:1744830463]	147	1			T16	1		T37	1		T89	1
auto[1744830464:1879048191]	134	1			T14	1		T20	1		T61	1
auto[1879048192:2013265919]	138	1			T14	1		T32	1		T122	1
auto[2013265920:2147483647]	146	1			T14	1		T18	1		T122	1
auto[2147483648:2281701375]	131	1			T30	1		T55	1		T144	1
auto[2281701376:2415919103]	143	1			T14	1		T29	2		T30	3
auto[2415919104:2550136831]	147	1			T20	1		T29	2		T30	1
auto[2550136832:2684354559]	146	1			T20	1		T29	2		T30	1
auto[2684354560:2818572287]	132	1			T61	1		T30	1		T32	1
auto[2818572288:2952790015]	139	1			T89	1		T210	1		T55	1
auto[2952790016:3087007743]	161	1			T18	1		T29	1		T209	1
auto[3087007744:3221225471]	135	1			T15	1		T20	3		T29	1
auto[3221225472:3355443199]	133	1			T14	1		T18	1		T30	2
auto[3355443200:3489660927]	119	1			T15	1		T89	1		T30	1
auto[3489660928:3623878655]	136	1			T20	1		T61	1		T37	1
auto[3623878656:3758096383]	150	1			T14	2		T20	1		T30	1
auto[3758096384:3892314111]	146	1			T14	1		T15	1		T20	1
auto[3892314112:4026531839]	139	1			T20	2		T30	1		T32	1
auto[4026531840:4160749567]	141	1			T47	1		T30	1		T38	1
auto[4160749568:4294967295]	148	1			T1	1		T37	1		T210	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	3079	1			T1	1		T14	7		T15	5
auto[0:134217727]	auto[1]	12	1			T20	1		T132	1		T136	1
auto[134217728:268435455]	auto[0]	165	1			T20	1		T128	1		T37	1
auto[134217728:268435455]	auto[1]	5	1			T136	1		T333	1		T312	1
auto[268435456:402653183]	auto[0]	162	1			T14	1		T16	1		T29	1
auto[268435456:402653183]	auto[1]	12	1			T144	1		T146	1		T136	1
auto[402653184:536870911]	auto[0]	148	1			T15	1		T209	1		T21	1
auto[402653184:536870911]	auto[1]	11	1			T304	1		T412	1		T408	1
auto[536870912:671088639]	auto[0]	135	1			T14	1		T15	2		T37	1
auto[536870912:671088639]	auto[1]	13	1			T129	1		T146	1		T330	2
auto[671088640:805306367]	auto[0]	143	1			T18	1		T29	1		T47	1
auto[671088640:805306367]	auto[1]	8	1			T145	1		T146	1		T273	1
auto[805306368:939524095]	auto[0]	135	1			T29	1		T61	1		T30	2
auto[805306368:939524095]	auto[1]	5	1			T20	1		T146	1		T247	1
auto[939524096:1073741823]	auto[0]	130	1			T18	1		T29	1		T128	1
auto[939524096:1073741823]	auto[1]	10	1			T129	1		T416	1		T396	1
auto[1073741824:1207959551]	auto[0]	144	1			T1	1		T37	2		T89	1
auto[1073741824:1207959551]	auto[1]	8	1			T129	1		T246	1		T413	1
auto[1207959552:1342177279]	auto[0]	152	1			T29	1		T37	2		T89	1
auto[1207959552:1342177279]	auto[1]	9	1			T20	2		T144	1		T273	1
auto[1342177280:1476395007]	auto[0]	134	1			T89	1		T30	1		T54	2
auto[1342177280:1476395007]	auto[1]	4	1			T20	1		T144	1		T416	1
auto[1476395008:1610612735]	auto[0]	125	1			T29	1		T30	1		T210	1
auto[1476395008:1610612735]	auto[1]	5	1			T146	1		T246	2		T304	1
auto[1610612736:1744830463]	auto[0]	142	1			T16	1		T37	1		T89	1
auto[1610612736:1744830463]	auto[1]	5	1			T409	2		T415	1		T422	1
auto[1744830464:1879048191]	auto[0]	127	1			T14	1		T61	1		T54	1
auto[1744830464:1879048191]	auto[1]	7	1			T20	1		T131	1		T146	1
auto[1879048192:2013265919]	auto[0]	127	1			T14	1		T32	1		T122	1
auto[1879048192:2013265919]	auto[1]	11	1			T133	1		T264	1		T324	1
auto[2013265920:2147483647]	auto[0]	141	1			T14	1		T18	1		T122	1
auto[2013265920:2147483647]	auto[1]	5	1			T144	2		T255	1		T326	1
auto[2147483648:2281701375]	auto[0]	125	1			T30	1		T55	1		T144	1
auto[2147483648:2281701375]	auto[1]	6	1			T247	1		T412	1		T411	1
auto[2281701376:2415919103]	auto[0]	136	1			T14	1		T29	2		T30	3
auto[2281701376:2415919103]	auto[1]	7	1			T110	1		T131	1		T146	1
auto[2415919104:2550136831]	auto[0]	137	1			T20	1		T29	2		T30	1
auto[2415919104:2550136831]	auto[1]	10	1			T146	1		T133	1		T247	1
auto[2550136832:2684354559]	auto[0]	137	1			T29	2		T30	1		T122	1
auto[2550136832:2684354559]	auto[1]	9	1			T20	1		T129	1		T146	1
auto[2684354560:2818572287]	auto[0]	126	1			T61	1		T30	1		T32	1
auto[2684354560:2818572287]	auto[1]	6	1			T410	1		T409	1		T411	1
auto[2818572288:2952790015]	auto[0]	130	1			T89	1		T210	1		T55	1
auto[2818572288:2952790015]	auto[1]	9	1			T146	1		T273	1		T134	1
auto[2952790016:3087007743]	auto[0]	154	1			T18	1		T29	1		T209	1
auto[2952790016:3087007743]	auto[1]	7	1			T135	1		T330	1		T423	1
auto[3087007744:3221225471]	auto[0]	124	1			T15	1		T20	2		T29	1
auto[3087007744:3221225471]	auto[1]	11	1			T20	1		T144	1		T264	1
auto[3221225472:3355443199]	auto[0]	129	1			T14	1		T18	1		T30	2
auto[3221225472:3355443199]	auto[1]	4	1			T129	1		T273	1		T135	1
auto[3355443200:3489660927]	auto[0]	109	1			T15	1		T89	1		T30	1
auto[3355443200:3489660927]	auto[1]	10	1			T416	1		T408	1		T255	1
auto[3489660928:3623878655]	auto[0]	125	1			T61	1		T37	1		T31	1
auto[3489660928:3623878655]	auto[1]	11	1			T20	1		T133	1		T264	1
auto[3623878656:3758096383]	auto[0]	139	1			T14	2		T20	1		T30	1
auto[3623878656:3758096383]	auto[1]	11	1			T110	1		T145	1		T273	2
auto[3758096384:3892314111]	auto[0]	134	1			T14	1		T15	1		T29	3
auto[3758096384:3892314111]	auto[1]	12	1			T20	1		T324	2		T410	2
auto[3892314112:4026531839]	auto[0]	134	1			T20	1		T30	1		T32	1
auto[3892314112:4026531839]	auto[1]	5	1			T20	1		T145	1		T136	1
auto[4026531840:4160749567]	auto[0]	135	1			T47	1		T30	1		T38	1
auto[4026531840:4160749567]	auto[1]	6	1			T264	1		T135	1		T330	2
auto[4160749568:4294967295]	auto[0]	141	1			T1	1		T37	1		T210	1
auto[4160749568:4294967295]	auto[1]	7	1			T264	1		T409	1		T248	1