Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4542

1

T14

6

T15

10

T18

6

auto[1]

2482

1

T1

4

T3

2

T14

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	218	1			T128	2		T37	2		T30	2
auto[134217728:268435455]	242	1			T20	2		T29	4		T37	2
auto[268435456:402653183]	162	1			T30	2		T110	2		T212	2
auto[402653184:536870911]	206	1			T15	2		T55	2		T45	4
auto[536870912:671088639]	232	1			T18	2		T37	4		T215	2
auto[671088640:805306367]	224	1			T30	4		T210	2		T122	2
auto[805306368:939524095]	242	1			T29	2		T55	2		T144	2
auto[939524096:1073741823]	228	1			T38	2		T218	2		T45	6
auto[1073741824:1207959551]	182	1			T1	2		T16	2		T29	2
auto[1207959552:1342177279]	242	1			T30	2		T54	2		T21	2
auto[1342177280:1476395007]	218	1			T3	2		T20	2		T29	2
auto[1476395008:1610612735]	218	1			T15	2		T30	6		T4	2
auto[1610612736:1744830463]	218	1			T14	4		T16	2		T38	2
auto[1744830464:1879048191]	224	1			T15	2		T89	2		T218	2
auto[1879048192:2013265919]	176	1			T20	4		T128	2		T37	2
auto[2013265920:2147483647]	248	1			T18	2		T29	2		T30	4
auto[2147483648:2281701375]	204	1			T128	2		T89	2		T32	2
auto[2281701376:2415919103]	252	1			T61	4		T215	2		T54	2
auto[2415919104:2550136831]	198	1			T54	2		T55	2		T76	2
auto[2550136832:2684354559]	224	1			T30	2		T215	2		T68	4
auto[2684354560:2818572287]	212	1			T61	2		T30	2		T122	2
auto[2818572288:2952790015]	262	1			T29	2		T30	2		T55	2
auto[2952790016:3087007743]	220	1			T18	2		T89	2		T30	10
auto[3087007744:3221225471]	178	1			T14	2		T15	2		T61	2
auto[3221225472:3355443199]	268	1			T89	2		T30	2		T210	2
auto[3355443200:3489660927]	192	1			T20	2		T29	2		T89	4
auto[3489660928:3623878655]	208	1			T29	4		T47	2		T89	2
auto[3623878656:3758096383]	206	1			T14	2		T30	4		T32	2
auto[3758096384:3892314111]	260	1			T18	2		T29	2		T30	6
auto[3892314112:4026531839]	220	1			T29	2		T37	2		T30	2
auto[4026531840:4160749567]	222	1			T30	4		T54	2		T45	2
auto[4160749568:4294967295]	218	1			T1	2		T14	2		T15	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	160	1			T128	2		T37	2		T30	2
auto[0:134217727]	auto[1]	58	1			T210	2		T145	2		T71	2
auto[134217728:268435455]	auto[0]	146	1			T20	2		T29	4		T210	2
auto[134217728:268435455]	auto[1]	96	1			T37	2		T54	2		T122	2
auto[268435456:402653183]	auto[0]	110	1			T30	2		T110	2		T212	2
auto[268435456:402653183]	auto[1]	52	1			T145	2		T60	2		T51	2
auto[402653184:536870911]	auto[0]	138	1			T15	2		T45	2		T4	2
auto[402653184:536870911]	auto[1]	68	1			T55	2		T45	2		T70	2
auto[536870912:671088639]	auto[0]	136	1			T18	2		T37	2		T215	2
auto[536870912:671088639]	auto[1]	96	1			T37	2		T38	2		T218	2
auto[671088640:805306367]	auto[0]	138	1			T30	2		T210	2		T122	2
auto[671088640:805306367]	auto[1]	86	1			T30	2		T38	2		T4	2
auto[805306368:939524095]	auto[0]	150	1			T29	2		T55	2		T144	2
auto[805306368:939524095]	auto[1]	92	1			T4	2		T28	2		T50	2
auto[939524096:1073741823]	auto[0]	162	1			T38	2		T45	2		T4	2
auto[939524096:1073741823]	auto[1]	66	1			T218	2		T45	4		T117	2
auto[1073741824:1207959551]	auto[0]	116	1			T54	2		T55	2		T269	2
auto[1073741824:1207959551]	auto[1]	66	1			T1	2		T16	2		T29	2
auto[1207959552:1342177279]	auto[0]	150	1			T54	2		T21	2		T84	4
auto[1207959552:1342177279]	auto[1]	92	1			T30	2		T45	4		T289	2
auto[1342177280:1476395007]	auto[0]	134	1			T20	2		T29	2		T37	2
auto[1342177280:1476395007]	auto[1]	84	1			T3	2		T215	2		T110	2
auto[1476395008:1610612735]	auto[0]	154	1			T15	2		T30	6		T4	2
auto[1476395008:1610612735]	auto[1]	64	1			T78	2		T46	2		T93	2
auto[1610612736:1744830463]	auto[0]	144	1			T14	4		T38	2		T33	2
auto[1610612736:1744830463]	auto[1]	74	1			T16	2		T117	2		T202	2
auto[1744830464:1879048191]	auto[0]	148	1			T15	2		T89	2		T4	2
auto[1744830464:1879048191]	auto[1]	76	1			T218	2		T4	6		T78	2
auto[1879048192:2013265919]	auto[0]	114	1			T20	4		T128	2		T297	2
auto[1879048192:2013265919]	auto[1]	62	1			T37	2		T31	2		T209	4
auto[2013265920:2147483647]	auto[0]	154	1			T29	2		T30	4		T122	4
auto[2013265920:2147483647]	auto[1]	94	1			T18	2		T296	2		T131	2
auto[2147483648:2281701375]	auto[0]	134	1			T128	2		T89	2		T210	2
auto[2147483648:2281701375]	auto[1]	70	1			T32	2		T54	2		T110	2
auto[2281701376:2415919103]	auto[0]	158	1			T215	2		T38	2		T76	2
auto[2281701376:2415919103]	auto[1]	94	1			T61	4		T54	2		T77	2
auto[2415919104:2550136831]	auto[0]	128	1			T55	2		T4	2		T129	2
auto[2415919104:2550136831]	auto[1]	70	1			T54	2		T76	2		T211	2
auto[2550136832:2684354559]	auto[0]	158	1			T30	2		T215	2		T45	2
auto[2550136832:2684354559]	auto[1]	66	1			T68	4		T4	4		T78	2
auto[2684354560:2818572287]	auto[0]	136	1			T61	2		T30	2		T122	2
auto[2684354560:2818572287]	auto[1]	76	1			T21	2		T401	2		T81	2
auto[2818572288:2952790015]	auto[0]	166	1			T30	2		T55	2		T43	2
auto[2818572288:2952790015]	auto[1]	96	1			T29	2		T78	2		T257	2
auto[2952790016:3087007743]	auto[0]	144	1			T18	2		T89	2		T30	10
auto[2952790016:3087007743]	auto[1]	76	1			T144	2		T4	2		T219	2
auto[3087007744:3221225471]	auto[0]	112	1			T15	2		T30	2		T84	2
auto[3087007744:3221225471]	auto[1]	66	1			T14	2		T61	2		T32	2
auto[3221225472:3355443199]	auto[0]	176	1			T89	2		T45	2		T212	2
auto[3221225472:3355443199]	auto[1]	92	1			T30	2		T210	2		T77	2
auto[3355443200:3489660927]	auto[0]	126	1			T20	2		T29	2		T89	4
auto[3355443200:3489660927]	auto[1]	66	1			T31	2		T32	2		T33	2
auto[3489660928:3623878655]	auto[0]	134	1			T29	4		T54	2		T68	2
auto[3489660928:3623878655]	auto[1]	74	1			T47	2		T89	2		T54	2
auto[3623878656:3758096383]	auto[0]	128	1			T30	2		T43	2		T4	2
auto[3623878656:3758096383]	auto[1]	78	1			T14	2		T30	2		T32	2
auto[3758096384:3892314111]	auto[0]	156	1			T18	2		T29	2		T30	4
auto[3758096384:3892314111]	auto[1]	104	1			T30	2		T54	4		T45	2
auto[3892314112:4026531839]	auto[0]	120	1			T45	2		T219	2		T403	2
auto[3892314112:4026531839]	auto[1]	100	1			T29	2		T37	2		T30	2
auto[4026531840:4160749567]	auto[0]	158	1			T30	4		T54	2		T45	2
auto[4026531840:4160749567]	auto[1]	64	1			T346	2		T252	2		T274	2
auto[4160749568:4294967295]	auto[0]	154	1			T14	2		T15	2		T30	2
auto[4160749568:4294967295]	auto[1]	64	1			T1	2		T45	2		T26	2