Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.04 98.15 98.38 100.00 99.02 98.41 91.14


Total test records in report: 1089
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1008 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.51118751 Jul 11 05:30:44 PM PDT 24 Jul 11 05:30:46 PM PDT 24 14200519 ps
T1009 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3347650218 Jul 11 05:30:20 PM PDT 24 Jul 11 05:30:26 PM PDT 24 255467358 ps
T1010 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2515530888 Jul 11 05:30:06 PM PDT 24 Jul 11 05:30:10 PM PDT 24 55761880 ps
T1011 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.446777971 Jul 11 05:30:23 PM PDT 24 Jul 11 05:30:29 PM PDT 24 10825211 ps
T1012 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2615104241 Jul 11 05:30:06 PM PDT 24 Jul 11 05:30:11 PM PDT 24 512401753 ps
T1013 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.374187076 Jul 11 05:29:15 PM PDT 24 Jul 11 05:29:17 PM PDT 24 18437505 ps
T1014 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.938151612 Jul 11 05:30:19 PM PDT 24 Jul 11 05:30:25 PM PDT 24 48980736 ps
T1015 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1137861004 Jul 11 05:29:16 PM PDT 24 Jul 11 05:29:19 PM PDT 24 37778600 ps
T1016 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.577021273 Jul 11 05:30:24 PM PDT 24 Jul 11 05:30:30 PM PDT 24 59436344 ps
T1017 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2149389458 Jul 11 05:29:55 PM PDT 24 Jul 11 05:29:59 PM PDT 24 75277135 ps
T1018 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.600711022 Jul 11 05:29:42 PM PDT 24 Jul 11 05:29:45 PM PDT 24 61930649 ps
T1019 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.869049567 Jul 11 05:30:32 PM PDT 24 Jul 11 05:30:36 PM PDT 24 24813826 ps
T1020 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1287107701 Jul 11 05:30:12 PM PDT 24 Jul 11 05:30:15 PM PDT 24 15337519 ps
T1021 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3365750992 Jul 11 05:30:25 PM PDT 24 Jul 11 05:30:31 PM PDT 24 24434314 ps
T1022 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2729842088 Jul 11 05:30:04 PM PDT 24 Jul 11 05:30:09 PM PDT 24 48532774 ps
T1023 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1583933424 Jul 11 05:30:19 PM PDT 24 Jul 11 05:30:24 PM PDT 24 45317863 ps
T1024 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3241953232 Jul 11 05:29:22 PM PDT 24 Jul 11 05:29:24 PM PDT 24 46952147 ps
T1025 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.4014325504 Jul 11 05:30:18 PM PDT 24 Jul 11 05:30:28 PM PDT 24 1671658356 ps
T1026 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3043537955 Jul 11 05:30:18 PM PDT 24 Jul 11 05:30:24 PM PDT 24 122497992 ps
T1027 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2094929857 Jul 11 05:30:10 PM PDT 24 Jul 11 05:30:16 PM PDT 24 770895672 ps
T1028 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1582281545 Jul 11 05:30:29 PM PDT 24 Jul 11 05:30:34 PM PDT 24 145501937 ps
T1029 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1187581899 Jul 11 05:30:12 PM PDT 24 Jul 11 05:30:17 PM PDT 24 955362509 ps
T1030 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2728941132 Jul 11 05:30:20 PM PDT 24 Jul 11 05:30:27 PM PDT 24 50981285 ps
T1031 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1597617606 Jul 11 05:30:09 PM PDT 24 Jul 11 05:30:12 PM PDT 24 170873769 ps
T1032 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.336895451 Jul 11 05:30:24 PM PDT 24 Jul 11 05:30:31 PM PDT 24 44405429 ps
T1033 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3290418416 Jul 11 05:30:23 PM PDT 24 Jul 11 05:30:30 PM PDT 24 438523821 ps
T1034 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3982406390 Jul 11 05:30:15 PM PDT 24 Jul 11 05:30:20 PM PDT 24 61792726 ps
T1035 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.226191308 Jul 11 05:29:45 PM PDT 24 Jul 11 05:29:49 PM PDT 24 379296244 ps
T1036 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.586419187 Jul 11 05:30:32 PM PDT 24 Jul 11 05:30:36 PM PDT 24 23049909 ps
T1037 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2194653678 Jul 11 05:29:19 PM PDT 24 Jul 11 05:29:21 PM PDT 24 30372135 ps
T1038 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.21098615 Jul 11 05:30:40 PM PDT 24 Jul 11 05:30:42 PM PDT 24 115571336 ps
T1039 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3465311111 Jul 11 05:30:18 PM PDT 24 Jul 11 05:30:25 PM PDT 24 161571826 ps
T168 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2117443078 Jul 11 05:29:42 PM PDT 24 Jul 11 05:29:48 PM PDT 24 501476360 ps
T1040 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3319803095 Jul 11 05:29:16 PM PDT 24 Jul 11 05:29:30 PM PDT 24 3335730919 ps
T171 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3406557474 Jul 11 05:30:31 PM PDT 24 Jul 11 05:30:37 PM PDT 24 251431847 ps
T1041 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.464050257 Jul 11 05:30:08 PM PDT 24 Jul 11 05:30:13 PM PDT 24 79096561 ps
T1042 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1655077183 Jul 11 05:30:28 PM PDT 24 Jul 11 05:30:33 PM PDT 24 95557728 ps
T1043 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3579797824 Jul 11 05:29:19 PM PDT 24 Jul 11 05:29:21 PM PDT 24 49837778 ps
T1044 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3725729583 Jul 11 05:30:05 PM PDT 24 Jul 11 05:30:11 PM PDT 24 298349951 ps
T1045 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.4063301799 Jul 11 05:29:37 PM PDT 24 Jul 11 05:29:40 PM PDT 24 18930640 ps
T1046 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.205153900 Jul 11 05:29:45 PM PDT 24 Jul 11 05:29:58 PM PDT 24 1048970476 ps
T1047 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2841824740 Jul 11 05:29:42 PM PDT 24 Jul 11 05:29:44 PM PDT 24 51353697 ps
T1048 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.4158890141 Jul 11 05:30:29 PM PDT 24 Jul 11 05:30:33 PM PDT 24 81436908 ps
T1049 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.792608148 Jul 11 05:29:36 PM PDT 24 Jul 11 05:29:42 PM PDT 24 164814855 ps
T165 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3080476470 Jul 11 05:29:30 PM PDT 24 Jul 11 05:29:39 PM PDT 24 273159060 ps
T1050 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1518844802 Jul 11 05:30:24 PM PDT 24 Jul 11 05:30:32 PM PDT 24 674247408 ps
T1051 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2243439493 Jul 11 05:29:33 PM PDT 24 Jul 11 05:29:36 PM PDT 24 23618959 ps
T1052 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.563219779 Jul 11 05:30:02 PM PDT 24 Jul 11 05:30:12 PM PDT 24 419786037 ps
T1053 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.469688142 Jul 11 05:30:13 PM PDT 24 Jul 11 05:30:18 PM PDT 24 421372252 ps
T1054 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4000402746 Jul 11 05:29:28 PM PDT 24 Jul 11 05:29:30 PM PDT 24 13370912 ps
T1055 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1294832644 Jul 11 05:29:55 PM PDT 24 Jul 11 05:30:00 PM PDT 24 2069419794 ps
T1056 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.771411831 Jul 11 05:30:14 PM PDT 24 Jul 11 05:30:24 PM PDT 24 317751633 ps
T1057 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1823916441 Jul 11 05:30:17 PM PDT 24 Jul 11 05:30:22 PM PDT 24 40080036 ps
T1058 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.219233408 Jul 11 05:29:54 PM PDT 24 Jul 11 05:30:00 PM PDT 24 237591568 ps
T1059 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3923316261 Jul 11 05:30:43 PM PDT 24 Jul 11 05:30:46 PM PDT 24 52517817 ps
T160 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.716525775 Jul 11 05:30:14 PM PDT 24 Jul 11 05:30:22 PM PDT 24 348683696 ps
T1060 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.114719631 Jul 11 05:30:17 PM PDT 24 Jul 11 05:30:23 PM PDT 24 141391214 ps
T172 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3963607714 Jul 11 05:29:13 PM PDT 24 Jul 11 05:29:24 PM PDT 24 411598022 ps
T1061 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1279284444 Jul 11 05:30:12 PM PDT 24 Jul 11 05:30:15 PM PDT 24 27618930 ps
T1062 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.800797452 Jul 11 05:30:43 PM PDT 24 Jul 11 05:30:46 PM PDT 24 17858539 ps
T1063 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2140761092 Jul 11 05:29:27 PM PDT 24 Jul 11 05:29:31 PM PDT 24 250705577 ps
T1064 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3938771126 Jul 11 05:29:44 PM PDT 24 Jul 11 05:29:47 PM PDT 24 93119100 ps
T1065 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.4152662701 Jul 11 05:30:14 PM PDT 24 Jul 11 05:30:19 PM PDT 24 115322955 ps
T173 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.69523902 Jul 11 05:30:07 PM PDT 24 Jul 11 05:30:18 PM PDT 24 945598967 ps
T1066 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2525190311 Jul 11 05:30:04 PM PDT 24 Jul 11 05:30:08 PM PDT 24 483104716 ps
T1067 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2173074434 Jul 11 05:30:18 PM PDT 24 Jul 11 05:30:22 PM PDT 24 13498698 ps
T1068 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3378266748 Jul 11 05:30:24 PM PDT 24 Jul 11 05:30:32 PM PDT 24 80576031 ps
T1069 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1700141253 Jul 11 05:29:30 PM PDT 24 Jul 11 05:29:34 PM PDT 24 35306547 ps
T1070 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.4099592453 Jul 11 05:30:27 PM PDT 24 Jul 11 05:30:33 PM PDT 24 37039169 ps
T1071 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.170094684 Jul 11 05:30:04 PM PDT 24 Jul 11 05:30:08 PM PDT 24 18030234 ps
T1072 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4096088431 Jul 11 05:29:30 PM PDT 24 Jul 11 05:29:35 PM PDT 24 44698880 ps
T1073 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2476238675 Jul 11 05:30:12 PM PDT 24 Jul 11 05:30:17 PM PDT 24 857949266 ps
T1074 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.566664539 Jul 11 05:30:19 PM PDT 24 Jul 11 05:30:26 PM PDT 24 171048667 ps
T1075 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3309670119 Jul 11 05:29:27 PM PDT 24 Jul 11 05:29:36 PM PDT 24 339633352 ps
T1076 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1279562615 Jul 11 05:30:37 PM PDT 24 Jul 11 05:30:39 PM PDT 24 79391082 ps
T1077 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2238646911 Jul 11 05:30:16 PM PDT 24 Jul 11 05:30:29 PM PDT 24 251570032 ps
T1078 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3780314784 Jul 11 05:29:16 PM PDT 24 Jul 11 05:29:19 PM PDT 24 389832440 ps
T1079 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3958349032 Jul 11 05:30:12 PM PDT 24 Jul 11 05:30:16 PM PDT 24 200206420 ps
T1080 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1446620155 Jul 11 05:29:26 PM PDT 24 Jul 11 05:29:28 PM PDT 24 32809112 ps
T1081 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3155082134 Jul 11 05:29:54 PM PDT 24 Jul 11 05:29:59 PM PDT 24 394129141 ps
T1082 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.252300747 Jul 11 05:30:34 PM PDT 24 Jul 11 05:30:37 PM PDT 24 11227893 ps
T1083 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1629722098 Jul 11 05:29:37 PM PDT 24 Jul 11 05:29:40 PM PDT 24 101447665 ps
T1084 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1416358154 Jul 11 05:29:56 PM PDT 24 Jul 11 05:30:03 PM PDT 24 849061280 ps
T1085 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2416668533 Jul 11 05:30:17 PM PDT 24 Jul 11 05:30:36 PM PDT 24 409512405 ps
T166 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3220053833 Jul 11 05:30:12 PM PDT 24 Jul 11 05:30:17 PM PDT 24 168281749 ps
T1086 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1483632978 Jul 11 05:30:07 PM PDT 24 Jul 11 05:30:10 PM PDT 24 690389521 ps
T1087 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3130931222 Jul 11 05:30:04 PM PDT 24 Jul 11 05:30:07 PM PDT 24 32617719 ps
T1088 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.33408084 Jul 11 05:30:47 PM PDT 24 Jul 11 05:30:51 PM PDT 24 62403275 ps
T1089 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2350420126 Jul 11 05:30:23 PM PDT 24 Jul 11 05:30:32 PM PDT 24 1506957035 ps

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3019687451
Short name T14
Test name
Test status
Simulation time 105778531 ps
CPU time 5.09 seconds
Started Jul 11 05:34:41 PM PDT 24
Finished Jul 11 05:34:55 PM PDT 24
Peak memory 220200 kb
Host smart-33013bf4-19c7-4c02-9301-07fb59054d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019687451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3019687451
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1794168717
Short name T30
Test name
Test status
Simulation time 3638169655 ps
CPU time 28.79 seconds
Started Jul 11 05:34:39 PM PDT 24
Finished Jul 11 05:35:16 PM PDT 24
Peak memory 222660 kb
Host smart-b3473281-d40b-427d-a94c-9fee7284ec12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794168717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1794168717
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1823037451
Short name T4
Test name
Test status
Simulation time 2892985138 ps
CPU time 49.19 seconds
Started Jul 11 05:35:34 PM PDT 24
Finished Jul 11 05:36:30 PM PDT 24
Peak memory 215196 kb
Host smart-838a222f-7205-4f97-ae45-f6bc48a78901
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823037451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1823037451
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.1787006178
Short name T46
Test name
Test status
Simulation time 858823616 ps
CPU time 12.55 seconds
Started Jul 11 05:34:02 PM PDT 24
Finished Jul 11 05:34:27 PM PDT 24
Peak memory 221528 kb
Host smart-c8ad4a89-a258-4724-9a4a-6a3b5a61935c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787006178 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.1787006178
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.420371118
Short name T10
Test name
Test status
Simulation time 1660827137 ps
CPU time 6.92 seconds
Started Jul 11 05:33:34 PM PDT 24
Finished Jul 11 05:33:43 PM PDT 24
Peak memory 230832 kb
Host smart-8b34c86b-3d1f-4a71-9525-5e5335062445
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420371118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.420371118
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.2909298555
Short name T67
Test name
Test status
Simulation time 1499285806 ps
CPU time 26.62 seconds
Started Jul 11 05:35:56 PM PDT 24
Finished Jul 11 05:36:25 PM PDT 24
Peak memory 223304 kb
Host smart-35159be2-7b46-470c-a716-09ad521edcf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909298555 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.2909298555
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3019167508
Short name T20
Test name
Test status
Simulation time 1090629496 ps
CPU time 29.88 seconds
Started Jul 11 05:34:20 PM PDT 24
Finished Jul 11 05:35:01 PM PDT 24
Peak memory 215824 kb
Host smart-b80ef744-49d1-4370-9c27-8abeba276a6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3019167508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3019167508
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3134372888
Short name T45
Test name
Test status
Simulation time 5838817288 ps
CPU time 65.19 seconds
Started Jul 11 05:36:17 PM PDT 24
Finished Jul 11 05:37:26 PM PDT 24
Peak memory 216828 kb
Host smart-fa466a34-a016-4c19-bbaa-23708623af83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134372888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3134372888
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2937148396
Short name T50
Test name
Test status
Simulation time 254596000 ps
CPU time 3.6 seconds
Started Jul 11 05:35:16 PM PDT 24
Finished Jul 11 05:35:24 PM PDT 24
Peak memory 214260 kb
Host smart-c25e4752-a2bf-4535-8120-e93488787fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937148396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2937148396
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1112992779
Short name T7
Test name
Test status
Simulation time 601086233 ps
CPU time 16.58 seconds
Started Jul 11 05:34:58 PM PDT 24
Finished Jul 11 05:35:20 PM PDT 24
Peak memory 222912 kb
Host smart-48037f75-65e6-4bf2-bcb5-5efdf65a01a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112992779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1112992779
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.4145171028
Short name T108
Test name
Test status
Simulation time 169529809 ps
CPU time 6.55 seconds
Started Jul 11 05:29:45 PM PDT 24
Finished Jul 11 05:29:52 PM PDT 24
Peak memory 213824 kb
Host smart-9e665517-e26d-4867-a75b-b79f8bf47af7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145171028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.4145171028
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1592249308
Short name T29
Test name
Test status
Simulation time 2924742578 ps
CPU time 14.82 seconds
Started Jul 11 05:33:33 PM PDT 24
Finished Jul 11 05:33:50 PM PDT 24
Peak memory 214568 kb
Host smart-dbb7eaa6-29dc-4032-beb9-71087d7e9014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592249308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1592249308
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3523404354
Short name T146
Test name
Test status
Simulation time 1357543356 ps
CPU time 74.84 seconds
Started Jul 11 05:34:43 PM PDT 24
Finished Jul 11 05:36:06 PM PDT 24
Peak memory 216648 kb
Host smart-95e7720e-5e99-435d-8aee-5f0b0b07d2bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3523404354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3523404354
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3791664830
Short name T95
Test name
Test status
Simulation time 215853597 ps
CPU time 5.07 seconds
Started Jul 11 05:34:58 PM PDT 24
Finished Jul 11 05:35:09 PM PDT 24
Peak memory 214264 kb
Host smart-5b45f017-ffb2-4f06-a3b4-4cef13d48515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791664830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3791664830
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.4251584252
Short name T219
Test name
Test status
Simulation time 2507136359 ps
CPU time 18.89 seconds
Started Jul 11 05:35:53 PM PDT 24
Finished Jul 11 05:36:14 PM PDT 24
Peak memory 222616 kb
Host smart-32ce8998-d00d-4f59-8333-699c40e738d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251584252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.4251584252
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3388327969
Short name T273
Test name
Test status
Simulation time 1876534810 ps
CPU time 7.06 seconds
Started Jul 11 05:36:17 PM PDT 24
Finished Jul 11 05:36:28 PM PDT 24
Peak memory 215400 kb
Host smart-59e7d1dc-3536-46e2-a121-1372f110dea3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388327969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3388327969
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1639612399
Short name T81
Test name
Test status
Simulation time 14759046365 ps
CPU time 91.88 seconds
Started Jul 11 05:34:33 PM PDT 24
Finished Jul 11 05:36:15 PM PDT 24
Peak memory 215448 kb
Host smart-f1fabaaf-3f53-4a8d-bbd4-dc4bc3180b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639612399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1639612399
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.901624299
Short name T428
Test name
Test status
Simulation time 143848183 ps
CPU time 7 seconds
Started Jul 11 05:34:57 PM PDT 24
Finished Jul 11 05:35:10 PM PDT 24
Peak memory 215244 kb
Host smart-6937059a-645b-4e8a-bb50-934087fa5ea1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=901624299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.901624299
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1465883236
Short name T55
Test name
Test status
Simulation time 640500194 ps
CPU time 16.63 seconds
Started Jul 11 05:35:22 PM PDT 24
Finished Jul 11 05:35:43 PM PDT 24
Peak memory 222508 kb
Host smart-b54bfa48-ab15-4522-add7-5a8d047b0ab4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465883236 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1465883236
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3083190456
Short name T132
Test name
Test status
Simulation time 415650015 ps
CPU time 6.09 seconds
Started Jul 11 05:33:38 PM PDT 24
Finished Jul 11 05:33:46 PM PDT 24
Peak memory 215424 kb
Host smart-ff6ffd4e-798b-4714-b104-7a9cb37cb088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3083190456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3083190456
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.312093147
Short name T972
Test name
Test status
Simulation time 159962478 ps
CPU time 3.29 seconds
Started Jul 11 05:30:23 PM PDT 24
Finished Jul 11 05:30:32 PM PDT 24
Peak memory 214028 kb
Host smart-20d67528-7105-4675-8877-73b32ac44813
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312093147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.312093147
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1212738469
Short name T409
Test name
Test status
Simulation time 109862241 ps
CPU time 5.85 seconds
Started Jul 11 05:33:35 PM PDT 24
Finished Jul 11 05:33:43 PM PDT 24
Peak memory 215216 kb
Host smart-10f7c64d-ca31-4736-9367-bc6027eac7f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1212738469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1212738469
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1310269664
Short name T70
Test name
Test status
Simulation time 192561233 ps
CPU time 8.57 seconds
Started Jul 11 05:33:36 PM PDT 24
Finished Jul 11 05:33:47 PM PDT 24
Peak memory 219704 kb
Host smart-0de5d24e-2a8a-4296-b6c2-cfeeae0a0084
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310269664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1310269664
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3434215347
Short name T144
Test name
Test status
Simulation time 88706729 ps
CPU time 3.29 seconds
Started Jul 11 05:35:16 PM PDT 24
Finished Jul 11 05:35:24 PM PDT 24
Peak memory 215184 kb
Host smart-5ae5a1a7-5d2b-4119-95f3-8184bfd2f434
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3434215347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3434215347
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.387359484
Short name T41
Test name
Test status
Simulation time 195872345 ps
CPU time 5.55 seconds
Started Jul 11 05:33:36 PM PDT 24
Finished Jul 11 05:33:44 PM PDT 24
Peak memory 220684 kb
Host smart-0f55a060-965d-4d4a-b0b1-dde739cf028e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387359484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.387359484
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3462145016
Short name T24
Test name
Test status
Simulation time 297441615 ps
CPU time 3.46 seconds
Started Jul 11 05:36:09 PM PDT 24
Finished Jul 11 05:36:14 PM PDT 24
Peak memory 214680 kb
Host smart-6b2266a2-9f97-4f8b-8efa-a576849dfdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462145016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3462145016
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1935547484
Short name T202
Test name
Test status
Simulation time 4211786055 ps
CPU time 44.01 seconds
Started Jul 11 05:34:23 PM PDT 24
Finished Jul 11 05:35:18 PM PDT 24
Peak memory 222496 kb
Host smart-e92f97bf-9b0d-4566-bf4b-131f6b6aca01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935547484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1935547484
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2273302361
Short name T148
Test name
Test status
Simulation time 309763783 ps
CPU time 3.84 seconds
Started Jul 11 05:35:26 PM PDT 24
Finished Jul 11 05:35:36 PM PDT 24
Peak memory 218072 kb
Host smart-837ac8a5-542f-4e4a-8875-4082a0ade740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273302361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2273302361
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2226756169
Short name T34
Test name
Test status
Simulation time 86920718 ps
CPU time 4.31 seconds
Started Jul 11 05:34:11 PM PDT 24
Finished Jul 11 05:34:29 PM PDT 24
Peak memory 217952 kb
Host smart-ff7e05c4-7b06-41da-9a17-03a70fe3d9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226756169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2226756169
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.832802339
Short name T23
Test name
Test status
Simulation time 1917162455 ps
CPU time 7.76 seconds
Started Jul 11 05:35:55 PM PDT 24
Finished Jul 11 05:36:05 PM PDT 24
Peak memory 209644 kb
Host smart-992933b7-520f-4872-828e-867318ca8dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832802339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.832802339
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.3742211317
Short name T51
Test name
Test status
Simulation time 247952539 ps
CPU time 10.96 seconds
Started Jul 11 05:33:58 PM PDT 24
Finished Jul 11 05:34:21 PM PDT 24
Peak memory 222716 kb
Host smart-477bea0a-07f9-4735-92dc-12fc2a978f37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742211317 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.3742211317
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3133680777
Short name T167
Test name
Test status
Simulation time 205241613 ps
CPU time 8.53 seconds
Started Jul 11 05:29:58 PM PDT 24
Finished Jul 11 05:30:09 PM PDT 24
Peak memory 213572 kb
Host smart-9050e589-3bb6-446b-8e5d-953147e1cdfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133680777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3133680777
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3532584317
Short name T415
Test name
Test status
Simulation time 368699483 ps
CPU time 9.81 seconds
Started Jul 11 05:36:25 PM PDT 24
Finished Jul 11 05:36:37 PM PDT 24
Peak memory 214744 kb
Host smart-55829e26-097f-43a5-85dc-f2653d9444cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3532584317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3532584317
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1317821588
Short name T71
Test name
Test status
Simulation time 1585994416 ps
CPU time 16.31 seconds
Started Jul 11 05:35:22 PM PDT 24
Finished Jul 11 05:35:43 PM PDT 24
Peak memory 222608 kb
Host smart-338d9dda-0def-4b19-84ba-dd1ff9d0b0e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317821588 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1317821588
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1394458826
Short name T63
Test name
Test status
Simulation time 400952729 ps
CPU time 6.53 seconds
Started Jul 11 05:33:41 PM PDT 24
Finished Jul 11 05:33:50 PM PDT 24
Peak memory 211032 kb
Host smart-5c99d99a-4c4d-45a2-a164-cfdba78ce8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394458826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1394458826
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2823332328
Short name T247
Test name
Test status
Simulation time 11643214327 ps
CPU time 70.51 seconds
Started Jul 11 05:36:33 PM PDT 24
Finished Jul 11 05:37:47 PM PDT 24
Peak memory 214280 kb
Host smart-9f615344-8d5e-417d-a04c-571e07134abb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2823332328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2823332328
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.688951213
Short name T434
Test name
Test status
Simulation time 75137737 ps
CPU time 0.74 seconds
Started Jul 11 05:33:52 PM PDT 24
Finished Jul 11 05:34:01 PM PDT 24
Peak memory 205852 kb
Host smart-3f4c7112-95d8-40cf-ae94-4ad987816410
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688951213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.688951213
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.340123341
Short name T158
Test name
Test status
Simulation time 351051641 ps
CPU time 4.17 seconds
Started Jul 11 05:30:20 PM PDT 24
Finished Jul 11 05:30:30 PM PDT 24
Peak memory 213620 kb
Host smart-f8ef87f7-5409-430f-afef-3b0783322b98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340123341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.340123341
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2585988099
Short name T350
Test name
Test status
Simulation time 276300853 ps
CPU time 7.29 seconds
Started Jul 11 05:35:06 PM PDT 24
Finished Jul 11 05:35:18 PM PDT 24
Peak memory 222476 kb
Host smart-d27aad57-6163-40ac-9db0-03388959be54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2585988099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2585988099
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1857258463
Short name T224
Test name
Test status
Simulation time 9343232569 ps
CPU time 90.08 seconds
Started Jul 11 05:35:17 PM PDT 24
Finished Jul 11 05:36:51 PM PDT 24
Peak memory 217316 kb
Host smart-2c2b0244-31ee-49cd-94fb-5fede3dba788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857258463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1857258463
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2883256902
Short name T54
Test name
Test status
Simulation time 212992855 ps
CPU time 8.32 seconds
Started Jul 11 05:33:47 PM PDT 24
Finished Jul 11 05:33:59 PM PDT 24
Peak memory 222564 kb
Host smart-85390ad2-63f4-43ce-8272-a3b5df610851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883256902 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2883256902
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1263544242
Short name T262
Test name
Test status
Simulation time 104438655 ps
CPU time 3.15 seconds
Started Jul 11 05:36:23 PM PDT 24
Finished Jul 11 05:36:29 PM PDT 24
Peak memory 214360 kb
Host smart-67fb0d53-17d8-4da9-82e1-f81dc4658f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263544242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1263544242
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2693161492
Short name T3
Test name
Test status
Simulation time 99487358 ps
CPU time 3.83 seconds
Started Jul 11 05:36:07 PM PDT 24
Finished Jul 11 05:36:13 PM PDT 24
Peak memory 222824 kb
Host smart-1b8ddcb7-7115-440d-8c3e-089db968c18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693161492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2693161492
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3517753364
Short name T131
Test name
Test status
Simulation time 67566061 ps
CPU time 4.07 seconds
Started Jul 11 05:34:13 PM PDT 24
Finished Jul 11 05:34:31 PM PDT 24
Peak memory 214328 kb
Host smart-65de5cd2-869f-4792-a876-086fa61c12e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3517753364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3517753364
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1748853043
Short name T242
Test name
Test status
Simulation time 1399324729 ps
CPU time 37.96 seconds
Started Jul 11 05:36:15 PM PDT 24
Finished Jul 11 05:36:56 PM PDT 24
Peak memory 216140 kb
Host smart-07df67d1-9597-4800-8493-c1922af87daa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748853043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1748853043
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.464009871
Short name T149
Test name
Test status
Simulation time 505683585 ps
CPU time 4.05 seconds
Started Jul 11 05:34:42 PM PDT 24
Finished Jul 11 05:34:55 PM PDT 24
Peak memory 216932 kb
Host smart-39181062-7782-43da-90b5-991c164de88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464009871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.464009871
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3317364795
Short name T38
Test name
Test status
Simulation time 174964624 ps
CPU time 4.55 seconds
Started Jul 11 05:33:45 PM PDT 24
Finished Jul 11 05:33:52 PM PDT 24
Peak memory 222456 kb
Host smart-7c0d14df-8464-4f45-b516-79f6c95d044a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317364795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3317364795
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1836388021
Short name T411
Test name
Test status
Simulation time 198657617 ps
CPU time 10.5 seconds
Started Jul 11 05:34:06 PM PDT 24
Finished Jul 11 05:34:29 PM PDT 24
Peak memory 214340 kb
Host smart-5fffa85a-17e1-43e9-b912-78a2d3910fac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1836388021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1836388021
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2362294995
Short name T229
Test name
Test status
Simulation time 5263802884 ps
CPU time 88.41 seconds
Started Jul 11 05:36:11 PM PDT 24
Finished Jul 11 05:37:41 PM PDT 24
Peak memory 222452 kb
Host smart-adb1ad77-6ce8-409d-9ad9-c5ec9c11d332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362294995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2362294995
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.730862483
Short name T270
Test name
Test status
Simulation time 241698280 ps
CPU time 3.99 seconds
Started Jul 11 05:36:13 PM PDT 24
Finished Jul 11 05:36:19 PM PDT 24
Peak memory 206432 kb
Host smart-884d52b0-98b2-4dc7-b546-c80a9af9b071
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730862483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.730862483
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3963607714
Short name T172
Test name
Test status
Simulation time 411598022 ps
CPU time 9.45 seconds
Started Jul 11 05:29:13 PM PDT 24
Finished Jul 11 05:29:24 PM PDT 24
Peak memory 213532 kb
Host smart-dc5e6bc1-8ae4-46bf-b97f-1b9501d87ad8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963607714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3963607714
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.4014662285
Short name T302
Test name
Test status
Simulation time 516523292 ps
CPU time 6.39 seconds
Started Jul 11 05:34:13 PM PDT 24
Finished Jul 11 05:34:33 PM PDT 24
Peak memory 222568 kb
Host smart-69cdd218-6d64-4f9b-8cf5-90989eae5647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014662285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.4014662285
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1140531955
Short name T92
Test name
Test status
Simulation time 418760868 ps
CPU time 2.99 seconds
Started Jul 11 05:34:37 PM PDT 24
Finished Jul 11 05:34:49 PM PDT 24
Peak memory 214316 kb
Host smart-5a1ae849-b4f1-4c83-b82a-77e115babd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140531955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1140531955
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1280753479
Short name T362
Test name
Test status
Simulation time 217995643 ps
CPU time 2.38 seconds
Started Jul 11 05:36:13 PM PDT 24
Finished Jul 11 05:36:17 PM PDT 24
Peak memory 214168 kb
Host smart-35621772-f782-4a48-a7f8-b93e561003e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280753479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1280753479
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2611188764
Short name T178
Test name
Test status
Simulation time 291098729 ps
CPU time 2.58 seconds
Started Jul 11 05:33:39 PM PDT 24
Finished Jul 11 05:33:44 PM PDT 24
Peak memory 210272 kb
Host smart-1b8b027d-668b-4f51-9651-028d736031d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611188764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2611188764
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2896051036
Short name T985
Test name
Test status
Simulation time 385320030 ps
CPU time 13.36 seconds
Started Jul 11 05:29:17 PM PDT 24
Finished Jul 11 05:29:31 PM PDT 24
Peak memory 214032 kb
Host smart-cef65a6b-810e-4276-a330-7bf4b0218a35
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896051036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2896051036
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.837903850
Short name T159
Test name
Test status
Simulation time 410479996 ps
CPU time 6.1 seconds
Started Jul 11 05:30:28 PM PDT 24
Finished Jul 11 05:30:38 PM PDT 24
Peak memory 213580 kb
Host smart-92689d78-fad6-41c7-8850-3e24bcc6532f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837903850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.837903850
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.694798341
Short name T272
Test name
Test status
Simulation time 2030794596 ps
CPU time 61.89 seconds
Started Jul 11 05:34:40 PM PDT 24
Finished Jul 11 05:35:51 PM PDT 24
Peak memory 222508 kb
Host smart-0f448b3e-64f0-4d8e-aaa3-4b2d93ae449f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694798341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.694798341
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2530136512
Short name T136
Test name
Test status
Simulation time 376575956 ps
CPU time 9.76 seconds
Started Jul 11 05:34:52 PM PDT 24
Finished Jul 11 05:35:09 PM PDT 24
Peak memory 214348 kb
Host smart-2564945e-d834-4d82-8063-8aa8be2a684d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2530136512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2530136512
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3456084332
Short name T341
Test name
Test status
Simulation time 104894803 ps
CPU time 4.68 seconds
Started Jul 11 05:34:47 PM PDT 24
Finished Jul 11 05:35:00 PM PDT 24
Peak memory 215352 kb
Host smart-a25bf305-0d72-45f0-8dea-00506111a9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456084332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3456084332
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3806164242
Short name T364
Test name
Test status
Simulation time 2462202800 ps
CPU time 56.7 seconds
Started Jul 11 05:33:33 PM PDT 24
Finished Jul 11 05:34:32 PM PDT 24
Peak memory 222560 kb
Host smart-7ffee142-5787-4e8c-876d-2689671f5cf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806164242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3806164242
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2978392123
Short name T288
Test name
Test status
Simulation time 57875650735 ps
CPU time 444.32 seconds
Started Jul 11 05:35:02 PM PDT 24
Finished Jul 11 05:42:32 PM PDT 24
Peak memory 217696 kb
Host smart-bf8293b5-1317-4aca-a165-03770d25fdb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978392123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2978392123
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3271425823
Short name T93
Test name
Test status
Simulation time 49081929 ps
CPU time 1.8 seconds
Started Jul 11 05:35:21 PM PDT 24
Finished Jul 11 05:35:27 PM PDT 24
Peak memory 214352 kb
Host smart-038e95a0-5261-4f63-9547-1cadfe339db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271425823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3271425823
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.521050059
Short name T28
Test name
Test status
Simulation time 1621821156 ps
CPU time 5.16 seconds
Started Jul 11 05:36:02 PM PDT 24
Finished Jul 11 05:36:11 PM PDT 24
Peak memory 214312 kb
Host smart-68c85b8c-7300-47af-b4c4-d908d5b481a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521050059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.521050059
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3260739197
Short name T150
Test name
Test status
Simulation time 96020966 ps
CPU time 2.95 seconds
Started Jul 11 05:33:58 PM PDT 24
Finished Jul 11 05:34:13 PM PDT 24
Peak memory 218040 kb
Host smart-b4a76afd-a393-4050-8d56-bbb5ba9cc0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260739197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3260739197
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1355684365
Short name T153
Test name
Test status
Simulation time 167318750 ps
CPU time 2.82 seconds
Started Jul 11 05:34:43 PM PDT 24
Finished Jul 11 05:34:54 PM PDT 24
Peak memory 218352 kb
Host smart-2726cbb6-9bec-41c4-88fe-2d92e85610f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355684365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1355684365
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3459805620
Short name T152
Test name
Test status
Simulation time 272326142 ps
CPU time 3.43 seconds
Started Jul 11 05:34:58 PM PDT 24
Finished Jul 11 05:35:07 PM PDT 24
Peak memory 217932 kb
Host smart-13f0903f-b987-471a-8ce4-16d5f48e8d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459805620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3459805620
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2838332873
Short name T151
Test name
Test status
Simulation time 57421970 ps
CPU time 1.61 seconds
Started Jul 11 05:35:06 PM PDT 24
Finished Jul 11 05:35:12 PM PDT 24
Peak memory 217088 kb
Host smart-b5a832d7-4522-4e1b-bcc3-69ccc0d54d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838332873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2838332873
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2586626714
Short name T287
Test name
Test status
Simulation time 409355615 ps
CPU time 5.89 seconds
Started Jul 11 05:33:49 PM PDT 24
Finished Jul 11 05:34:01 PM PDT 24
Peak memory 214524 kb
Host smart-25a62217-1e11-4a07-bba8-bd8e193a0c7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2586626714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2586626714
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2867535407
Short name T192
Test name
Test status
Simulation time 112523296 ps
CPU time 2.9 seconds
Started Jul 11 05:33:49 PM PDT 24
Finished Jul 11 05:33:58 PM PDT 24
Peak memory 206948 kb
Host smart-41fb5b61-578b-4523-8421-b450f1a6df50
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867535407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2867535407
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1492500680
Short name T69
Test name
Test status
Simulation time 425543244 ps
CPU time 3.54 seconds
Started Jul 11 05:33:59 PM PDT 24
Finished Jul 11 05:34:14 PM PDT 24
Peak memory 210340 kb
Host smart-6bdc3ea3-064b-4e23-8d05-8d283c35f807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492500680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1492500680
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1759044348
Short name T320
Test name
Test status
Simulation time 63426240 ps
CPU time 2.22 seconds
Started Jul 11 05:34:12 PM PDT 24
Finished Jul 11 05:34:28 PM PDT 24
Peak memory 214276 kb
Host smart-49a287ec-2618-442a-aff3-c8c089a2516f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759044348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1759044348
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_random.3282243991
Short name T211
Test name
Test status
Simulation time 219875702 ps
CPU time 5.93 seconds
Started Jul 11 05:34:14 PM PDT 24
Finished Jul 11 05:34:33 PM PDT 24
Peak memory 209448 kb
Host smart-a8aff4d4-271a-467e-a7dd-a0a413b2d0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282243991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3282243991
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2332761377
Short name T330
Test name
Test status
Simulation time 454256705 ps
CPU time 9.66 seconds
Started Jul 11 05:34:36 PM PDT 24
Finished Jul 11 05:34:55 PM PDT 24
Peak memory 214228 kb
Host smart-bcef7840-5ac5-4f32-8a3f-4b10eee0a6a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2332761377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2332761377
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1619375241
Short name T889
Test name
Test status
Simulation time 118753128 ps
CPU time 4.97 seconds
Started Jul 11 05:34:45 PM PDT 24
Finished Jul 11 05:34:58 PM PDT 24
Peak memory 215120 kb
Host smart-e63f7e4a-b433-4306-8c31-d55f9084c359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619375241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1619375241
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.791933625
Short name T338
Test name
Test status
Simulation time 97183836 ps
CPU time 3.36 seconds
Started Jul 11 05:34:50 PM PDT 24
Finished Jul 11 05:35:01 PM PDT 24
Peak memory 214276 kb
Host smart-7d1a0682-c10a-40de-92c7-7b0a7512d36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791933625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.791933625
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1256085264
Short name T666
Test name
Test status
Simulation time 253126365 ps
CPU time 6.9 seconds
Started Jul 11 05:35:00 PM PDT 24
Finished Jul 11 05:35:13 PM PDT 24
Peak memory 208660 kb
Host smart-81df8fcd-00bb-440b-a50c-17903208af90
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256085264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1256085264
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_random.3035075098
Short name T293
Test name
Test status
Simulation time 178022443 ps
CPU time 6.64 seconds
Started Jul 11 05:36:19 PM PDT 24
Finished Jul 11 05:36:29 PM PDT 24
Peak memory 209864 kb
Host smart-78c92b65-e07d-4205-aeb7-f05944690815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035075098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3035075098
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2327537431
Short name T414
Test name
Test status
Simulation time 2389788578 ps
CPU time 88.51 seconds
Started Jul 11 05:36:22 PM PDT 24
Finished Jul 11 05:37:54 PM PDT 24
Peak memory 214616 kb
Host smart-f850bee1-d234-46af-bd56-8fd40394da3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2327537431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2327537431
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2539540545
Short name T235
Test name
Test status
Simulation time 2120828661 ps
CPU time 26.6 seconds
Started Jul 11 05:33:48 PM PDT 24
Finished Jul 11 05:34:19 PM PDT 24
Peak memory 215228 kb
Host smart-29705ce5-6f98-457a-8c36-a66a570e7ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539540545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2539540545
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3080476470
Short name T165
Test name
Test status
Simulation time 273159060 ps
CPU time 6.99 seconds
Started Jul 11 05:29:30 PM PDT 24
Finished Jul 11 05:29:39 PM PDT 24
Peak memory 213716 kb
Host smart-ccae4e7e-f399-4c2d-9c7e-c34d432a7628
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080476470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3080476470
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.741024891
Short name T170
Test name
Test status
Simulation time 344637643 ps
CPU time 5.11 seconds
Started Jul 11 05:30:13 PM PDT 24
Finished Jul 11 05:30:21 PM PDT 24
Peak memory 213696 kb
Host smart-818939d6-e111-496c-9fe0-135353d12dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741024891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.741024891
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.716525775
Short name T160
Test name
Test status
Simulation time 348683696 ps
CPU time 5.2 seconds
Started Jul 11 05:30:14 PM PDT 24
Finished Jul 11 05:30:22 PM PDT 24
Peak memory 213660 kb
Host smart-ecec155a-7022-42e0-89d7-13125cb00c44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716525775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.716525775
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3220053833
Short name T166
Test name
Test status
Simulation time 168281749 ps
CPU time 2.97 seconds
Started Jul 11 05:30:12 PM PDT 24
Finished Jul 11 05:30:17 PM PDT 24
Peak memory 213700 kb
Host smart-3e613d6e-42bc-4d5c-9966-77ecf0de3506
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220053833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3220053833
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2284359498
Short name T175
Test name
Test status
Simulation time 431037787 ps
CPU time 3.59 seconds
Started Jul 11 05:30:18 PM PDT 24
Finished Jul 11 05:30:25 PM PDT 24
Peak memory 213720 kb
Host smart-ea5d733f-4380-4a7c-962e-c7d11d55102c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284359498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2284359498
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2117443078
Short name T168
Test name
Test status
Simulation time 501476360 ps
CPU time 3.73 seconds
Started Jul 11 05:29:42 PM PDT 24
Finished Jul 11 05:29:48 PM PDT 24
Peak memory 213636 kb
Host smart-c19542c0-a9a6-47be-9e7a-d7ea5257e010
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117443078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2117443078
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1741979589
Short name T11
Test name
Test status
Simulation time 849633298 ps
CPU time 11.31 seconds
Started Jul 11 05:32:57 PM PDT 24
Finished Jul 11 05:33:10 PM PDT 24
Peak memory 229792 kb
Host smart-5435b18e-d635-4462-94a8-bc766020913c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741979589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1741979589
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1975773479
Short name T75
Test name
Test status
Simulation time 100523082 ps
CPU time 4.94 seconds
Started Jul 11 05:35:36 PM PDT 24
Finished Jul 11 05:35:49 PM PDT 24
Peak memory 223080 kb
Host smart-8ca720a2-96b5-4110-b4e3-c946fe165e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975773479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1975773479
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2800479067
Short name T241
Test name
Test status
Simulation time 220579967 ps
CPU time 10.86 seconds
Started Jul 11 05:34:07 PM PDT 24
Finished Jul 11 05:34:31 PM PDT 24
Peak memory 214996 kb
Host smart-92efe9fd-d73e-4e26-a5db-e687d7d27498
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800479067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2800479067
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3748296480
Short name T236
Test name
Test status
Simulation time 5306160564 ps
CPU time 18.2 seconds
Started Jul 11 05:34:11 PM PDT 24
Finished Jul 11 05:34:42 PM PDT 24
Peak memory 221456 kb
Host smart-b8d40efa-4c65-46eb-bcd5-03adbe21d08f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748296480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3748296480
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2762175748
Short name T368
Test name
Test status
Simulation time 348334076 ps
CPU time 2.5 seconds
Started Jul 11 05:34:22 PM PDT 24
Finished Jul 11 05:34:36 PM PDT 24
Peak memory 206948 kb
Host smart-cb3da5f9-7aff-4431-aa44-ab573114556a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762175748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2762175748
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1107162117
Short name T80
Test name
Test status
Simulation time 329596243 ps
CPU time 13.87 seconds
Started Jul 11 05:34:36 PM PDT 24
Finished Jul 11 05:35:00 PM PDT 24
Peak memory 222716 kb
Host smart-b9ce09ce-ebe8-4d7d-aa2b-af37c5bddc96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107162117 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1107162117
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1423591531
Short name T246
Test name
Test status
Simulation time 113367649 ps
CPU time 4.31 seconds
Started Jul 11 05:34:44 PM PDT 24
Finished Jul 11 05:34:56 PM PDT 24
Peak memory 215448 kb
Host smart-6f794e34-3d93-4419-9633-62efecd3fa89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1423591531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1423591531
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.623944244
Short name T184
Test name
Test status
Simulation time 2716023996 ps
CPU time 22.8 seconds
Started Jul 11 05:34:52 PM PDT 24
Finished Jul 11 05:35:23 PM PDT 24
Peak memory 221292 kb
Host smart-9dd05e03-c68b-43da-8bdf-e6884d0beb2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623944244 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.623944244
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3557750211
Short name T226
Test name
Test status
Simulation time 131985327 ps
CPU time 4.94 seconds
Started Jul 11 05:35:04 PM PDT 24
Finished Jul 11 05:35:15 PM PDT 24
Peak memory 222836 kb
Host smart-7269cd5a-0072-4c01-8413-bc757e517c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557750211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3557750211
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1692808123
Short name T360
Test name
Test status
Simulation time 185182628 ps
CPU time 2.72 seconds
Started Jul 11 05:35:13 PM PDT 24
Finished Jul 11 05:35:20 PM PDT 24
Peak memory 222396 kb
Host smart-90ab2c51-65d3-4e28-a967-f37ee5617125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692808123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1692808123
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.4070167299
Short name T233
Test name
Test status
Simulation time 348034017 ps
CPU time 4.45 seconds
Started Jul 11 05:36:01 PM PDT 24
Finished Jul 11 05:36:09 PM PDT 24
Peak memory 209272 kb
Host smart-f6fe603b-edc8-4a4a-a349-b7d7d6d84a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070167299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.4070167299
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3682943810
Short name T18
Test name
Test status
Simulation time 310525760 ps
CPU time 4.14 seconds
Started Jul 11 05:33:50 PM PDT 24
Finished Jul 11 05:34:00 PM PDT 24
Peak memory 208908 kb
Host smart-1ecec7e5-6a26-44d4-91b9-84d781fd58e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682943810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3682943810
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1669187453
Short name T60
Test name
Test status
Simulation time 252164138 ps
CPU time 3.62 seconds
Started Jul 11 05:33:52 PM PDT 24
Finished Jul 11 05:34:03 PM PDT 24
Peak memory 214456 kb
Host smart-3d085a9d-cd88-4d2e-98a9-3b02cb5b35e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669187453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1669187453
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1447811932
Short name T147
Test name
Test status
Simulation time 1750997190 ps
CPU time 3.36 seconds
Started Jul 11 05:35:04 PM PDT 24
Finished Jul 11 05:35:13 PM PDT 24
Peak memory 222600 kb
Host smart-e33adbcd-6d72-4d63-bc30-c8ccf16ccf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447811932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1447811932
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3822850812
Short name T155
Test name
Test status
Simulation time 1171567729 ps
CPU time 9.09 seconds
Started Jul 11 05:29:22 PM PDT 24
Finished Jul 11 05:29:32 PM PDT 24
Peak memory 205408 kb
Host smart-300c1128-c190-45fd-9a53-6e2624f5bdc5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822850812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
822850812
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3319803095
Short name T1040
Test name
Test status
Simulation time 3335730919 ps
CPU time 12.76 seconds
Started Jul 11 05:29:16 PM PDT 24
Finished Jul 11 05:29:30 PM PDT 24
Peak memory 205484 kb
Host smart-889bc9e7-726b-4193-8ec3-d0b996957236
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319803095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
319803095
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3780314784
Short name T1078
Test name
Test status
Simulation time 389832440 ps
CPU time 1.46 seconds
Started Jul 11 05:29:16 PM PDT 24
Finished Jul 11 05:29:19 PM PDT 24
Peak memory 205516 kb
Host smart-8c2e874e-b9a5-4fb2-a357-211b28c80258
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780314784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
780314784
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3241953232
Short name T1024
Test name
Test status
Simulation time 46952147 ps
CPU time 1.26 seconds
Started Jul 11 05:29:22 PM PDT 24
Finished Jul 11 05:29:24 PM PDT 24
Peak memory 213768 kb
Host smart-03be23e5-f7d5-4979-9978-fcf7bda64a5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241953232 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3241953232
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.374187076
Short name T1013
Test name
Test status
Simulation time 18437505 ps
CPU time 1.09 seconds
Started Jul 11 05:29:15 PM PDT 24
Finished Jul 11 05:29:17 PM PDT 24
Peak memory 205480 kb
Host smart-52a6ec79-0478-4413-84c6-ac63ef5ae84a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374187076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.374187076
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1137861004
Short name T1015
Test name
Test status
Simulation time 37778600 ps
CPU time 0.77 seconds
Started Jul 11 05:29:16 PM PDT 24
Finished Jul 11 05:29:19 PM PDT 24
Peak memory 205236 kb
Host smart-1ed2e26a-0651-4d8a-bfdc-5f3e904ba413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137861004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1137861004
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2694773457
Short name T137
Test name
Test status
Simulation time 70399489 ps
CPU time 2.5 seconds
Started Jul 11 05:29:24 PM PDT 24
Finished Jul 11 05:29:27 PM PDT 24
Peak memory 205440 kb
Host smart-bd907803-708b-49f7-b1aa-231c5b9cadac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694773457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2694773457
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2539497469
Short name T995
Test name
Test status
Simulation time 51869250 ps
CPU time 1.24 seconds
Started Jul 11 05:29:15 PM PDT 24
Finished Jul 11 05:29:17 PM PDT 24
Peak memory 213984 kb
Host smart-4e791f01-8855-4a1b-bc74-23177ddf17b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539497469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2539497469
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2892647277
Short name T931
Test name
Test status
Simulation time 114286242 ps
CPU time 3.77 seconds
Started Jul 11 05:29:14 PM PDT 24
Finished Jul 11 05:29:20 PM PDT 24
Peak memory 215720 kb
Host smart-d47bc543-37d7-403d-a788-ef0d6489975b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892647277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2892647277
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.461298773
Short name T957
Test name
Test status
Simulation time 72598829 ps
CPU time 4.15 seconds
Started Jul 11 05:29:20 PM PDT 24
Finished Jul 11 05:29:25 PM PDT 24
Peak memory 205388 kb
Host smart-89e069ca-d8f0-42a2-b92b-6e04281c849a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461298773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.461298773
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.473385307
Short name T952
Test name
Test status
Simulation time 2580332548 ps
CPU time 17.49 seconds
Started Jul 11 05:29:21 PM PDT 24
Finished Jul 11 05:29:39 PM PDT 24
Peak memory 205580 kb
Host smart-3fdc759d-c95d-405e-be37-ee5c2abbd47c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473385307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.473385307
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2194653678
Short name T1037
Test name
Test status
Simulation time 30372135 ps
CPU time 1.19 seconds
Started Jul 11 05:29:19 PM PDT 24
Finished Jul 11 05:29:21 PM PDT 24
Peak memory 205552 kb
Host smart-a4f8fd22-1320-4f30-90e0-7d7fef7d3fd8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194653678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
194653678
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1700141253
Short name T1069
Test name
Test status
Simulation time 35306547 ps
CPU time 2.38 seconds
Started Jul 11 05:29:30 PM PDT 24
Finished Jul 11 05:29:34 PM PDT 24
Peak memory 213784 kb
Host smart-486b7d7a-8805-47d8-8023-cee097506e18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700141253 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1700141253
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3579797824
Short name T1043
Test name
Test status
Simulation time 49837778 ps
CPU time 1.15 seconds
Started Jul 11 05:29:19 PM PDT 24
Finished Jul 11 05:29:21 PM PDT 24
Peak memory 205376 kb
Host smart-65ecbcef-de33-45df-a4eb-c494e0b4b30d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579797824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3579797824
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2672120312
Short name T993
Test name
Test status
Simulation time 87436505 ps
CPU time 0.78 seconds
Started Jul 11 05:29:24 PM PDT 24
Finished Jul 11 05:29:26 PM PDT 24
Peak memory 205340 kb
Host smart-4751f71b-391f-47ed-a6a6-bafe21e4c075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672120312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2672120312
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.196875317
Short name T967
Test name
Test status
Simulation time 453472233 ps
CPU time 2.29 seconds
Started Jul 11 05:29:20 PM PDT 24
Finished Jul 11 05:29:24 PM PDT 24
Peak memory 205516 kb
Host smart-ec96eb9e-ee2d-4469-aa36-2e8f578a5fd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196875317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.196875317
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1039448642
Short name T974
Test name
Test status
Simulation time 150581040 ps
CPU time 3.13 seconds
Started Jul 11 05:29:30 PM PDT 24
Finished Jul 11 05:29:35 PM PDT 24
Peak memory 214028 kb
Host smart-de8689af-9d57-4ae0-86c8-615ed22e18ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039448642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1039448642
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3574174014
Short name T109
Test name
Test status
Simulation time 687473885 ps
CPU time 7.08 seconds
Started Jul 11 05:29:25 PM PDT 24
Finished Jul 11 05:29:33 PM PDT 24
Peak memory 220204 kb
Host smart-f041646b-0ca6-4690-ab85-5850e5522130
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574174014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3574174014
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4096088431
Short name T1072
Test name
Test status
Simulation time 44698880 ps
CPU time 2.65 seconds
Started Jul 11 05:29:30 PM PDT 24
Finished Jul 11 05:29:35 PM PDT 24
Peak memory 213684 kb
Host smart-95f7a74e-99d7-404b-9908-7372890daf1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096088431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4096088431
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.918338108
Short name T939
Test name
Test status
Simulation time 42951130 ps
CPU time 1.31 seconds
Started Jul 11 05:30:14 PM PDT 24
Finished Jul 11 05:30:17 PM PDT 24
Peak memory 205528 kb
Host smart-32d25f7f-84f9-46fc-814a-344006de51a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918338108 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.918338108
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3982406390
Short name T1034
Test name
Test status
Simulation time 61792726 ps
CPU time 0.95 seconds
Started Jul 11 05:30:15 PM PDT 24
Finished Jul 11 05:30:20 PM PDT 24
Peak memory 205460 kb
Host smart-30ead3ce-944e-4b48-9b46-97ab7db45137
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982406390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3982406390
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.4220372109
Short name T921
Test name
Test status
Simulation time 10473029 ps
CPU time 0.83 seconds
Started Jul 11 05:30:16 PM PDT 24
Finished Jul 11 05:30:21 PM PDT 24
Peak memory 205256 kb
Host smart-20e40d59-70ed-4ea7-b891-15aa03b0198b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220372109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.4220372109
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.395217473
Short name T994
Test name
Test status
Simulation time 187028127 ps
CPU time 1.91 seconds
Started Jul 11 05:30:12 PM PDT 24
Finished Jul 11 05:30:17 PM PDT 24
Peak memory 205536 kb
Host smart-0b53567d-87f3-41d2-9b21-fb66edd8d125
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395217473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.395217473
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1680561917
Short name T107
Test name
Test status
Simulation time 109176736 ps
CPU time 1.25 seconds
Started Jul 11 05:30:05 PM PDT 24
Finished Jul 11 05:30:09 PM PDT 24
Peak memory 213988 kb
Host smart-1d5847ab-6862-4b06-9b06-463234c09b57
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680561917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1680561917
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.464050257
Short name T1041
Test name
Test status
Simulation time 79096561 ps
CPU time 3.63 seconds
Started Jul 11 05:30:08 PM PDT 24
Finished Jul 11 05:30:13 PM PDT 24
Peak memory 214040 kb
Host smart-0b72a05e-43cf-4c4f-99c2-9c9cbf52e86b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464050257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.464050257
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.771411831
Short name T1056
Test name
Test status
Simulation time 317751633 ps
CPU time 5.86 seconds
Started Jul 11 05:30:14 PM PDT 24
Finished Jul 11 05:30:24 PM PDT 24
Peak memory 213636 kb
Host smart-4ea6728e-378a-4029-a90e-a48341e15866
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771411831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.771411831
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3958349032
Short name T1079
Test name
Test status
Simulation time 200206420 ps
CPU time 1.4 seconds
Started Jul 11 05:30:12 PM PDT 24
Finished Jul 11 05:30:16 PM PDT 24
Peak memory 205604 kb
Host smart-653c6a51-0db5-44ef-8a50-492e8e126b08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958349032 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3958349032
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.4152662701
Short name T1065
Test name
Test status
Simulation time 115322955 ps
CPU time 1.15 seconds
Started Jul 11 05:30:14 PM PDT 24
Finished Jul 11 05:30:19 PM PDT 24
Peak memory 205392 kb
Host smart-964f9543-f3c4-4705-a328-907fed8ff995
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152662701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.4152662701
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.368733548
Short name T953
Test name
Test status
Simulation time 23541116 ps
CPU time 0.74 seconds
Started Jul 11 05:30:11 PM PDT 24
Finished Jul 11 05:30:14 PM PDT 24
Peak memory 205240 kb
Host smart-d453ba82-013b-44b8-baa5-3c56814de69a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368733548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.368733548
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.114719631
Short name T1060
Test name
Test status
Simulation time 141391214 ps
CPU time 1.63 seconds
Started Jul 11 05:30:17 PM PDT 24
Finished Jul 11 05:30:23 PM PDT 24
Peak memory 205396 kb
Host smart-7f9acb5d-760a-4f26-be29-ca9b3f23f7e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114719631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.114719631
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.469688142
Short name T1053
Test name
Test status
Simulation time 421372252 ps
CPU time 2.42 seconds
Started Jul 11 05:30:13 PM PDT 24
Finished Jul 11 05:30:18 PM PDT 24
Peak memory 213928 kb
Host smart-e6262d30-a20c-4dbe-9353-e28ffe3ef284
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469688142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.469688142
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3716553076
Short name T991
Test name
Test status
Simulation time 677688859 ps
CPU time 8.43 seconds
Started Jul 11 05:30:16 PM PDT 24
Finished Jul 11 05:30:28 PM PDT 24
Peak memory 220708 kb
Host smart-0865269d-5c53-4ff0-9f83-74c3dc637f9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716553076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3716553076
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1815904509
Short name T936
Test name
Test status
Simulation time 144858647 ps
CPU time 3.73 seconds
Started Jul 11 05:30:15 PM PDT 24
Finished Jul 11 05:30:22 PM PDT 24
Peak memory 213684 kb
Host smart-450b0de8-af14-474a-825c-ee60c718a6cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815904509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1815904509
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2476238675
Short name T1073
Test name
Test status
Simulation time 857949266 ps
CPU time 3.68 seconds
Started Jul 11 05:30:12 PM PDT 24
Finished Jul 11 05:30:17 PM PDT 24
Peak memory 213760 kb
Host smart-8da2c416-8190-4efa-b3fb-62f545e8c551
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476238675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2476238675
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3180857977
Short name T1005
Test name
Test status
Simulation time 43030821 ps
CPU time 1.61 seconds
Started Jul 11 05:30:12 PM PDT 24
Finished Jul 11 05:30:17 PM PDT 24
Peak memory 213724 kb
Host smart-af8fa702-f0d7-496c-adda-57b76ed44651
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180857977 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3180857977
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3498760844
Short name T933
Test name
Test status
Simulation time 59230473 ps
CPU time 0.95 seconds
Started Jul 11 05:30:18 PM PDT 24
Finished Jul 11 05:30:22 PM PDT 24
Peak memory 205456 kb
Host smart-a2a3ba05-dcd5-41f7-bef1-281a0a95b66e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498760844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3498760844
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2986947569
Short name T932
Test name
Test status
Simulation time 39409921 ps
CPU time 0.71 seconds
Started Jul 11 05:30:13 PM PDT 24
Finished Jul 11 05:30:16 PM PDT 24
Peak memory 205388 kb
Host smart-fb4f19b8-ace2-46c2-8517-89c5d73689f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986947569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2986947569
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3043537955
Short name T1026
Test name
Test status
Simulation time 122497992 ps
CPU time 2.47 seconds
Started Jul 11 05:30:18 PM PDT 24
Finished Jul 11 05:30:24 PM PDT 24
Peak memory 205580 kb
Host smart-823760c0-683a-42ca-8a6f-3fb16acc3df3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043537955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3043537955
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1187581899
Short name T1029
Test name
Test status
Simulation time 955362509 ps
CPU time 2.59 seconds
Started Jul 11 05:30:12 PM PDT 24
Finished Jul 11 05:30:17 PM PDT 24
Peak memory 213952 kb
Host smart-d72fb67f-10cd-4bd5-b0d6-1997711d3892
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187581899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1187581899
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.965878679
Short name T969
Test name
Test status
Simulation time 78155125 ps
CPU time 4.28 seconds
Started Jul 11 05:30:17 PM PDT 24
Finished Jul 11 05:30:25 PM PDT 24
Peak memory 213976 kb
Host smart-716da8b9-3e26-4f12-bb41-0c34be26677f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965878679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.965878679
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2941264482
Short name T978
Test name
Test status
Simulation time 117780380 ps
CPU time 2.14 seconds
Started Jul 11 05:30:14 PM PDT 24
Finished Jul 11 05:30:20 PM PDT 24
Peak memory 213672 kb
Host smart-88dbf2d8-46bd-4560-b80a-658e3447e450
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941264482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2941264482
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1821616974
Short name T940
Test name
Test status
Simulation time 23002534 ps
CPU time 1.59 seconds
Started Jul 11 05:30:27 PM PDT 24
Finished Jul 11 05:30:33 PM PDT 24
Peak memory 213748 kb
Host smart-24f5ab22-90ac-4c14-b035-ccf03e7528ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821616974 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1821616974
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1287107701
Short name T1020
Test name
Test status
Simulation time 15337519 ps
CPU time 0.99 seconds
Started Jul 11 05:30:12 PM PDT 24
Finished Jul 11 05:30:15 PM PDT 24
Peak memory 205452 kb
Host smart-78cf165e-f01f-46da-b4aa-7c63fb6ba168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287107701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1287107701
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1583933424
Short name T1023
Test name
Test status
Simulation time 45317863 ps
CPU time 0.85 seconds
Started Jul 11 05:30:19 PM PDT 24
Finished Jul 11 05:30:24 PM PDT 24
Peak memory 205344 kb
Host smart-90ab402a-cde6-479c-97c0-c0782ad0d016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583933424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1583933424
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2030954297
Short name T963
Test name
Test status
Simulation time 23713597 ps
CPU time 1.34 seconds
Started Jul 11 05:30:20 PM PDT 24
Finished Jul 11 05:30:26 PM PDT 24
Peak memory 205572 kb
Host smart-e4cc0a0d-0c3e-4ae1-84ae-f5bed4273e3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030954297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2030954297
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.885201605
Short name T976
Test name
Test status
Simulation time 364465432 ps
CPU time 2.03 seconds
Started Jul 11 05:30:16 PM PDT 24
Finished Jul 11 05:30:22 PM PDT 24
Peak memory 214036 kb
Host smart-1f8dd002-d8b3-4312-91f7-5c0b0447ebee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885201605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.885201605
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4109379618
Short name T980
Test name
Test status
Simulation time 329882238 ps
CPU time 12.02 seconds
Started Jul 11 05:30:12 PM PDT 24
Finished Jul 11 05:30:27 PM PDT 24
Peak memory 213956 kb
Host smart-c9086f72-bbea-4e51-a049-5fbffd008716
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109379618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.4109379618
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.250160753
Short name T984
Test name
Test status
Simulation time 40236652 ps
CPU time 2.62 seconds
Started Jul 11 05:30:19 PM PDT 24
Finished Jul 11 05:30:26 PM PDT 24
Peak memory 213756 kb
Host smart-dde5b39c-471f-4506-9a37-92096bbc4ff6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250160753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.250160753
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.123018580
Short name T938
Test name
Test status
Simulation time 46859742 ps
CPU time 1.1 seconds
Started Jul 11 05:30:17 PM PDT 24
Finished Jul 11 05:30:22 PM PDT 24
Peak memory 205468 kb
Host smart-e00ce81e-8da0-4cb4-9bb2-985de0e0ff56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123018580 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.123018580
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2590026637
Short name T142
Test name
Test status
Simulation time 47535167 ps
CPU time 1.01 seconds
Started Jul 11 05:30:27 PM PDT 24
Finished Jul 11 05:30:32 PM PDT 24
Peak memory 205320 kb
Host smart-8894a2a7-47f4-4c87-a890-ccb5fc72d819
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590026637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2590026637
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.869874489
Short name T990
Test name
Test status
Simulation time 11106588 ps
CPU time 0.75 seconds
Started Jul 11 05:30:20 PM PDT 24
Finished Jul 11 05:30:26 PM PDT 24
Peak memory 205236 kb
Host smart-578826ee-437a-46f0-b3bb-4d3c86043d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869874489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.869874489
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1363699177
Short name T140
Test name
Test status
Simulation time 119796915 ps
CPU time 2.29 seconds
Started Jul 11 05:30:22 PM PDT 24
Finished Jul 11 05:30:29 PM PDT 24
Peak memory 205464 kb
Host smart-610d2ee5-d523-4989-a176-5f025f50e931
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363699177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1363699177
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3465311111
Short name T1039
Test name
Test status
Simulation time 161571826 ps
CPU time 3.32 seconds
Started Jul 11 05:30:18 PM PDT 24
Finished Jul 11 05:30:25 PM PDT 24
Peak memory 214020 kb
Host smart-34e80ccd-a962-4b39-9d42-e543367714f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465311111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3465311111
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2238646911
Short name T1077
Test name
Test status
Simulation time 251570032 ps
CPU time 9.15 seconds
Started Jul 11 05:30:16 PM PDT 24
Finished Jul 11 05:30:29 PM PDT 24
Peak memory 220012 kb
Host smart-de482015-5b80-434f-9ed0-35496c747fbc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238646911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2238646911
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.938151612
Short name T1014
Test name
Test status
Simulation time 48980736 ps
CPU time 1.32 seconds
Started Jul 11 05:30:19 PM PDT 24
Finished Jul 11 05:30:25 PM PDT 24
Peak memory 213668 kb
Host smart-d210e6f0-5aba-4e04-bb44-e2dbf76e2e51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938151612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.938151612
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1341104332
Short name T961
Test name
Test status
Simulation time 52371546 ps
CPU time 1.96 seconds
Started Jul 11 05:30:17 PM PDT 24
Finished Jul 11 05:30:23 PM PDT 24
Peak memory 213788 kb
Host smart-35301cb6-3e69-4394-a90a-3b0d13005688
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341104332 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1341104332
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1823916441
Short name T1057
Test name
Test status
Simulation time 40080036 ps
CPU time 1 seconds
Started Jul 11 05:30:17 PM PDT 24
Finished Jul 11 05:30:22 PM PDT 24
Peak memory 205380 kb
Host smart-623561b5-4516-418e-917d-b927493b6d0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823916441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1823916441
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2173074434
Short name T1067
Test name
Test status
Simulation time 13498698 ps
CPU time 0.77 seconds
Started Jul 11 05:30:18 PM PDT 24
Finished Jul 11 05:30:22 PM PDT 24
Peak memory 205344 kb
Host smart-77d6f80b-4684-4f92-ad33-b55372ed09f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173074434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2173074434
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2728941132
Short name T1030
Test name
Test status
Simulation time 50981285 ps
CPU time 2.27 seconds
Started Jul 11 05:30:20 PM PDT 24
Finished Jul 11 05:30:27 PM PDT 24
Peak memory 205440 kb
Host smart-620d8fd0-042f-42d9-b52b-3b4e9d438716
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728941132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2728941132
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.724477114
Short name T111
Test name
Test status
Simulation time 362820412 ps
CPU time 1.99 seconds
Started Jul 11 05:30:27 PM PDT 24
Finished Jul 11 05:30:33 PM PDT 24
Peak memory 213992 kb
Host smart-5d0f15a2-70b2-482a-bf26-12a617f61830
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724477114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.724477114
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2416668533
Short name T1085
Test name
Test status
Simulation time 409512405 ps
CPU time 15.28 seconds
Started Jul 11 05:30:17 PM PDT 24
Finished Jul 11 05:30:36 PM PDT 24
Peak memory 214032 kb
Host smart-7ca36676-533c-40e5-8473-995662ea22c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416668533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2416668533
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1899025595
Short name T997
Test name
Test status
Simulation time 181471556 ps
CPU time 3.04 seconds
Started Jul 11 05:30:19 PM PDT 24
Finished Jul 11 05:30:27 PM PDT 24
Peak memory 213788 kb
Host smart-9766860d-cc55-43ed-a19f-15f68c07a635
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899025595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1899025595
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3347650218
Short name T1009
Test name
Test status
Simulation time 255467358 ps
CPU time 1.23 seconds
Started Jul 11 05:30:20 PM PDT 24
Finished Jul 11 05:30:26 PM PDT 24
Peak memory 205568 kb
Host smart-206ef8e3-28ed-4cc3-923a-2966a29069e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347650218 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3347650218
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2700679226
Short name T143
Test name
Test status
Simulation time 28043571 ps
CPU time 1.19 seconds
Started Jul 11 05:30:18 PM PDT 24
Finished Jul 11 05:30:22 PM PDT 24
Peak memory 205412 kb
Host smart-6a266b92-d0fe-4b73-abd5-bcf2a827dc28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700679226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2700679226
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.4115093637
Short name T929
Test name
Test status
Simulation time 7899823 ps
CPU time 0.8 seconds
Started Jul 11 05:30:27 PM PDT 24
Finished Jul 11 05:30:33 PM PDT 24
Peak memory 205208 kb
Host smart-4f74f939-a140-4a11-97ff-3ea7112b7a0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115093637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.4115093637
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.4099592453
Short name T1070
Test name
Test status
Simulation time 37039169 ps
CPU time 2.06 seconds
Started Jul 11 05:30:27 PM PDT 24
Finished Jul 11 05:30:33 PM PDT 24
Peak memory 205548 kb
Host smart-58dd68aa-de95-499c-8782-df783a51e3e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099592453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.4099592453
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.566664539
Short name T1074
Test name
Test status
Simulation time 171048667 ps
CPU time 3.24 seconds
Started Jul 11 05:30:19 PM PDT 24
Finished Jul 11 05:30:26 PM PDT 24
Peak memory 213988 kb
Host smart-29cc9ad5-54ca-4553-a530-2b6a3f05a072
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566664539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.566664539
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.4014325504
Short name T1025
Test name
Test status
Simulation time 1671658356 ps
CPU time 6.35 seconds
Started Jul 11 05:30:18 PM PDT 24
Finished Jul 11 05:30:28 PM PDT 24
Peak memory 214036 kb
Host smart-cc7be6e5-9ba5-41ef-9c39-7eee51893273
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014325504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.4014325504
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.957109879
Short name T958
Test name
Test status
Simulation time 74856392 ps
CPU time 2.86 seconds
Started Jul 11 05:30:18 PM PDT 24
Finished Jul 11 05:30:25 PM PDT 24
Peak memory 213660 kb
Host smart-0e9b6367-33e5-471d-95b9-abf06ffffee3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957109879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.957109879
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1936452849
Short name T179
Test name
Test status
Simulation time 998048464 ps
CPU time 5.83 seconds
Started Jul 11 05:30:19 PM PDT 24
Finished Jul 11 05:30:29 PM PDT 24
Peak memory 205508 kb
Host smart-88949d2f-57df-46cf-ae9f-b4d66bf0bc69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936452849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1936452849
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3356278135
Short name T923
Test name
Test status
Simulation time 37530707 ps
CPU time 1.84 seconds
Started Jul 11 05:30:25 PM PDT 24
Finished Jul 11 05:30:32 PM PDT 24
Peak memory 213788 kb
Host smart-ddc2c84c-f4a9-4c9c-b498-464eeb720ffb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356278135 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3356278135
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.336895451
Short name T1032
Test name
Test status
Simulation time 44405429 ps
CPU time 1.27 seconds
Started Jul 11 05:30:24 PM PDT 24
Finished Jul 11 05:30:31 PM PDT 24
Peak memory 205400 kb
Host smart-fb6e0f22-e86f-4c7f-a6fe-754c95e2e722
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336895451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.336895451
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3365750992
Short name T1021
Test name
Test status
Simulation time 24434314 ps
CPU time 0.73 seconds
Started Jul 11 05:30:25 PM PDT 24
Finished Jul 11 05:30:31 PM PDT 24
Peak memory 205264 kb
Host smart-292874dd-d7da-46e1-811a-c6c9fcb2e0ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365750992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3365750992
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1655077183
Short name T1042
Test name
Test status
Simulation time 95557728 ps
CPU time 1.42 seconds
Started Jul 11 05:30:28 PM PDT 24
Finished Jul 11 05:30:33 PM PDT 24
Peak memory 205420 kb
Host smart-86c589cc-6a4d-4ef7-8a46-562ec5dfb6e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655077183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1655077183
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1818395197
Short name T115
Test name
Test status
Simulation time 528109769 ps
CPU time 17.52 seconds
Started Jul 11 05:30:25 PM PDT 24
Finished Jul 11 05:30:48 PM PDT 24
Peak memory 214016 kb
Host smart-5ac43705-d8a0-4096-bbd8-33b845592558
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818395197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1818395197
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3378266748
Short name T1068
Test name
Test status
Simulation time 80576031 ps
CPU time 2.86 seconds
Started Jul 11 05:30:24 PM PDT 24
Finished Jul 11 05:30:32 PM PDT 24
Peak memory 213648 kb
Host smart-8ff3fb5f-4b39-475b-9a81-59098c64eaf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378266748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3378266748
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3931349297
Short name T975
Test name
Test status
Simulation time 173007875 ps
CPU time 2.72 seconds
Started Jul 11 05:30:28 PM PDT 24
Finished Jul 11 05:30:34 PM PDT 24
Peak memory 213620 kb
Host smart-705eac60-ab86-4f2c-873f-59922c7959d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931349297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3931349297
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.4042036395
Short name T948
Test name
Test status
Simulation time 123044670 ps
CPU time 1.9 seconds
Started Jul 11 05:30:27 PM PDT 24
Finished Jul 11 05:30:33 PM PDT 24
Peak memory 218500 kb
Host smart-0be92e59-d89e-4ae7-947f-8727f37c252b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042036395 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.4042036395
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.577021273
Short name T1016
Test name
Test status
Simulation time 59436344 ps
CPU time 0.99 seconds
Started Jul 11 05:30:24 PM PDT 24
Finished Jul 11 05:30:30 PM PDT 24
Peak memory 205360 kb
Host smart-81426750-6c16-48a7-9182-7d7ba44e4524
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577021273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.577021273
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.446777971
Short name T1011
Test name
Test status
Simulation time 10825211 ps
CPU time 0.74 seconds
Started Jul 11 05:30:23 PM PDT 24
Finished Jul 11 05:30:29 PM PDT 24
Peak memory 205268 kb
Host smart-b48fbed3-b82e-4405-b725-b48041bb8f14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446777971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.446777971
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1518844802
Short name T1050
Test name
Test status
Simulation time 674247408 ps
CPU time 3.43 seconds
Started Jul 11 05:30:24 PM PDT 24
Finished Jul 11 05:30:32 PM PDT 24
Peak memory 205424 kb
Host smart-ecccb0cf-8584-4793-bfd3-442383337ae5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518844802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1518844802
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3290418416
Short name T1033
Test name
Test status
Simulation time 438523821 ps
CPU time 1.63 seconds
Started Jul 11 05:30:23 PM PDT 24
Finished Jul 11 05:30:30 PM PDT 24
Peak memory 213916 kb
Host smart-0bccaed0-882d-4209-bdaa-97ec9dd85916
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290418416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3290418416
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2350420126
Short name T1089
Test name
Test status
Simulation time 1506957035 ps
CPU time 3.72 seconds
Started Jul 11 05:30:23 PM PDT 24
Finished Jul 11 05:30:32 PM PDT 24
Peak memory 213932 kb
Host smart-18d814dd-7ff8-4b9d-8182-55820af2424f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350420126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2350420126
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.6140887
Short name T930
Test name
Test status
Simulation time 105386370 ps
CPU time 2.75 seconds
Started Jul 11 05:30:27 PM PDT 24
Finished Jul 11 05:30:34 PM PDT 24
Peak memory 213600 kb
Host smart-c1ec98c9-c739-44f9-b2b6-11ecde48485a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6140887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.6140887
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.364748893
Short name T971
Test name
Test status
Simulation time 46998809 ps
CPU time 1.61 seconds
Started Jul 11 05:30:30 PM PDT 24
Finished Jul 11 05:30:35 PM PDT 24
Peak memory 213760 kb
Host smart-2a46c09a-6765-4a3d-a949-586bf35ab679
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364748893 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.364748893
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.869049567
Short name T1019
Test name
Test status
Simulation time 24813826 ps
CPU time 1 seconds
Started Jul 11 05:30:32 PM PDT 24
Finished Jul 11 05:30:36 PM PDT 24
Peak memory 205308 kb
Host smart-dc3baa4d-df95-43ea-ba2b-713e88d1cca0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869049567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.869049567
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2439496090
Short name T962
Test name
Test status
Simulation time 44144539 ps
CPU time 0.79 seconds
Started Jul 11 05:30:32 PM PDT 24
Finished Jul 11 05:30:36 PM PDT 24
Peak memory 205148 kb
Host smart-159a88b0-f788-48f5-a602-e058b5343580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439496090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2439496090
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1582281545
Short name T1028
Test name
Test status
Simulation time 145501937 ps
CPU time 2.02 seconds
Started Jul 11 05:30:29 PM PDT 24
Finished Jul 11 05:30:34 PM PDT 24
Peak memory 205572 kb
Host smart-a6c956f6-cf95-4b8f-90a8-cbab2be5f07a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582281545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1582281545
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2126631099
Short name T114
Test name
Test status
Simulation time 322321550 ps
CPU time 2.53 seconds
Started Jul 11 05:30:24 PM PDT 24
Finished Jul 11 05:30:31 PM PDT 24
Peak memory 213968 kb
Host smart-4bc13a28-4710-4f25-9761-a25f82d8aeab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126631099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2126631099
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.297539160
Short name T113
Test name
Test status
Simulation time 2399912333 ps
CPU time 5.86 seconds
Started Jul 11 05:30:32 PM PDT 24
Finished Jul 11 05:30:40 PM PDT 24
Peak memory 214100 kb
Host smart-5fc03bc0-ce0d-4536-bfef-ff7030c296cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297539160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.297539160
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.33408084
Short name T1088
Test name
Test status
Simulation time 62403275 ps
CPU time 1.87 seconds
Started Jul 11 05:30:47 PM PDT 24
Finished Jul 11 05:30:51 PM PDT 24
Peak memory 221976 kb
Host smart-a27e6e53-f2a8-495e-906d-d84b9b5c1956
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33408084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.33408084
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3406557474
Short name T171
Test name
Test status
Simulation time 251431847 ps
CPU time 2.57 seconds
Started Jul 11 05:30:31 PM PDT 24
Finished Jul 11 05:30:37 PM PDT 24
Peak memory 213644 kb
Host smart-7e9a3730-32f1-4089-b403-b244785b12b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406557474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3406557474
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3538553615
Short name T139
Test name
Test status
Simulation time 722277623 ps
CPU time 4.15 seconds
Started Jul 11 05:29:31 PM PDT 24
Finished Jul 11 05:29:37 PM PDT 24
Peak memory 205404 kb
Host smart-1ff272ee-2715-4592-918c-f9ac341a9fbf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538553615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
538553615
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.135730080
Short name T928
Test name
Test status
Simulation time 6520362925 ps
CPU time 24.64 seconds
Started Jul 11 05:29:28 PM PDT 24
Finished Jul 11 05:29:53 PM PDT 24
Peak memory 205568 kb
Host smart-0e595a0a-503a-4fc1-8f2a-23cd402180e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135730080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.135730080
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1446620155
Short name T1080
Test name
Test status
Simulation time 32809112 ps
CPU time 1.45 seconds
Started Jul 11 05:29:26 PM PDT 24
Finished Jul 11 05:29:28 PM PDT 24
Peak memory 205436 kb
Host smart-88a8f059-f7a4-45ee-9e25-8274481012b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446620155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
446620155
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2750212971
Short name T944
Test name
Test status
Simulation time 42325226 ps
CPU time 1.3 seconds
Started Jul 11 05:29:35 PM PDT 24
Finished Jul 11 05:29:38 PM PDT 24
Peak memory 213676 kb
Host smart-bf093065-c816-4382-a282-35dee03ef8b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750212971 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2750212971
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2243439493
Short name T1051
Test name
Test status
Simulation time 23618959 ps
CPU time 1.05 seconds
Started Jul 11 05:29:33 PM PDT 24
Finished Jul 11 05:29:36 PM PDT 24
Peak memory 205520 kb
Host smart-521ce77e-1aab-4a15-abeb-6da57f58ff00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243439493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2243439493
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4000402746
Short name T1054
Test name
Test status
Simulation time 13370912 ps
CPU time 0.73 seconds
Started Jul 11 05:29:28 PM PDT 24
Finished Jul 11 05:29:30 PM PDT 24
Peak memory 205276 kb
Host smart-ec966a48-f990-41ac-be66-be35ef7d3b06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000402746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.4000402746
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1629722098
Short name T1083
Test name
Test status
Simulation time 101447665 ps
CPU time 1.86 seconds
Started Jul 11 05:29:37 PM PDT 24
Finished Jul 11 05:29:40 PM PDT 24
Peak memory 205516 kb
Host smart-bc231d8a-cd94-40e3-907d-b35b1bad30b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629722098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1629722098
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.614316607
Short name T112
Test name
Test status
Simulation time 166006117 ps
CPU time 1.55 seconds
Started Jul 11 05:29:30 PM PDT 24
Finished Jul 11 05:29:33 PM PDT 24
Peak memory 214088 kb
Host smart-d4707a0d-5746-466f-bcd9-361e3d8b0d51
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614316607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.614316607
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3309670119
Short name T1075
Test name
Test status
Simulation time 339633352 ps
CPU time 7.66 seconds
Started Jul 11 05:29:27 PM PDT 24
Finished Jul 11 05:29:36 PM PDT 24
Peak memory 213984 kb
Host smart-2992e30b-b958-4708-9b97-b9b653839bef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309670119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3309670119
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2140761092
Short name T1063
Test name
Test status
Simulation time 250705577 ps
CPU time 2.93 seconds
Started Jul 11 05:29:27 PM PDT 24
Finished Jul 11 05:29:31 PM PDT 24
Peak memory 216008 kb
Host smart-80e3c500-8d45-4792-a8e4-802ab5729d28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140761092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2140761092
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.796519623
Short name T180
Test name
Test status
Simulation time 712362148 ps
CPU time 6.48 seconds
Started Jul 11 05:29:27 PM PDT 24
Finished Jul 11 05:29:35 PM PDT 24
Peak memory 213640 kb
Host smart-d8e1b390-e71f-4df9-a8f7-c01013bf0aa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796519623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
796519623
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.586419187
Short name T1036
Test name
Test status
Simulation time 23049909 ps
CPU time 1.06 seconds
Started Jul 11 05:30:32 PM PDT 24
Finished Jul 11 05:30:36 PM PDT 24
Peak memory 205408 kb
Host smart-4a1b9ea9-baa3-40fa-bb85-b5437e90f646
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586419187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.586419187
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.507279483
Short name T970
Test name
Test status
Simulation time 37949545 ps
CPU time 0.73 seconds
Started Jul 11 05:30:29 PM PDT 24
Finished Jul 11 05:30:33 PM PDT 24
Peak memory 205344 kb
Host smart-4f9a21bf-62d7-45c7-9a08-cd444fb87f30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507279483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.507279483
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2371266188
Short name T920
Test name
Test status
Simulation time 17740912 ps
CPU time 0.76 seconds
Started Jul 11 05:30:36 PM PDT 24
Finished Jul 11 05:30:38 PM PDT 24
Peak memory 205344 kb
Host smart-b15478b4-ea2a-4278-89d7-c479ca7da96b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371266188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2371266188
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3828019577
Short name T960
Test name
Test status
Simulation time 21980566 ps
CPU time 0.72 seconds
Started Jul 11 05:30:32 PM PDT 24
Finished Jul 11 05:30:36 PM PDT 24
Peak memory 205324 kb
Host smart-8ec309d6-0930-4524-a4d3-c6d43c558c09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828019577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3828019577
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1279562615
Short name T1076
Test name
Test status
Simulation time 79391082 ps
CPU time 0.86 seconds
Started Jul 11 05:30:37 PM PDT 24
Finished Jul 11 05:30:39 PM PDT 24
Peak memory 205108 kb
Host smart-6b9ad870-5f47-494a-94a8-7fc8e5b64309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279562615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1279562615
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.4158890141
Short name T1048
Test name
Test status
Simulation time 81436908 ps
CPU time 0.81 seconds
Started Jul 11 05:30:29 PM PDT 24
Finished Jul 11 05:30:33 PM PDT 24
Peak memory 205332 kb
Host smart-7a14e2fe-3c6b-4426-b5bf-3066d1c4529f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158890141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.4158890141
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2544423171
Short name T925
Test name
Test status
Simulation time 45006979 ps
CPU time 0.78 seconds
Started Jul 11 05:30:36 PM PDT 24
Finished Jul 11 05:30:38 PM PDT 24
Peak memory 205340 kb
Host smart-119cb89c-caee-477c-a10b-715c090b7b49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544423171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2544423171
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.252300747
Short name T1082
Test name
Test status
Simulation time 11227893 ps
CPU time 0.84 seconds
Started Jul 11 05:30:34 PM PDT 24
Finished Jul 11 05:30:37 PM PDT 24
Peak memory 205244 kb
Host smart-1da02753-45aa-4862-9d46-68dd892acbda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252300747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.252300747
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2738651560
Short name T981
Test name
Test status
Simulation time 137044310 ps
CPU time 0.73 seconds
Started Jul 11 05:30:35 PM PDT 24
Finished Jul 11 05:30:37 PM PDT 24
Peak memory 205344 kb
Host smart-7f78d27b-61a0-48c5-970a-b37e1c5fa7c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738651560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2738651560
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.4243815538
Short name T945
Test name
Test status
Simulation time 10382104 ps
CPU time 0.82 seconds
Started Jul 11 05:30:36 PM PDT 24
Finished Jul 11 05:30:39 PM PDT 24
Peak memory 205160 kb
Host smart-c9adcf62-cea3-4ba8-89ec-0d5aeb2f2537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243815538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.4243815538
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1724234960
Short name T998
Test name
Test status
Simulation time 67695808 ps
CPU time 4.07 seconds
Started Jul 11 05:29:41 PM PDT 24
Finished Jul 11 05:29:47 PM PDT 24
Peak memory 205528 kb
Host smart-12bd1f36-ff62-443e-9368-d6963b58f628
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724234960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
724234960
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.870743005
Short name T966
Test name
Test status
Simulation time 5129073468 ps
CPU time 16.28 seconds
Started Jul 11 05:29:37 PM PDT 24
Finished Jul 11 05:29:55 PM PDT 24
Peak memory 205632 kb
Host smart-a48991c5-3d2b-4413-8759-304fcef09222
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870743005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.870743005
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2432708871
Short name T942
Test name
Test status
Simulation time 20555669 ps
CPU time 0.98 seconds
Started Jul 11 05:29:34 PM PDT 24
Finished Jul 11 05:29:37 PM PDT 24
Peak memory 205372 kb
Host smart-e623f85f-5862-431a-bea8-a29fed138c79
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432708871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
432708871
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2384473611
Short name T973
Test name
Test status
Simulation time 55641299 ps
CPU time 1.71 seconds
Started Jul 11 05:29:46 PM PDT 24
Finished Jul 11 05:29:49 PM PDT 24
Peak memory 221992 kb
Host smart-4237e1e0-e0c0-4136-b315-d59cc2aef6e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384473611 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2384473611
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.4063301799
Short name T1045
Test name
Test status
Simulation time 18930640 ps
CPU time 0.94 seconds
Started Jul 11 05:29:37 PM PDT 24
Finished Jul 11 05:29:40 PM PDT 24
Peak memory 205460 kb
Host smart-5afdcbcb-96b7-4ddc-abc0-80c8a1d36fc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063301799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.4063301799
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1920367779
Short name T927
Test name
Test status
Simulation time 47640962 ps
CPU time 0.79 seconds
Started Jul 11 05:29:40 PM PDT 24
Finished Jul 11 05:29:42 PM PDT 24
Peak memory 205192 kb
Host smart-46e56947-7fa5-417d-9622-922ad86c9415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920367779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1920367779
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1027322921
Short name T996
Test name
Test status
Simulation time 110399874 ps
CPU time 3.6 seconds
Started Jul 11 05:29:49 PM PDT 24
Finished Jul 11 05:29:53 PM PDT 24
Peak memory 205508 kb
Host smart-f50be38e-a6f8-407a-aac7-0738d3b5e772
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027322921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1027322921
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.792608148
Short name T1049
Test name
Test status
Simulation time 164814855 ps
CPU time 3.73 seconds
Started Jul 11 05:29:36 PM PDT 24
Finished Jul 11 05:29:42 PM PDT 24
Peak memory 214012 kb
Host smart-0b20b56e-7fc1-4d23-96f3-2e5514464fcd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792608148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.792608148
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.942441305
Short name T1006
Test name
Test status
Simulation time 160964530 ps
CPU time 3.93 seconds
Started Jul 11 05:29:35 PM PDT 24
Finished Jul 11 05:29:42 PM PDT 24
Peak memory 220036 kb
Host smart-758f97f9-b7fc-4694-b5bd-d2ccbd62f14a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942441305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.942441305
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3594603027
Short name T943
Test name
Test status
Simulation time 120328289 ps
CPU time 2.39 seconds
Started Jul 11 05:29:40 PM PDT 24
Finished Jul 11 05:29:44 PM PDT 24
Peak memory 213704 kb
Host smart-7165752c-c5e1-4122-b276-84adbb3e407e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594603027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3594603027
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1775555844
Short name T176
Test name
Test status
Simulation time 68290935 ps
CPU time 2.81 seconds
Started Jul 11 05:29:38 PM PDT 24
Finished Jul 11 05:29:42 PM PDT 24
Peak memory 213736 kb
Host smart-50577cd7-22cc-45bc-acc5-096fb64563dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775555844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1775555844
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.654995053
Short name T934
Test name
Test status
Simulation time 36717914 ps
CPU time 0.74 seconds
Started Jul 11 05:30:38 PM PDT 24
Finished Jul 11 05:30:40 PM PDT 24
Peak memory 205344 kb
Host smart-d8f4b6f9-7255-4d20-b131-1bf416af037b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654995053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.654995053
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.726725861
Short name T937
Test name
Test status
Simulation time 11070463 ps
CPU time 0.84 seconds
Started Jul 11 05:30:35 PM PDT 24
Finished Jul 11 05:30:38 PM PDT 24
Peak memory 205312 kb
Host smart-c05bc4e6-710e-4d34-9108-87249ca7b6bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726725861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.726725861
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1481451686
Short name T989
Test name
Test status
Simulation time 68245483 ps
CPU time 0.72 seconds
Started Jul 11 05:30:35 PM PDT 24
Finished Jul 11 05:30:38 PM PDT 24
Peak memory 205236 kb
Host smart-58daa638-6dfe-4c23-a0f5-141ec4ab278e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481451686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1481451686
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2348762007
Short name T941
Test name
Test status
Simulation time 9005957 ps
CPU time 0.7 seconds
Started Jul 11 05:30:34 PM PDT 24
Finished Jul 11 05:30:37 PM PDT 24
Peak memory 205240 kb
Host smart-274c4d49-8ea9-43fb-b9de-aa9288ee0c10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348762007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2348762007
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2289725241
Short name T951
Test name
Test status
Simulation time 14527880 ps
CPU time 0.93 seconds
Started Jul 11 05:30:39 PM PDT 24
Finished Jul 11 05:30:41 PM PDT 24
Peak memory 205320 kb
Host smart-0c9a4b6b-e940-43c2-8401-ad2ce507a128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289725241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2289725241
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3923316261
Short name T1059
Test name
Test status
Simulation time 52517817 ps
CPU time 0.89 seconds
Started Jul 11 05:30:43 PM PDT 24
Finished Jul 11 05:30:46 PM PDT 24
Peak memory 205332 kb
Host smart-3f3eb435-f738-4c24-aeeb-f8c76166d0b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923316261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3923316261
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3760698050
Short name T956
Test name
Test status
Simulation time 10994512 ps
CPU time 0.72 seconds
Started Jul 11 05:30:36 PM PDT 24
Finished Jul 11 05:30:38 PM PDT 24
Peak memory 205140 kb
Host smart-4357bc00-9abb-4481-9016-fc2584da9606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760698050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3760698050
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.17028218
Short name T954
Test name
Test status
Simulation time 22425843 ps
CPU time 0.74 seconds
Started Jul 11 05:30:46 PM PDT 24
Finished Jul 11 05:30:49 PM PDT 24
Peak memory 205280 kb
Host smart-6f6fe2cc-145f-433e-b480-9dcff69edc4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17028218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.17028218
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2703590098
Short name T1000
Test name
Test status
Simulation time 11016081 ps
CPU time 0.71 seconds
Started Jul 11 05:30:37 PM PDT 24
Finished Jul 11 05:30:39 PM PDT 24
Peak memory 205344 kb
Host smart-3169dda7-1c70-4949-b9cf-3356a97bd00c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703590098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2703590098
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.692483199
Short name T919
Test name
Test status
Simulation time 60371080 ps
CPU time 0.71 seconds
Started Jul 11 05:30:43 PM PDT 24
Finished Jul 11 05:30:45 PM PDT 24
Peak memory 205344 kb
Host smart-3740e3fd-3e66-4d8f-8885-0b527f8bcba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692483199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.692483199
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.936724262
Short name T141
Test name
Test status
Simulation time 2018089940 ps
CPU time 7.81 seconds
Started Jul 11 05:29:45 PM PDT 24
Finished Jul 11 05:29:54 PM PDT 24
Peak memory 205548 kb
Host smart-5a8af6e6-5948-4752-8f8b-5ceceaa1ac95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936724262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.936724262
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.205153900
Short name T1046
Test name
Test status
Simulation time 1048970476 ps
CPU time 11.38 seconds
Started Jul 11 05:29:45 PM PDT 24
Finished Jul 11 05:29:58 PM PDT 24
Peak memory 205336 kb
Host smart-505efe64-cd42-4ab0-98f0-6488bd91e85a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205153900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.205153900
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.600711022
Short name T1018
Test name
Test status
Simulation time 61930649 ps
CPU time 1.07 seconds
Started Jul 11 05:29:42 PM PDT 24
Finished Jul 11 05:29:45 PM PDT 24
Peak memory 205516 kb
Host smart-0dcbb6c4-1bbb-4087-a2a4-10c5715204fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600711022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.600711022
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3938771126
Short name T1064
Test name
Test status
Simulation time 93119100 ps
CPU time 1.25 seconds
Started Jul 11 05:29:44 PM PDT 24
Finished Jul 11 05:29:47 PM PDT 24
Peak memory 205384 kb
Host smart-e78e9478-6d70-498a-8bbe-d0d2d392ee0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938771126 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3938771126
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2841824740
Short name T1047
Test name
Test status
Simulation time 51353697 ps
CPU time 1.02 seconds
Started Jul 11 05:29:42 PM PDT 24
Finished Jul 11 05:29:44 PM PDT 24
Peak memory 205300 kb
Host smart-7c23e03b-1dda-413e-b702-089adeb2063c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841824740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2841824740
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.664864890
Short name T950
Test name
Test status
Simulation time 24681631 ps
CPU time 0.67 seconds
Started Jul 11 05:29:48 PM PDT 24
Finished Jul 11 05:29:49 PM PDT 24
Peak memory 205264 kb
Host smart-26584bd9-8013-4953-8431-ae2cffcc51ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664864890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.664864890
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.226191308
Short name T1035
Test name
Test status
Simulation time 379296244 ps
CPU time 3.1 seconds
Started Jul 11 05:29:45 PM PDT 24
Finished Jul 11 05:29:49 PM PDT 24
Peak memory 205440 kb
Host smart-cf42fbf7-6b9c-463f-ba12-0b6610a4bf2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226191308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.226191308
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1559937688
Short name T977
Test name
Test status
Simulation time 124200069 ps
CPU time 4.23 seconds
Started Jul 11 05:29:45 PM PDT 24
Finished Jul 11 05:29:51 PM PDT 24
Peak memory 214096 kb
Host smart-7f141a8b-999b-4b32-8e75-53be73e8953d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559937688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1559937688
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2010212702
Short name T922
Test name
Test status
Simulation time 21605730 ps
CPU time 1.53 seconds
Started Jul 11 05:29:43 PM PDT 24
Finished Jul 11 05:29:46 PM PDT 24
Peak memory 214752 kb
Host smart-e7227749-7ad3-43d9-b9bc-c48411e05180
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010212702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2010212702
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.643220410
Short name T1007
Test name
Test status
Simulation time 57894326 ps
CPU time 0.85 seconds
Started Jul 11 05:30:41 PM PDT 24
Finished Jul 11 05:30:43 PM PDT 24
Peak memory 205312 kb
Host smart-56c9d917-1a95-4200-905f-4192cc3d9c81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643220410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.643220410
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2257225631
Short name T955
Test name
Test status
Simulation time 11328674 ps
CPU time 0.86 seconds
Started Jul 11 05:30:40 PM PDT 24
Finished Jul 11 05:30:43 PM PDT 24
Peak memory 205344 kb
Host smart-6b095a99-68e0-4087-a993-e1e71df41436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257225631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2257225631
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1301871422
Short name T949
Test name
Test status
Simulation time 30052824 ps
CPU time 1.07 seconds
Started Jul 11 05:30:40 PM PDT 24
Finished Jul 11 05:30:43 PM PDT 24
Peak memory 205460 kb
Host smart-47b98922-a2f0-4369-801c-742d4fc7b4ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301871422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1301871422
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.51118751
Short name T1008
Test name
Test status
Simulation time 14200519 ps
CPU time 0.86 seconds
Started Jul 11 05:30:44 PM PDT 24
Finished Jul 11 05:30:46 PM PDT 24
Peak memory 205212 kb
Host smart-a7958f20-6cb4-43bd-8708-21d9e9b1e4b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51118751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.51118751
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1321039747
Short name T968
Test name
Test status
Simulation time 11248954 ps
CPU time 0.74 seconds
Started Jul 11 05:30:43 PM PDT 24
Finished Jul 11 05:30:46 PM PDT 24
Peak memory 205344 kb
Host smart-0a306430-7492-4dbd-8a45-f5f5974558e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321039747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1321039747
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.800797452
Short name T1062
Test name
Test status
Simulation time 17858539 ps
CPU time 0.76 seconds
Started Jul 11 05:30:43 PM PDT 24
Finished Jul 11 05:30:46 PM PDT 24
Peak memory 205344 kb
Host smart-38c7931d-f2f6-4084-8138-4e8b93fcb4df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800797452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.800797452
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.21098615
Short name T1038
Test name
Test status
Simulation time 115571336 ps
CPU time 0.7 seconds
Started Jul 11 05:30:40 PM PDT 24
Finished Jul 11 05:30:42 PM PDT 24
Peak memory 205312 kb
Host smart-16eca526-7ee9-4a06-a819-e349ee520fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21098615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.21098615
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1635635669
Short name T935
Test name
Test status
Simulation time 32093388 ps
CPU time 0.72 seconds
Started Jul 11 05:30:47 PM PDT 24
Finished Jul 11 05:30:50 PM PDT 24
Peak memory 205272 kb
Host smart-7deb6354-b6b9-4354-be9b-db0c3e39ce88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635635669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1635635669
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2865611929
Short name T924
Test name
Test status
Simulation time 20232411 ps
CPU time 0.76 seconds
Started Jul 11 05:30:50 PM PDT 24
Finished Jul 11 05:30:53 PM PDT 24
Peak memory 205356 kb
Host smart-de4d6687-f002-474d-bd93-5f8084a2ad63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865611929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2865611929
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.418976390
Short name T986
Test name
Test status
Simulation time 15093534 ps
CPU time 0.75 seconds
Started Jul 11 05:30:39 PM PDT 24
Finished Jul 11 05:30:41 PM PDT 24
Peak memory 205268 kb
Host smart-8ab5a3a5-53f3-456d-9356-9ae3ffe7551d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418976390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.418976390
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3649104499
Short name T964
Test name
Test status
Simulation time 52587514 ps
CPU time 1.18 seconds
Started Jul 11 05:29:55 PM PDT 24
Finished Jul 11 05:29:58 PM PDT 24
Peak memory 205588 kb
Host smart-4cdc1baf-b9ca-4c20-b448-4aef2de2371b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649104499 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3649104499
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2491496819
Short name T138
Test name
Test status
Simulation time 116205466 ps
CPU time 1.06 seconds
Started Jul 11 05:29:55 PM PDT 24
Finished Jul 11 05:29:58 PM PDT 24
Peak memory 205420 kb
Host smart-ce79dd45-37cd-4072-ae20-843ce2a83abb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491496819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2491496819
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2771175276
Short name T946
Test name
Test status
Simulation time 44531079 ps
CPU time 0.72 seconds
Started Jul 11 05:29:52 PM PDT 24
Finished Jul 11 05:29:54 PM PDT 24
Peak memory 205344 kb
Host smart-f01b2d13-5fbb-40f9-a993-35bcb56e0e13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771175276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2771175276
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.366121345
Short name T992
Test name
Test status
Simulation time 179742152 ps
CPU time 2.78 seconds
Started Jul 11 05:29:57 PM PDT 24
Finished Jul 11 05:30:01 PM PDT 24
Peak memory 205440 kb
Host smart-bec51baa-3bcd-4c16-8aaa-fad3f11f7f7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366121345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.366121345
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1294832644
Short name T1055
Test name
Test status
Simulation time 2069419794 ps
CPU time 3.57 seconds
Started Jul 11 05:29:55 PM PDT 24
Finished Jul 11 05:30:00 PM PDT 24
Peak memory 213976 kb
Host smart-b3755635-4c9b-4eee-a5f6-42beaeeacba2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294832644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1294832644
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.219233408
Short name T1058
Test name
Test status
Simulation time 237591568 ps
CPU time 4.98 seconds
Started Jul 11 05:29:54 PM PDT 24
Finished Jul 11 05:30:00 PM PDT 24
Peak memory 213956 kb
Host smart-47bec47d-4f40-4cf4-9648-2704508ba422
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219233408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.219233408
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2149389458
Short name T1017
Test name
Test status
Simulation time 75277135 ps
CPU time 1.93 seconds
Started Jul 11 05:29:55 PM PDT 24
Finished Jul 11 05:29:59 PM PDT 24
Peak memory 213728 kb
Host smart-1ee9df86-0502-409b-ba4a-657772202f88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149389458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2149389458
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1304220953
Short name T157
Test name
Test status
Simulation time 1096934510 ps
CPU time 10.9 seconds
Started Jul 11 05:29:55 PM PDT 24
Finished Jul 11 05:30:08 PM PDT 24
Peak memory 205708 kb
Host smart-0e454f42-0905-455a-830d-cb096c0e9ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304220953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1304220953
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.4245321653
Short name T999
Test name
Test status
Simulation time 106849174 ps
CPU time 1.28 seconds
Started Jul 11 05:30:05 PM PDT 24
Finished Jul 11 05:30:09 PM PDT 24
Peak memory 213844 kb
Host smart-aabec837-f58a-4188-b94b-05c03a626852
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245321653 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.4245321653
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.156052161
Short name T959
Test name
Test status
Simulation time 185717418 ps
CPU time 1.14 seconds
Started Jul 11 05:30:11 PM PDT 24
Finished Jul 11 05:30:14 PM PDT 24
Peak memory 205456 kb
Host smart-89b3d20e-8aab-4ff9-9234-33bf98c7b9ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156052161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.156052161
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3627132577
Short name T1001
Test name
Test status
Simulation time 11568401 ps
CPU time 0.73 seconds
Started Jul 11 05:30:03 PM PDT 24
Finished Jul 11 05:30:06 PM PDT 24
Peak memory 205252 kb
Host smart-38dfd7e8-1a87-4aa1-9e93-c0bc70c49076
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627132577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3627132577
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1483632978
Short name T1086
Test name
Test status
Simulation time 690389521 ps
CPU time 1.68 seconds
Started Jul 11 05:30:07 PM PDT 24
Finished Jul 11 05:30:10 PM PDT 24
Peak memory 205564 kb
Host smart-a24754a6-4dab-4062-89ed-f6ef3d2ace48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483632978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1483632978
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3110678856
Short name T988
Test name
Test status
Simulation time 453354518 ps
CPU time 2.19 seconds
Started Jul 11 05:29:59 PM PDT 24
Finished Jul 11 05:30:03 PM PDT 24
Peak memory 214032 kb
Host smart-7a7082be-dd10-44dd-8dd6-e3167e3fe14e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110678856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3110678856
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1416358154
Short name T1084
Test name
Test status
Simulation time 849061280 ps
CPU time 5.36 seconds
Started Jul 11 05:29:56 PM PDT 24
Finished Jul 11 05:30:03 PM PDT 24
Peak memory 214076 kb
Host smart-fc062227-3e12-490a-8a37-4ea578717b76
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416358154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1416358154
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3155082134
Short name T1081
Test name
Test status
Simulation time 394129141 ps
CPU time 3.71 seconds
Started Jul 11 05:29:54 PM PDT 24
Finished Jul 11 05:29:59 PM PDT 24
Peak memory 213716 kb
Host smart-b4f5e8bc-4729-4702-9368-7758f68644dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155082134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3155082134
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2729842088
Short name T1022
Test name
Test status
Simulation time 48532774 ps
CPU time 1.87 seconds
Started Jul 11 05:30:04 PM PDT 24
Finished Jul 11 05:30:09 PM PDT 24
Peak memory 213604 kb
Host smart-e1b6c508-afdc-4997-876b-cf28da3a6bc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729842088 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2729842088
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3516533002
Short name T926
Test name
Test status
Simulation time 19701062 ps
CPU time 0.96 seconds
Started Jul 11 05:30:06 PM PDT 24
Finished Jul 11 05:30:09 PM PDT 24
Peak memory 205292 kb
Host smart-754efa85-0382-4f6e-97dd-f1dab82c9534
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516533002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3516533002
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3130931222
Short name T1087
Test name
Test status
Simulation time 32617719 ps
CPU time 0.73 seconds
Started Jul 11 05:30:04 PM PDT 24
Finished Jul 11 05:30:07 PM PDT 24
Peak memory 205244 kb
Host smart-f0023f7e-22a7-4142-86cf-b38ee0d65c64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130931222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3130931222
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1837338211
Short name T965
Test name
Test status
Simulation time 947177745 ps
CPU time 4.6 seconds
Started Jul 11 05:30:09 PM PDT 24
Finished Jul 11 05:30:15 PM PDT 24
Peak memory 205516 kb
Host smart-49bbfd62-f897-422f-a6fa-4ddbf129681f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837338211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1837338211
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2615104241
Short name T1012
Test name
Test status
Simulation time 512401753 ps
CPU time 2.73 seconds
Started Jul 11 05:30:06 PM PDT 24
Finished Jul 11 05:30:11 PM PDT 24
Peak memory 214004 kb
Host smart-df33bd7c-cea2-48e6-b7ad-121683945c4d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615104241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2615104241
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2094929857
Short name T1027
Test name
Test status
Simulation time 770895672 ps
CPU time 4.76 seconds
Started Jul 11 05:30:10 PM PDT 24
Finished Jul 11 05:30:16 PM PDT 24
Peak memory 213908 kb
Host smart-a3d36131-d3a9-46b0-b6c5-ed2ed2f32c13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094929857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2094929857
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4260656586
Short name T1004
Test name
Test status
Simulation time 307634336 ps
CPU time 2.19 seconds
Started Jul 11 05:30:05 PM PDT 24
Finished Jul 11 05:30:09 PM PDT 24
Peak memory 213584 kb
Host smart-3d2a9f11-9280-4f4b-a20e-0e96e5b41380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260656586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.4260656586
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.70710117
Short name T174
Test name
Test status
Simulation time 220113034 ps
CPU time 3.34 seconds
Started Jul 11 05:30:05 PM PDT 24
Finished Jul 11 05:30:11 PM PDT 24
Peak memory 205748 kb
Host smart-b482a4df-88ad-4978-b4fd-2e0e7019eada
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70710117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.70710117
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1597617606
Short name T1031
Test name
Test status
Simulation time 170873769 ps
CPU time 1.55 seconds
Started Jul 11 05:30:09 PM PDT 24
Finished Jul 11 05:30:12 PM PDT 24
Peak memory 213760 kb
Host smart-3a81aa62-bfd6-4dec-b8e9-f0f151d09f03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597617606 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1597617606
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.170094684
Short name T1071
Test name
Test status
Simulation time 18030234 ps
CPU time 0.96 seconds
Started Jul 11 05:30:04 PM PDT 24
Finished Jul 11 05:30:08 PM PDT 24
Peak memory 205376 kb
Host smart-7200e946-e79c-4932-817a-a8d614de32dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170094684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.170094684
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.774876554
Short name T947
Test name
Test status
Simulation time 19757306 ps
CPU time 0.71 seconds
Started Jul 11 05:30:10 PM PDT 24
Finished Jul 11 05:30:12 PM PDT 24
Peak memory 205344 kb
Host smart-6a3c5c3f-b69f-498b-8253-276a20bd3cbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774876554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.774876554
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3304120689
Short name T979
Test name
Test status
Simulation time 484556835 ps
CPU time 3.66 seconds
Started Jul 11 05:30:04 PM PDT 24
Finished Jul 11 05:30:11 PM PDT 24
Peak memory 205348 kb
Host smart-e08abefb-53b2-431b-96ef-14ad00d2366a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304120689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3304120689
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3087130417
Short name T116
Test name
Test status
Simulation time 318557954 ps
CPU time 1.58 seconds
Started Jul 11 05:30:04 PM PDT 24
Finished Jul 11 05:30:08 PM PDT 24
Peak memory 214084 kb
Host smart-b8e82fc8-41be-4f53-b9d1-b8ad87ac4767
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087130417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3087130417
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.563219779
Short name T1052
Test name
Test status
Simulation time 419786037 ps
CPU time 8.07 seconds
Started Jul 11 05:30:02 PM PDT 24
Finished Jul 11 05:30:12 PM PDT 24
Peak memory 214128 kb
Host smart-762cde95-6aef-4561-b824-f8fb4355d272
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563219779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.563219779
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2515530888
Short name T1010
Test name
Test status
Simulation time 55761880 ps
CPU time 2.19 seconds
Started Jul 11 05:30:06 PM PDT 24
Finished Jul 11 05:30:10 PM PDT 24
Peak memory 213756 kb
Host smart-be7265d2-f113-4437-909d-4a7b21ce1385
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515530888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2515530888
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3725729583
Short name T1044
Test name
Test status
Simulation time 298349951 ps
CPU time 3.83 seconds
Started Jul 11 05:30:05 PM PDT 24
Finished Jul 11 05:30:11 PM PDT 24
Peak memory 213720 kb
Host smart-1d041c77-554b-46a9-94d9-02ac32b395b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725729583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3725729583
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2525190311
Short name T1066
Test name
Test status
Simulation time 483104716 ps
CPU time 2.03 seconds
Started Jul 11 05:30:04 PM PDT 24
Finished Jul 11 05:30:08 PM PDT 24
Peak memory 213624 kb
Host smart-3faddcbb-7000-4ab2-babe-fcf1007118f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525190311 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2525190311
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1279284444
Short name T1061
Test name
Test status
Simulation time 27618930 ps
CPU time 1.06 seconds
Started Jul 11 05:30:12 PM PDT 24
Finished Jul 11 05:30:15 PM PDT 24
Peak memory 205464 kb
Host smart-1d793770-a2fa-4307-a5de-e9e7e33113bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279284444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1279284444
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.892409984
Short name T982
Test name
Test status
Simulation time 34080250 ps
CPU time 0.8 seconds
Started Jul 11 05:30:05 PM PDT 24
Finished Jul 11 05:30:08 PM PDT 24
Peak memory 205388 kb
Host smart-8d107b6a-5383-4e39-9dcc-497bb58c9a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892409984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.892409984
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.918845384
Short name T987
Test name
Test status
Simulation time 474665893 ps
CPU time 1.7 seconds
Started Jul 11 05:30:10 PM PDT 24
Finished Jul 11 05:30:13 PM PDT 24
Peak memory 205512 kb
Host smart-abbbe411-c3ad-4f86-a2e7-132c2a4ecf80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918845384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.918845384
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1456615637
Short name T1002
Test name
Test status
Simulation time 63916244 ps
CPU time 1.83 seconds
Started Jul 11 05:30:08 PM PDT 24
Finished Jul 11 05:30:11 PM PDT 24
Peak memory 214064 kb
Host smart-7bdfa0c9-2b8b-4a1e-927a-d43ac3c980f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456615637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1456615637
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3578080799
Short name T1003
Test name
Test status
Simulation time 1279080126 ps
CPU time 8.68 seconds
Started Jul 11 05:30:38 PM PDT 24
Finished Jul 11 05:30:48 PM PDT 24
Peak memory 222200 kb
Host smart-2aa9ee76-2a3d-493d-8fd1-c55c0ff63071
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578080799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3578080799
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2291007995
Short name T983
Test name
Test status
Simulation time 165249019 ps
CPU time 2.06 seconds
Started Jul 11 05:30:05 PM PDT 24
Finished Jul 11 05:30:10 PM PDT 24
Peak memory 213744 kb
Host smart-74061ea4-fc19-407d-b11b-caf8fc4fd6af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291007995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2291007995
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.69523902
Short name T173
Test name
Test status
Simulation time 945598967 ps
CPU time 10.1 seconds
Started Jul 11 05:30:07 PM PDT 24
Finished Jul 11 05:30:18 PM PDT 24
Peak memory 213892 kb
Host smart-d366b144-4f03-48ac-97a9-26ebbb6e7078
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69523902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.69523902
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2675410066
Short name T203
Test name
Test status
Simulation time 10297376 ps
CPU time 0.85 seconds
Started Jul 11 05:33:02 PM PDT 24
Finished Jul 11 05:33:05 PM PDT 24
Peak memory 205868 kb
Host smart-201a1a89-6453-4ac3-ad49-8f8d07893d81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675410066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2675410066
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2294034570
Short name T324
Test name
Test status
Simulation time 220857445 ps
CPU time 4.11 seconds
Started Jul 11 05:33:00 PM PDT 24
Finished Jul 11 05:33:07 PM PDT 24
Peak memory 215136 kb
Host smart-248721f0-a850-4c09-ab63-8b651d63ef9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2294034570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2294034570
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.350664940
Short name T772
Test name
Test status
Simulation time 1883625604 ps
CPU time 5.64 seconds
Started Jul 11 05:33:00 PM PDT 24
Finished Jul 11 05:33:08 PM PDT 24
Peak memory 222856 kb
Host smart-45b1699a-7de0-4afe-b137-fa53bcc6ac86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350664940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.350664940
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.532290621
Short name T856
Test name
Test status
Simulation time 38241440 ps
CPU time 2.57 seconds
Started Jul 11 05:32:59 PM PDT 24
Finished Jul 11 05:33:04 PM PDT 24
Peak memory 207404 kb
Host smart-b80492ba-d4c4-4555-aa80-119b4e61875c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532290621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.532290621
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2751127067
Short name T385
Test name
Test status
Simulation time 539566923 ps
CPU time 7.51 seconds
Started Jul 11 05:33:00 PM PDT 24
Finished Jul 11 05:33:10 PM PDT 24
Peak memory 214316 kb
Host smart-1276c4c2-d601-497b-8a1c-1eb0a239b378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751127067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2751127067
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2342998665
Short name T339
Test name
Test status
Simulation time 284723319 ps
CPU time 4.08 seconds
Started Jul 11 05:33:00 PM PDT 24
Finished Jul 11 05:33:07 PM PDT 24
Peak memory 214360 kb
Host smart-1cb2fe25-8edc-4f96-a03a-9640fc163b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342998665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2342998665
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2379428056
Short name T57
Test name
Test status
Simulation time 144427368 ps
CPU time 3.6 seconds
Started Jul 11 05:32:59 PM PDT 24
Finished Jul 11 05:33:05 PM PDT 24
Peak memory 222464 kb
Host smart-a00ddaab-486c-4cfc-a2fb-28764908162e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379428056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2379428056
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3147896495
Short name T251
Test name
Test status
Simulation time 250440683 ps
CPU time 5.59 seconds
Started Jul 11 05:33:01 PM PDT 24
Finished Jul 11 05:33:09 PM PDT 24
Peak memory 210012 kb
Host smart-699c8cf2-4625-4fd6-9f71-d2cfb137fd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147896495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3147896495
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.316559565
Short name T575
Test name
Test status
Simulation time 107518239 ps
CPU time 4.4 seconds
Started Jul 11 05:32:58 PM PDT 24
Finished Jul 11 05:33:04 PM PDT 24
Peak memory 208340 kb
Host smart-d3721c0e-f2d0-40d0-9bca-ad972c1dc11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316559565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.316559565
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.220616283
Short name T630
Test name
Test status
Simulation time 56522501 ps
CPU time 3.38 seconds
Started Jul 11 05:32:58 PM PDT 24
Finished Jul 11 05:33:04 PM PDT 24
Peak memory 208456 kb
Host smart-feda32c2-8212-4dab-a386-2a4e153781e3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220616283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.220616283
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.959314168
Short name T284
Test name
Test status
Simulation time 306100663 ps
CPU time 2.87 seconds
Started Jul 11 05:32:58 PM PDT 24
Finished Jul 11 05:33:04 PM PDT 24
Peak memory 207980 kb
Host smart-c0177134-c6ca-4f61-9829-7aefaf1373e7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959314168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.959314168
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3391578786
Short name T812
Test name
Test status
Simulation time 236129507 ps
CPU time 3.84 seconds
Started Jul 11 05:32:59 PM PDT 24
Finished Jul 11 05:33:06 PM PDT 24
Peak memory 208500 kb
Host smart-60e82720-7e86-4519-b22a-e7c4f96bb4cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391578786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3391578786
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1557571010
Short name T917
Test name
Test status
Simulation time 240656023 ps
CPU time 2.96 seconds
Started Jul 11 05:32:59 PM PDT 24
Finished Jul 11 05:33:04 PM PDT 24
Peak memory 209308 kb
Host smart-d01cc025-ad52-4f86-b898-fc38e67f7059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557571010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1557571010
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3957091153
Short name T444
Test name
Test status
Simulation time 80865252 ps
CPU time 2.37 seconds
Started Jul 11 05:32:59 PM PDT 24
Finished Jul 11 05:33:04 PM PDT 24
Peak memory 206748 kb
Host smart-f6cd752c-7bd8-4fa6-8b7d-fb02b9ecacca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957091153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3957091153
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2176745108
Short name T884
Test name
Test status
Simulation time 6152291438 ps
CPU time 96.68 seconds
Started Jul 11 05:32:58 PM PDT 24
Finished Jul 11 05:34:37 PM PDT 24
Peak memory 215564 kb
Host smart-11fd59f5-0d3f-44c5-b843-97c65aa299a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176745108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2176745108
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1282756637
Short name T827
Test name
Test status
Simulation time 2359628189 ps
CPU time 21.84 seconds
Started Jul 11 05:33:00 PM PDT 24
Finished Jul 11 05:33:25 PM PDT 24
Peak memory 222672 kb
Host smart-ce80d7d3-06c6-40b0-ba4b-9f0e1e8b18f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282756637 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1282756637
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2210995533
Short name T336
Test name
Test status
Simulation time 2466310891 ps
CPU time 56.75 seconds
Started Jul 11 05:33:02 PM PDT 24
Finished Jul 11 05:34:01 PM PDT 24
Peak memory 208472 kb
Host smart-54f3ad0c-8162-42de-aba6-92aed64b2bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210995533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2210995533
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3377389819
Short name T649
Test name
Test status
Simulation time 263892908 ps
CPU time 2.74 seconds
Started Jul 11 05:33:00 PM PDT 24
Finished Jul 11 05:33:05 PM PDT 24
Peak memory 209848 kb
Host smart-e6fee6aa-6cd3-4bb8-a555-ce8bc4c37eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377389819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3377389819
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1001737127
Short name T672
Test name
Test status
Simulation time 18154062 ps
CPU time 0.84 seconds
Started Jul 11 05:33:10 PM PDT 24
Finished Jul 11 05:33:14 PM PDT 24
Peak memory 205936 kb
Host smart-c824f8bf-7fc9-49f9-9b80-590f937837b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001737127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1001737127
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.4247966639
Short name T717
Test name
Test status
Simulation time 33247202 ps
CPU time 2.75 seconds
Started Jul 11 05:33:09 PM PDT 24
Finished Jul 11 05:33:14 PM PDT 24
Peak memory 214192 kb
Host smart-3351f8a3-6aad-410b-a609-e11e8efa9f05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4247966639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.4247966639
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3841784127
Short name T483
Test name
Test status
Simulation time 380436655 ps
CPU time 7.16 seconds
Started Jul 11 05:33:06 PM PDT 24
Finished Jul 11 05:33:15 PM PDT 24
Peak memory 214620 kb
Host smart-1d834978-1ac2-4bc3-82dc-b3b371b21317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841784127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3841784127
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1623622889
Short name T538
Test name
Test status
Simulation time 109143285 ps
CPU time 2.88 seconds
Started Jul 11 05:33:04 PM PDT 24
Finished Jul 11 05:33:10 PM PDT 24
Peak memory 207564 kb
Host smart-f9628499-784c-4d88-a808-0b96b19e43cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623622889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1623622889
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2833500078
Short name T91
Test name
Test status
Simulation time 115716342 ps
CPU time 2.29 seconds
Started Jul 11 05:33:04 PM PDT 24
Finished Jul 11 05:33:09 PM PDT 24
Peak memory 214392 kb
Host smart-296eeaf9-1ebf-458a-a195-d1c990f3275f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833500078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2833500078
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2480614813
Short name T652
Test name
Test status
Simulation time 226144225 ps
CPU time 2.72 seconds
Started Jul 11 05:33:06 PM PDT 24
Finished Jul 11 05:33:11 PM PDT 24
Peak memory 214288 kb
Host smart-517449cc-3267-49f1-9791-7a121cb66695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480614813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2480614813
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2756792718
Short name T854
Test name
Test status
Simulation time 79936200 ps
CPU time 3.53 seconds
Started Jul 11 05:33:07 PM PDT 24
Finished Jul 11 05:33:13 PM PDT 24
Peak memory 214376 kb
Host smart-ad03ed97-aa36-4521-9317-ac30cab561b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756792718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2756792718
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3953156789
Short name T380
Test name
Test status
Simulation time 42874228 ps
CPU time 2.95 seconds
Started Jul 11 05:33:04 PM PDT 24
Finished Jul 11 05:33:10 PM PDT 24
Peak memory 214260 kb
Host smart-2f3e4526-99e8-4a9d-a1be-b8202e574c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953156789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3953156789
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3459682457
Short name T12
Test name
Test status
Simulation time 935162107 ps
CPU time 5.75 seconds
Started Jul 11 05:33:06 PM PDT 24
Finished Jul 11 05:33:14 PM PDT 24
Peak memory 237188 kb
Host smart-4ac4f1c3-9fb4-4115-98da-4746e085eb16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459682457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3459682457
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.95833003
Short name T874
Test name
Test status
Simulation time 55692318 ps
CPU time 2.75 seconds
Started Jul 11 05:32:59 PM PDT 24
Finished Jul 11 05:33:04 PM PDT 24
Peak memory 208376 kb
Host smart-d5cabc7b-26c0-4785-8174-5ddc582e22a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95833003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.95833003
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2432084656
Short name T794
Test name
Test status
Simulation time 123559870 ps
CPU time 2.52 seconds
Started Jul 11 05:33:00 PM PDT 24
Finished Jul 11 05:33:05 PM PDT 24
Peak memory 208808 kb
Host smart-a4101ee1-83cd-4507-9f92-c208816f3027
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432084656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2432084656
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2058043583
Short name T531
Test name
Test status
Simulation time 39856029 ps
CPU time 2.39 seconds
Started Jul 11 05:33:00 PM PDT 24
Finished Jul 11 05:33:05 PM PDT 24
Peak memory 206768 kb
Host smart-7685c74c-fa54-417e-a3b3-0461e936f832
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058043583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2058043583
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2997153940
Short name T587
Test name
Test status
Simulation time 566768340 ps
CPU time 4.88 seconds
Started Jul 11 05:33:06 PM PDT 24
Finished Jul 11 05:33:13 PM PDT 24
Peak memory 206960 kb
Host smart-e3e8382c-45f8-4025-a555-3ab731812afe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997153940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2997153940
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.4199119982
Short name T766
Test name
Test status
Simulation time 939401502 ps
CPU time 4.99 seconds
Started Jul 11 05:33:10 PM PDT 24
Finished Jul 11 05:33:17 PM PDT 24
Peak memory 218368 kb
Host smart-82195094-e1d2-44b6-b3fb-096bddcdf67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199119982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.4199119982
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1846919358
Short name T489
Test name
Test status
Simulation time 437002060 ps
CPU time 2.19 seconds
Started Jul 11 05:33:03 PM PDT 24
Finished Jul 11 05:33:07 PM PDT 24
Peak memory 206768 kb
Host smart-c3501235-f1a2-441e-aa85-a2e90e2687f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846919358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1846919358
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1414811877
Short name T612
Test name
Test status
Simulation time 49387266 ps
CPU time 0.88 seconds
Started Jul 11 05:33:03 PM PDT 24
Finished Jul 11 05:33:07 PM PDT 24
Peak memory 205936 kb
Host smart-ec23acc2-69e9-479b-a744-27ba66791a0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414811877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1414811877
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3535791613
Short name T66
Test name
Test status
Simulation time 1291941816 ps
CPU time 18.07 seconds
Started Jul 11 05:33:05 PM PDT 24
Finished Jul 11 05:33:26 PM PDT 24
Peak memory 221276 kb
Host smart-effcc7fa-bbc5-4dcb-bce2-dd0acc47bc12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535791613 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3535791613
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1270248958
Short name T622
Test name
Test status
Simulation time 389284392 ps
CPU time 5.79 seconds
Started Jul 11 05:33:04 PM PDT 24
Finished Jul 11 05:33:13 PM PDT 24
Peak memory 208176 kb
Host smart-7a780926-f641-4b0f-a6db-3dc7b13ab70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270248958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1270248958
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2058480894
Short name T164
Test name
Test status
Simulation time 421459054 ps
CPU time 2.11 seconds
Started Jul 11 05:33:05 PM PDT 24
Finished Jul 11 05:33:10 PM PDT 24
Peak memory 210436 kb
Host smart-f8a4e921-0af7-4906-a394-f7211b1ea5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058480894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2058480894
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3148170070
Short name T429
Test name
Test status
Simulation time 207760292 ps
CPU time 3.91 seconds
Started Jul 11 05:33:44 PM PDT 24
Finished Jul 11 05:33:51 PM PDT 24
Peak memory 214320 kb
Host smart-d9bb7da4-63ed-4259-bc77-ccb2bc9e2083
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3148170070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3148170070
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.378027683
Short name T899
Test name
Test status
Simulation time 177723925 ps
CPU time 6.52 seconds
Started Jul 11 05:33:57 PM PDT 24
Finished Jul 11 05:34:14 PM PDT 24
Peak memory 214708 kb
Host smart-a3180a34-dbae-4832-9136-4a5fd2e27db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378027683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.378027683
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.794037321
Short name T1
Test name
Test status
Simulation time 164883731 ps
CPU time 2.21 seconds
Started Jul 11 05:33:51 PM PDT 24
Finished Jul 11 05:34:00 PM PDT 24
Peak memory 207804 kb
Host smart-a7b6a81e-53ed-4d9c-9800-833537fb57f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794037321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.794037321
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3926823145
Short name T811
Test name
Test status
Simulation time 282026618 ps
CPU time 7.56 seconds
Started Jul 11 05:33:50 PM PDT 24
Finished Jul 11 05:34:04 PM PDT 24
Peak memory 214224 kb
Host smart-e6d668ef-af42-4b1d-82fc-473b1191b416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926823145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3926823145
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.575113434
Short name T465
Test name
Test status
Simulation time 259058210 ps
CPU time 3.58 seconds
Started Jul 11 05:33:52 PM PDT 24
Finished Jul 11 05:34:04 PM PDT 24
Peak memory 222468 kb
Host smart-46ec4e0f-d578-4963-a1f7-02712c88c1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575113434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.575113434
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2406493731
Short name T249
Test name
Test status
Simulation time 146640438 ps
CPU time 2.76 seconds
Started Jul 11 05:33:47 PM PDT 24
Finished Jul 11 05:33:53 PM PDT 24
Peak memory 208168 kb
Host smart-a47d22bf-9653-49c7-bc41-0b281edc81c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406493731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2406493731
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2829965811
Short name T285
Test name
Test status
Simulation time 52734854 ps
CPU time 2.88 seconds
Started Jul 11 05:33:53 PM PDT 24
Finished Jul 11 05:34:04 PM PDT 24
Peak memory 208680 kb
Host smart-d3915a80-283e-4113-b8f1-fd348fa7e15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829965811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2829965811
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.36040178
Short name T470
Test name
Test status
Simulation time 62295295 ps
CPU time 3.32 seconds
Started Jul 11 05:33:52 PM PDT 24
Finished Jul 11 05:34:02 PM PDT 24
Peak memory 208732 kb
Host smart-712684dc-d718-4ac0-96bb-3652de50e7db
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36040178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.36040178
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3785512980
Short name T542
Test name
Test status
Simulation time 352059207 ps
CPU time 4 seconds
Started Jul 11 05:33:44 PM PDT 24
Finished Jul 11 05:33:51 PM PDT 24
Peak memory 208656 kb
Host smart-cc037de5-2700-4967-9f4e-dabec4e93e35
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785512980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3785512980
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.938346045
Short name T599
Test name
Test status
Simulation time 950949615 ps
CPU time 5.12 seconds
Started Jul 11 05:33:52 PM PDT 24
Finished Jul 11 05:34:04 PM PDT 24
Peak memory 208188 kb
Host smart-7a206753-6fe4-410a-9e03-c4d14f4b3aa4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938346045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.938346045
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3174942832
Short name T710
Test name
Test status
Simulation time 45982406 ps
CPU time 1.78 seconds
Started Jul 11 05:33:50 PM PDT 24
Finished Jul 11 05:33:59 PM PDT 24
Peak memory 207196 kb
Host smart-491df3cb-69e6-418d-b314-fe46dfd7466c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174942832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3174942832
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3450862933
Short name T655
Test name
Test status
Simulation time 330894900 ps
CPU time 4.31 seconds
Started Jul 11 05:33:51 PM PDT 24
Finished Jul 11 05:34:02 PM PDT 24
Peak memory 208628 kb
Host smart-70dc420f-e0ef-4581-854d-336db47ec52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450862933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3450862933
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.792988634
Short name T815
Test name
Test status
Simulation time 771948171 ps
CPU time 19.17 seconds
Started Jul 11 05:33:43 PM PDT 24
Finished Jul 11 05:34:05 PM PDT 24
Peak memory 221028 kb
Host smart-eb6ad56b-3f6a-435c-be8e-31543731426e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792988634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.792988634
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.862493653
Short name T752
Test name
Test status
Simulation time 231347531 ps
CPU time 3.83 seconds
Started Jul 11 05:33:44 PM PDT 24
Finished Jul 11 05:33:51 PM PDT 24
Peak memory 207040 kb
Host smart-8ea12c47-fa96-4bd2-8f43-4651de242d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862493653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.862493653
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1002719060
Short name T392
Test name
Test status
Simulation time 83975462 ps
CPU time 1.54 seconds
Started Jul 11 05:33:50 PM PDT 24
Finished Jul 11 05:33:57 PM PDT 24
Peak memory 209920 kb
Host smart-76d4db93-ccd9-4b43-96ec-502efb69b771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002719060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1002719060
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3004365785
Short name T554
Test name
Test status
Simulation time 18428060 ps
CPU time 0.85 seconds
Started Jul 11 05:33:53 PM PDT 24
Finished Jul 11 05:34:02 PM PDT 24
Peak memory 206028 kb
Host smart-cce06b6c-9081-4315-9e76-f2d3c02e904a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004365785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3004365785
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3175490517
Short name T667
Test name
Test status
Simulation time 1453920548 ps
CPU time 37.19 seconds
Started Jul 11 05:33:51 PM PDT 24
Finished Jul 11 05:34:36 PM PDT 24
Peak memory 221736 kb
Host smart-f338e74d-aa5f-4af4-9df5-5cea84a4ab0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175490517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3175490517
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3894467865
Short name T735
Test name
Test status
Simulation time 946408660 ps
CPU time 2.96 seconds
Started Jul 11 05:33:47 PM PDT 24
Finished Jul 11 05:33:53 PM PDT 24
Peak memory 207412 kb
Host smart-788a4fd0-96fe-4a2d-b06a-c1dd3da552aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894467865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3894467865
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1550796705
Short name T841
Test name
Test status
Simulation time 165897411 ps
CPU time 2.88 seconds
Started Jul 11 05:33:54 PM PDT 24
Finished Jul 11 05:34:06 PM PDT 24
Peak memory 214328 kb
Host smart-6e2165e2-679e-48ce-8bbb-ed9e0348c37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550796705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1550796705
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.891772207
Short name T275
Test name
Test status
Simulation time 258042347 ps
CPU time 3.09 seconds
Started Jul 11 05:33:57 PM PDT 24
Finished Jul 11 05:34:10 PM PDT 24
Peak memory 217100 kb
Host smart-14665558-ceee-4479-8a52-ea78dd5aca46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891772207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.891772207
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3718229694
Short name T239
Test name
Test status
Simulation time 73017300 ps
CPU time 3.45 seconds
Started Jul 11 05:33:48 PM PDT 24
Finished Jul 11 05:33:55 PM PDT 24
Peak memory 208084 kb
Host smart-95c3f09a-65ac-4133-b1ff-7967370253af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718229694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3718229694
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.4132661112
Short name T679
Test name
Test status
Simulation time 322086769 ps
CPU time 3.81 seconds
Started Jul 11 05:33:51 PM PDT 24
Finished Jul 11 05:34:02 PM PDT 24
Peak memory 208836 kb
Host smart-6568c467-de39-49ac-8eca-78b3a2dd7dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132661112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.4132661112
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3388954966
Short name T13
Test name
Test status
Simulation time 109493168 ps
CPU time 2.19 seconds
Started Jul 11 05:33:52 PM PDT 24
Finished Jul 11 05:34:01 PM PDT 24
Peak memory 206808 kb
Host smart-6ad3365c-8565-49fc-a67d-a30fa80937ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388954966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3388954966
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.4097955847
Short name T565
Test name
Test status
Simulation time 35869644 ps
CPU time 2.5 seconds
Started Jul 11 05:33:57 PM PDT 24
Finished Jul 11 05:34:10 PM PDT 24
Peak memory 208752 kb
Host smart-1525f08a-aecd-41af-ab0f-e6be2dc34b5d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097955847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.4097955847
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3058341032
Short name T498
Test name
Test status
Simulation time 88199611 ps
CPU time 1.83 seconds
Started Jul 11 05:33:55 PM PDT 24
Finished Jul 11 05:34:07 PM PDT 24
Peak memory 206784 kb
Host smart-c9260237-a599-4e4d-ae94-51d677201f4f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058341032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3058341032
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1189199810
Short name T788
Test name
Test status
Simulation time 402547079 ps
CPU time 4.42 seconds
Started Jul 11 05:33:50 PM PDT 24
Finished Jul 11 05:34:01 PM PDT 24
Peak memory 209900 kb
Host smart-4af9cdb9-caa5-45e9-8bab-4a840b6ef3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189199810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1189199810
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3600360551
Short name T464
Test name
Test status
Simulation time 320652269 ps
CPU time 2.65 seconds
Started Jul 11 05:33:57 PM PDT 24
Finished Jul 11 05:34:10 PM PDT 24
Peak memory 208304 kb
Host smart-ad293a33-ff94-4e6e-a52a-333c1bbce490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600360551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3600360551
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1234204764
Short name T661
Test name
Test status
Simulation time 7680820652 ps
CPU time 77.47 seconds
Started Jul 11 05:33:55 PM PDT 24
Finished Jul 11 05:35:21 PM PDT 24
Peak memory 222608 kb
Host smart-693a86de-af63-4437-8521-97fb3b275e43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234204764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1234204764
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3149969871
Short name T238
Test name
Test status
Simulation time 706257189 ps
CPU time 20.28 seconds
Started Jul 11 05:33:51 PM PDT 24
Finished Jul 11 05:34:19 PM PDT 24
Peak memory 221496 kb
Host smart-406b717b-1c2a-40ac-bf56-d4a262f50bb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149969871 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3149969871
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.350701985
Short name T907
Test name
Test status
Simulation time 1471592675 ps
CPU time 42.58 seconds
Started Jul 11 05:33:43 PM PDT 24
Finished Jul 11 05:34:29 PM PDT 24
Peak memory 214356 kb
Host smart-27e74824-3b36-4f48-92c1-981566aee1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350701985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.350701985
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2957678214
Short name T594
Test name
Test status
Simulation time 299144328 ps
CPU time 2.08 seconds
Started Jul 11 05:33:52 PM PDT 24
Finished Jul 11 05:34:01 PM PDT 24
Peak memory 209980 kb
Host smart-50571bd4-b74d-45e3-8555-f226d69ce404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957678214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2957678214
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.389155692
Short name T446
Test name
Test status
Simulation time 61662370 ps
CPU time 0.96 seconds
Started Jul 11 05:33:54 PM PDT 24
Finished Jul 11 05:34:04 PM PDT 24
Peak memory 206132 kb
Host smart-a19aa17c-3b17-4bc7-a6ce-331250066942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389155692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.389155692
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2265322326
Short name T135
Test name
Test status
Simulation time 176309841 ps
CPU time 9.94 seconds
Started Jul 11 05:33:53 PM PDT 24
Finished Jul 11 05:34:11 PM PDT 24
Peak memory 214376 kb
Host smart-43f10dfd-c2d8-4d06-96d4-2c6df2da47bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2265322326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2265322326
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2987352522
Short name T703
Test name
Test status
Simulation time 314331644 ps
CPU time 2.11 seconds
Started Jul 11 05:33:53 PM PDT 24
Finished Jul 11 05:34:03 PM PDT 24
Peak memory 209388 kb
Host smart-b10f8bdf-4324-4abe-8454-b3cc56df2e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987352522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2987352522
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1545614168
Short name T47
Test name
Test status
Simulation time 180807594 ps
CPU time 2.61 seconds
Started Jul 11 05:33:56 PM PDT 24
Finished Jul 11 05:34:09 PM PDT 24
Peak memory 207648 kb
Host smart-64463df0-bcf3-40e5-8ec1-b0e2174dad8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545614168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1545614168
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.390420587
Short name T96
Test name
Test status
Simulation time 4622880143 ps
CPU time 32.79 seconds
Started Jul 11 05:33:55 PM PDT 24
Finished Jul 11 05:34:37 PM PDT 24
Peak memory 214388 kb
Host smart-deba0bb4-b83a-4385-a925-ca31711627c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390420587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.390420587
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.494643482
Short name T383
Test name
Test status
Simulation time 264528173 ps
CPU time 4.07 seconds
Started Jul 11 05:33:57 PM PDT 24
Finished Jul 11 05:34:11 PM PDT 24
Peak memory 214304 kb
Host smart-2a4790fd-8b55-46c0-9374-a3825707c890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494643482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.494643482
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.62820937
Short name T645
Test name
Test status
Simulation time 114141914 ps
CPU time 5.08 seconds
Started Jul 11 05:33:52 PM PDT 24
Finished Jul 11 05:34:05 PM PDT 24
Peak memory 214340 kb
Host smart-5d301804-3e1e-4999-9673-0c61f9ca9f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62820937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.62820937
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2657921122
Short name T418
Test name
Test status
Simulation time 566047096 ps
CPU time 5.77 seconds
Started Jul 11 05:33:54 PM PDT 24
Finished Jul 11 05:34:09 PM PDT 24
Peak memory 210476 kb
Host smart-11ecbce0-4327-4230-a3ea-981333a76e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657921122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2657921122
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3601902786
Short name T514
Test name
Test status
Simulation time 392440884 ps
CPU time 2.36 seconds
Started Jul 11 05:33:53 PM PDT 24
Finished Jul 11 05:34:03 PM PDT 24
Peak memory 206824 kb
Host smart-363371a9-4c54-436d-9910-28303710cea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601902786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3601902786
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3936571477
Short name T532
Test name
Test status
Simulation time 344600140 ps
CPU time 3.16 seconds
Started Jul 11 05:33:53 PM PDT 24
Finished Jul 11 05:34:04 PM PDT 24
Peak memory 206780 kb
Host smart-a402f1e7-b988-4aee-9ab6-09a0ae508159
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936571477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3936571477
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.567386645
Short name T549
Test name
Test status
Simulation time 239368074 ps
CPU time 2.97 seconds
Started Jul 11 05:33:48 PM PDT 24
Finished Jul 11 05:33:56 PM PDT 24
Peak memory 208772 kb
Host smart-92393070-86af-4218-98fd-f436b1a8b85f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567386645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.567386645
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1835597093
Short name T601
Test name
Test status
Simulation time 1142362891 ps
CPU time 29.45 seconds
Started Jul 11 05:33:54 PM PDT 24
Finished Jul 11 05:34:31 PM PDT 24
Peak memory 208396 kb
Host smart-baf59872-96c0-4a73-b64f-cbf25baa655c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835597093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1835597093
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.742623372
Short name T266
Test name
Test status
Simulation time 30585030 ps
CPU time 2.57 seconds
Started Jul 11 05:33:53 PM PDT 24
Finished Jul 11 05:34:04 PM PDT 24
Peak memory 214376 kb
Host smart-b90b1de7-8b9e-4c35-9c72-16068e2e673f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742623372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.742623372
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3600411914
Short name T123
Test name
Test status
Simulation time 36776478 ps
CPU time 2.18 seconds
Started Jul 11 05:33:55 PM PDT 24
Finished Jul 11 05:34:06 PM PDT 24
Peak memory 206992 kb
Host smart-6db9f92d-3516-477a-b04d-edad61c5c24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600411914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3600411914
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3199134994
Short name T819
Test name
Test status
Simulation time 2284527962 ps
CPU time 56.58 seconds
Started Jul 11 05:33:57 PM PDT 24
Finished Jul 11 05:35:05 PM PDT 24
Peak memory 216100 kb
Host smart-7ff62883-85f5-49f1-b3c8-de6b97043d0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199134994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3199134994
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3120058484
Short name T469
Test name
Test status
Simulation time 903295295 ps
CPU time 7.67 seconds
Started Jul 11 05:33:54 PM PDT 24
Finished Jul 11 05:34:11 PM PDT 24
Peak memory 209092 kb
Host smart-77ab3ba9-3b9a-4140-ab35-3b5328f059e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120058484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3120058484
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3677115063
Short name T106
Test name
Test status
Simulation time 28678879 ps
CPU time 1.97 seconds
Started Jul 11 05:33:55 PM PDT 24
Finished Jul 11 05:34:06 PM PDT 24
Peak memory 210004 kb
Host smart-7c6999e5-afe4-4115-9457-14afed6617fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677115063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3677115063
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1721896472
Short name T432
Test name
Test status
Simulation time 15911016 ps
CPU time 0.94 seconds
Started Jul 11 05:33:59 PM PDT 24
Finished Jul 11 05:34:12 PM PDT 24
Peak memory 206160 kb
Host smart-c9f0856c-4afe-4a6a-9acc-2fcaef8f79bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721896472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1721896472
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.190815354
Short name T430
Test name
Test status
Simulation time 35606427 ps
CPU time 2.55 seconds
Started Jul 11 05:33:54 PM PDT 24
Finished Jul 11 05:34:06 PM PDT 24
Peak memory 214956 kb
Host smart-8a266f1c-f7da-49d8-8f1c-74b70866d3da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=190815354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.190815354
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3173838629
Short name T68
Test name
Test status
Simulation time 167705379 ps
CPU time 3.01 seconds
Started Jul 11 05:33:58 PM PDT 24
Finished Jul 11 05:34:11 PM PDT 24
Peak memory 210308 kb
Host smart-6b70688b-3c9d-4ee9-b687-5db0f1f6b70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173838629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3173838629
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3176209015
Short name T259
Test name
Test status
Simulation time 29992176 ps
CPU time 2.36 seconds
Started Jul 11 05:33:55 PM PDT 24
Finished Jul 11 05:34:06 PM PDT 24
Peak memory 214328 kb
Host smart-12e13809-6c27-43b1-a233-7b9d740d3cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176209015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3176209015
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2933450882
Short name T342
Test name
Test status
Simulation time 277265488 ps
CPU time 3.92 seconds
Started Jul 11 05:33:59 PM PDT 24
Finished Jul 11 05:34:15 PM PDT 24
Peak memory 214028 kb
Host smart-1611fad7-c2f9-4f93-8bdf-afcd91f43c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933450882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2933450882
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_random.2339784954
Short name T401
Test name
Test status
Simulation time 227688553 ps
CPU time 8.4 seconds
Started Jul 11 05:33:55 PM PDT 24
Finished Jul 11 05:34:12 PM PDT 24
Peak memory 218388 kb
Host smart-3cfa32aa-3a3a-43e1-901a-d08c76722e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339784954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2339784954
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2820743333
Short name T328
Test name
Test status
Simulation time 1387041947 ps
CPU time 21.73 seconds
Started Jul 11 05:33:54 PM PDT 24
Finished Jul 11 05:34:25 PM PDT 24
Peak memory 208360 kb
Host smart-cb924280-d842-4583-80fe-34b0c739ba5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820743333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2820743333
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.870597979
Short name T442
Test name
Test status
Simulation time 4859871082 ps
CPU time 28.21 seconds
Started Jul 11 05:33:56 PM PDT 24
Finished Jul 11 05:34:33 PM PDT 24
Peak memory 208276 kb
Host smart-bf4300c5-2b2e-455f-a23c-dfb8f714be61
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870597979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.870597979
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2441190043
Short name T308
Test name
Test status
Simulation time 196639852 ps
CPU time 7.2 seconds
Started Jul 11 05:33:57 PM PDT 24
Finished Jul 11 05:34:15 PM PDT 24
Peak memory 208848 kb
Host smart-fe5034bc-5959-45fd-a41d-acffd085e96e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441190043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2441190043
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.301812779
Short name T471
Test name
Test status
Simulation time 153209321 ps
CPU time 5.71 seconds
Started Jul 11 05:33:58 PM PDT 24
Finished Jul 11 05:34:15 PM PDT 24
Peak memory 208088 kb
Host smart-e22e2c9c-f961-4633-a8e9-276836f516f5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301812779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.301812779
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1143068562
Short name T269
Test name
Test status
Simulation time 163085598 ps
CPU time 1.74 seconds
Started Jul 11 05:34:02 PM PDT 24
Finished Jul 11 05:34:15 PM PDT 24
Peak memory 207736 kb
Host smart-d629d257-67df-482e-90f2-8c09788226c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143068562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1143068562
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.4161368115
Short name T512
Test name
Test status
Simulation time 258297999 ps
CPU time 3.34 seconds
Started Jul 11 05:33:53 PM PDT 24
Finished Jul 11 05:34:05 PM PDT 24
Peak memory 208728 kb
Host smart-1459a919-0da1-40f5-809c-43500583b14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161368115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.4161368115
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3275118574
Short name T775
Test name
Test status
Simulation time 917775572 ps
CPU time 5.05 seconds
Started Jul 11 05:33:58 PM PDT 24
Finished Jul 11 05:34:15 PM PDT 24
Peak memory 207736 kb
Host smart-6dfd62de-2069-4677-9046-99ad12c5959e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275118574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3275118574
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1860829802
Short name T449
Test name
Test status
Simulation time 277703360 ps
CPU time 0.96 seconds
Started Jul 11 05:33:57 PM PDT 24
Finished Jul 11 05:34:09 PM PDT 24
Peak memory 206216 kb
Host smart-a94db117-afa0-456e-846d-db407924ba10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860829802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1860829802
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3915452515
Short name T423
Test name
Test status
Simulation time 129861112 ps
CPU time 2.9 seconds
Started Jul 11 05:34:05 PM PDT 24
Finished Jul 11 05:34:21 PM PDT 24
Peak memory 214332 kb
Host smart-cfb2817d-6403-45f7-a59f-797c7ca6ee3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3915452515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3915452515
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.622152807
Short name T22
Test name
Test status
Simulation time 58569011 ps
CPU time 2.64 seconds
Started Jul 11 05:34:07 PM PDT 24
Finished Jul 11 05:34:22 PM PDT 24
Peak memory 222672 kb
Host smart-078879b6-2065-42ed-9f6f-fb97918d08cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622152807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.622152807
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3276752360
Short name T289
Test name
Test status
Simulation time 46104559 ps
CPU time 2.06 seconds
Started Jul 11 05:34:00 PM PDT 24
Finished Jul 11 05:34:13 PM PDT 24
Peak memory 210212 kb
Host smart-e4418b28-b1a4-4620-b3bd-90d439a40d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276752360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3276752360
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.4226510159
Short name T607
Test name
Test status
Simulation time 2558340163 ps
CPU time 47.37 seconds
Started Jul 11 05:34:05 PM PDT 24
Finished Jul 11 05:35:05 PM PDT 24
Peak memory 209396 kb
Host smart-4833a406-0901-4282-a202-b2085a926f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226510159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.4226510159
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.226483815
Short name T608
Test name
Test status
Simulation time 122877877 ps
CPU time 3.22 seconds
Started Jul 11 05:34:04 PM PDT 24
Finished Jul 11 05:34:20 PM PDT 24
Peak memory 214280 kb
Host smart-2ade57fe-40f2-4d5a-ab39-05d79de2e8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226483815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.226483815
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2943317111
Short name T589
Test name
Test status
Simulation time 1552967752 ps
CPU time 4.61 seconds
Started Jul 11 05:33:58 PM PDT 24
Finished Jul 11 05:34:14 PM PDT 24
Peak memory 216788 kb
Host smart-5e7ec7aa-760d-41fb-bd8f-2298868b49aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943317111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2943317111
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.444201966
Short name T472
Test name
Test status
Simulation time 466260880 ps
CPU time 5.63 seconds
Started Jul 11 05:34:00 PM PDT 24
Finished Jul 11 05:34:18 PM PDT 24
Peak memory 209056 kb
Host smart-6c3a49e4-3f1c-4273-a67d-488caf83e9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444201966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.444201966
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.210410564
Short name T730
Test name
Test status
Simulation time 137581427 ps
CPU time 2.66 seconds
Started Jul 11 05:34:02 PM PDT 24
Finished Jul 11 05:34:17 PM PDT 24
Peak memory 208644 kb
Host smart-b2d53321-174f-4e88-aaf2-209be3c3ecf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210410564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.210410564
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.254438762
Short name T118
Test name
Test status
Simulation time 662898130 ps
CPU time 4.99 seconds
Started Jul 11 05:33:59 PM PDT 24
Finished Jul 11 05:34:16 PM PDT 24
Peak memory 207968 kb
Host smart-8edd8583-b7dd-45b0-ae46-2834435f9cf4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254438762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.254438762
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3313094428
Short name T453
Test name
Test status
Simulation time 41318063 ps
CPU time 2.21 seconds
Started Jul 11 05:33:57 PM PDT 24
Finished Jul 11 05:34:10 PM PDT 24
Peak memory 206960 kb
Host smart-5f2a11af-046d-492f-be71-4bc9f2c401e9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313094428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3313094428
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.455657890
Short name T592
Test name
Test status
Simulation time 159108880 ps
CPU time 4.63 seconds
Started Jul 11 05:34:03 PM PDT 24
Finished Jul 11 05:34:20 PM PDT 24
Peak memory 208728 kb
Host smart-8a59a91c-b4d0-43f1-8470-1fe89dec00ab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455657890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.455657890
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2287051490
Short name T369
Test name
Test status
Simulation time 88484455 ps
CPU time 1.83 seconds
Started Jul 11 05:34:03 PM PDT 24
Finished Jul 11 05:34:17 PM PDT 24
Peak memory 215936 kb
Host smart-5dc4e8d6-1d8a-47fb-b4fb-501fbad7b51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287051490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2287051490
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3522813587
Short name T759
Test name
Test status
Simulation time 176196337 ps
CPU time 2.46 seconds
Started Jul 11 05:34:00 PM PDT 24
Finished Jul 11 05:34:14 PM PDT 24
Peak memory 206872 kb
Host smart-90531334-26b5-4611-b5dc-5ec552b7293c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522813587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3522813587
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3358098514
Short name T690
Test name
Test status
Simulation time 4987275115 ps
CPU time 50.85 seconds
Started Jul 11 05:33:59 PM PDT 24
Finished Jul 11 05:35:02 PM PDT 24
Peak memory 215696 kb
Host smart-dd63fc30-0fbd-4465-a8cd-ba6b58a63b1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358098514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3358098514
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2619788808
Short name T524
Test name
Test status
Simulation time 6215176054 ps
CPU time 16.26 seconds
Started Jul 11 05:34:04 PM PDT 24
Finished Jul 11 05:34:33 PM PDT 24
Peak memory 208096 kb
Host smart-e29f6065-b8a8-4b51-a958-b98e505f6989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619788808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2619788808
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1997147864
Short name T745
Test name
Test status
Simulation time 492561498 ps
CPU time 4.36 seconds
Started Jul 11 05:33:58 PM PDT 24
Finished Jul 11 05:34:14 PM PDT 24
Peak memory 210640 kb
Host smart-efd03134-177a-4d86-8245-2478810d7f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997147864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1997147864
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3354045448
Short name T438
Test name
Test status
Simulation time 68567826 ps
CPU time 0.78 seconds
Started Jul 11 05:34:04 PM PDT 24
Finished Jul 11 05:34:17 PM PDT 24
Peak memory 206176 kb
Host smart-04924834-b1cf-4218-936f-6b3f49b0bf2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354045448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3354045448
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.640962088
Short name T530
Test name
Test status
Simulation time 189638238 ps
CPU time 2.46 seconds
Started Jul 11 05:34:05 PM PDT 24
Finished Jul 11 05:34:21 PM PDT 24
Peak memory 208620 kb
Host smart-085032f3-2244-48b2-92c9-1e4a7cec10b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640962088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.640962088
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1831637892
Short name T260
Test name
Test status
Simulation time 55242323 ps
CPU time 1.96 seconds
Started Jul 11 05:34:03 PM PDT 24
Finished Jul 11 05:34:18 PM PDT 24
Peak memory 214352 kb
Host smart-aaec4474-48aa-45f2-9e7c-248eec9ad219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831637892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1831637892
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3376203674
Short name T301
Test name
Test status
Simulation time 49224875 ps
CPU time 2.65 seconds
Started Jul 11 05:34:07 PM PDT 24
Finished Jul 11 05:34:23 PM PDT 24
Peak memory 214168 kb
Host smart-e21adabf-a8e3-48a3-9ca3-ab18deab46f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376203674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3376203674
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3560782368
Short name T223
Test name
Test status
Simulation time 285032006 ps
CPU time 3.73 seconds
Started Jul 11 05:34:03 PM PDT 24
Finished Jul 11 05:34:20 PM PDT 24
Peak memory 216144 kb
Host smart-8a906f41-c5dd-489d-acd4-f39fb9b4a261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560782368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3560782368
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3317649127
Short name T723
Test name
Test status
Simulation time 128875616 ps
CPU time 5.14 seconds
Started Jul 11 05:34:06 PM PDT 24
Finished Jul 11 05:34:23 PM PDT 24
Peak memory 222712 kb
Host smart-03ab6274-0c24-4bdd-8185-0a3ee8ec57e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317649127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3317649127
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.522850072
Short name T628
Test name
Test status
Simulation time 191913181 ps
CPU time 3.29 seconds
Started Jul 11 05:34:03 PM PDT 24
Finished Jul 11 05:34:19 PM PDT 24
Peak memory 208588 kb
Host smart-8bdb1440-0b84-4e6f-b96b-fe07d5f39b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522850072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.522850072
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.4055038522
Short name T621
Test name
Test status
Simulation time 833097888 ps
CPU time 8.48 seconds
Started Jul 11 05:34:00 PM PDT 24
Finished Jul 11 05:34:21 PM PDT 24
Peak memory 208568 kb
Host smart-0a9bfd60-8e7c-424b-b49b-ddb673952366
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055038522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.4055038522
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3841027203
Short name T458
Test name
Test status
Simulation time 447830044 ps
CPU time 3.3 seconds
Started Jul 11 05:34:03 PM PDT 24
Finished Jul 11 05:34:18 PM PDT 24
Peak memory 207064 kb
Host smart-3648ae05-e842-4f26-920b-b94b59ca65ef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841027203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3841027203
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2504403984
Short name T807
Test name
Test status
Simulation time 76458941 ps
CPU time 3.68 seconds
Started Jul 11 05:34:01 PM PDT 24
Finished Jul 11 05:34:17 PM PDT 24
Peak memory 208932 kb
Host smart-7228e875-599f-4718-add5-73424ba1cc6d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504403984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2504403984
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3216545714
Short name T888
Test name
Test status
Simulation time 184199028 ps
CPU time 2.32 seconds
Started Jul 11 05:34:02 PM PDT 24
Finished Jul 11 05:34:16 PM PDT 24
Peak memory 208576 kb
Host smart-c4f759ee-30c3-4e82-a319-bfd8356daf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216545714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3216545714
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2372680129
Short name T830
Test name
Test status
Simulation time 124871057 ps
CPU time 3.76 seconds
Started Jul 11 05:34:01 PM PDT 24
Finished Jul 11 05:34:16 PM PDT 24
Peak memory 208292 kb
Host smart-2866a3ca-a730-4048-82b5-7b694bbf4584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372680129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2372680129
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1612123709
Short name T126
Test name
Test status
Simulation time 586917444 ps
CPU time 28.04 seconds
Started Jul 11 05:34:06 PM PDT 24
Finished Jul 11 05:34:48 PM PDT 24
Peak memory 222504 kb
Host smart-7a0da782-7d8d-43f8-acb6-d0bd539e7e60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612123709 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1612123709
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3505610322
Short name T639
Test name
Test status
Simulation time 212345373 ps
CPU time 2.89 seconds
Started Jul 11 05:34:02 PM PDT 24
Finished Jul 11 05:34:18 PM PDT 24
Peak memory 209188 kb
Host smart-77d56bb6-b73f-4984-bca3-79a7838fef0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505610322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3505610322
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.938606194
Short name T478
Test name
Test status
Simulation time 44335606 ps
CPU time 2.28 seconds
Started Jul 11 05:34:08 PM PDT 24
Finished Jul 11 05:34:23 PM PDT 24
Peak memory 210144 kb
Host smart-3778ea1c-4a61-46f0-90dd-1da463749ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938606194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.938606194
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1101700108
Short name T443
Test name
Test status
Simulation time 53797622 ps
CPU time 0.9 seconds
Started Jul 11 05:34:16 PM PDT 24
Finished Jul 11 05:34:29 PM PDT 24
Peak memory 205944 kb
Host smart-a66b2395-9f77-498a-864f-c22bc2b286ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101700108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1101700108
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1080830345
Short name T33
Test name
Test status
Simulation time 64287111 ps
CPU time 2.28 seconds
Started Jul 11 05:34:11 PM PDT 24
Finished Jul 11 05:34:26 PM PDT 24
Peak memory 214304 kb
Host smart-20140463-f5bf-4eae-97b9-d2ce65625e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080830345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1080830345
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1074240752
Short name T738
Test name
Test status
Simulation time 80779613 ps
CPU time 2.18 seconds
Started Jul 11 05:34:08 PM PDT 24
Finished Jul 11 05:34:23 PM PDT 24
Peak memory 207924 kb
Host smart-4052022f-a117-4440-a10e-45457fbe915d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074240752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1074240752
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.348465572
Short name T915
Test name
Test status
Simulation time 556992479 ps
CPU time 4.46 seconds
Started Jul 11 05:34:10 PM PDT 24
Finished Jul 11 05:34:28 PM PDT 24
Peak memory 209396 kb
Host smart-2db7e128-d2ab-4f74-be3c-28a2801c8a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348465572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.348465572
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2881934223
Short name T537
Test name
Test status
Simulation time 83678736 ps
CPU time 3.68 seconds
Started Jul 11 05:34:12 PM PDT 24
Finished Jul 11 05:34:30 PM PDT 24
Peak memory 209476 kb
Host smart-ba4d12c3-5332-462d-8491-5c03da9a2af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881934223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2881934223
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2455441979
Short name T557
Test name
Test status
Simulation time 3046241643 ps
CPU time 54.5 seconds
Started Jul 11 05:34:11 PM PDT 24
Finished Jul 11 05:35:19 PM PDT 24
Peak memory 222376 kb
Host smart-52562667-c7ca-421b-9a21-987c49c1e160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455441979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2455441979
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2090225949
Short name T813
Test name
Test status
Simulation time 75383402 ps
CPU time 1.75 seconds
Started Jul 11 05:34:03 PM PDT 24
Finished Jul 11 05:34:18 PM PDT 24
Peak memory 206132 kb
Host smart-333d00ad-261d-4df0-85fc-01fa1826e8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090225949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2090225949
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3713240145
Short name T402
Test name
Test status
Simulation time 113669451 ps
CPU time 3.72 seconds
Started Jul 11 05:34:07 PM PDT 24
Finished Jul 11 05:34:24 PM PDT 24
Peak memory 208484 kb
Host smart-902a2c09-17fd-45a6-a653-30b4cb309898
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713240145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3713240145
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2614940733
Short name T726
Test name
Test status
Simulation time 319378634 ps
CPU time 4.97 seconds
Started Jul 11 05:34:07 PM PDT 24
Finished Jul 11 05:34:25 PM PDT 24
Peak memory 207856 kb
Host smart-725e4f7b-f204-40ae-b29c-f0aa94dfa012
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614940733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2614940733
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.363557150
Short name T800
Test name
Test status
Simulation time 54558160 ps
CPU time 2.97 seconds
Started Jul 11 05:34:03 PM PDT 24
Finished Jul 11 05:34:19 PM PDT 24
Peak memory 206932 kb
Host smart-61c8581d-138d-4838-976c-25d7d83f6d83
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363557150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.363557150
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1432613551
Short name T384
Test name
Test status
Simulation time 48753710 ps
CPU time 1.99 seconds
Started Jul 11 05:34:12 PM PDT 24
Finished Jul 11 05:34:28 PM PDT 24
Peak memory 217896 kb
Host smart-ba4da8f1-7347-4394-8f0f-c2bf07ab7b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432613551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1432613551
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.385926547
Short name T891
Test name
Test status
Simulation time 22086538 ps
CPU time 1.73 seconds
Started Jul 11 05:34:03 PM PDT 24
Finished Jul 11 05:34:17 PM PDT 24
Peak memory 206796 kb
Host smart-5f717c0e-0604-417b-a3b6-70c9c2969eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385926547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.385926547
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2777166081
Short name T879
Test name
Test status
Simulation time 4095033353 ps
CPU time 36.66 seconds
Started Jul 11 05:34:18 PM PDT 24
Finished Jul 11 05:35:07 PM PDT 24
Peak memory 222104 kb
Host smart-5b892f33-bcd5-401f-b5cb-36252fbab5b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777166081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2777166081
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.2429857724
Short name T313
Test name
Test status
Simulation time 556669678 ps
CPU time 8.89 seconds
Started Jul 11 05:34:18 PM PDT 24
Finished Jul 11 05:34:38 PM PDT 24
Peak memory 220468 kb
Host smart-a9ed7169-266b-4828-afd2-b3fbd12972a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429857724 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.2429857724
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3238481420
Short name T306
Test name
Test status
Simulation time 160969334 ps
CPU time 6.46 seconds
Started Jul 11 05:34:11 PM PDT 24
Finished Jul 11 05:34:31 PM PDT 24
Peak memory 208732 kb
Host smart-b9101e65-8bda-4af6-b013-d93100cd169c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238481420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3238481420
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.45492674
Short name T676
Test name
Test status
Simulation time 121385071 ps
CPU time 3.95 seconds
Started Jul 11 05:34:13 PM PDT 24
Finished Jul 11 05:34:31 PM PDT 24
Peak memory 210712 kb
Host smart-ca80c65f-84d8-4e1f-b5b3-5e388f7baa63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45492674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.45492674
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.546919590
Short name T797
Test name
Test status
Simulation time 12218929 ps
CPU time 0.79 seconds
Started Jul 11 05:34:31 PM PDT 24
Finished Jul 11 05:34:42 PM PDT 24
Peak memory 205920 kb
Host smart-7c192ef1-6fd8-4247-aac4-5ded6643d450
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546919590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.546919590
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.361698359
Short name T886
Test name
Test status
Simulation time 84825256 ps
CPU time 4.85 seconds
Started Jul 11 05:34:20 PM PDT 24
Finished Jul 11 05:34:37 PM PDT 24
Peak memory 215040 kb
Host smart-f521c25e-bbd0-4090-8b20-5d483d4d5753
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=361698359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.361698359
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2898671034
Short name T801
Test name
Test status
Simulation time 501340385 ps
CPU time 3.74 seconds
Started Jul 11 05:34:12 PM PDT 24
Finished Jul 11 05:34:30 PM PDT 24
Peak memory 214724 kb
Host smart-a7f484a8-888e-4881-b50d-3dc9c62a95ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898671034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2898671034
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3540130703
Short name T631
Test name
Test status
Simulation time 82576789 ps
CPU time 1.59 seconds
Started Jul 11 05:34:14 PM PDT 24
Finished Jul 11 05:34:29 PM PDT 24
Peak memory 207512 kb
Host smart-50684321-4d0a-43df-8631-27335cfd65a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540130703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3540130703
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3516425038
Short name T26
Test name
Test status
Simulation time 669030836 ps
CPU time 6.09 seconds
Started Jul 11 05:34:21 PM PDT 24
Finished Jul 11 05:34:39 PM PDT 24
Peak memory 214188 kb
Host smart-c90254dd-3dd1-456f-a82b-7a457ae5958d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516425038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3516425038
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3336337094
Short name T52
Test name
Test status
Simulation time 681113064 ps
CPU time 1.82 seconds
Started Jul 11 05:34:15 PM PDT 24
Finished Jul 11 05:34:30 PM PDT 24
Peak memory 214308 kb
Host smart-8c746a8b-65f1-49b6-b302-428caef05a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336337094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3336337094
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1896477958
Short name T733
Test name
Test status
Simulation time 455203274 ps
CPU time 5.27 seconds
Started Jul 11 05:34:17 PM PDT 24
Finished Jul 11 05:34:35 PM PDT 24
Peak memory 206708 kb
Host smart-e0156bcc-072b-45a2-aa33-db55cafc0292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896477958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1896477958
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.235512395
Short name T560
Test name
Test status
Simulation time 350504009 ps
CPU time 5.25 seconds
Started Jul 11 05:34:16 PM PDT 24
Finished Jul 11 05:34:33 PM PDT 24
Peak memory 208932 kb
Host smart-cfecc9da-5f86-415c-8ac4-514e1303fc81
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235512395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.235512395
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2017022335
Short name T705
Test name
Test status
Simulation time 60493802 ps
CPU time 2.32 seconds
Started Jul 11 05:34:15 PM PDT 24
Finished Jul 11 05:34:30 PM PDT 24
Peak memory 206768 kb
Host smart-54f0d24e-858f-44aa-92eb-dd197227ef17
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017022335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2017022335
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3725252302
Short name T352
Test name
Test status
Simulation time 110763084 ps
CPU time 2.88 seconds
Started Jul 11 05:34:15 PM PDT 24
Finished Jul 11 05:34:31 PM PDT 24
Peak memory 206988 kb
Host smart-3280deff-6897-40c5-a368-75b7e3b31337
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725252302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3725252302
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1476637518
Short name T694
Test name
Test status
Simulation time 106208417 ps
CPU time 4.48 seconds
Started Jul 11 05:34:21 PM PDT 24
Finished Jul 11 05:34:37 PM PDT 24
Peak memory 218444 kb
Host smart-95db8473-de7a-42c2-bdc0-3d83854d533a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476637518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1476637518
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.543578804
Short name T734
Test name
Test status
Simulation time 335986835 ps
CPU time 5.45 seconds
Started Jul 11 05:34:21 PM PDT 24
Finished Jul 11 05:34:38 PM PDT 24
Peak memory 208616 kb
Host smart-00014d25-5a6d-4aa3-8f26-ed9809e2efc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543578804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.543578804
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1735336146
Short name T256
Test name
Test status
Simulation time 275010423 ps
CPU time 3.77 seconds
Started Jul 11 05:34:13 PM PDT 24
Finished Jul 11 05:34:31 PM PDT 24
Peak memory 218432 kb
Host smart-20706e4c-2ac8-4c1d-ad43-9718047d84dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735336146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1735336146
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.47187616
Short name T181
Test name
Test status
Simulation time 142890630 ps
CPU time 1.59 seconds
Started Jul 11 05:34:21 PM PDT 24
Finished Jul 11 05:34:34 PM PDT 24
Peak memory 209756 kb
Host smart-7fc92880-0208-41a3-8429-9b64f41db5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47187616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.47187616
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1782520881
Short name T439
Test name
Test status
Simulation time 60922821 ps
CPU time 0.94 seconds
Started Jul 11 05:34:20 PM PDT 24
Finished Jul 11 05:34:33 PM PDT 24
Peak memory 206004 kb
Host smart-1add0d54-1c42-4035-b566-b2a7f5fbaafb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782520881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1782520881
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.636821398
Short name T110
Test name
Test status
Simulation time 138508996 ps
CPU time 7.8 seconds
Started Jul 11 05:34:24 PM PDT 24
Finished Jul 11 05:34:42 PM PDT 24
Peak memory 214504 kb
Host smart-105af446-6a40-4646-bcda-8fb8595df2c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=636821398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.636821398
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1171490300
Short name T21
Test name
Test status
Simulation time 118573089 ps
CPU time 2.9 seconds
Started Jul 11 05:34:22 PM PDT 24
Finished Jul 11 05:34:36 PM PDT 24
Peak memory 210216 kb
Host smart-8cc3d0eb-3315-43c1-a57d-c8052ee28fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171490300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1171490300
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.4039603964
Short name T712
Test name
Test status
Simulation time 69432057 ps
CPU time 2.05 seconds
Started Jul 11 05:34:21 PM PDT 24
Finished Jul 11 05:34:34 PM PDT 24
Peak memory 207532 kb
Host smart-627f8ee5-c4ae-4768-980e-7a53da07e491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039603964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.4039603964
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3596841009
Short name T802
Test name
Test status
Simulation time 78845270 ps
CPU time 2.38 seconds
Started Jul 11 05:34:23 PM PDT 24
Finished Jul 11 05:34:37 PM PDT 24
Peak memory 214296 kb
Host smart-eba173fe-225b-407a-b39d-2a02c2d95046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596841009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3596841009
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.4035735003
Short name T343
Test name
Test status
Simulation time 49576937 ps
CPU time 2.92 seconds
Started Jul 11 05:34:25 PM PDT 24
Finished Jul 11 05:34:39 PM PDT 24
Peak memory 214308 kb
Host smart-d2ad8196-44dd-42fe-bd4d-85b6581add96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035735003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.4035735003
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2577349384
Short name T747
Test name
Test status
Simulation time 39655679 ps
CPU time 2.86 seconds
Started Jul 11 05:34:25 PM PDT 24
Finished Jul 11 05:34:38 PM PDT 24
Peak memory 209324 kb
Host smart-495dd450-1283-4e4b-a749-8b8ae3742b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577349384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2577349384
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1216603106
Short name T376
Test name
Test status
Simulation time 212644047 ps
CPU time 7.83 seconds
Started Jul 11 05:34:20 PM PDT 24
Finished Jul 11 05:34:39 PM PDT 24
Peak memory 209024 kb
Host smart-30255b0a-b0fd-4f1a-9d28-4e72fcee7a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216603106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1216603106
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1445140310
Short name T258
Test name
Test status
Simulation time 289351643 ps
CPU time 2.87 seconds
Started Jul 11 05:34:19 PM PDT 24
Finished Jul 11 05:34:33 PM PDT 24
Peak memory 206844 kb
Host smart-a8066c44-09fb-469a-9fe9-802d9ecfdc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445140310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1445140310
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.217536980
Short name T540
Test name
Test status
Simulation time 57042253 ps
CPU time 3.09 seconds
Started Jul 11 05:34:26 PM PDT 24
Finished Jul 11 05:34:40 PM PDT 24
Peak memory 208648 kb
Host smart-9d59ccc7-e76c-4d63-80e2-49ad1aa5bc8c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217536980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.217536980
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1103084529
Short name T493
Test name
Test status
Simulation time 101492241 ps
CPU time 3.52 seconds
Started Jul 11 05:34:21 PM PDT 24
Finished Jul 11 05:34:36 PM PDT 24
Peak memory 206924 kb
Host smart-2e250caf-cc3d-47d4-ac5e-defff7e54a4c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103084529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1103084529
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3604829215
Short name T419
Test name
Test status
Simulation time 289165532 ps
CPU time 3.56 seconds
Started Jul 11 05:34:21 PM PDT 24
Finished Jul 11 05:34:36 PM PDT 24
Peak memory 208940 kb
Host smart-12ec3643-1efa-468c-9181-29adf83120a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604829215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3604829215
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.4024001939
Short name T522
Test name
Test status
Simulation time 334229340 ps
CPU time 4.25 seconds
Started Jul 11 05:34:21 PM PDT 24
Finished Jul 11 05:34:37 PM PDT 24
Peak memory 207980 kb
Host smart-2b10c862-1933-45ae-a1aa-2ba3e0791122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024001939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.4024001939
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3992316357
Short name T199
Test name
Test status
Simulation time 2373007035 ps
CPU time 22 seconds
Started Jul 11 05:34:20 PM PDT 24
Finished Jul 11 05:34:53 PM PDT 24
Peak memory 216964 kb
Host smart-8acc55c3-6465-45fb-b482-a826b6338be9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992316357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3992316357
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1806240554
Short name T185
Test name
Test status
Simulation time 2674029088 ps
CPU time 25.42 seconds
Started Jul 11 05:34:21 PM PDT 24
Finished Jul 11 05:34:58 PM PDT 24
Peak memory 222708 kb
Host smart-c893b790-9a84-4eb2-bd17-dbd89ee41925
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806240554 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1806240554
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3714564810
Short name T271
Test name
Test status
Simulation time 14566878555 ps
CPU time 54.35 seconds
Started Jul 11 05:34:31 PM PDT 24
Finished Jul 11 05:35:36 PM PDT 24
Peak memory 218144 kb
Host smart-32ab72ff-c266-4d79-95ae-01eddb17fdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714564810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3714564810
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1969404908
Short name T162
Test name
Test status
Simulation time 140448073 ps
CPU time 1.5 seconds
Started Jul 11 05:34:24 PM PDT 24
Finished Jul 11 05:34:36 PM PDT 24
Peak memory 214400 kb
Host smart-3388e65c-aa30-49e3-9057-45ef95ad2c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969404908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1969404908
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1694100114
Short name T87
Test name
Test status
Simulation time 52067244 ps
CPU time 0.96 seconds
Started Jul 11 05:34:30 PM PDT 24
Finished Jul 11 05:34:41 PM PDT 24
Peak memory 206116 kb
Host smart-f15989bc-801b-4af7-98da-fbae902979bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694100114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1694100114
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.517539029
Short name T9
Test name
Test status
Simulation time 338470049 ps
CPU time 4.96 seconds
Started Jul 11 05:34:27 PM PDT 24
Finished Jul 11 05:34:43 PM PDT 24
Peak memory 221936 kb
Host smart-8827f9f9-6ef9-4ea2-9dc3-0e25b83e59a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517539029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.517539029
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.4157084719
Short name T838
Test name
Test status
Simulation time 48516819 ps
CPU time 1.88 seconds
Started Jul 11 05:34:26 PM PDT 24
Finished Jul 11 05:34:38 PM PDT 24
Peak memory 207524 kb
Host smart-a67a11fd-63d6-4a35-bb05-29f850227f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157084719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.4157084719
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.139975720
Short name T303
Test name
Test status
Simulation time 294555560 ps
CPU time 6.24 seconds
Started Jul 11 05:34:25 PM PDT 24
Finished Jul 11 05:34:42 PM PDT 24
Peak memory 214332 kb
Host smart-abcb5e04-7412-49ab-b8e6-41a4e485b02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139975720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.139975720
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1813684956
Short name T299
Test name
Test status
Simulation time 33678101 ps
CPU time 1.81 seconds
Started Jul 11 05:34:29 PM PDT 24
Finished Jul 11 05:34:41 PM PDT 24
Peak memory 214260 kb
Host smart-c53ceeb2-bb18-448d-bd42-ea79ba8210ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813684956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1813684956
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.4119634944
Short name T65
Test name
Test status
Simulation time 71053105 ps
CPU time 3.4 seconds
Started Jul 11 05:34:32 PM PDT 24
Finished Jul 11 05:34:45 PM PDT 24
Peak memory 214376 kb
Host smart-25dc44e6-1285-4441-ab24-0481f0276286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119634944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.4119634944
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.4140638072
Short name T581
Test name
Test status
Simulation time 2832004488 ps
CPU time 87.01 seconds
Started Jul 11 05:34:20 PM PDT 24
Finished Jul 11 05:35:58 PM PDT 24
Peak memory 210612 kb
Host smart-f43b185c-b599-4d66-ba76-79c07a9fa30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140638072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.4140638072
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1349532882
Short name T785
Test name
Test status
Simulation time 2041300692 ps
CPU time 6.4 seconds
Started Jul 11 05:34:22 PM PDT 24
Finished Jul 11 05:34:39 PM PDT 24
Peak memory 208008 kb
Host smart-0dcfc3c5-1921-4355-9344-c80247706cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349532882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1349532882
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2160145764
Short name T642
Test name
Test status
Simulation time 77917807 ps
CPU time 2.85 seconds
Started Jul 11 05:34:21 PM PDT 24
Finished Jul 11 05:34:36 PM PDT 24
Peak memory 208068 kb
Host smart-a88ab6de-26c7-455b-b198-717d6b62c9fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160145764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2160145764
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3287949347
Short name T877
Test name
Test status
Simulation time 1991563923 ps
CPU time 18.43 seconds
Started Jul 11 05:34:31 PM PDT 24
Finished Jul 11 05:34:59 PM PDT 24
Peak memory 208088 kb
Host smart-3f48246f-ee85-4de3-9b66-0719f0975f1a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287949347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3287949347
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.637561516
Short name T728
Test name
Test status
Simulation time 470581441 ps
CPU time 4.3 seconds
Started Jul 11 05:34:21 PM PDT 24
Finished Jul 11 05:34:37 PM PDT 24
Peak memory 208652 kb
Host smart-4dea8767-bb52-4ec8-bf50-f47782393b15
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637561516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.637561516
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1651445707
Short name T696
Test name
Test status
Simulation time 147880996 ps
CPU time 2.33 seconds
Started Jul 11 05:34:36 PM PDT 24
Finished Jul 11 05:34:47 PM PDT 24
Peak memory 208260 kb
Host smart-70cac4a6-8f32-449e-ac81-ba855eccbb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651445707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1651445707
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1063156373
Short name T686
Test name
Test status
Simulation time 43555406 ps
CPU time 1.72 seconds
Started Jul 11 05:34:25 PM PDT 24
Finished Jul 11 05:34:37 PM PDT 24
Peak memory 206852 kb
Host smart-9c0e6786-7c8c-47da-aca2-439dacae58a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063156373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1063156373
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2781519331
Short name T348
Test name
Test status
Simulation time 5492575542 ps
CPU time 123.67 seconds
Started Jul 11 05:34:31 PM PDT 24
Finished Jul 11 05:36:45 PM PDT 24
Peak memory 221580 kb
Host smart-e9c8d4bf-18c7-44f2-8ca8-e1325e068cf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781519331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2781519331
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3144926075
Short name T481
Test name
Test status
Simulation time 2137657850 ps
CPU time 4.65 seconds
Started Jul 11 05:34:20 PM PDT 24
Finished Jul 11 05:34:36 PM PDT 24
Peak memory 208008 kb
Host smart-6605a9ce-fa83-47f4-893f-1c9cae9ca700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144926075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3144926075
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2681847278
Short name T391
Test name
Test status
Simulation time 208472400 ps
CPU time 4.07 seconds
Started Jul 11 05:34:27 PM PDT 24
Finished Jul 11 05:34:42 PM PDT 24
Peak memory 210364 kb
Host smart-9faca0dc-fae4-40ed-bea0-66fad47137fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681847278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2681847278
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.111963967
Short name T97
Test name
Test status
Simulation time 48708892 ps
CPU time 0.87 seconds
Started Jul 11 05:33:24 PM PDT 24
Finished Jul 11 05:33:27 PM PDT 24
Peak memory 205896 kb
Host smart-af6248ef-93fe-42b4-8b7f-c26b4469c8e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111963967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.111963967
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.4289177543
Short name T410
Test name
Test status
Simulation time 1750878503 ps
CPU time 14.18 seconds
Started Jul 11 05:33:07 PM PDT 24
Finished Jul 11 05:33:23 PM PDT 24
Peak memory 215528 kb
Host smart-f7d74f39-27f2-4cd0-b1b0-113339eb6702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4289177543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.4289177543
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2177510513
Short name T40
Test name
Test status
Simulation time 942026309 ps
CPU time 6.49 seconds
Started Jul 11 05:33:03 PM PDT 24
Finished Jul 11 05:33:11 PM PDT 24
Peak memory 214300 kb
Host smart-1ecd2e7b-fdff-4d41-bd94-6bd44754b18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177510513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2177510513
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.330432808
Short name T274
Test name
Test status
Simulation time 203744224 ps
CPU time 3.89 seconds
Started Jul 11 05:33:06 PM PDT 24
Finished Jul 11 05:33:13 PM PDT 24
Peak memory 214328 kb
Host smart-279b78ba-4b99-43e3-a60e-53ab2ea14f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330432808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.330432808
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.4160026393
Short name T643
Test name
Test status
Simulation time 106348254 ps
CPU time 3.03 seconds
Started Jul 11 05:33:10 PM PDT 24
Finished Jul 11 05:33:16 PM PDT 24
Peak memory 214364 kb
Host smart-70e0ae21-242f-448f-b3a5-92fa05e8063d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160026393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4160026393
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2172310365
Short name T603
Test name
Test status
Simulation time 48189616 ps
CPU time 2.13 seconds
Started Jul 11 05:33:05 PM PDT 24
Finished Jul 11 05:33:10 PM PDT 24
Peak memory 214272 kb
Host smart-f370c334-90b8-4975-ac43-3bce1b372174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172310365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2172310365
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1157099838
Short name T282
Test name
Test status
Simulation time 68399091 ps
CPU time 1.96 seconds
Started Jul 11 05:33:10 PM PDT 24
Finished Jul 11 05:33:15 PM PDT 24
Peak memory 208156 kb
Host smart-c3c571bc-24b4-424f-b2da-93b848e41eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157099838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1157099838
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2982524774
Short name T823
Test name
Test status
Simulation time 1246347960 ps
CPU time 8.61 seconds
Started Jul 11 05:33:07 PM PDT 24
Finished Jul 11 05:33:18 PM PDT 24
Peak memory 214176 kb
Host smart-2acf4fe9-0595-4e8c-aaa8-6b228d2daf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982524774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2982524774
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2432645926
Short name T44
Test name
Test status
Simulation time 1127522885 ps
CPU time 12.13 seconds
Started Jul 11 05:33:28 PM PDT 24
Finished Jul 11 05:33:42 PM PDT 24
Peak memory 232176 kb
Host smart-8b6d4858-5e68-427b-9b02-32eef30878e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432645926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2432645926
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1543925982
Short name T862
Test name
Test status
Simulation time 287635168 ps
CPU time 4.35 seconds
Started Jul 11 05:33:06 PM PDT 24
Finished Jul 11 05:33:13 PM PDT 24
Peak memory 208612 kb
Host smart-d36ea740-a4cf-43e3-b08d-05b221423927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543925982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1543925982
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3077004202
Short name T650
Test name
Test status
Simulation time 187788513 ps
CPU time 3.46 seconds
Started Jul 11 05:33:07 PM PDT 24
Finished Jul 11 05:33:13 PM PDT 24
Peak memory 206784 kb
Host smart-12e51c78-19aa-4336-969f-01396e0cec98
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077004202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3077004202
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3308314211
Short name T479
Test name
Test status
Simulation time 836226899 ps
CPU time 6.05 seconds
Started Jul 11 05:33:04 PM PDT 24
Finished Jul 11 05:33:13 PM PDT 24
Peak memory 208900 kb
Host smart-065fe498-f34a-4db0-846c-dc59785a68b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308314211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3308314211
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.4177446659
Short name T663
Test name
Test status
Simulation time 55658742 ps
CPU time 2.85 seconds
Started Jul 11 05:33:07 PM PDT 24
Finished Jul 11 05:33:12 PM PDT 24
Peak memory 207024 kb
Host smart-c80f1150-a41b-4a4d-b949-ec50bfd6d3ba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177446659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.4177446659
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2758988748
Short name T577
Test name
Test status
Simulation time 79878558 ps
CPU time 2.24 seconds
Started Jul 11 05:33:25 PM PDT 24
Finished Jul 11 05:33:31 PM PDT 24
Peak memory 209024 kb
Host smart-8875b1dc-aa2f-43ac-b9fa-d8a263b15d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758988748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2758988748
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1959702731
Short name T485
Test name
Test status
Simulation time 98366069 ps
CPU time 3.7 seconds
Started Jul 11 05:33:04 PM PDT 24
Finished Jul 11 05:33:10 PM PDT 24
Peak memory 208856 kb
Host smart-d0e25aa1-0249-4ba7-8fa4-dc2f043beca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959702731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1959702731
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2118755845
Short name T117
Test name
Test status
Simulation time 504098331 ps
CPU time 10.87 seconds
Started Jul 11 05:33:28 PM PDT 24
Finished Jul 11 05:33:41 PM PDT 24
Peak memory 222572 kb
Host smart-5da5dfa7-c8d7-4444-b9d2-8afbae3192d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118755845 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2118755845
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.970299502
Short name T296
Test name
Test status
Simulation time 540453231 ps
CPU time 2.45 seconds
Started Jul 11 05:33:08 PM PDT 24
Finished Jul 11 05:33:13 PM PDT 24
Peak memory 207976 kb
Host smart-5913e93c-d870-493f-8011-87336fb57701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970299502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.970299502
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3154006130
Short name T393
Test name
Test status
Simulation time 593566595 ps
CPU time 3.7 seconds
Started Jul 11 05:33:27 PM PDT 24
Finished Jul 11 05:33:33 PM PDT 24
Peak memory 210236 kb
Host smart-9b95440b-39cc-48f0-a9c9-b1aa1148c325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154006130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3154006130
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2054901663
Short name T820
Test name
Test status
Simulation time 27262978 ps
CPU time 0.77 seconds
Started Jul 11 05:34:35 PM PDT 24
Finished Jul 11 05:34:45 PM PDT 24
Peak memory 205992 kb
Host smart-3a85c7bd-4ef5-42a5-8b22-91c427160f11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054901663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2054901663
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2798081335
Short name T910
Test name
Test status
Simulation time 564136444 ps
CPU time 8.31 seconds
Started Jul 11 05:34:33 PM PDT 24
Finished Jul 11 05:34:51 PM PDT 24
Peak memory 209648 kb
Host smart-0ed3165a-8fa8-4c03-b352-062826451af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798081335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2798081335
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3353598066
Short name T716
Test name
Test status
Simulation time 176424992 ps
CPU time 3.37 seconds
Started Jul 11 05:34:25 PM PDT 24
Finished Jul 11 05:34:39 PM PDT 24
Peak memory 218392 kb
Host smart-08701406-9e2f-4253-b843-eeb8b343a6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353598066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3353598066
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.620641774
Short name T27
Test name
Test status
Simulation time 113906596 ps
CPU time 3.73 seconds
Started Jul 11 05:34:27 PM PDT 24
Finished Jul 11 05:34:40 PM PDT 24
Peak memory 209612 kb
Host smart-1be268a3-def2-4f2b-9f90-e7411401c166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620641774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.620641774
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2480349328
Short name T344
Test name
Test status
Simulation time 43676296 ps
CPU time 2.1 seconds
Started Jul 11 05:34:25 PM PDT 24
Finished Jul 11 05:34:38 PM PDT 24
Peak memory 214312 kb
Host smart-27791201-b758-465f-8fc4-678e40c664cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480349328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2480349328
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.600363740
Short name T850
Test name
Test status
Simulation time 39017201 ps
CPU time 1.75 seconds
Started Jul 11 05:34:32 PM PDT 24
Finished Jul 11 05:34:43 PM PDT 24
Peak memory 206832 kb
Host smart-9eee76ea-e827-454f-9569-7cb8b929fe8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600363740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.600363740
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2289672092
Short name T297
Test name
Test status
Simulation time 92503254 ps
CPU time 4.35 seconds
Started Jul 11 05:34:30 PM PDT 24
Finished Jul 11 05:34:45 PM PDT 24
Peak memory 209940 kb
Host smart-72f0bd2e-86a9-4f1d-afe7-cd71579051b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289672092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2289672092
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3975567898
Short name T101
Test name
Test status
Simulation time 645968641 ps
CPU time 16.47 seconds
Started Jul 11 05:34:27 PM PDT 24
Finished Jul 11 05:34:54 PM PDT 24
Peak memory 207896 kb
Host smart-412817be-0f17-4ff7-be30-b487436c580b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975567898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3975567898
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.885393680
Short name T771
Test name
Test status
Simulation time 2953956262 ps
CPU time 35.58 seconds
Started Jul 11 05:34:27 PM PDT 24
Finished Jul 11 05:35:13 PM PDT 24
Peak memory 209032 kb
Host smart-eacc0c73-344c-4621-9922-0b62605b49f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885393680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.885393680
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.555947318
Short name T253
Test name
Test status
Simulation time 136255879 ps
CPU time 2.55 seconds
Started Jul 11 05:34:28 PM PDT 24
Finished Jul 11 05:34:41 PM PDT 24
Peak memory 206832 kb
Host smart-a0284d6d-c68b-467d-bfa3-6ef7967a1525
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555947318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.555947318
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1766711952
Short name T191
Test name
Test status
Simulation time 34504249 ps
CPU time 2.55 seconds
Started Jul 11 05:34:29 PM PDT 24
Finished Jul 11 05:34:42 PM PDT 24
Peak memory 207400 kb
Host smart-43b4d244-6088-4515-8ffd-b9ce2d58075f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766711952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1766711952
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2506162198
Short name T787
Test name
Test status
Simulation time 80611149 ps
CPU time 2.51 seconds
Started Jul 11 05:34:46 PM PDT 24
Finished Jul 11 05:34:56 PM PDT 24
Peak memory 208028 kb
Host smart-dcbcc94c-7103-41c8-beb7-4147f49c1489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506162198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2506162198
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.293391808
Short name T616
Test name
Test status
Simulation time 622571674 ps
CPU time 6.8 seconds
Started Jul 11 05:34:28 PM PDT 24
Finished Jul 11 05:34:45 PM PDT 24
Peak memory 208552 kb
Host smart-66eccea1-59e3-44a4-9968-6609eec6aae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293391808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.293391808
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.4159729874
Short name T887
Test name
Test status
Simulation time 98576752 ps
CPU time 5.17 seconds
Started Jul 11 05:34:26 PM PDT 24
Finished Jul 11 05:34:41 PM PDT 24
Peak memory 209124 kb
Host smart-a52dfb17-e2cd-471c-9bd9-89cc404aea23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159729874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.4159729874
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.493208532
Short name T188
Test name
Test status
Simulation time 594032126 ps
CPU time 21.37 seconds
Started Jul 11 05:34:42 PM PDT 24
Finished Jul 11 05:35:11 PM PDT 24
Peak memory 221384 kb
Host smart-edf60830-b3fe-48e6-bc65-877892febe92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493208532 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.493208532
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3983688469
Short name T329
Test name
Test status
Simulation time 272015780 ps
CPU time 8.22 seconds
Started Jul 11 05:34:29 PM PDT 24
Finished Jul 11 05:34:47 PM PDT 24
Peak memory 214224 kb
Host smart-4b69dc4f-b2ee-412c-8080-d1a0ef94bbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983688469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3983688469
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1796041806
Short name T685
Test name
Test status
Simulation time 128997228 ps
CPU time 1.76 seconds
Started Jul 11 05:34:28 PM PDT 24
Finished Jul 11 05:34:40 PM PDT 24
Peak memory 210036 kb
Host smart-34cbb2f7-5e36-4599-819b-5f7117c7e795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796041806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1796041806
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2813227954
Short name T739
Test name
Test status
Simulation time 42306786 ps
CPU time 0.83 seconds
Started Jul 11 05:34:36 PM PDT 24
Finished Jul 11 05:34:47 PM PDT 24
Peak memory 205900 kb
Host smart-ce754ad5-2756-440b-b4a9-7e8ac6f121a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813227954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2813227954
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.702759269
Short name T248
Test name
Test status
Simulation time 218980702 ps
CPU time 2.74 seconds
Started Jul 11 05:34:33 PM PDT 24
Finished Jul 11 05:34:45 PM PDT 24
Peak memory 214440 kb
Host smart-dbe133d7-ee91-4d31-b8c8-9cfa501d3514
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=702759269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.702759269
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2563328529
Short name T32
Test name
Test status
Simulation time 44244280 ps
CPU time 2.25 seconds
Started Jul 11 05:34:38 PM PDT 24
Finished Jul 11 05:34:49 PM PDT 24
Peak memory 222768 kb
Host smart-b0b1efbb-71cb-4449-b4b8-56551ebd346d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563328529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2563328529
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.443175910
Short name T76
Test name
Test status
Simulation time 1010192384 ps
CPU time 3.12 seconds
Started Jul 11 05:34:39 PM PDT 24
Finished Jul 11 05:34:51 PM PDT 24
Peak memory 214356 kb
Host smart-bd8bd9db-ca9b-4dba-85b9-e71fb4b45e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443175910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.443175910
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3997919104
Short name T707
Test name
Test status
Simulation time 305252235 ps
CPU time 1.83 seconds
Started Jul 11 05:34:36 PM PDT 24
Finished Jul 11 05:34:48 PM PDT 24
Peak memory 214248 kb
Host smart-04e8a685-babb-47a7-bf57-246272eb3ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997919104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3997919104
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1521666491
Short name T821
Test name
Test status
Simulation time 49719249 ps
CPU time 3.69 seconds
Started Jul 11 05:34:35 PM PDT 24
Finished Jul 11 05:34:48 PM PDT 24
Peak memory 214288 kb
Host smart-e7104a36-a59d-4f14-b6ae-053e414837cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521666491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1521666491
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.4026445105
Short name T307
Test name
Test status
Simulation time 59432670 ps
CPU time 3.81 seconds
Started Jul 11 05:34:29 PM PDT 24
Finished Jul 11 05:34:43 PM PDT 24
Peak memory 210512 kb
Host smart-5d224155-6967-4c6f-bad4-63101e245167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026445105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.4026445105
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2391069265
Short name T851
Test name
Test status
Simulation time 209512388 ps
CPU time 2.86 seconds
Started Jul 11 05:34:26 PM PDT 24
Finished Jul 11 05:34:40 PM PDT 24
Peak memory 208532 kb
Host smart-9cd2801f-153a-4e2c-b2c6-d281eec1582d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391069265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2391069265
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1993189578
Short name T784
Test name
Test status
Simulation time 549796136 ps
CPU time 3.71 seconds
Started Jul 11 05:34:26 PM PDT 24
Finished Jul 11 05:34:40 PM PDT 24
Peak memory 207984 kb
Host smart-06e00b7a-b42f-454e-9033-a7e154261566
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993189578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1993189578
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2141213711
Short name T783
Test name
Test status
Simulation time 343616824 ps
CPU time 3.39 seconds
Started Jul 11 05:34:26 PM PDT 24
Finished Jul 11 05:34:39 PM PDT 24
Peak memory 208588 kb
Host smart-f2bcaa47-2f0c-4212-be7c-b8ce4be7767f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141213711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2141213711
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3230496599
Short name T508
Test name
Test status
Simulation time 440636674 ps
CPU time 3.57 seconds
Started Jul 11 05:34:26 PM PDT 24
Finished Jul 11 05:34:40 PM PDT 24
Peak memory 206968 kb
Host smart-5e02c591-bf49-48e3-a075-657501959729
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230496599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3230496599
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.4291457718
Short name T876
Test name
Test status
Simulation time 30938702 ps
CPU time 1.9 seconds
Started Jul 11 05:34:33 PM PDT 24
Finished Jul 11 05:34:45 PM PDT 24
Peak memory 208796 kb
Host smart-ca18dbca-0bf6-41c4-b588-c80b81727097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291457718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.4291457718
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3308043200
Short name T454
Test name
Test status
Simulation time 262620926 ps
CPU time 2.51 seconds
Started Jul 11 05:34:29 PM PDT 24
Finished Jul 11 05:34:41 PM PDT 24
Peak memory 207048 kb
Host smart-68d542ff-9e34-4931-ae7b-ccf688d0de39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308043200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3308043200
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2294637695
Short name T836
Test name
Test status
Simulation time 2926326849 ps
CPU time 34.02 seconds
Started Jul 11 05:34:41 PM PDT 24
Finished Jul 11 05:35:23 PM PDT 24
Peak memory 216448 kb
Host smart-78a06414-65a4-476f-b30c-2656b31ffdb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294637695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2294637695
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1210580314
Short name T757
Test name
Test status
Simulation time 183235925 ps
CPU time 3.97 seconds
Started Jul 11 05:34:39 PM PDT 24
Finished Jul 11 05:34:51 PM PDT 24
Peak memory 207792 kb
Host smart-ec5c0640-94b8-4568-a3b4-026765fc45b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210580314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1210580314
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3682639890
Short name T390
Test name
Test status
Simulation time 35026270 ps
CPU time 1.5 seconds
Started Jul 11 05:34:41 PM PDT 24
Finished Jul 11 05:34:50 PM PDT 24
Peak memory 210100 kb
Host smart-fb51a07f-d333-4b1c-90aa-5d8245210a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682639890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3682639890
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.2301102925
Short name T477
Test name
Test status
Simulation time 89030622 ps
CPU time 1.05 seconds
Started Jul 11 05:34:33 PM PDT 24
Finished Jul 11 05:34:43 PM PDT 24
Peak memory 206028 kb
Host smart-b2005180-474d-4b8b-8356-bf9fc42f8d40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301102925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2301102925
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1054115875
Short name T129
Test name
Test status
Simulation time 101249683 ps
CPU time 4.67 seconds
Started Jul 11 05:34:40 PM PDT 24
Finished Jul 11 05:34:53 PM PDT 24
Peak memory 214920 kb
Host smart-4667e236-d270-46fe-ae59-1f4e7a5442f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1054115875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1054115875
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2949937002
Short name T863
Test name
Test status
Simulation time 106679209 ps
CPU time 4.44 seconds
Started Jul 11 05:34:39 PM PDT 24
Finished Jul 11 05:34:53 PM PDT 24
Peak memory 218528 kb
Host smart-991f1108-dd97-4a95-8cc9-23e38d018daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949937002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2949937002
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3675648076
Short name T834
Test name
Test status
Simulation time 296816400 ps
CPU time 3.89 seconds
Started Jul 11 05:34:46 PM PDT 24
Finished Jul 11 05:34:58 PM PDT 24
Peak memory 218228 kb
Host smart-66834151-e5f0-404d-8f1a-06f32ca9fa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675648076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3675648076
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3261627138
Short name T268
Test name
Test status
Simulation time 37577932 ps
CPU time 2.51 seconds
Started Jul 11 05:34:33 PM PDT 24
Finished Jul 11 05:34:46 PM PDT 24
Peak memory 209280 kb
Host smart-82db937e-fd96-46db-b572-1af8351b145e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261627138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3261627138
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.177641996
Short name T556
Test name
Test status
Simulation time 299171240 ps
CPU time 2.63 seconds
Started Jul 11 05:34:36 PM PDT 24
Finished Jul 11 05:34:48 PM PDT 24
Peak memory 220428 kb
Host smart-353277ac-69d0-4ff4-9a22-996759eccbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177641996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.177641996
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.504436651
Short name T656
Test name
Test status
Simulation time 373600683 ps
CPU time 3.76 seconds
Started Jul 11 05:34:39 PM PDT 24
Finished Jul 11 05:34:51 PM PDT 24
Peak memory 214868 kb
Host smart-8484110a-52eb-4cb1-ac07-826e2b3a927a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504436651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.504436651
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1771417217
Short name T584
Test name
Test status
Simulation time 41198379 ps
CPU time 2.8 seconds
Started Jul 11 05:34:37 PM PDT 24
Finished Jul 11 05:34:49 PM PDT 24
Peak memory 207724 kb
Host smart-1d0b6b77-e2df-43bf-9d3a-780df3415b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771417217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1771417217
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.4244835607
Short name T460
Test name
Test status
Simulation time 559645538 ps
CPU time 11.3 seconds
Started Jul 11 05:34:34 PM PDT 24
Finished Jul 11 05:34:55 PM PDT 24
Peak memory 207860 kb
Host smart-65935a8d-d6f5-48fc-b392-8bc696dbc526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244835607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.4244835607
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1122708883
Short name T105
Test name
Test status
Simulation time 2128210234 ps
CPU time 5.5 seconds
Started Jul 11 05:34:42 PM PDT 24
Finished Jul 11 05:34:56 PM PDT 24
Peak memory 207976 kb
Host smart-e836bfdc-d34a-446f-9fe3-48bd1108af3d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122708883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1122708883
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2570282972
Short name T683
Test name
Test status
Simulation time 16937867689 ps
CPU time 39.8 seconds
Started Jul 11 05:34:36 PM PDT 24
Finished Jul 11 05:35:25 PM PDT 24
Peak memory 208572 kb
Host smart-fee4bc01-6d25-4817-bdae-1ace0ca499ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570282972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2570282972
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2445834939
Short name T450
Test name
Test status
Simulation time 1341406317 ps
CPU time 4.23 seconds
Started Jul 11 05:34:37 PM PDT 24
Finished Jul 11 05:34:50 PM PDT 24
Peak memory 208664 kb
Host smart-b9a60d88-4e83-4018-bae0-60cc79aca0f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445834939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2445834939
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.49695681
Short name T912
Test name
Test status
Simulation time 72653372 ps
CPU time 3.49 seconds
Started Jul 11 05:34:41 PM PDT 24
Finished Jul 11 05:34:52 PM PDT 24
Peak memory 210216 kb
Host smart-6913a9b3-0453-4135-be68-cf5aa0eb9304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49695681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.49695681
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.70082998
Short name T440
Test name
Test status
Simulation time 148568323 ps
CPU time 3.27 seconds
Started Jul 11 05:34:38 PM PDT 24
Finished Jul 11 05:34:50 PM PDT 24
Peak memory 208392 kb
Host smart-ed7a8852-5b7e-4d63-af4f-6b4286ba2811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70082998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.70082998
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2541470220
Short name T196
Test name
Test status
Simulation time 1190359364 ps
CPU time 44.25 seconds
Started Jul 11 05:34:36 PM PDT 24
Finished Jul 11 05:35:29 PM PDT 24
Peak memory 221196 kb
Host smart-6366902d-8b19-4b3d-ba75-9f0e494f97fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541470220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2541470220
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.306450563
Short name T845
Test name
Test status
Simulation time 1198252033 ps
CPU time 6.96 seconds
Started Jul 11 05:34:40 PM PDT 24
Finished Jul 11 05:34:56 PM PDT 24
Peak memory 207240 kb
Host smart-ca4d8438-c414-4323-ab64-63a0b19178c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306450563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.306450563
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.4254576885
Short name T169
Test name
Test status
Simulation time 267005383 ps
CPU time 2.92 seconds
Started Jul 11 05:34:40 PM PDT 24
Finished Jul 11 05:34:52 PM PDT 24
Peak memory 210728 kb
Host smart-5154df88-60bd-43bb-82fd-7b7542823a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254576885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.4254576885
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1449993528
Short name T461
Test name
Test status
Simulation time 15849762 ps
CPU time 0.77 seconds
Started Jul 11 05:34:49 PM PDT 24
Finished Jul 11 05:34:58 PM PDT 24
Peak memory 206016 kb
Host smart-8a065265-58a3-411a-9520-447b30e88097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449993528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1449993528
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2159045510
Short name T375
Test name
Test status
Simulation time 240691515 ps
CPU time 4.41 seconds
Started Jul 11 05:34:33 PM PDT 24
Finished Jul 11 05:34:47 PM PDT 24
Peak memory 214352 kb
Host smart-77251b09-2f2e-4a08-bdd9-63d816201b57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2159045510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2159045510
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3173114573
Short name T8
Test name
Test status
Simulation time 274157648 ps
CPU time 2.75 seconds
Started Jul 11 05:34:40 PM PDT 24
Finished Jul 11 05:34:51 PM PDT 24
Peak memory 207764 kb
Host smart-bbd384b1-5790-475f-b155-06d8c0fb4079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173114573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3173114573
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.4130821441
Short name T864
Test name
Test status
Simulation time 53289215 ps
CPU time 1.96 seconds
Started Jul 11 05:34:36 PM PDT 24
Finished Jul 11 05:34:48 PM PDT 24
Peak memory 218316 kb
Host smart-3f5d8895-c007-48e3-9d70-2667c35950ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130821441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.4130821441
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1592248886
Short name T361
Test name
Test status
Simulation time 1366854093 ps
CPU time 3.94 seconds
Started Jul 11 05:34:36 PM PDT 24
Finished Jul 11 05:34:49 PM PDT 24
Peak memory 222416 kb
Host smart-6246f45e-dfed-45fd-b985-886942183ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592248886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1592248886
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3939621881
Short name T615
Test name
Test status
Simulation time 74591342 ps
CPU time 3.68 seconds
Started Jul 11 05:34:34 PM PDT 24
Finished Jul 11 05:34:47 PM PDT 24
Peak memory 209796 kb
Host smart-ae9b0312-cf10-4afa-901c-d2323f64d70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939621881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3939621881
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3450396618
Short name T332
Test name
Test status
Simulation time 864627526 ps
CPU time 5.24 seconds
Started Jul 11 05:34:36 PM PDT 24
Finished Jul 11 05:34:50 PM PDT 24
Peak memory 207736 kb
Host smart-7be41f58-0834-41d2-83d6-ab7a1099cf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450396618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3450396618
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.4235646002
Short name T407
Test name
Test status
Simulation time 366567609 ps
CPU time 3.2 seconds
Started Jul 11 05:34:32 PM PDT 24
Finished Jul 11 05:34:44 PM PDT 24
Peak memory 206932 kb
Host smart-b52747c6-a342-4582-987c-3b120a78fa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235646002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.4235646002
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1708814391
Short name T335
Test name
Test status
Simulation time 191379546 ps
CPU time 3.04 seconds
Started Jul 11 05:34:42 PM PDT 24
Finished Jul 11 05:34:53 PM PDT 24
Peak memory 209124 kb
Host smart-3fa5d728-76cd-4810-b332-d58f650c88a4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708814391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1708814391
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.827726447
Short name T200
Test name
Test status
Simulation time 281247906 ps
CPU time 2.99 seconds
Started Jul 11 05:34:39 PM PDT 24
Finished Jul 11 05:34:51 PM PDT 24
Peak memory 208844 kb
Host smart-c4a7b639-3352-42bf-8a93-b73b82ce3df5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827726447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.827726447
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1506163120
Short name T693
Test name
Test status
Simulation time 597681900 ps
CPU time 3.27 seconds
Started Jul 11 05:34:40 PM PDT 24
Finished Jul 11 05:34:52 PM PDT 24
Peak memory 206464 kb
Host smart-38cf4d79-04be-43b0-88aa-1db46b12589b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506163120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1506163120
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2265299555
Short name T86
Test name
Test status
Simulation time 510248705 ps
CPU time 3.59 seconds
Started Jul 11 05:34:34 PM PDT 24
Finished Jul 11 05:34:47 PM PDT 24
Peak memory 209340 kb
Host smart-2c50c103-61f8-4d9b-a99c-35ce2e07e01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265299555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2265299555
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1861511777
Short name T405
Test name
Test status
Simulation time 26832854 ps
CPU time 1.75 seconds
Started Jul 11 05:34:37 PM PDT 24
Finished Jul 11 05:34:48 PM PDT 24
Peak memory 206876 kb
Host smart-109f8205-57ce-4b14-8304-6670d2cae9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861511777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1861511777
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2527895962
Short name T377
Test name
Test status
Simulation time 1270205944 ps
CPU time 13.09 seconds
Started Jul 11 05:34:40 PM PDT 24
Finished Jul 11 05:35:02 PM PDT 24
Peak memory 218628 kb
Host smart-3b914a35-3c37-41ef-b101-97c870bfcec1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527895962 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2527895962
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2038970076
Short name T748
Test name
Test status
Simulation time 93480829 ps
CPU time 3.69 seconds
Started Jul 11 05:34:38 PM PDT 24
Finished Jul 11 05:34:51 PM PDT 24
Peak memory 209560 kb
Host smart-f36c51f2-55af-4527-b4d9-9d6a474b3b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038970076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2038970076
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2643068760
Short name T39
Test name
Test status
Simulation time 329180990 ps
CPU time 6.27 seconds
Started Jul 11 05:34:32 PM PDT 24
Finished Jul 11 05:34:48 PM PDT 24
Peak memory 210152 kb
Host smart-1c182521-d960-45b5-b5df-a2f5cdfac945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643068760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2643068760
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3818180043
Short name T708
Test name
Test status
Simulation time 19740462 ps
CPU time 0.77 seconds
Started Jul 11 05:34:43 PM PDT 24
Finished Jul 11 05:34:52 PM PDT 24
Peak memory 206000 kb
Host smart-a1748acf-8a17-4e56-ab16-40aedee7a6a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818180043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3818180043
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.264947269
Short name T727
Test name
Test status
Simulation time 273991767 ps
CPU time 2.12 seconds
Started Jul 11 05:34:46 PM PDT 24
Finished Jul 11 05:34:57 PM PDT 24
Peak memory 218548 kb
Host smart-84c56fd1-d0a6-40a9-9b56-e37038d9a837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264947269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.264947269
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3995559092
Short name T736
Test name
Test status
Simulation time 1335022088 ps
CPU time 7.68 seconds
Started Jul 11 05:34:45 PM PDT 24
Finished Jul 11 05:35:00 PM PDT 24
Peak memory 214440 kb
Host smart-19137c9e-92dd-4086-8558-bb4ff6cf08f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995559092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3995559092
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3391662467
Short name T37
Test name
Test status
Simulation time 223166353 ps
CPU time 7.24 seconds
Started Jul 11 05:34:43 PM PDT 24
Finished Jul 11 05:34:58 PM PDT 24
Peak memory 222424 kb
Host smart-8adf9552-f908-4464-ab0e-3c512f8797c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391662467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3391662467
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1866990135
Short name T237
Test name
Test status
Simulation time 52038623 ps
CPU time 3.71 seconds
Started Jul 11 05:34:43 PM PDT 24
Finished Jul 11 05:34:55 PM PDT 24
Peak memory 222536 kb
Host smart-b694e247-9357-4be7-b6a4-37736577d2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866990135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1866990135
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3523803482
Short name T102
Test name
Test status
Simulation time 217168528 ps
CPU time 6.68 seconds
Started Jul 11 05:34:41 PM PDT 24
Finished Jul 11 05:34:56 PM PDT 24
Peak memory 209380 kb
Host smart-3c840476-aa73-48f3-8da1-120205b5b1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523803482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3523803482
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3818462383
Short name T322
Test name
Test status
Simulation time 350143315 ps
CPU time 3.42 seconds
Started Jul 11 05:35:10 PM PDT 24
Finished Jul 11 05:35:17 PM PDT 24
Peak memory 208544 kb
Host smart-91b2ae2e-eb87-4cac-8b8c-a2ee66bc1e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818462383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3818462383
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3425447845
Short name T548
Test name
Test status
Simulation time 63566723 ps
CPU time 3.31 seconds
Started Jul 11 05:34:44 PM PDT 24
Finished Jul 11 05:34:55 PM PDT 24
Peak memory 208740 kb
Host smart-e8b83feb-27f9-41b4-8b90-e92fec82a9dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425447845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3425447845
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1545356744
Short name T913
Test name
Test status
Simulation time 88951877 ps
CPU time 4.12 seconds
Started Jul 11 05:34:58 PM PDT 24
Finished Jul 11 05:35:08 PM PDT 24
Peak memory 208988 kb
Host smart-fd04634b-e551-4f16-90d1-d388fd1728c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545356744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1545356744
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3230456223
Short name T406
Test name
Test status
Simulation time 617625246 ps
CPU time 14.04 seconds
Started Jul 11 05:34:51 PM PDT 24
Finished Jul 11 05:35:13 PM PDT 24
Peak memory 207924 kb
Host smart-8349dc7b-08b8-49c6-bcf8-6f93ea1d016d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230456223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3230456223
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1629552272
Short name T128
Test name
Test status
Simulation time 89637438 ps
CPU time 3.33 seconds
Started Jul 11 05:34:43 PM PDT 24
Finished Jul 11 05:34:55 PM PDT 24
Peak memory 218456 kb
Host smart-2df1f6a1-e8a0-44e4-8174-f883b08aa155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629552272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1629552272
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2952119482
Short name T121
Test name
Test status
Simulation time 56824780 ps
CPU time 2.68 seconds
Started Jul 11 05:34:42 PM PDT 24
Finished Jul 11 05:34:53 PM PDT 24
Peak memory 206960 kb
Host smart-b394182e-8c91-4dc3-87cb-d89b568df0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952119482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2952119482
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.4158786683
Short name T868
Test name
Test status
Simulation time 772974573 ps
CPU time 8.62 seconds
Started Jul 11 05:34:44 PM PDT 24
Finished Jul 11 05:35:01 PM PDT 24
Peak memory 219204 kb
Host smart-28aa69d6-795e-4034-8330-8069ce0b3490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158786683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.4158786683
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2033585032
Short name T389
Test name
Test status
Simulation time 40067898 ps
CPU time 2.46 seconds
Started Jul 11 05:34:43 PM PDT 24
Finished Jul 11 05:34:54 PM PDT 24
Peak memory 210316 kb
Host smart-3390b1ba-aab7-4489-a3c5-632c89909f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033585032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2033585032
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.943059712
Short name T452
Test name
Test status
Simulation time 46235510 ps
CPU time 0.81 seconds
Started Jul 11 05:34:58 PM PDT 24
Finished Jul 11 05:35:05 PM PDT 24
Peak memory 205984 kb
Host smart-5f8e6946-6dc5-48fa-9791-a14c156cf9a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943059712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.943059712
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.4091880449
Short name T82
Test name
Test status
Simulation time 60289170 ps
CPU time 1.82 seconds
Started Jul 11 05:34:44 PM PDT 24
Finished Jul 11 05:34:54 PM PDT 24
Peak memory 214340 kb
Host smart-962302da-687d-4a55-9a17-3bafcad4395e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091880449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.4091880449
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2031282832
Short name T277
Test name
Test status
Simulation time 353150814 ps
CPU time 3.18 seconds
Started Jul 11 05:34:51 PM PDT 24
Finished Jul 11 05:35:02 PM PDT 24
Peak memory 214224 kb
Host smart-24a4a639-f800-40dc-ac60-ecd8e1e667f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031282832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2031282832
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3844755429
Short name T778
Test name
Test status
Simulation time 76496255 ps
CPU time 3.88 seconds
Started Jul 11 05:34:44 PM PDT 24
Finished Jul 11 05:34:56 PM PDT 24
Peak memory 219276 kb
Host smart-70a9cc20-132b-405e-b1b3-2e5eaf840c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844755429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3844755429
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2449857926
Short name T374
Test name
Test status
Simulation time 2748144913 ps
CPU time 9.59 seconds
Started Jul 11 05:34:43 PM PDT 24
Finished Jul 11 05:35:00 PM PDT 24
Peak memory 214388 kb
Host smart-4387d572-d65a-44c0-8f27-d9752a93495c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449857926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2449857926
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3963271389
Short name T85
Test name
Test status
Simulation time 537103059 ps
CPU time 4.44 seconds
Started Jul 11 05:34:42 PM PDT 24
Finished Jul 11 05:34:54 PM PDT 24
Peak memory 208640 kb
Host smart-3985d5d4-486d-4e6c-9a40-44c90db60fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963271389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3963271389
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3214677268
Short name T596
Test name
Test status
Simulation time 234726264 ps
CPU time 6.05 seconds
Started Jul 11 05:34:42 PM PDT 24
Finished Jul 11 05:34:57 PM PDT 24
Peak memory 208580 kb
Host smart-6f362496-25a8-45d6-a99c-42aa5c1d193e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214677268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3214677268
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.12515355
Short name T398
Test name
Test status
Simulation time 117305719 ps
CPU time 3.05 seconds
Started Jul 11 05:34:45 PM PDT 24
Finished Jul 11 05:34:56 PM PDT 24
Peak memory 206972 kb
Host smart-cd71c62f-a1f1-49eb-a6b1-a6e6288f23b5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12515355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.12515355
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.850801589
Short name T527
Test name
Test status
Simulation time 350087250 ps
CPU time 7.64 seconds
Started Jul 11 05:34:46 PM PDT 24
Finished Jul 11 05:35:01 PM PDT 24
Peak memory 208668 kb
Host smart-d3334e71-8a6f-45f6-821c-28d09297c7fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850801589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.850801589
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.798329903
Short name T756
Test name
Test status
Simulation time 1720651539 ps
CPU time 8.99 seconds
Started Jul 11 05:34:43 PM PDT 24
Finished Jul 11 05:35:00 PM PDT 24
Peak memory 209760 kb
Host smart-a189dbd8-1d4f-4f01-ad03-6bedb5d67ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798329903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.798329903
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.4139773986
Short name T545
Test name
Test status
Simulation time 291376877 ps
CPU time 2.56 seconds
Started Jul 11 05:34:42 PM PDT 24
Finished Jul 11 05:34:53 PM PDT 24
Peak memory 206844 kb
Host smart-27eb5e85-81f1-4dcd-8625-f44b0efb6647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139773986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.4139773986
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1497509575
Short name T83
Test name
Test status
Simulation time 627042609 ps
CPU time 9.35 seconds
Started Jul 11 05:34:51 PM PDT 24
Finished Jul 11 05:35:08 PM PDT 24
Peak memory 222532 kb
Host smart-15df90e0-8885-4513-9f9c-305ca8275c18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497509575 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1497509575
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2439632781
Short name T673
Test name
Test status
Simulation time 82953170 ps
CPU time 3.92 seconds
Started Jul 11 05:34:39 PM PDT 24
Finished Jul 11 05:34:52 PM PDT 24
Peak memory 209072 kb
Host smart-705674be-cd2f-491c-995c-ca8b33b69e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439632781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2439632781
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.460188352
Short name T59
Test name
Test status
Simulation time 237084269 ps
CPU time 2.38 seconds
Started Jul 11 05:34:51 PM PDT 24
Finished Jul 11 05:35:01 PM PDT 24
Peak memory 210340 kb
Host smart-8b9e8f53-147e-4c6f-91dc-2f356219d23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460188352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.460188352
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1718151808
Short name T567
Test name
Test status
Simulation time 160790482 ps
CPU time 0.83 seconds
Started Jul 11 05:34:49 PM PDT 24
Finished Jul 11 05:34:57 PM PDT 24
Peak memory 206000 kb
Host smart-9d33626c-62d7-4d9f-bb00-ff22ff7a5e1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718151808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1718151808
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2310537599
Short name T58
Test name
Test status
Simulation time 258577629 ps
CPU time 2.92 seconds
Started Jul 11 05:35:08 PM PDT 24
Finished Jul 11 05:35:16 PM PDT 24
Peak memory 207708 kb
Host smart-daf8e137-dee5-4cb5-9fe3-191f886cb285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310537599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2310537599
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3239739685
Short name T585
Test name
Test status
Simulation time 350655338 ps
CPU time 3.68 seconds
Started Jul 11 05:34:50 PM PDT 24
Finished Jul 11 05:35:02 PM PDT 24
Peak memory 215484 kb
Host smart-d7c43661-86bc-48a8-b30e-e0ecadaf38b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239739685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3239739685
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.4167049230
Short name T892
Test name
Test status
Simulation time 76373277 ps
CPU time 2.47 seconds
Started Jul 11 05:34:49 PM PDT 24
Finished Jul 11 05:34:59 PM PDT 24
Peak memory 219012 kb
Host smart-773852ba-3489-4612-b917-19aa2bcc13d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167049230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.4167049230
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1870550025
Short name T499
Test name
Test status
Simulation time 158719026 ps
CPU time 6.53 seconds
Started Jul 11 05:34:49 PM PDT 24
Finished Jul 11 05:35:03 PM PDT 24
Peak memory 208076 kb
Host smart-c7e3760c-4394-4090-a33f-d7b7ff72fa63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870550025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1870550025
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1721267716
Short name T718
Test name
Test status
Simulation time 225418331 ps
CPU time 3.79 seconds
Started Jul 11 05:34:47 PM PDT 24
Finished Jul 11 05:34:59 PM PDT 24
Peak memory 208820 kb
Host smart-fe26625c-1fa1-412c-989d-5216b73cde6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721267716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1721267716
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2533924371
Short name T455
Test name
Test status
Simulation time 68080076 ps
CPU time 2.34 seconds
Started Jul 11 05:34:49 PM PDT 24
Finished Jul 11 05:35:00 PM PDT 24
Peak memory 206948 kb
Host smart-fd8bb6b0-8a8c-4ca6-870a-23303f6e8f6d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533924371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2533924371
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3484338310
Short name T855
Test name
Test status
Simulation time 1782776959 ps
CPU time 12.61 seconds
Started Jul 11 05:34:48 PM PDT 24
Finished Jul 11 05:35:08 PM PDT 24
Peak memory 208864 kb
Host smart-b1de1790-9046-42d2-9dee-21616b9d2dae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484338310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3484338310
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.271441723
Short name T668
Test name
Test status
Simulation time 145648891 ps
CPU time 3.63 seconds
Started Jul 11 05:34:50 PM PDT 24
Finished Jul 11 05:35:01 PM PDT 24
Peak memory 208964 kb
Host smart-5098074e-d7de-464f-bbc5-3bc76e99c6c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271441723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.271441723
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.185734177
Short name T551
Test name
Test status
Simulation time 173700168 ps
CPU time 3.24 seconds
Started Jul 11 05:35:08 PM PDT 24
Finished Jul 11 05:35:16 PM PDT 24
Peak memory 216096 kb
Host smart-e4746051-baf9-41d2-9ee9-4cef406e2ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185734177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.185734177
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3410600040
Short name T213
Test name
Test status
Simulation time 63922927 ps
CPU time 2.56 seconds
Started Jul 11 05:34:47 PM PDT 24
Finished Jul 11 05:34:58 PM PDT 24
Peak memory 206880 kb
Host smart-e55cdfd9-e32d-499b-9562-b6304526c918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410600040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3410600040
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1634504779
Short name T234
Test name
Test status
Simulation time 6222684243 ps
CPU time 46.84 seconds
Started Jul 11 05:34:48 PM PDT 24
Finished Jul 11 05:35:43 PM PDT 24
Peak memory 215628 kb
Host smart-ea87e399-a3f6-4eb2-a8f3-38a953e99cb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634504779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1634504779
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2471609917
Short name T900
Test name
Test status
Simulation time 517329759 ps
CPU time 5.81 seconds
Started Jul 11 05:34:49 PM PDT 24
Finished Jul 11 05:35:03 PM PDT 24
Peak memory 208104 kb
Host smart-5204a31f-2955-4c3a-a840-7922f4368798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471609917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2471609917
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3382938315
Short name T546
Test name
Test status
Simulation time 85069631 ps
CPU time 3.05 seconds
Started Jul 11 05:34:50 PM PDT 24
Finished Jul 11 05:35:01 PM PDT 24
Peak memory 210248 kb
Host smart-5e4e70ce-3430-4abb-a444-e87e08b15666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382938315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3382938315
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3261874051
Short name T435
Test name
Test status
Simulation time 16215583 ps
CPU time 0.77 seconds
Started Jul 11 05:34:50 PM PDT 24
Finished Jul 11 05:34:58 PM PDT 24
Peak memory 206004 kb
Host smart-2b523d6f-9ec6-4c8e-9ab7-8a378e0fb92a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261874051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3261874051
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2588208630
Short name T909
Test name
Test status
Simulation time 93460654 ps
CPU time 2.83 seconds
Started Jul 11 05:34:49 PM PDT 24
Finished Jul 11 05:35:00 PM PDT 24
Peak memory 214348 kb
Host smart-ddbc53f8-dd5e-4926-abe0-b7e59d73b6d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2588208630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2588208630
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.788994750
Short name T796
Test name
Test status
Simulation time 28597001 ps
CPU time 2.31 seconds
Started Jul 11 05:34:52 PM PDT 24
Finished Jul 11 05:35:02 PM PDT 24
Peak memory 210068 kb
Host smart-f6d9be0c-a818-4a02-bd84-3bced1912147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788994750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.788994750
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1538588017
Short name T323
Test name
Test status
Simulation time 357722655 ps
CPU time 3.25 seconds
Started Jul 11 05:34:48 PM PDT 24
Finished Jul 11 05:34:59 PM PDT 24
Peak memory 222496 kb
Host smart-8f1c1454-7b94-4f79-a0b1-f4ceba1dd16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538588017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1538588017
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2643863743
Short name T15
Test name
Test status
Simulation time 112449998 ps
CPU time 4.86 seconds
Started Jul 11 05:34:50 PM PDT 24
Finished Jul 11 05:35:03 PM PDT 24
Peak memory 208928 kb
Host smart-1982dbb2-c599-42d6-8b25-334f456536be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643863743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2643863743
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3485624309
Short name T124
Test name
Test status
Simulation time 7654565108 ps
CPU time 39.23 seconds
Started Jul 11 05:34:48 PM PDT 24
Finished Jul 11 05:35:35 PM PDT 24
Peak memory 208348 kb
Host smart-81b95edd-45e1-4e4e-8cf1-46e7b8148420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485624309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3485624309
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.343600855
Short name T803
Test name
Test status
Simulation time 161778289 ps
CPU time 5.22 seconds
Started Jul 11 05:34:48 PM PDT 24
Finished Jul 11 05:35:02 PM PDT 24
Peak memory 208584 kb
Host smart-ee6d9609-8fc6-4e30-84e5-e5331a1aed38
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343600855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.343600855
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2793452289
Short name T457
Test name
Test status
Simulation time 97174021 ps
CPU time 4.32 seconds
Started Jul 11 05:34:51 PM PDT 24
Finished Jul 11 05:35:03 PM PDT 24
Peak memory 206996 kb
Host smart-70884758-d660-4c30-9b72-270384cbecd2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793452289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2793452289
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2883975759
Short name T638
Test name
Test status
Simulation time 244798166 ps
CPU time 3.02 seconds
Started Jul 11 05:35:55 PM PDT 24
Finished Jul 11 05:35:59 PM PDT 24
Peak memory 206844 kb
Host smart-7810cace-f775-4480-b0a0-46a10c78f7a2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883975759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2883975759
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.864532270
Short name T625
Test name
Test status
Simulation time 94504972 ps
CPU time 3.12 seconds
Started Jul 11 05:35:07 PM PDT 24
Finished Jul 11 05:35:15 PM PDT 24
Peak memory 207744 kb
Host smart-7ea58fe9-1921-44c5-996c-87763fc307b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864532270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.864532270
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1384450188
Short name T436
Test name
Test status
Simulation time 8491130715 ps
CPU time 25.46 seconds
Started Jul 11 05:34:51 PM PDT 24
Finished Jul 11 05:35:24 PM PDT 24
Peak memory 208344 kb
Host smart-c381b2ea-0f6a-42c4-bbcd-ab6f2e943165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384450188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1384450188
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.4084702399
Short name T641
Test name
Test status
Simulation time 463072809 ps
CPU time 6.73 seconds
Started Jul 11 05:34:47 PM PDT 24
Finished Jul 11 05:35:02 PM PDT 24
Peak memory 222396 kb
Host smart-536f1039-c289-4d68-855b-c80e7fb07a15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084702399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.4084702399
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2052451117
Short name T279
Test name
Test status
Simulation time 171085352 ps
CPU time 6.21 seconds
Started Jul 11 05:35:08 PM PDT 24
Finished Jul 11 05:35:19 PM PDT 24
Peak memory 210236 kb
Host smart-32a746be-adca-4c4f-80b7-c4ba7c656759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052451117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2052451117
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1228551344
Short name T64
Test name
Test status
Simulation time 36974349 ps
CPU time 2.07 seconds
Started Jul 11 05:34:52 PM PDT 24
Finished Jul 11 05:35:01 PM PDT 24
Peak memory 210208 kb
Host smart-64ae203f-1a90-4b14-82cc-f6b16303b9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228551344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1228551344
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1098044190
Short name T765
Test name
Test status
Simulation time 16714185 ps
CPU time 0.84 seconds
Started Jul 11 05:35:14 PM PDT 24
Finished Jul 11 05:35:19 PM PDT 24
Peak memory 205980 kb
Host smart-fbd0ca1e-70ee-45f0-9e03-6f313f4016bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098044190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1098044190
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1964476847
Short name T61
Test name
Test status
Simulation time 937535780 ps
CPU time 3.52 seconds
Started Jul 11 05:35:04 PM PDT 24
Finished Jul 11 05:35:12 PM PDT 24
Peak memory 209136 kb
Host smart-7771755e-5ac2-4747-bb7f-8a66f880c092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964476847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1964476847
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.71096628
Short name T880
Test name
Test status
Simulation time 906232343 ps
CPU time 9.26 seconds
Started Jul 11 05:35:01 PM PDT 24
Finished Jul 11 05:35:16 PM PDT 24
Peak memory 214264 kb
Host smart-29d419bf-066d-4d14-b1a3-076092f6099a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71096628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.71096628
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1814427052
Short name T363
Test name
Test status
Simulation time 89915320 ps
CPU time 2.72 seconds
Started Jul 11 05:34:59 PM PDT 24
Finished Jul 11 05:35:07 PM PDT 24
Peak memory 222376 kb
Host smart-e37cb59b-6305-4c39-8a9b-539892505ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814427052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1814427052
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.532846846
Short name T518
Test name
Test status
Simulation time 96127729 ps
CPU time 3.15 seconds
Started Jul 11 05:34:54 PM PDT 24
Finished Jul 11 05:35:04 PM PDT 24
Peak memory 214844 kb
Host smart-df15e690-6b35-4172-b55f-a6f670d5914d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532846846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.532846846
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2879596230
Short name T212
Test name
Test status
Simulation time 5206019199 ps
CPU time 37.21 seconds
Started Jul 11 05:34:58 PM PDT 24
Finished Jul 11 05:35:41 PM PDT 24
Peak memory 208992 kb
Host smart-8e5a9281-0297-43e7-b186-abb49d5dfc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879596230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2879596230
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.729330897
Short name T822
Test name
Test status
Simulation time 136839458 ps
CPU time 2.64 seconds
Started Jul 11 05:34:57 PM PDT 24
Finished Jul 11 05:35:06 PM PDT 24
Peak memory 208688 kb
Host smart-9ace2f37-5fe0-4334-9176-b86e97a5abd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729330897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.729330897
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2284280365
Short name T755
Test name
Test status
Simulation time 705375571 ps
CPU time 3.72 seconds
Started Jul 11 05:35:14 PM PDT 24
Finished Jul 11 05:35:22 PM PDT 24
Peak memory 206988 kb
Host smart-3e1045be-15c9-4682-9553-a68cef5ba41c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284280365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2284280365
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1468435374
Short name T674
Test name
Test status
Simulation time 154946127 ps
CPU time 3.26 seconds
Started Jul 11 05:35:14 PM PDT 24
Finished Jul 11 05:35:21 PM PDT 24
Peak memory 208476 kb
Host smart-33f5a142-e83d-4283-970c-677140be3d4e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468435374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1468435374
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.4179572707
Short name T743
Test name
Test status
Simulation time 3534827949 ps
CPU time 13.59 seconds
Started Jul 11 05:34:56 PM PDT 24
Finished Jul 11 05:35:16 PM PDT 24
Peak memory 208544 kb
Host smart-46708a35-1e74-4fc2-95da-030a6b9b1e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179572707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.4179572707
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2084549419
Short name T776
Test name
Test status
Simulation time 211714932 ps
CPU time 3.97 seconds
Started Jul 11 05:34:59 PM PDT 24
Finished Jul 11 05:35:08 PM PDT 24
Peak memory 207964 kb
Host smart-7ab2c582-d38a-4df6-829a-5225a06573fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084549419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2084549419
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2741493062
Short name T349
Test name
Test status
Simulation time 527881993 ps
CPU time 11.7 seconds
Started Jul 11 05:35:05 PM PDT 24
Finished Jul 11 05:35:22 PM PDT 24
Peak memory 216244 kb
Host smart-426a5df9-af2b-48fa-b6b4-6e16abde78d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741493062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2741493062
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1966393052
Short name T378
Test name
Test status
Simulation time 90960758 ps
CPU time 3.53 seconds
Started Jul 11 05:34:56 PM PDT 24
Finished Jul 11 05:35:06 PM PDT 24
Peak memory 207316 kb
Host smart-691d0808-8524-424c-bcf2-3a4101dcf17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966393052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1966393052
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.465074357
Short name T513
Test name
Test status
Simulation time 80553302 ps
CPU time 2.05 seconds
Started Jul 11 05:34:59 PM PDT 24
Finished Jul 11 05:35:07 PM PDT 24
Peak memory 209624 kb
Host smart-fc460726-1867-42b8-86e6-dc3144cd8af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465074357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.465074357
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2041259570
Short name T502
Test name
Test status
Simulation time 176868106 ps
CPU time 0.8 seconds
Started Jul 11 05:35:01 PM PDT 24
Finished Jul 11 05:35:07 PM PDT 24
Peak memory 206008 kb
Host smart-fd733994-5c69-48af-be76-673a59b8c68b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041259570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2041259570
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1055633846
Short name T255
Test name
Test status
Simulation time 164796449 ps
CPU time 3.18 seconds
Started Jul 11 05:34:59 PM PDT 24
Finished Jul 11 05:35:08 PM PDT 24
Peak memory 214340 kb
Host smart-a4df2fd0-e545-4faf-9190-508919096502
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1055633846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1055633846
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.4143641244
Short name T729
Test name
Test status
Simulation time 205156156 ps
CPU time 2.31 seconds
Started Jul 11 05:34:57 PM PDT 24
Finished Jul 11 05:35:05 PM PDT 24
Peak memory 218120 kb
Host smart-68a206f2-e6a9-4331-bc94-4d8753af0016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143641244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.4143641244
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.92410151
Short name T357
Test name
Test status
Simulation time 48117430 ps
CPU time 1.84 seconds
Started Jul 11 05:35:02 PM PDT 24
Finished Jul 11 05:35:09 PM PDT 24
Peak memory 207224 kb
Host smart-7e7ccf29-724e-49a1-a8b7-81d6c887c242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92410151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.92410151
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1095703086
Short name T724
Test name
Test status
Simulation time 99220220 ps
CPU time 4.65 seconds
Started Jul 11 05:35:02 PM PDT 24
Finished Jul 11 05:35:12 PM PDT 24
Peak memory 222312 kb
Host smart-fa63ec44-2dbc-4c3c-bc05-0c91e9e6d344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095703086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1095703086
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3377980913
Short name T777
Test name
Test status
Simulation time 99750046 ps
CPU time 4.48 seconds
Started Jul 11 05:34:57 PM PDT 24
Finished Jul 11 05:35:08 PM PDT 24
Peak memory 221164 kb
Host smart-4139532a-3b69-4428-8978-85dc893e8212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377980913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3377980913
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3605522022
Short name T647
Test name
Test status
Simulation time 152213726 ps
CPU time 8.4 seconds
Started Jul 11 05:34:58 PM PDT 24
Finished Jul 11 05:35:12 PM PDT 24
Peak memory 221012 kb
Host smart-b0556912-c0e5-4559-aec2-a6eff0b21a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605522022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3605522022
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3711546581
Short name T372
Test name
Test status
Simulation time 325956019 ps
CPU time 3.92 seconds
Started Jul 11 05:35:00 PM PDT 24
Finished Jul 11 05:35:09 PM PDT 24
Peak memory 207728 kb
Host smart-2b4fe79a-b8c5-423f-bb47-c9f98ec1a65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711546581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3711546581
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1887803788
Short name T682
Test name
Test status
Simulation time 177187720 ps
CPU time 2.64 seconds
Started Jul 11 05:34:57 PM PDT 24
Finished Jul 11 05:35:06 PM PDT 24
Peak memory 208536 kb
Host smart-5b3706c3-23c8-4c67-ba99-037f9c8a3d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887803788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1887803788
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1973566034
Short name T463
Test name
Test status
Simulation time 60324324 ps
CPU time 2.97 seconds
Started Jul 11 05:34:57 PM PDT 24
Finished Jul 11 05:35:07 PM PDT 24
Peak memory 208808 kb
Host smart-2e4e446d-797f-4537-ba22-0db30b8a228c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973566034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1973566034
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.4250406963
Short name T404
Test name
Test status
Simulation time 526089145 ps
CPU time 5.5 seconds
Started Jul 11 05:35:08 PM PDT 24
Finished Jul 11 05:35:18 PM PDT 24
Peak memory 208528 kb
Host smart-876e74f1-66b6-449f-88cd-1fc33084b31f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250406963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.4250406963
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1396243349
Short name T379
Test name
Test status
Simulation time 37090233 ps
CPU time 1.7 seconds
Started Jul 11 05:35:00 PM PDT 24
Finished Jul 11 05:35:07 PM PDT 24
Peak memory 207016 kb
Host smart-35845a8b-f16e-4cf9-95a3-2eee7bf5a263
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396243349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1396243349
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1292628460
Short name T744
Test name
Test status
Simulation time 38094228 ps
CPU time 2.47 seconds
Started Jul 11 05:35:08 PM PDT 24
Finished Jul 11 05:35:15 PM PDT 24
Peak memory 214432 kb
Host smart-bf64e5a8-c626-4a05-ac83-7c5885de28c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292628460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1292628460
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2666052440
Short name T591
Test name
Test status
Simulation time 908086806 ps
CPU time 4.26 seconds
Started Jul 11 05:35:00 PM PDT 24
Finished Jul 11 05:35:10 PM PDT 24
Peak memory 208008 kb
Host smart-34a8bdff-e684-4f20-8c53-9fb8fa3c4d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666052440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2666052440
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2406498
Short name T244
Test name
Test status
Simulation time 1460547315 ps
CPU time 50.77 seconds
Started Jul 11 05:35:00 PM PDT 24
Finished Jul 11 05:35:57 PM PDT 24
Peak memory 222512 kb
Host smart-aaec0c71-6149-4879-b83c-a36021d0fbc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2406498
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3668302496
Short name T828
Test name
Test status
Simulation time 1317728674 ps
CPU time 18.7 seconds
Started Jul 11 05:34:55 PM PDT 24
Finished Jul 11 05:35:21 PM PDT 24
Peak memory 222712 kb
Host smart-4b54a66c-7606-4057-b835-b498992bf8de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668302496 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3668302496
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2378181294
Short name T709
Test name
Test status
Simulation time 210262717 ps
CPU time 3.91 seconds
Started Jul 11 05:34:59 PM PDT 24
Finished Jul 11 05:35:09 PM PDT 24
Peak memory 209720 kb
Host smart-f0fe2c95-0500-4ff2-a4ee-ae26dfaddbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378181294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2378181294
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1338532924
Short name T541
Test name
Test status
Simulation time 84041605 ps
CPU time 2.21 seconds
Started Jul 11 05:35:03 PM PDT 24
Finished Jul 11 05:35:10 PM PDT 24
Peak memory 210072 kb
Host smart-2547bdc4-848d-473f-8385-afbc22467cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338532924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1338532924
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1893923754
Short name T869
Test name
Test status
Simulation time 16203380 ps
CPU time 0.72 seconds
Started Jul 11 05:33:32 PM PDT 24
Finished Jul 11 05:33:35 PM PDT 24
Peak memory 205976 kb
Host smart-37929398-7fcb-41ac-a3bc-b6146fdbc488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893923754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1893923754
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2384482579
Short name T422
Test name
Test status
Simulation time 5969820325 ps
CPU time 45.37 seconds
Started Jul 11 05:33:36 PM PDT 24
Finished Jul 11 05:34:25 PM PDT 24
Peak memory 215188 kb
Host smart-cb55bb53-2900-48a9-a490-a1d6bdee1f78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384482579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2384482579
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1946722842
Short name T699
Test name
Test status
Simulation time 499115800 ps
CPU time 6.35 seconds
Started Jul 11 05:33:34 PM PDT 24
Finished Jul 11 05:33:43 PM PDT 24
Peak memory 214688 kb
Host smart-a9c47539-0cda-4a53-b421-d951b68c2414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946722842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1946722842
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2304935479
Short name T571
Test name
Test status
Simulation time 1115546060 ps
CPU time 30.22 seconds
Started Jul 11 05:33:35 PM PDT 24
Finished Jul 11 05:34:09 PM PDT 24
Peak memory 208480 kb
Host smart-67343e6b-54be-4d14-b17f-4cadb71d7a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304935479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2304935479
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1354859724
Short name T387
Test name
Test status
Simulation time 19689905530 ps
CPU time 27.16 seconds
Started Jul 11 05:33:32 PM PDT 24
Finished Jul 11 05:34:01 PM PDT 24
Peak memory 209784 kb
Host smart-95d132f6-7819-4b64-9e8f-a68ed243c1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354859724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1354859724
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3316536692
Short name T657
Test name
Test status
Simulation time 44637146 ps
CPU time 1.64 seconds
Started Jul 11 05:33:37 PM PDT 24
Finished Jul 11 05:33:42 PM PDT 24
Peak memory 214300 kb
Host smart-00adbc27-d950-4c4b-811c-c102c064c1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316536692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3316536692
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2394978616
Short name T895
Test name
Test status
Simulation time 115914164 ps
CPU time 4.88 seconds
Started Jul 11 05:33:41 PM PDT 24
Finished Jul 11 05:33:48 PM PDT 24
Peak memory 209852 kb
Host smart-51023d31-6c30-436f-b519-b92eeab6f96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394978616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2394978616
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.357486263
Short name T768
Test name
Test status
Simulation time 40171542 ps
CPU time 2.6 seconds
Started Jul 11 05:33:28 PM PDT 24
Finished Jul 11 05:33:33 PM PDT 24
Peak memory 207220 kb
Host smart-e2d63e51-4cc1-4705-a718-f0ccc484f028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357486263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.357486263
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.815295934
Short name T654
Test name
Test status
Simulation time 334273429 ps
CPU time 3.19 seconds
Started Jul 11 05:33:26 PM PDT 24
Finished Jul 11 05:33:32 PM PDT 24
Peak memory 208604 kb
Host smart-7ccccd40-3ebc-411b-b43f-3f2594bc3642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815295934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.815295934
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1260658828
Short name T720
Test name
Test status
Simulation time 150282205 ps
CPU time 4.23 seconds
Started Jul 11 05:33:27 PM PDT 24
Finished Jul 11 05:33:34 PM PDT 24
Peak memory 208540 kb
Host smart-24de1008-da19-4095-8639-77fbda36eff3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260658828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1260658828
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3607027905
Short name T809
Test name
Test status
Simulation time 36306847 ps
CPU time 2.43 seconds
Started Jul 11 05:33:35 PM PDT 24
Finished Jul 11 05:33:41 PM PDT 24
Peak memory 207004 kb
Host smart-e5b24b8d-2e1b-4e7f-a670-022e5c94c5c3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607027905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3607027905
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2924649760
Short name T519
Test name
Test status
Simulation time 17225839409 ps
CPU time 48.26 seconds
Started Jul 11 05:33:27 PM PDT 24
Finished Jul 11 05:34:18 PM PDT 24
Peak memory 209060 kb
Host smart-6590716c-1d01-4ee3-b6f0-f9203f8acaa7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924649760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2924649760
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2088327972
Short name T190
Test name
Test status
Simulation time 101078400 ps
CPU time 4.25 seconds
Started Jul 11 05:33:34 PM PDT 24
Finished Jul 11 05:33:41 PM PDT 24
Peak memory 214244 kb
Host smart-9b0f7eeb-7c33-4e7a-806c-0d007aa2bd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088327972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2088327972
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2829976857
Short name T529
Test name
Test status
Simulation time 59736337 ps
CPU time 2.63 seconds
Started Jul 11 05:33:25 PM PDT 24
Finished Jul 11 05:33:31 PM PDT 24
Peak memory 208352 kb
Host smart-4760339a-2699-4005-88b0-997060c447ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829976857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2829976857
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.184116455
Short name T501
Test name
Test status
Simulation time 531190708 ps
CPU time 10.36 seconds
Started Jul 11 05:33:35 PM PDT 24
Finished Jul 11 05:33:48 PM PDT 24
Peak memory 207884 kb
Host smart-5e9a1875-c1de-4518-865e-817a012087fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184116455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.184116455
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3270883415
Short name T490
Test name
Test status
Simulation time 89163585 ps
CPU time 0.74 seconds
Started Jul 11 05:35:05 PM PDT 24
Finished Jul 11 05:35:11 PM PDT 24
Peak memory 205940 kb
Host smart-9d639fda-5743-49ea-a49d-86224f788918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270883415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3270883415
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2190259773
Short name T408
Test name
Test status
Simulation time 281800630 ps
CPU time 8.27 seconds
Started Jul 11 05:35:05 PM PDT 24
Finished Jul 11 05:35:18 PM PDT 24
Peak memory 214348 kb
Host smart-c5fe8fac-aed2-475c-a044-86b1a29c7f6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2190259773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2190259773
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.603224779
Short name T79
Test name
Test status
Simulation time 45733112 ps
CPU time 1.99 seconds
Started Jul 11 05:35:09 PM PDT 24
Finished Jul 11 05:35:16 PM PDT 24
Peak memory 218304 kb
Host smart-911255dd-c195-49cd-b8ce-fd69ed78995f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603224779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.603224779
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.807335596
Short name T318
Test name
Test status
Simulation time 135608209 ps
CPU time 3.27 seconds
Started Jul 11 05:35:12 PM PDT 24
Finished Jul 11 05:35:20 PM PDT 24
Peak memory 214696 kb
Host smart-c2023fb5-729d-4e2a-a90c-cc3c73cf4153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807335596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.807335596
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.430786792
Short name T780
Test name
Test status
Simulation time 75882121 ps
CPU time 2.38 seconds
Started Jul 11 05:35:06 PM PDT 24
Finished Jul 11 05:35:13 PM PDT 24
Peak memory 214224 kb
Host smart-359af426-4bcf-4a5a-96cc-7806ce8dd5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430786792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.430786792
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.590861689
Short name T425
Test name
Test status
Simulation time 133846261 ps
CPU time 2.59 seconds
Started Jul 11 05:35:04 PM PDT 24
Finished Jul 11 05:35:11 PM PDT 24
Peak memory 208512 kb
Host smart-47655cee-1d88-45f2-89a2-ee706d90f8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590861689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.590861689
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.28618774
Short name T424
Test name
Test status
Simulation time 470998595 ps
CPU time 5.24 seconds
Started Jul 11 05:35:08 PM PDT 24
Finished Jul 11 05:35:17 PM PDT 24
Peak memory 210148 kb
Host smart-8c671539-5c1f-43ba-b993-69c5af0dcd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28618774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.28618774
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2169022044
Short name T466
Test name
Test status
Simulation time 206868892 ps
CPU time 4.63 seconds
Started Jul 11 05:35:04 PM PDT 24
Finished Jul 11 05:35:13 PM PDT 24
Peak memory 207876 kb
Host smart-a9c626d7-c9e4-4512-b06c-d5bf6ef241ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169022044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2169022044
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3810991724
Short name T681
Test name
Test status
Simulation time 228914327 ps
CPU time 2.67 seconds
Started Jul 11 05:35:06 PM PDT 24
Finished Jul 11 05:35:13 PM PDT 24
Peak memory 208448 kb
Host smart-25720fd8-e4f1-45c6-8188-287512d0bee4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810991724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3810991724
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3391267563
Short name T725
Test name
Test status
Simulation time 150988976 ps
CPU time 5.48 seconds
Started Jul 11 05:35:06 PM PDT 24
Finished Jul 11 05:35:17 PM PDT 24
Peak memory 208732 kb
Host smart-3670bebb-5ce4-4a2d-a4ff-615b448d2a4d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391267563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3391267563
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1307673786
Short name T746
Test name
Test status
Simulation time 92171755 ps
CPU time 2.6 seconds
Started Jul 11 05:35:05 PM PDT 24
Finished Jul 11 05:35:13 PM PDT 24
Peak memory 206992 kb
Host smart-81c47268-0dc2-4b86-a2d7-0e0d85182ce9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307673786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1307673786
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1829628719
Short name T576
Test name
Test status
Simulation time 30548032 ps
CPU time 2.49 seconds
Started Jul 11 05:35:07 PM PDT 24
Finished Jul 11 05:35:14 PM PDT 24
Peak memory 218376 kb
Host smart-e9aa4677-a133-4330-9f74-767f1042a46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829628719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1829628719
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.650860697
Short name T916
Test name
Test status
Simulation time 36686472 ps
CPU time 2.32 seconds
Started Jul 11 05:34:59 PM PDT 24
Finished Jul 11 05:35:07 PM PDT 24
Peak memory 208412 kb
Host smart-12295e7a-aee4-43bb-9b1e-ac1bde93e3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650860697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.650860697
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2824331332
Short name T366
Test name
Test status
Simulation time 2238057903 ps
CPU time 19.23 seconds
Started Jul 11 05:35:06 PM PDT 24
Finished Jul 11 05:35:30 PM PDT 24
Peak memory 220728 kb
Host smart-46bdd72d-ed35-4bb7-848a-075cab70bcbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824331332 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2824331332
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3415630152
Short name T84
Test name
Test status
Simulation time 180548045 ps
CPU time 4.59 seconds
Started Jul 11 05:35:04 PM PDT 24
Finished Jul 11 05:35:13 PM PDT 24
Peak memory 209020 kb
Host smart-d8a09649-60a3-4e3d-a206-d9c41686593d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415630152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3415630152
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2952451558
Short name T474
Test name
Test status
Simulation time 221504272 ps
CPU time 2.2 seconds
Started Jul 11 05:35:06 PM PDT 24
Finished Jul 11 05:35:13 PM PDT 24
Peak memory 209864 kb
Host smart-0ae14370-95f3-43c2-a7e0-5a985a205606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952451558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2952451558
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2676032321
Short name T476
Test name
Test status
Simulation time 15920001 ps
CPU time 0.77 seconds
Started Jul 11 05:35:12 PM PDT 24
Finished Jul 11 05:35:16 PM PDT 24
Peak memory 205980 kb
Host smart-0e557753-41ec-4206-b44c-e3028e7de1fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676032321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2676032321
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.306133588
Short name T365
Test name
Test status
Simulation time 99113419 ps
CPU time 3.88 seconds
Started Jul 11 05:35:06 PM PDT 24
Finished Jul 11 05:35:15 PM PDT 24
Peak memory 215396 kb
Host smart-530ba182-8d46-4648-af19-3b9aa0357cb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=306133588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.306133588
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2448262813
Short name T781
Test name
Test status
Simulation time 921453970 ps
CPU time 29.12 seconds
Started Jul 11 05:42:22 PM PDT 24
Finished Jul 11 05:42:58 PM PDT 24
Peak memory 214352 kb
Host smart-df4e37ed-368f-490a-b6ca-741ea4b1a410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448262813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2448262813
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.4212616450
Short name T280
Test name
Test status
Simulation time 232250020 ps
CPU time 6.05 seconds
Started Jul 11 05:35:14 PM PDT 24
Finished Jul 11 05:35:25 PM PDT 24
Peak memory 220900 kb
Host smart-87e60f63-5161-4c40-ae2a-b64c31c4829b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212616450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.4212616450
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2914153780
Short name T539
Test name
Test status
Simulation time 586340095 ps
CPU time 5.02 seconds
Started Jul 11 05:35:04 PM PDT 24
Finished Jul 11 05:35:14 PM PDT 24
Peak memory 214372 kb
Host smart-b50c1723-e21a-4e7e-b67f-d08e68900d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914153780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2914153780
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3550271575
Short name T243
Test name
Test status
Simulation time 207002497 ps
CPU time 10.11 seconds
Started Jul 11 05:35:07 PM PDT 24
Finished Jul 11 05:35:22 PM PDT 24
Peak memory 214336 kb
Host smart-c004695f-7d74-4e38-927f-8229d549e90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550271575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3550271575
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3752988467
Short name T252
Test name
Test status
Simulation time 897030496 ps
CPU time 6.34 seconds
Started Jul 11 05:35:06 PM PDT 24
Finished Jul 11 05:35:17 PM PDT 24
Peak memory 214252 kb
Host smart-792966a0-dcc9-49f8-8168-1b4f73397c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752988467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3752988467
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.884660225
Short name T795
Test name
Test status
Simulation time 2551353495 ps
CPU time 4.34 seconds
Started Jul 11 05:35:08 PM PDT 24
Finished Jul 11 05:35:17 PM PDT 24
Peak memory 206780 kb
Host smart-518d83fc-c458-4dde-bc7a-13fa1345de69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884660225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.884660225
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3757878497
Short name T651
Test name
Test status
Simulation time 292987380 ps
CPU time 2.8 seconds
Started Jul 11 05:35:04 PM PDT 24
Finished Jul 11 05:35:12 PM PDT 24
Peak memory 207040 kb
Host smart-53594965-a85a-4e0b-a016-60225c7d2464
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757878497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3757878497
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.385551849
Short name T437
Test name
Test status
Simulation time 73669424 ps
CPU time 1.79 seconds
Started Jul 11 05:35:05 PM PDT 24
Finished Jul 11 05:35:12 PM PDT 24
Peak memory 206992 kb
Host smart-7811e732-bae8-4830-900d-ff94755d34c3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385551849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.385551849
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.140883626
Short name T732
Test name
Test status
Simulation time 237077243 ps
CPU time 6.61 seconds
Started Jul 11 05:35:07 PM PDT 24
Finished Jul 11 05:35:18 PM PDT 24
Peak memory 208552 kb
Host smart-231671d4-08a6-440a-b66a-36189d884909
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140883626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.140883626
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2928731804
Short name T626
Test name
Test status
Simulation time 31949754 ps
CPU time 1.81 seconds
Started Jul 11 05:35:06 PM PDT 24
Finished Jul 11 05:35:13 PM PDT 24
Peak memory 209224 kb
Host smart-519b16d1-acb7-4165-b09f-45d193325b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928731804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2928731804
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2793559747
Short name T462
Test name
Test status
Simulation time 37588907 ps
CPU time 1.81 seconds
Started Jul 11 05:35:06 PM PDT 24
Finished Jul 11 05:35:13 PM PDT 24
Peak memory 207196 kb
Host smart-f547b007-6c88-4c51-8f1f-c210ad437c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793559747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2793559747
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2603791739
Short name T6
Test name
Test status
Simulation time 7382971706 ps
CPU time 45.76 seconds
Started Jul 11 05:35:05 PM PDT 24
Finished Jul 11 05:35:55 PM PDT 24
Peak memory 216196 kb
Host smart-3799a57a-835c-4202-8a66-6e3884263b25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603791739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2603791739
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.598889884
Short name T764
Test name
Test status
Simulation time 128285442 ps
CPU time 4.19 seconds
Started Jul 11 05:35:08 PM PDT 24
Finished Jul 11 05:35:17 PM PDT 24
Peak memory 214420 kb
Host smart-dbb48dfa-ad57-4c70-95f6-1f55e5cff755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598889884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.598889884
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2114931414
Short name T606
Test name
Test status
Simulation time 777583663 ps
CPU time 2.03 seconds
Started Jul 11 05:35:07 PM PDT 24
Finished Jul 11 05:35:14 PM PDT 24
Peak memory 210016 kb
Host smart-7eebc8e2-bd23-49f4-9275-b5b8afe01377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114931414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2114931414
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3142228793
Short name T715
Test name
Test status
Simulation time 9839338 ps
CPU time 0.72 seconds
Started Jul 11 05:35:15 PM PDT 24
Finished Jul 11 05:35:20 PM PDT 24
Peak memory 206008 kb
Host smart-0dd481f2-3139-4a7c-a47c-12df7a2abe0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142228793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3142228793
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3480484689
Short name T240
Test name
Test status
Simulation time 892686273 ps
CPU time 6.69 seconds
Started Jul 11 05:35:20 PM PDT 24
Finished Jul 11 05:35:31 PM PDT 24
Peak memory 209944 kb
Host smart-66f6bef2-20be-46c2-a0df-49213b6de84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480484689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3480484689
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3583725981
Short name T544
Test name
Test status
Simulation time 116616393 ps
CPU time 3.1 seconds
Started Jul 11 05:35:15 PM PDT 24
Finished Jul 11 05:35:23 PM PDT 24
Peak memory 206972 kb
Host smart-fb6f5904-3b56-4d06-ad97-3010407b2618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583725981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3583725981
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3223435900
Short name T298
Test name
Test status
Simulation time 172046117 ps
CPU time 2.91 seconds
Started Jul 11 05:35:17 PM PDT 24
Finished Jul 11 05:35:24 PM PDT 24
Peak memory 214240 kb
Host smart-a01ab606-561e-4432-b6ee-41f4bb016434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223435900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3223435900
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2009013477
Short name T130
Test name
Test status
Simulation time 97236371 ps
CPU time 4.29 seconds
Started Jul 11 05:35:12 PM PDT 24
Finished Jul 11 05:35:20 PM PDT 24
Peak memory 209964 kb
Host smart-0514e1b0-c640-4cb5-8886-97ba294d4924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009013477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2009013477
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.500076008
Short name T773
Test name
Test status
Simulation time 89734577 ps
CPU time 4.02 seconds
Started Jul 11 05:35:14 PM PDT 24
Finished Jul 11 05:35:22 PM PDT 24
Peak memory 207592 kb
Host smart-dfaf3ac6-137e-4b81-a177-043019ab3ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500076008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.500076008
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.910843198
Short name T523
Test name
Test status
Simulation time 37101929 ps
CPU time 2.44 seconds
Started Jul 11 05:35:12 PM PDT 24
Finished Jul 11 05:35:18 PM PDT 24
Peak memory 208636 kb
Host smart-4f275278-4255-4168-9745-4559ab01c2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910843198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.910843198
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.514266427
Short name T356
Test name
Test status
Simulation time 134589328 ps
CPU time 2.47 seconds
Started Jul 11 05:35:11 PM PDT 24
Finished Jul 11 05:35:18 PM PDT 24
Peak memory 206864 kb
Host smart-1fc7d1ad-eb6e-4a1b-abb0-1d99403b7769
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514266427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.514266427
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2633655474
Short name T635
Test name
Test status
Simulation time 121697659 ps
CPU time 3.89 seconds
Started Jul 11 05:35:14 PM PDT 24
Finished Jul 11 05:35:21 PM PDT 24
Peak memory 206960 kb
Host smart-ef99d8e9-30f6-4d48-90de-15f44779e135
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633655474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2633655474
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2934027516
Short name T805
Test name
Test status
Simulation time 708179154 ps
CPU time 17.11 seconds
Started Jul 11 05:35:04 PM PDT 24
Finished Jul 11 05:35:26 PM PDT 24
Peak memory 208040 kb
Host smart-6f1a86c2-463e-4734-8696-65c6aebd3b8e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934027516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2934027516
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1182520105
Short name T633
Test name
Test status
Simulation time 1027351359 ps
CPU time 17.09 seconds
Started Jul 11 05:35:11 PM PDT 24
Finished Jul 11 05:35:32 PM PDT 24
Peak memory 209324 kb
Host smart-42cf3e5b-0649-4a9b-8484-cc02a650ef50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182520105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1182520105
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.84922855
Short name T214
Test name
Test status
Simulation time 94061409 ps
CPU time 1.91 seconds
Started Jul 11 05:35:11 PM PDT 24
Finished Jul 11 05:35:17 PM PDT 24
Peak memory 208464 kb
Host smart-b086dc05-25fc-4601-8038-d72925dc8bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84922855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.84922855
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3507448977
Short name T684
Test name
Test status
Simulation time 189869667 ps
CPU time 8.99 seconds
Started Jul 11 05:35:16 PM PDT 24
Finished Jul 11 05:35:29 PM PDT 24
Peak memory 215268 kb
Host smart-9ee58290-2b6a-4acd-9e2d-c778f3c12a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507448977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3507448977
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3791375036
Short name T182
Test name
Test status
Simulation time 594871489 ps
CPU time 12.29 seconds
Started Jul 11 05:35:24 PM PDT 24
Finished Jul 11 05:35:41 PM PDT 24
Peak memory 222556 kb
Host smart-c34c1a1d-d2df-4da8-ab95-bd091b3c09c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791375036 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3791375036
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3602039745
Short name T510
Test name
Test status
Simulation time 122587216 ps
CPU time 5.32 seconds
Started Jul 11 05:35:14 PM PDT 24
Finished Jul 11 05:35:23 PM PDT 24
Peak memory 214436 kb
Host smart-c79aa96f-ebb5-4ddd-90e2-b8dec0c5d0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602039745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3602039745
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3798519457
Short name T163
Test name
Test status
Simulation time 126840571 ps
CPU time 3.23 seconds
Started Jul 11 05:35:12 PM PDT 24
Finished Jul 11 05:35:19 PM PDT 24
Peak memory 210552 kb
Host smart-82c19d5e-8fde-470d-9d38-b4e2a58fc401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798519457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3798519457
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3714655617
Short name T579
Test name
Test status
Simulation time 32811080 ps
CPU time 0.93 seconds
Started Jul 11 05:35:16 PM PDT 24
Finished Jul 11 05:35:21 PM PDT 24
Peak memory 206164 kb
Host smart-f814c9c8-b3fb-459f-a4e9-04440dfe45e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714655617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3714655617
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.796986868
Short name T154
Test name
Test status
Simulation time 88499686 ps
CPU time 2.9 seconds
Started Jul 11 05:35:13 PM PDT 24
Finished Jul 11 05:35:19 PM PDT 24
Peak memory 222596 kb
Host smart-810fbc2b-788c-40dc-9240-b47db0d15756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796986868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.796986868
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2312708171
Short name T526
Test name
Test status
Simulation time 154686902 ps
CPU time 3.36 seconds
Started Jul 11 05:35:23 PM PDT 24
Finished Jul 11 05:35:31 PM PDT 24
Peak memory 222452 kb
Host smart-a43284ec-7214-4d2f-8612-ccc328bbd46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312708171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2312708171
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1290616751
Short name T300
Test name
Test status
Simulation time 316388931 ps
CPU time 2.82 seconds
Started Jul 11 05:35:13 PM PDT 24
Finished Jul 11 05:35:20 PM PDT 24
Peak memory 214492 kb
Host smart-10921cf9-12c3-4b08-8048-3a66c352e2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290616751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1290616751
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1723284618
Short name T451
Test name
Test status
Simulation time 629660066 ps
CPU time 4.41 seconds
Started Jul 11 05:35:14 PM PDT 24
Finished Jul 11 05:35:22 PM PDT 24
Peak memory 220208 kb
Host smart-31b06792-2891-4fc5-987d-46aaf7a97e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723284618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1723284618
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1974207616
Short name T104
Test name
Test status
Simulation time 292792536 ps
CPU time 3.99 seconds
Started Jul 11 05:35:16 PM PDT 24
Finished Jul 11 05:35:24 PM PDT 24
Peak memory 207684 kb
Host smart-ede8dbf3-9213-477d-a10f-c25c461c8a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974207616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1974207616
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.731909778
Short name T2
Test name
Test status
Simulation time 126875126 ps
CPU time 2.27 seconds
Started Jul 11 05:35:13 PM PDT 24
Finished Jul 11 05:35:19 PM PDT 24
Peak memory 206716 kb
Host smart-014df092-bb9d-4a02-93e2-a3f72a6e9096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731909778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.731909778
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.469181227
Short name T842
Test name
Test status
Simulation time 54497327 ps
CPU time 2.88 seconds
Started Jul 11 05:35:15 PM PDT 24
Finished Jul 11 05:35:21 PM PDT 24
Peak memory 208748 kb
Host smart-ba45d964-fc47-49f8-9054-f35484472b07
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469181227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.469181227
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1623677780
Short name T492
Test name
Test status
Simulation time 143183539 ps
CPU time 2.78 seconds
Started Jul 11 05:35:15 PM PDT 24
Finished Jul 11 05:35:22 PM PDT 24
Peak memory 206824 kb
Host smart-bea68547-bf8e-4788-bc21-af12e6c56122
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623677780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1623677780
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2564051801
Short name T468
Test name
Test status
Simulation time 1127044080 ps
CPU time 30.05 seconds
Started Jul 11 05:35:11 PM PDT 24
Finished Jul 11 05:35:45 PM PDT 24
Peak memory 207956 kb
Host smart-09b0a0de-8cb8-463b-aead-7c24eab4c084
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564051801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2564051801
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2676269277
Short name T222
Test name
Test status
Simulation time 201569173 ps
CPU time 4.53 seconds
Started Jul 11 05:35:17 PM PDT 24
Finished Jul 11 05:35:26 PM PDT 24
Peak memory 214304 kb
Host smart-d18c8114-fef6-4e86-a817-db6a6510ea0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676269277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2676269277
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.191876973
Short name T473
Test name
Test status
Simulation time 123488006 ps
CPU time 4.09 seconds
Started Jul 11 05:35:17 PM PDT 24
Finished Jul 11 05:35:25 PM PDT 24
Peak memory 208276 kb
Host smart-8a361ecc-c355-406c-9756-a850193df41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191876973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.191876973
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3157421979
Short name T496
Test name
Test status
Simulation time 295948091 ps
CPU time 6.28 seconds
Started Jul 11 05:35:15 PM PDT 24
Finished Jul 11 05:35:25 PM PDT 24
Peak memory 218388 kb
Host smart-3c6b245b-676e-4d76-a016-805721181265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157421979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3157421979
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.144257253
Short name T569
Test name
Test status
Simulation time 116270600 ps
CPU time 2.42 seconds
Started Jul 11 05:35:16 PM PDT 24
Finished Jul 11 05:35:22 PM PDT 24
Peak memory 210176 kb
Host smart-c94e0903-ce1f-4da6-b6a9-b7e4857f57fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144257253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.144257253
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3522655096
Short name T653
Test name
Test status
Simulation time 37047667 ps
CPU time 0.74 seconds
Started Jul 11 05:35:23 PM PDT 24
Finished Jul 11 05:35:29 PM PDT 24
Peak memory 205996 kb
Host smart-a9fc8730-1c1d-455e-8e54-9bb23c144324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522655096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3522655096
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.925689691
Short name T145
Test name
Test status
Simulation time 172903856 ps
CPU time 2.7 seconds
Started Jul 11 05:35:18 PM PDT 24
Finished Jul 11 05:35:25 PM PDT 24
Peak memory 214268 kb
Host smart-d624ebbf-a8c0-43ff-ad86-6598e7373deb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=925689691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.925689691
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.65506697
Short name T31
Test name
Test status
Simulation time 246170848 ps
CPU time 3.26 seconds
Started Jul 11 05:35:16 PM PDT 24
Finished Jul 11 05:35:23 PM PDT 24
Peak memory 210128 kb
Host smart-56818371-869e-4619-9ff2-24c49a8151e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65506697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.65506697
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.4122424662
Short name T103
Test name
Test status
Simulation time 124252416 ps
CPU time 3.15 seconds
Started Jul 11 05:35:13 PM PDT 24
Finished Jul 11 05:35:20 PM PDT 24
Peak memory 218344 kb
Host smart-d9016f3a-f8f2-4ffd-8842-9ddc1932280c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122424662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.4122424662
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2189780006
Short name T791
Test name
Test status
Simulation time 156768520 ps
CPU time 4.7 seconds
Started Jul 11 05:35:16 PM PDT 24
Finished Jul 11 05:35:25 PM PDT 24
Peak memory 208960 kb
Host smart-d3427233-8f3b-48b1-bf58-585ddc4694c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189780006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2189780006
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.41764883
Short name T563
Test name
Test status
Simulation time 79992160 ps
CPU time 3.56 seconds
Started Jul 11 05:35:18 PM PDT 24
Finished Jul 11 05:35:26 PM PDT 24
Peak memory 214220 kb
Host smart-5d84ca90-43fb-479f-bd4c-b87196e9286c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41764883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.41764883
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2350663996
Short name T5
Test name
Test status
Simulation time 180104470 ps
CPU time 3.18 seconds
Started Jul 11 05:35:19 PM PDT 24
Finished Jul 11 05:35:26 PM PDT 24
Peak memory 208184 kb
Host smart-9be931aa-995a-4336-940d-817bebdd1285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350663996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2350663996
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2401571209
Short name T761
Test name
Test status
Simulation time 89403699 ps
CPU time 4.25 seconds
Started Jul 11 05:35:15 PM PDT 24
Finished Jul 11 05:35:23 PM PDT 24
Peak memory 207056 kb
Host smart-c2413a45-bfd8-438a-bcf9-2d2a7714c05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401571209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2401571209
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3960000006
Short name T597
Test name
Test status
Simulation time 344108062 ps
CPU time 3.15 seconds
Started Jul 11 05:35:14 PM PDT 24
Finished Jul 11 05:35:20 PM PDT 24
Peak memory 206824 kb
Host smart-ed4a1401-26b7-4d6e-b909-e4ff6ae3db41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960000006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3960000006
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.778422098
Short name T614
Test name
Test status
Simulation time 58586518 ps
CPU time 2.33 seconds
Started Jul 11 05:35:15 PM PDT 24
Finished Jul 11 05:35:21 PM PDT 24
Peak memory 207056 kb
Host smart-35aca265-944a-4c86-ad1f-841ecd3f76a1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778422098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.778422098
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2344853704
Short name T220
Test name
Test status
Simulation time 1045319125 ps
CPU time 7.92 seconds
Started Jul 11 05:35:14 PM PDT 24
Finished Jul 11 05:35:26 PM PDT 24
Peak memory 208612 kb
Host smart-c394cf7f-06cd-4c82-84ca-6ad8f8b8b10f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344853704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2344853704
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2760909999
Short name T613
Test name
Test status
Simulation time 64286914 ps
CPU time 3.25 seconds
Started Jul 11 05:35:15 PM PDT 24
Finished Jul 11 05:35:22 PM PDT 24
Peak memory 207720 kb
Host smart-3d48109e-84f9-43a7-8897-75a6716a1565
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760909999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2760909999
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.4015310976
Short name T662
Test name
Test status
Simulation time 695426844 ps
CPU time 19.64 seconds
Started Jul 11 05:35:23 PM PDT 24
Finished Jul 11 05:35:47 PM PDT 24
Peak memory 218412 kb
Host smart-7ea76db3-7ed7-4878-88ae-063a6c03376f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015310976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4015310976
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1639241405
Short name T706
Test name
Test status
Simulation time 183118747 ps
CPU time 4.8 seconds
Started Jul 11 05:35:17 PM PDT 24
Finished Jul 11 05:35:26 PM PDT 24
Peak memory 208160 kb
Host smart-31234201-8c10-48c7-9d63-bee7f683e709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639241405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1639241405
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3682850718
Short name T486
Test name
Test status
Simulation time 410481497 ps
CPU time 11.02 seconds
Started Jul 11 05:35:18 PM PDT 24
Finished Jul 11 05:35:33 PM PDT 24
Peak memory 214384 kb
Host smart-62ce78c3-bd48-4145-940d-10ac521a6d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682850718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3682850718
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1617497266
Short name T195
Test name
Test status
Simulation time 60479430 ps
CPU time 2.49 seconds
Started Jul 11 05:35:27 PM PDT 24
Finished Jul 11 05:35:36 PM PDT 24
Peak memory 210072 kb
Host smart-4133a50e-6ed7-4789-a2c0-c67f72dbe29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617497266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1617497266
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3164611162
Short name T445
Test name
Test status
Simulation time 15388023 ps
CPU time 0.93 seconds
Started Jul 11 05:35:28 PM PDT 24
Finished Jul 11 05:35:36 PM PDT 24
Peak memory 206104 kb
Host smart-d40a91bb-ac80-41ca-a524-831a4d756161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164611162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3164611162
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2561669883
Short name T427
Test name
Test status
Simulation time 1157922713 ps
CPU time 26.83 seconds
Started Jul 11 05:35:35 PM PDT 24
Finished Jul 11 05:36:09 PM PDT 24
Peak memory 215256 kb
Host smart-0dd109b8-e448-495b-968f-6a879cfb7a56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2561669883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2561669883
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.947945519
Short name T194
Test name
Test status
Simulation time 45981026 ps
CPU time 2.25 seconds
Started Jul 11 05:35:20 PM PDT 24
Finished Jul 11 05:35:26 PM PDT 24
Peak memory 207536 kb
Host smart-1255d694-da58-4c53-9437-ab28b1a1dfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947945519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.947945519
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.4187343235
Short name T359
Test name
Test status
Simulation time 99712411 ps
CPU time 1.48 seconds
Started Jul 11 05:35:35 PM PDT 24
Finished Jul 11 05:35:44 PM PDT 24
Peak memory 214608 kb
Host smart-4b4a7541-2d3a-440f-9860-425fd47dc167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187343235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.4187343235
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2252581597
Short name T793
Test name
Test status
Simulation time 355659791 ps
CPU time 6.57 seconds
Started Jul 11 05:35:22 PM PDT 24
Finished Jul 11 05:35:32 PM PDT 24
Peak memory 222128 kb
Host smart-65a042ba-1f45-43a3-8d13-c7165517ed5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252581597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2252581597
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.472460073
Short name T225
Test name
Test status
Simulation time 383646016 ps
CPU time 2.89 seconds
Started Jul 11 05:35:24 PM PDT 24
Finished Jul 11 05:35:32 PM PDT 24
Peak memory 210408 kb
Host smart-da9ffbb9-7d6d-4bf4-8847-900d86b24dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472460073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.472460073
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1241444039
Short name T774
Test name
Test status
Simulation time 798557185 ps
CPU time 6.94 seconds
Started Jul 11 05:35:23 PM PDT 24
Finished Jul 11 05:35:34 PM PDT 24
Peak memory 209736 kb
Host smart-aa9c6c97-3762-43bb-a1df-e20153dbbaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241444039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1241444039
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3292757824
Short name T688
Test name
Test status
Simulation time 2110784512 ps
CPU time 43.03 seconds
Started Jul 11 05:35:24 PM PDT 24
Finished Jul 11 05:36:13 PM PDT 24
Peak memory 209012 kb
Host smart-bef79636-e1a5-4eea-8584-0f5742325338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292757824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3292757824
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3600731135
Short name T337
Test name
Test status
Simulation time 54526754 ps
CPU time 1.79 seconds
Started Jul 11 05:35:27 PM PDT 24
Finished Jul 11 05:35:36 PM PDT 24
Peak memory 206908 kb
Host smart-bf334373-5df1-42e6-8dde-8354eeccd050
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600731135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3600731135
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3690735428
Short name T623
Test name
Test status
Simulation time 150917274 ps
CPU time 4.64 seconds
Started Jul 11 05:35:24 PM PDT 24
Finished Jul 11 05:35:34 PM PDT 24
Peak memory 208700 kb
Host smart-dd18eede-eeb8-4547-a480-500a2abff96d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690735428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3690735428
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1148627207
Short name T897
Test name
Test status
Simulation time 193491928 ps
CPU time 2.91 seconds
Started Jul 11 05:35:26 PM PDT 24
Finished Jul 11 05:35:35 PM PDT 24
Peak memory 208676 kb
Host smart-e1750ba4-58c8-47c1-8f8b-66cd421c57dd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148627207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1148627207
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1708495319
Short name T294
Test name
Test status
Simulation time 437150559 ps
CPU time 15.76 seconds
Started Jul 11 05:35:30 PM PDT 24
Finished Jul 11 05:35:52 PM PDT 24
Peak memory 218204 kb
Host smart-4972a915-f636-48f4-81ca-c6e782a7da4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708495319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1708495319
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.202786962
Short name T840
Test name
Test status
Simulation time 200169647 ps
CPU time 4.48 seconds
Started Jul 11 05:35:23 PM PDT 24
Finished Jul 11 05:35:32 PM PDT 24
Peak memory 208104 kb
Host smart-6d504b17-148a-4910-bb9a-b18880d37a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202786962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.202786962
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.4145431136
Short name T53
Test name
Test status
Simulation time 67739387328 ps
CPU time 160.42 seconds
Started Jul 11 05:35:21 PM PDT 24
Finished Jul 11 05:38:06 PM PDT 24
Peak memory 216416 kb
Host smart-6fffbc87-ce8b-4bb1-9e80-e686434cea12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145431136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.4145431136
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.4155350022
Short name T156
Test name
Test status
Simulation time 216567163 ps
CPU time 7.23 seconds
Started Jul 11 05:35:28 PM PDT 24
Finished Jul 11 05:35:42 PM PDT 24
Peak memory 219432 kb
Host smart-0b2ab9e9-908e-4f62-94e0-e6c80dd41f3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155350022 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.4155350022
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1204394002
Short name T475
Test name
Test status
Simulation time 3494016880 ps
CPU time 57.84 seconds
Started Jul 11 05:35:22 PM PDT 24
Finished Jul 11 05:36:24 PM PDT 24
Peak memory 209800 kb
Host smart-280c5267-3a99-43bb-ba43-ec4f14a6e72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204394002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1204394002
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.61317395
Short name T533
Test name
Test status
Simulation time 31797040 ps
CPU time 1.66 seconds
Started Jul 11 05:35:21 PM PDT 24
Finished Jul 11 05:35:27 PM PDT 24
Peak memory 209696 kb
Host smart-4761ab68-bf9e-4473-b0d7-d174d76a2e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61317395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.61317395
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2154158518
Short name T497
Test name
Test status
Simulation time 44653548 ps
CPU time 0.75 seconds
Started Jul 11 05:35:24 PM PDT 24
Finished Jul 11 05:35:30 PM PDT 24
Peak memory 206008 kb
Host smart-d7cd484b-931c-4097-8fa4-40990cda2810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154158518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2154158518
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1550940192
Short name T762
Test name
Test status
Simulation time 46833891 ps
CPU time 3.09 seconds
Started Jul 11 05:35:23 PM PDT 24
Finished Jul 11 05:35:31 PM PDT 24
Peak memory 214340 kb
Host smart-32e517f8-77e9-4025-8605-c862527910d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1550940192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1550940192
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2785872691
Short name T35
Test name
Test status
Simulation time 118468695 ps
CPU time 4.81 seconds
Started Jul 11 05:35:26 PM PDT 24
Finished Jul 11 05:35:38 PM PDT 24
Peak memory 214336 kb
Host smart-7def9e00-9bf0-4e2e-bfd5-671e67f543ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785872691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2785872691
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.684981076
Short name T669
Test name
Test status
Simulation time 59522929 ps
CPU time 2.3 seconds
Started Jul 11 05:35:22 PM PDT 24
Finished Jul 11 05:35:29 PM PDT 24
Peak memory 207616 kb
Host smart-bb9514b7-fcd2-450c-8d30-488537834c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684981076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.684981076
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.690781738
Short name T291
Test name
Test status
Simulation time 998832106 ps
CPU time 3.86 seconds
Started Jul 11 05:35:27 PM PDT 24
Finished Jul 11 05:35:38 PM PDT 24
Peak memory 215304 kb
Host smart-102148a5-a7ac-4bd7-a636-5752b99de003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690781738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.690781738
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3923370722
Short name T281
Test name
Test status
Simulation time 135883050 ps
CPU time 3.07 seconds
Started Jul 11 05:35:21 PM PDT 24
Finished Jul 11 05:35:28 PM PDT 24
Peak memory 220024 kb
Host smart-85c04899-c835-4fa6-9884-759c499937cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923370722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3923370722
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1386597400
Short name T882
Test name
Test status
Simulation time 169654530 ps
CPU time 3.56 seconds
Started Jul 11 05:35:29 PM PDT 24
Finished Jul 11 05:35:39 PM PDT 24
Peak memory 219500 kb
Host smart-cfaeab97-8078-4ef0-9d49-7752e6cd3606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386597400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1386597400
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3831237725
Short name T467
Test name
Test status
Simulation time 105363875 ps
CPU time 2.33 seconds
Started Jul 11 05:35:26 PM PDT 24
Finished Jul 11 05:35:34 PM PDT 24
Peak memory 206896 kb
Host smart-f0e40a73-24e4-43d1-9c57-f9c1b69235fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831237725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3831237725
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.268454624
Short name T90
Test name
Test status
Simulation time 60997222 ps
CPU time 3.27 seconds
Started Jul 11 05:35:25 PM PDT 24
Finished Jul 11 05:35:33 PM PDT 24
Peak memory 208884 kb
Host smart-3ac52a9b-4fbc-4983-b4b5-7ae865ffcc5b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268454624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.268454624
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.324303405
Short name T871
Test name
Test status
Simulation time 988786615 ps
CPU time 7.73 seconds
Started Jul 11 05:35:23 PM PDT 24
Finished Jul 11 05:35:35 PM PDT 24
Peak memory 208880 kb
Host smart-ed00e827-db31-4c99-8ae8-81243cfd4d03
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324303405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.324303405
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.493151632
Short name T351
Test name
Test status
Simulation time 266943360 ps
CPU time 3.02 seconds
Started Jul 11 05:35:26 PM PDT 24
Finished Jul 11 05:35:35 PM PDT 24
Peak memory 206960 kb
Host smart-820ee48f-90cb-4c97-9f2c-a294bcbf93dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493151632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.493151632
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3530643595
Short name T837
Test name
Test status
Simulation time 83399252 ps
CPU time 3.43 seconds
Started Jul 11 05:35:27 PM PDT 24
Finished Jul 11 05:35:37 PM PDT 24
Peak memory 209640 kb
Host smart-d8ae208b-09e8-4a4a-b0fb-6d007fc05dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530643595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3530643595
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3584931695
Short name T488
Test name
Test status
Simulation time 152539568 ps
CPU time 4.68 seconds
Started Jul 11 05:35:23 PM PDT 24
Finished Jul 11 05:35:32 PM PDT 24
Peak memory 207724 kb
Host smart-bf52ff97-45cd-4e6e-8b42-90faac15863d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584931695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3584931695
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1444298281
Short name T816
Test name
Test status
Simulation time 9687476586 ps
CPU time 21.73 seconds
Started Jul 11 05:35:24 PM PDT 24
Finished Jul 11 05:35:52 PM PDT 24
Peak memory 222588 kb
Host smart-04321ff6-fd49-454a-ba83-0e5bc820d107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444298281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1444298281
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2410283809
Short name T327
Test name
Test status
Simulation time 62289846 ps
CPU time 3.96 seconds
Started Jul 11 05:35:20 PM PDT 24
Finished Jul 11 05:35:28 PM PDT 24
Peak memory 218628 kb
Host smart-e77dcb93-66b1-43ae-b526-0fed8f869c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410283809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2410283809
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3724593324
Short name T56
Test name
Test status
Simulation time 101701492 ps
CPU time 2 seconds
Started Jul 11 05:35:34 PM PDT 24
Finished Jul 11 05:35:43 PM PDT 24
Peak memory 209864 kb
Host smart-27ec83d2-8de1-4098-acfe-5ff42b129c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724593324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3724593324
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1206323844
Short name T98
Test name
Test status
Simulation time 9355272 ps
CPU time 0.82 seconds
Started Jul 11 05:35:27 PM PDT 24
Finished Jul 11 05:35:35 PM PDT 24
Peak memory 205940 kb
Host smart-0f4f4d64-a37a-4cda-926f-4187c74597a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206323844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1206323844
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3071396929
Short name T133
Test name
Test status
Simulation time 54314557 ps
CPU time 4.12 seconds
Started Jul 11 05:35:27 PM PDT 24
Finished Jul 11 05:35:38 PM PDT 24
Peak memory 222464 kb
Host smart-1d3573e6-7980-4f46-bfc8-a62bd1e786fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3071396929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3071396929
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.495087892
Short name T680
Test name
Test status
Simulation time 155819133 ps
CPU time 2.03 seconds
Started Jul 11 05:35:23 PM PDT 24
Finished Jul 11 05:35:29 PM PDT 24
Peak memory 207376 kb
Host smart-2f8f992c-a893-4648-9932-baf4b49d7fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495087892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.495087892
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2844740054
Short name T867
Test name
Test status
Simulation time 451807208 ps
CPU time 4.05 seconds
Started Jul 11 05:35:24 PM PDT 24
Finished Jul 11 05:35:33 PM PDT 24
Peak memory 214340 kb
Host smart-7f5c2d89-8ba0-42c0-bb5d-719a0eeba133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844740054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2844740054
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3094137415
Short name T276
Test name
Test status
Simulation time 122331068 ps
CPU time 2.22 seconds
Started Jul 11 05:35:35 PM PDT 24
Finished Jul 11 05:35:45 PM PDT 24
Peak memory 206296 kb
Host smart-02a5fe10-8b81-49d2-922e-7c8e345fb724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094137415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3094137415
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.280351608
Short name T227
Test name
Test status
Simulation time 83991459 ps
CPU time 2.53 seconds
Started Jul 11 05:35:26 PM PDT 24
Finished Jul 11 05:35:36 PM PDT 24
Peak memory 214880 kb
Host smart-46901278-cd77-4409-adfd-749375371bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280351608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.280351608
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2031103676
Short name T403
Test name
Test status
Simulation time 131926731 ps
CPU time 5.1 seconds
Started Jul 11 05:35:23 PM PDT 24
Finished Jul 11 05:35:32 PM PDT 24
Peak memory 208108 kb
Host smart-e9ec91aa-d2e5-48f6-a028-9a1aebceebc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031103676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2031103676
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.4057845330
Short name T267
Test name
Test status
Simulation time 1337463923 ps
CPU time 33.34 seconds
Started Jul 11 05:35:24 PM PDT 24
Finished Jul 11 05:36:02 PM PDT 24
Peak memory 208876 kb
Host smart-b06943ba-f8d8-4579-a583-0edb2094b480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057845330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.4057845330
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1979184765
Short name T719
Test name
Test status
Simulation time 61973695 ps
CPU time 3.13 seconds
Started Jul 11 05:35:25 PM PDT 24
Finished Jul 11 05:35:34 PM PDT 24
Peak memory 208656 kb
Host smart-da61a89f-d645-45dc-bc6f-6315df2098ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979184765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1979184765
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2562744900
Short name T741
Test name
Test status
Simulation time 66549070 ps
CPU time 2.37 seconds
Started Jul 11 05:35:24 PM PDT 24
Finished Jul 11 05:35:31 PM PDT 24
Peak memory 208468 kb
Host smart-435a7df5-03a1-44fc-98d0-68fbb3147914
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562744900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2562744900
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.631377891
Short name T754
Test name
Test status
Simulation time 30881558 ps
CPU time 2.17 seconds
Started Jul 11 05:35:27 PM PDT 24
Finished Jul 11 05:35:35 PM PDT 24
Peak memory 208676 kb
Host smart-1aeaf33d-ef37-4ab9-9306-3b1a39612f51
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631377891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.631377891
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3323315152
Short name T201
Test name
Test status
Simulation time 406964331 ps
CPU time 3.47 seconds
Started Jul 11 05:35:27 PM PDT 24
Finished Jul 11 05:35:37 PM PDT 24
Peak memory 209664 kb
Host smart-dce3a8f7-b3d0-4f99-9993-d8c4e97a8cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323315152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3323315152
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.107567398
Short name T555
Test name
Test status
Simulation time 14993128387 ps
CPU time 41.47 seconds
Started Jul 11 05:35:23 PM PDT 24
Finished Jul 11 05:36:08 PM PDT 24
Peak memory 208456 kb
Host smart-5c794c09-d1bc-4324-9836-45b18d29b330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107567398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.107567398
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2416925473
Short name T228
Test name
Test status
Simulation time 10213009825 ps
CPU time 69.63 seconds
Started Jul 11 05:35:35 PM PDT 24
Finished Jul 11 05:36:53 PM PDT 24
Peak memory 222756 kb
Host smart-083bfcd4-f677-4884-91a1-5b7c1e676162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416925473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2416925473
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3046146545
Short name T205
Test name
Test status
Simulation time 945896737 ps
CPU time 11.96 seconds
Started Jul 11 05:35:24 PM PDT 24
Finished Jul 11 05:35:41 PM PDT 24
Peak memory 208820 kb
Host smart-a06e65e7-2159-454a-9e41-b0cdde308b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046146545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3046146545
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2938840124
Short name T697
Test name
Test status
Simulation time 50458405 ps
CPU time 1.91 seconds
Started Jul 11 05:35:35 PM PDT 24
Finished Jul 11 05:35:45 PM PDT 24
Peak memory 210220 kb
Host smart-2d9e55b5-1f1c-4bfe-804c-48c6fb7e5abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938840124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2938840124
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.4115208531
Short name T749
Test name
Test status
Simulation time 40470206 ps
CPU time 0.79 seconds
Started Jul 11 05:35:59 PM PDT 24
Finished Jul 11 05:36:02 PM PDT 24
Peak memory 205944 kb
Host smart-8aaf4159-db8d-4b39-a81c-7db97cba5102
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115208531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.4115208531
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1785284750
Short name T134
Test name
Test status
Simulation time 29671837 ps
CPU time 2.77 seconds
Started Jul 11 05:35:51 PM PDT 24
Finished Jul 11 05:35:55 PM PDT 24
Peak memory 214340 kb
Host smart-55bbc5d4-abc3-48f0-9f60-77a77ba72658
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1785284750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1785284750
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3850482092
Short name T839
Test name
Test status
Simulation time 61583615 ps
CPU time 1.78 seconds
Started Jul 11 05:35:53 PM PDT 24
Finished Jul 11 05:35:56 PM PDT 24
Peak memory 218120 kb
Host smart-3bfc5835-0429-4a8c-bd52-a1fd251f3599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850482092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3850482092
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1387336078
Short name T659
Test name
Test status
Simulation time 424158126 ps
CPU time 4.01 seconds
Started Jul 11 05:35:55 PM PDT 24
Finished Jul 11 05:36:01 PM PDT 24
Peak memory 219596 kb
Host smart-ae3702e9-77d4-4fef-bd77-49817b150a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387336078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1387336078
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3381664348
Short name T602
Test name
Test status
Simulation time 179387979 ps
CPU time 3.37 seconds
Started Jul 11 05:35:52 PM PDT 24
Finished Jul 11 05:35:56 PM PDT 24
Peak memory 209460 kb
Host smart-3495f0f7-40c3-4573-ab2c-43ccaae21461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381664348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3381664348
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2342709869
Short name T319
Test name
Test status
Simulation time 242700379 ps
CPU time 3.17 seconds
Started Jul 11 05:36:01 PM PDT 24
Finished Jul 11 05:36:06 PM PDT 24
Peak memory 214256 kb
Host smart-c0e27098-8f15-43cd-82ad-c344b3500d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342709869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2342709869
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3638439342
Short name T417
Test name
Test status
Simulation time 120547251 ps
CPU time 3.17 seconds
Started Jul 11 05:35:49 PM PDT 24
Finished Jul 11 05:35:53 PM PDT 24
Peak memory 219784 kb
Host smart-e99fa693-91ff-451f-a57c-2e9bbd9a1178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638439342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3638439342
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3968129898
Short name T691
Test name
Test status
Simulation time 720308929 ps
CPU time 4.37 seconds
Started Jul 11 05:35:37 PM PDT 24
Finished Jul 11 05:35:49 PM PDT 24
Peak memory 218272 kb
Host smart-7029ba09-61f3-429b-b525-9000bac7dcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968129898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3968129898
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1661644501
Short name T636
Test name
Test status
Simulation time 1311397278 ps
CPU time 17.09 seconds
Started Jul 11 05:35:26 PM PDT 24
Finished Jul 11 05:35:50 PM PDT 24
Peak memory 208212 kb
Host smart-45f6bd35-26f7-411d-9db3-abd35826bff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661644501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1661644501
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.497939914
Short name T857
Test name
Test status
Simulation time 50657622 ps
CPU time 2.6 seconds
Started Jul 11 05:35:58 PM PDT 24
Finished Jul 11 05:36:02 PM PDT 24
Peak memory 206976 kb
Host smart-dbcf58c5-5f52-487f-a32c-b4ee001b8f77
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497939914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.497939914
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2074685741
Short name T558
Test name
Test status
Simulation time 1307027409 ps
CPU time 33.21 seconds
Started Jul 11 05:35:35 PM PDT 24
Finished Jul 11 05:36:16 PM PDT 24
Peak memory 208360 kb
Host smart-11171239-429c-44ea-9ef0-77a30fda7612
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074685741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2074685741
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3821461482
Short name T627
Test name
Test status
Simulation time 231637659 ps
CPU time 6.73 seconds
Started Jul 11 05:35:33 PM PDT 24
Finished Jul 11 05:35:46 PM PDT 24
Peak memory 207968 kb
Host smart-9cbf0287-e3a4-4c8d-b46c-55692ccbb493
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821461482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3821461482
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2125785926
Short name T367
Test name
Test status
Simulation time 43015908 ps
CPU time 2.66 seconds
Started Jul 11 05:35:53 PM PDT 24
Finished Jul 11 05:35:57 PM PDT 24
Peak memory 214420 kb
Host smart-5bccfa89-9426-4a14-810b-d2c01f952e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125785926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2125785926
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3774219107
Short name T507
Test name
Test status
Simulation time 36248581 ps
CPU time 2.25 seconds
Started Jul 11 05:35:34 PM PDT 24
Finished Jul 11 05:35:43 PM PDT 24
Peak memory 206724 kb
Host smart-f21131ec-1fae-4ec1-a6aa-0913d16558ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774219107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3774219107
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.4275781720
Short name T731
Test name
Test status
Simulation time 510296139 ps
CPU time 6.16 seconds
Started Jul 11 05:35:55 PM PDT 24
Finished Jul 11 05:36:02 PM PDT 24
Peak memory 218388 kb
Host smart-4d75b482-e00a-4040-8014-86b4731411ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275781720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.4275781720
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3841314693
Short name T62
Test name
Test status
Simulation time 460256119 ps
CPU time 3.08 seconds
Started Jul 11 05:35:53 PM PDT 24
Finished Jul 11 05:35:57 PM PDT 24
Peak memory 210580 kb
Host smart-05a2898d-a5f8-45c5-9373-9977cdd089d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841314693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3841314693
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3430066178
Short name T505
Test name
Test status
Simulation time 24173816 ps
CPU time 1.02 seconds
Started Jul 11 05:36:30 PM PDT 24
Finished Jul 11 05:36:35 PM PDT 24
Peak memory 206204 kb
Host smart-fff33909-ecf2-46db-974e-09f8f30f1c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430066178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3430066178
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2040762344
Short name T397
Test name
Test status
Simulation time 62540013 ps
CPU time 3.65 seconds
Started Jul 11 05:36:04 PM PDT 24
Finished Jul 11 05:36:11 PM PDT 24
Peak memory 214948 kb
Host smart-b061d90e-9347-410d-8c65-0595beda551a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2040762344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2040762344
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3286458018
Short name T714
Test name
Test status
Simulation time 250683608 ps
CPU time 3.99 seconds
Started Jul 11 05:35:57 PM PDT 24
Finished Jul 11 05:36:03 PM PDT 24
Peak memory 221788 kb
Host smart-20c9b794-bd0a-4adf-bf76-4cf5edc442fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286458018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3286458018
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3906318458
Short name T689
Test name
Test status
Simulation time 82552115 ps
CPU time 3.01 seconds
Started Jul 11 05:35:57 PM PDT 24
Finished Jul 11 05:36:02 PM PDT 24
Peak memory 218588 kb
Host smart-13f2730d-a56d-44a1-be27-0433b818dadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906318458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3906318458
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3718523151
Short name T911
Test name
Test status
Simulation time 770873170 ps
CPU time 5.21 seconds
Started Jul 11 05:36:08 PM PDT 24
Finished Jul 11 05:36:15 PM PDT 24
Peak memory 211380 kb
Host smart-a646c9da-f43e-4d2f-8ef5-d67bf8bc39ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718523151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3718523151
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3787573807
Short name T905
Test name
Test status
Simulation time 423823630 ps
CPU time 3.74 seconds
Started Jul 11 05:36:30 PM PDT 24
Finished Jul 11 05:36:37 PM PDT 24
Peak memory 218964 kb
Host smart-7eee6975-b5b5-4983-a66b-360510f698ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787573807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3787573807
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3828438920
Short name T818
Test name
Test status
Simulation time 670072570 ps
CPU time 8.35 seconds
Started Jul 11 05:35:53 PM PDT 24
Finished Jul 11 05:36:02 PM PDT 24
Peak memory 208412 kb
Host smart-dff41db1-1d4d-47b5-8af0-f5e4438288bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828438920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3828438920
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1351126642
Short name T315
Test name
Test status
Simulation time 115223335 ps
CPU time 3.12 seconds
Started Jul 11 05:35:57 PM PDT 24
Finished Jul 11 05:36:02 PM PDT 24
Peak memory 206844 kb
Host smart-3f97ead7-8bac-48f2-846f-179d76e7c670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351126642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1351126642
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1705073158
Short name T831
Test name
Test status
Simulation time 1755309251 ps
CPU time 4.03 seconds
Started Jul 11 05:35:55 PM PDT 24
Finished Jul 11 05:36:00 PM PDT 24
Peak memory 208984 kb
Host smart-56137db2-7b90-4c70-8345-29ea5984c5cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705073158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1705073158
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.367152062
Short name T798
Test name
Test status
Simulation time 245287156 ps
CPU time 1.98 seconds
Started Jul 11 05:35:53 PM PDT 24
Finished Jul 11 05:35:56 PM PDT 24
Peak memory 207344 kb
Host smart-b8d00e16-26f7-40e9-87d9-eaabdff27944
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367152062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.367152062
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2689356564
Short name T574
Test name
Test status
Simulation time 100853626 ps
CPU time 3.39 seconds
Started Jul 11 05:36:30 PM PDT 24
Finished Jul 11 05:36:37 PM PDT 24
Peak memory 208044 kb
Host smart-af594582-9bd9-4530-b590-080e8d906f47
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689356564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2689356564
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.4289939435
Short name T553
Test name
Test status
Simulation time 165314092 ps
CPU time 2.82 seconds
Started Jul 11 05:35:53 PM PDT 24
Finished Jul 11 05:35:57 PM PDT 24
Peak memory 215460 kb
Host smart-331c4ea8-9ec6-4d06-9623-088c893c4568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289939435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.4289939435
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.34195504
Short name T901
Test name
Test status
Simulation time 200235506 ps
CPU time 4.73 seconds
Started Jul 11 05:36:30 PM PDT 24
Finished Jul 11 05:36:38 PM PDT 24
Peak memory 208344 kb
Host smart-b105eecd-1895-452f-9203-804768756557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34195504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.34195504
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3440618588
Short name T78
Test name
Test status
Simulation time 2003280810 ps
CPU time 24.53 seconds
Started Jul 11 05:36:00 PM PDT 24
Finished Jul 11 05:36:26 PM PDT 24
Peak memory 215632 kb
Host smart-10246579-9179-4752-b405-983209f402af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440618588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3440618588
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2276264002
Short name T186
Test name
Test status
Simulation time 1135539859 ps
CPU time 7.26 seconds
Started Jul 11 05:35:59 PM PDT 24
Finished Jul 11 05:36:07 PM PDT 24
Peak memory 218628 kb
Host smart-d953fcb9-1656-47a9-8ac4-5d75d9797317
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276264002 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2276264002
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3251447481
Short name T646
Test name
Test status
Simulation time 559527883 ps
CPU time 5.16 seconds
Started Jul 11 05:36:05 PM PDT 24
Finished Jul 11 05:36:12 PM PDT 24
Peak memory 209132 kb
Host smart-3ff20b17-d7ec-48f9-8b60-691ad9f9df8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251447481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3251447481
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2538991638
Short name T161
Test name
Test status
Simulation time 109487943 ps
CPU time 2.34 seconds
Started Jul 11 05:35:59 PM PDT 24
Finished Jul 11 05:36:03 PM PDT 24
Peak memory 210188 kb
Host smart-98b27be8-a56f-4a33-b9db-6977b6390fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538991638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2538991638
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2372017780
Short name T751
Test name
Test status
Simulation time 25020416 ps
CPU time 0.92 seconds
Started Jul 11 05:33:33 PM PDT 24
Finished Jul 11 05:33:37 PM PDT 24
Peak memory 206044 kb
Host smart-00037c9a-f44f-428e-8b28-48f37245f5b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372017780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2372017780
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3891016131
Short name T520
Test name
Test status
Simulation time 51758064 ps
CPU time 2.24 seconds
Started Jul 11 05:33:33 PM PDT 24
Finished Jul 11 05:33:38 PM PDT 24
Peak memory 217908 kb
Host smart-f93ffaf3-7ce0-48c2-883f-e5dfcf56abd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891016131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3891016131
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.4052268959
Short name T853
Test name
Test status
Simulation time 72914987 ps
CPU time 2.62 seconds
Started Jul 11 05:33:31 PM PDT 24
Finished Jul 11 05:33:36 PM PDT 24
Peak memory 214336 kb
Host smart-ca6d930a-ba4f-4131-9270-cfadb28cdc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052268959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.4052268959
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1150587156
Short name T770
Test name
Test status
Simulation time 203080929 ps
CPU time 3.33 seconds
Started Jul 11 05:33:41 PM PDT 24
Finished Jul 11 05:33:47 PM PDT 24
Peak memory 222584 kb
Host smart-55092d08-73dd-4ebb-84fd-f6a75275529b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150587156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1150587156
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2401116998
Short name T420
Test name
Test status
Simulation time 134290357 ps
CPU time 4.17 seconds
Started Jul 11 05:33:34 PM PDT 24
Finished Jul 11 05:33:41 PM PDT 24
Peak memory 207404 kb
Host smart-428883f6-dc07-4408-a6e7-837ce4382a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401116998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2401116998
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3146830481
Short name T99
Test name
Test status
Simulation time 500985841 ps
CPU time 12.35 seconds
Started Jul 11 05:33:37 PM PDT 24
Finished Jul 11 05:33:52 PM PDT 24
Peak memory 230300 kb
Host smart-ba6d0b56-334e-4926-a55d-3365b4932308
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146830481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3146830481
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.497305930
Short name T896
Test name
Test status
Simulation time 69895558 ps
CPU time 1.67 seconds
Started Jul 11 05:33:32 PM PDT 24
Finished Jul 11 05:33:36 PM PDT 24
Peak memory 207108 kb
Host smart-2edd3c1d-c62c-4f7b-ba37-246aea8026f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497305930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.497305930
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.634037124
Short name T737
Test name
Test status
Simulation time 189471684 ps
CPU time 5.35 seconds
Started Jul 11 05:33:33 PM PDT 24
Finished Jul 11 05:33:41 PM PDT 24
Peak memory 209024 kb
Host smart-08a63908-1a42-4e38-ba6b-8bd4f2f3a64f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634037124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.634037124
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1371543593
Short name T216
Test name
Test status
Simulation time 1833618029 ps
CPU time 52.65 seconds
Started Jul 11 05:33:30 PM PDT 24
Finished Jul 11 05:34:24 PM PDT 24
Peak memory 208332 kb
Host smart-8260a304-150a-4309-9c53-30976d6970ae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371543593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1371543593
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.465137466
Short name T504
Test name
Test status
Simulation time 59848065 ps
CPU time 1.84 seconds
Started Jul 11 05:33:34 PM PDT 24
Finished Jul 11 05:33:38 PM PDT 24
Peak memory 206044 kb
Host smart-9f220b0c-0243-4b79-93c0-151431df72e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465137466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.465137466
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3556526430
Short name T421
Test name
Test status
Simulation time 1346265353 ps
CPU time 13.34 seconds
Started Jul 11 05:33:37 PM PDT 24
Finished Jul 11 05:33:53 PM PDT 24
Peak memory 209288 kb
Host smart-3715f119-9e2e-4427-b63e-43b9b495eae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556526430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3556526430
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1067155917
Short name T431
Test name
Test status
Simulation time 64945292 ps
CPU time 2.88 seconds
Started Jul 11 05:33:35 PM PDT 24
Finished Jul 11 05:33:40 PM PDT 24
Peak memory 206648 kb
Host smart-2b927a0d-b6e8-4223-83f3-23e23e757aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067155917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1067155917
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3259697299
Short name T562
Test name
Test status
Simulation time 90829717 ps
CPU time 3.81 seconds
Started Jul 11 05:33:36 PM PDT 24
Finished Jul 11 05:33:43 PM PDT 24
Peak memory 207448 kb
Host smart-e63f8351-bbed-4456-ba05-da77e8974ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259697299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3259697299
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.683453926
Short name T814
Test name
Test status
Simulation time 38432846 ps
CPU time 0.77 seconds
Started Jul 11 05:36:00 PM PDT 24
Finished Jul 11 05:36:03 PM PDT 24
Peak memory 205960 kb
Host smart-965360a5-bfcc-4e7b-bcd0-c6a2a4359454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683453926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.683453926
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3237212189
Short name T74
Test name
Test status
Simulation time 129141874 ps
CPU time 2.7 seconds
Started Jul 11 05:36:08 PM PDT 24
Finished Jul 11 05:36:13 PM PDT 24
Peak memory 219640 kb
Host smart-0fb47fc7-7de6-41ba-8ba7-c2b94292ec92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237212189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3237212189
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.802700857
Short name T678
Test name
Test status
Simulation time 67021818 ps
CPU time 2.68 seconds
Started Jul 11 05:36:04 PM PDT 24
Finished Jul 11 05:36:10 PM PDT 24
Peak memory 210448 kb
Host smart-afe3c922-4efd-4434-aced-95ea6ce56c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802700857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.802700857
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1065226481
Short name T860
Test name
Test status
Simulation time 58602461 ps
CPU time 3.78 seconds
Started Jul 11 05:35:59 PM PDT 24
Finished Jul 11 05:36:04 PM PDT 24
Peak memory 209708 kb
Host smart-4f47d8b8-f4ba-4e78-aa52-28fc38e87ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065226481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1065226481
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2231950313
Short name T846
Test name
Test status
Simulation time 368309378 ps
CPU time 4.55 seconds
Started Jul 11 05:36:11 PM PDT 24
Finished Jul 11 05:36:17 PM PDT 24
Peak memory 214252 kb
Host smart-f8e8e11c-421b-4e9a-9e2a-60227131d087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231950313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2231950313
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.762271933
Short name T658
Test name
Test status
Simulation time 41150913 ps
CPU time 2.82 seconds
Started Jul 11 05:36:00 PM PDT 24
Finished Jul 11 05:36:05 PM PDT 24
Peak memory 220308 kb
Host smart-f2ee0a61-d20e-4ed4-a394-fad9973a8c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762271933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.762271933
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1472323276
Short name T193
Test name
Test status
Simulation time 4101155897 ps
CPU time 23.24 seconds
Started Jul 11 05:36:00 PM PDT 24
Finished Jul 11 05:36:25 PM PDT 24
Peak memory 210288 kb
Host smart-9944281f-7c7b-4ded-b2ce-ff328531602f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472323276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1472323276
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3145246286
Short name T543
Test name
Test status
Simulation time 2059752712 ps
CPU time 27.27 seconds
Started Jul 11 05:36:07 PM PDT 24
Finished Jul 11 05:36:37 PM PDT 24
Peak memory 208020 kb
Host smart-9c99ccbe-5548-4bb9-98c3-53a25be8cb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145246286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3145246286
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3894925387
Short name T806
Test name
Test status
Simulation time 83770397 ps
CPU time 3.57 seconds
Started Jul 11 05:36:02 PM PDT 24
Finished Jul 11 05:36:09 PM PDT 24
Peak memory 208684 kb
Host smart-d8f050ce-6560-43fa-869f-6c18c70773b5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894925387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3894925387
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.4223507477
Short name T283
Test name
Test status
Simulation time 246003014 ps
CPU time 3.47 seconds
Started Jul 11 05:36:01 PM PDT 24
Finished Jul 11 05:36:07 PM PDT 24
Peak memory 207008 kb
Host smart-905e90ae-b802-480e-91b1-477965bada80
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223507477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.4223507477
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1718139693
Short name T844
Test name
Test status
Simulation time 284187197 ps
CPU time 3.63 seconds
Started Jul 11 05:36:02 PM PDT 24
Finished Jul 11 05:36:09 PM PDT 24
Peak memory 208736 kb
Host smart-91c69bf7-e0d5-466a-a7f2-5cfb1e81f570
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718139693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1718139693
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3825088134
Short name T215
Test name
Test status
Simulation time 193625402 ps
CPU time 1.73 seconds
Started Jul 11 05:35:58 PM PDT 24
Finished Jul 11 05:36:02 PM PDT 24
Peak memory 210172 kb
Host smart-4f1e6530-3850-4451-b37b-b7d75bdae825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825088134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3825088134
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1050620267
Short name T852
Test name
Test status
Simulation time 96197745 ps
CPU time 2.74 seconds
Started Jul 11 05:35:59 PM PDT 24
Finished Jul 11 05:36:03 PM PDT 24
Peak memory 206944 kb
Host smart-74d8b05d-92c9-486a-a343-1fbeab5f799f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050620267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1050620267
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1380908362
Short name T189
Test name
Test status
Simulation time 447431644 ps
CPU time 15.68 seconds
Started Jul 11 05:36:30 PM PDT 24
Finished Jul 11 05:36:49 PM PDT 24
Peak memory 222528 kb
Host smart-b9701548-2ebd-4216-8adc-fe41a08be15b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380908362 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1380908362
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1800375454
Short name T265
Test name
Test status
Simulation time 1617266097 ps
CPU time 9.3 seconds
Started Jul 11 05:36:01 PM PDT 24
Finished Jul 11 05:36:14 PM PDT 24
Peak memory 218480 kb
Host smart-10ce2cc6-12c5-4817-b86e-419e3fe8e686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800375454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1800375454
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1508635484
Short name T456
Test name
Test status
Simulation time 143971731 ps
CPU time 4.27 seconds
Started Jul 11 05:36:11 PM PDT 24
Finished Jul 11 05:36:17 PM PDT 24
Peak memory 211128 kb
Host smart-f86322c5-d13f-4849-92b9-f66b6bfd8016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508635484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1508635484
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.946875166
Short name T525
Test name
Test status
Simulation time 67934545 ps
CPU time 0.76 seconds
Started Jul 11 05:36:01 PM PDT 24
Finished Jul 11 05:36:05 PM PDT 24
Peak memory 206004 kb
Host smart-7012cb54-3493-4db3-a393-3e92fc415d14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946875166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.946875166
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.938733406
Short name T413
Test name
Test status
Simulation time 161187618 ps
CPU time 8.49 seconds
Started Jul 11 05:36:00 PM PDT 24
Finished Jul 11 05:36:11 PM PDT 24
Peak memory 214356 kb
Host smart-4c0b4a95-96f3-48f3-a29f-6313a3a5cfe8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=938733406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.938733406
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2418990198
Short name T347
Test name
Test status
Simulation time 110070680 ps
CPU time 4.67 seconds
Started Jul 11 05:36:06 PM PDT 24
Finished Jul 11 05:36:13 PM PDT 24
Peak memory 210480 kb
Host smart-c121bd86-665d-40c2-9edf-2787ab929bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418990198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2418990198
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3256382448
Short name T373
Test name
Test status
Simulation time 94857272 ps
CPU time 2.03 seconds
Started Jul 11 05:36:00 PM PDT 24
Finished Jul 11 05:36:03 PM PDT 24
Peak memory 208148 kb
Host smart-4d83a0f8-50a3-45ac-8a37-7fd569caee9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256382448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3256382448
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2000425877
Short name T261
Test name
Test status
Simulation time 442981210 ps
CPU time 3.81 seconds
Started Jul 11 05:36:00 PM PDT 24
Finished Jul 11 05:36:06 PM PDT 24
Peak memory 214340 kb
Host smart-6e884bd8-7cfd-4846-aef1-3c99987572ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000425877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2000425877
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2799724824
Short name T790
Test name
Test status
Simulation time 285300974 ps
CPU time 3.98 seconds
Started Jul 11 05:35:58 PM PDT 24
Finished Jul 11 05:36:04 PM PDT 24
Peak memory 220304 kb
Host smart-cfbd606a-9639-4bba-8b07-fa110a6ad98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799724824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2799724824
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2716338098
Short name T789
Test name
Test status
Simulation time 75509914 ps
CPU time 3.47 seconds
Started Jul 11 05:36:01 PM PDT 24
Finished Jul 11 05:36:08 PM PDT 24
Peak memory 220316 kb
Host smart-a15278cd-bd06-4e1d-bf2f-ddb323b429d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716338098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2716338098
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3062745621
Short name T210
Test name
Test status
Simulation time 641620459 ps
CPU time 10.2 seconds
Started Jul 11 05:36:25 PM PDT 24
Finished Jul 11 05:36:38 PM PDT 24
Peak memory 207844 kb
Host smart-e8fdb999-43cd-46f2-b32e-26bd55f2bbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062745621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3062745621
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2001576909
Short name T588
Test name
Test status
Simulation time 1531511606 ps
CPU time 4.16 seconds
Started Jul 11 05:36:13 PM PDT 24
Finished Jul 11 05:36:20 PM PDT 24
Peak memory 206676 kb
Host smart-6fe0032d-7bb8-4474-a8e5-f0d63fec9387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001576909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2001576909
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1423520822
Short name T865
Test name
Test status
Simulation time 315569390 ps
CPU time 3.43 seconds
Started Jul 11 05:35:58 PM PDT 24
Finished Jul 11 05:36:03 PM PDT 24
Peak memory 206832 kb
Host smart-1f4826f1-d1b4-4813-8f00-388cd15089b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423520822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1423520822
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3259402642
Short name T675
Test name
Test status
Simulation time 182550673 ps
CPU time 4.58 seconds
Started Jul 11 05:35:57 PM PDT 24
Finished Jul 11 05:36:04 PM PDT 24
Peak memory 208948 kb
Host smart-797053db-f31f-4fc7-8bff-5569296f6bca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259402642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3259402642
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3299619793
Short name T878
Test name
Test status
Simulation time 148548548 ps
CPU time 5.71 seconds
Started Jul 11 05:36:02 PM PDT 24
Finished Jul 11 05:36:10 PM PDT 24
Peak memory 206796 kb
Host smart-e2c7aba0-9e69-4ef9-a45f-674c652252a9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299619793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3299619793
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1009706237
Short name T590
Test name
Test status
Simulation time 6714659175 ps
CPU time 19.68 seconds
Started Jul 11 05:36:06 PM PDT 24
Finished Jul 11 05:36:28 PM PDT 24
Peak memory 209356 kb
Host smart-4900678e-8f72-4768-a43c-3b8e3f873495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009706237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1009706237
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1604022258
Short name T611
Test name
Test status
Simulation time 21284964 ps
CPU time 1.69 seconds
Started Jul 11 05:35:56 PM PDT 24
Finished Jul 11 05:36:00 PM PDT 24
Peak memory 206872 kb
Host smart-952b52d2-d635-40b6-a0b9-c7a36c54d91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604022258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1604022258
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.4127871181
Short name T311
Test name
Test status
Simulation time 761996906 ps
CPU time 15.08 seconds
Started Jul 11 05:36:01 PM PDT 24
Finished Jul 11 05:36:18 PM PDT 24
Peak memory 222644 kb
Host smart-d7283235-096a-469f-ba58-ae2b8d114523
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127871181 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.4127871181
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1088653748
Short name T875
Test name
Test status
Simulation time 59775357 ps
CPU time 3.53 seconds
Started Jul 11 05:36:03 PM PDT 24
Finished Jul 11 05:36:10 PM PDT 24
Peak memory 207700 kb
Host smart-d1957c92-63bb-4c37-947a-ce11c7d4fc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088653748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1088653748
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.520646940
Short name T394
Test name
Test status
Simulation time 33061904 ps
CPU time 1.73 seconds
Started Jul 11 05:36:06 PM PDT 24
Finished Jul 11 05:36:10 PM PDT 24
Peak memory 209696 kb
Host smart-5122ad05-6307-403f-a554-3bb82c9540f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520646940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.520646940
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1744994437
Short name T586
Test name
Test status
Simulation time 9873446 ps
CPU time 0.8 seconds
Started Jul 11 05:36:05 PM PDT 24
Finished Jul 11 05:36:09 PM PDT 24
Peak memory 206004 kb
Host smart-e9d9c26b-ffc4-4cf2-a1ff-b830d19246b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744994437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1744994437
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1442332101
Short name T312
Test name
Test status
Simulation time 835724569 ps
CPU time 26.84 seconds
Started Jul 11 05:36:05 PM PDT 24
Finished Jul 11 05:36:35 PM PDT 24
Peak memory 222596 kb
Host smart-c46c5df3-fbca-4550-b712-618a4884c6a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1442332101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1442332101
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1277489008
Short name T898
Test name
Test status
Simulation time 37405467 ps
CPU time 1.56 seconds
Started Jul 11 05:36:07 PM PDT 24
Finished Jul 11 05:36:11 PM PDT 24
Peak memory 215084 kb
Host smart-596739b1-c330-4111-9c73-8f93bfb6b94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277489008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1277489008
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2516713151
Short name T358
Test name
Test status
Simulation time 67619512 ps
CPU time 2.32 seconds
Started Jul 11 05:36:01 PM PDT 24
Finished Jul 11 05:36:06 PM PDT 24
Peak memory 208800 kb
Host smart-170f2658-c581-41eb-bdc3-344e5a22e84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516713151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2516713151
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.58183010
Short name T388
Test name
Test status
Simulation time 52737950 ps
CPU time 2.12 seconds
Started Jul 11 05:36:02 PM PDT 24
Finished Jul 11 05:36:07 PM PDT 24
Peak memory 208672 kb
Host smart-5db27531-419e-44b7-bba9-307536baa6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58183010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.58183010
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1835086577
Short name T49
Test name
Test status
Simulation time 38066152 ps
CPU time 2.32 seconds
Started Jul 11 05:36:01 PM PDT 24
Finished Jul 11 05:36:06 PM PDT 24
Peak memory 214276 kb
Host smart-23ac6ca3-f3de-4958-9582-018f1158a1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835086577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1835086577
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_random.1345442252
Short name T331
Test name
Test status
Simulation time 60191346 ps
CPU time 3.9 seconds
Started Jul 11 05:36:17 PM PDT 24
Finished Jul 11 05:36:24 PM PDT 24
Peak memory 218072 kb
Host smart-ea2952ce-61ec-47c5-855e-ad5076771305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345442252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1345442252
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2475430028
Short name T883
Test name
Test status
Simulation time 718283252 ps
CPU time 8.06 seconds
Started Jul 11 05:36:13 PM PDT 24
Finished Jul 11 05:36:24 PM PDT 24
Peak memory 206740 kb
Host smart-7db95452-c8a7-433a-ad52-03e6d26366f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475430028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2475430028
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3695064485
Short name T799
Test name
Test status
Simulation time 565250930 ps
CPU time 4.3 seconds
Started Jul 11 05:36:13 PM PDT 24
Finished Jul 11 05:36:20 PM PDT 24
Peak memory 207860 kb
Host smart-bbd47366-e294-4cf8-8b1a-089126ca7b3f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695064485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3695064485
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.700489039
Short name T517
Test name
Test status
Simulation time 906037586 ps
CPU time 28.74 seconds
Started Jul 11 05:36:02 PM PDT 24
Finished Jul 11 05:36:34 PM PDT 24
Peak memory 208088 kb
Host smart-55c04c42-573c-4382-acd8-d47659344c62
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700489039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.700489039
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.897041142
Short name T670
Test name
Test status
Simulation time 238206617 ps
CPU time 3.21 seconds
Started Jul 11 05:36:00 PM PDT 24
Finished Jul 11 05:36:06 PM PDT 24
Peak memory 207940 kb
Host smart-f31de147-c746-4f65-b818-3114a8d50b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897041142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.897041142
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2439518223
Short name T578
Test name
Test status
Simulation time 839441064 ps
CPU time 2.93 seconds
Started Jul 11 05:36:00 PM PDT 24
Finished Jul 11 05:36:06 PM PDT 24
Peak memory 206748 kb
Host smart-1532ae14-90c7-4c5f-870a-7c9cc80d7e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439518223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2439518223
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2451739631
Short name T245
Test name
Test status
Simulation time 1639397681 ps
CPU time 21.4 seconds
Started Jul 11 05:36:07 PM PDT 24
Finished Jul 11 05:36:31 PM PDT 24
Peak memory 214916 kb
Host smart-21e0141f-9b4f-44d3-a4db-e8d63d7b2bff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451739631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2451739631
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3014584579
Short name T127
Test name
Test status
Simulation time 1039000421 ps
CPU time 9.17 seconds
Started Jul 11 05:36:05 PM PDT 24
Finished Jul 11 05:36:17 PM PDT 24
Peak memory 222656 kb
Host smart-93982c45-080c-47c7-be38-f1661a162958
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014584579 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3014584579
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2044071464
Short name T286
Test name
Test status
Simulation time 120805539 ps
CPU time 5.66 seconds
Started Jul 11 05:35:59 PM PDT 24
Finished Jul 11 05:36:06 PM PDT 24
Peak memory 209548 kb
Host smart-65f0a26c-bb06-47a7-b088-fdccf3b803cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044071464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2044071464
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2815828270
Short name T125
Test name
Test status
Simulation time 63899177 ps
CPU time 2.62 seconds
Started Jul 11 05:36:02 PM PDT 24
Finished Jul 11 05:36:08 PM PDT 24
Peak memory 210340 kb
Host smart-0055ba6e-f2d9-4231-af21-41bbb4cbbd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815828270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2815828270
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.521556934
Short name T521
Test name
Test status
Simulation time 31172950 ps
CPU time 0.83 seconds
Started Jul 11 05:36:13 PM PDT 24
Finished Jul 11 05:36:15 PM PDT 24
Peak memory 205996 kb
Host smart-cc920fc5-dba1-4dd3-a46e-23e915328582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521556934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.521556934
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2524111224
Short name T908
Test name
Test status
Simulation time 357865925 ps
CPU time 4.2 seconds
Started Jul 11 05:36:29 PM PDT 24
Finished Jul 11 05:36:38 PM PDT 24
Peak memory 215300 kb
Host smart-f043047e-727d-454f-a014-21e4508d0750
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2524111224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2524111224
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3527185646
Short name T634
Test name
Test status
Simulation time 680234455 ps
CPU time 3.93 seconds
Started Jul 11 05:36:05 PM PDT 24
Finished Jul 11 05:36:12 PM PDT 24
Peak memory 222492 kb
Host smart-cecae0b8-5e19-40e3-a530-ab8ffc2d952c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527185646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3527185646
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1384193130
Short name T604
Test name
Test status
Simulation time 59518259 ps
CPU time 1.92 seconds
Started Jul 11 05:36:03 PM PDT 24
Finished Jul 11 05:36:08 PM PDT 24
Peak memory 214268 kb
Host smart-de0713cb-70ce-4b26-b113-68ede6b2cc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384193130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1384193130
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.483876624
Short name T534
Test name
Test status
Simulation time 563825213 ps
CPU time 3.2 seconds
Started Jul 11 05:36:09 PM PDT 24
Finished Jul 11 05:36:14 PM PDT 24
Peak memory 210192 kb
Host smart-58eaa97b-0d29-4e74-b971-b0d29eed1483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483876624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.483876624
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2053436584
Short name T209
Test name
Test status
Simulation time 867436397 ps
CPU time 3.56 seconds
Started Jul 11 05:36:15 PM PDT 24
Finished Jul 11 05:36:20 PM PDT 24
Peak memory 209200 kb
Host smart-18aa3324-cbbf-4d56-b54d-fbfef7d27350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053436584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2053436584
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2688358205
Short name T580
Test name
Test status
Simulation time 123668056 ps
CPU time 2.61 seconds
Started Jul 11 05:36:06 PM PDT 24
Finished Jul 11 05:36:12 PM PDT 24
Peak memory 206836 kb
Host smart-1115233c-e9f8-43bb-8ff1-389a5d4f2fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688358205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2688358205
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.835101617
Short name T19
Test name
Test status
Simulation time 37918143 ps
CPU time 2.24 seconds
Started Jul 11 05:36:17 PM PDT 24
Finished Jul 11 05:36:23 PM PDT 24
Peak memory 206968 kb
Host smart-4f3515ed-b2f6-45b7-b30a-465e60b8904e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835101617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.835101617
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.4247996970
Short name T494
Test name
Test status
Simulation time 780099497 ps
CPU time 14.28 seconds
Started Jul 11 05:36:17 PM PDT 24
Finished Jul 11 05:36:35 PM PDT 24
Peak memory 207896 kb
Host smart-87b1bbb6-06fa-4bea-8c55-dbf1c9ac2b18
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247996970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4247996970
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3622520869
Short name T500
Test name
Test status
Simulation time 81963317 ps
CPU time 1.76 seconds
Started Jul 11 05:36:06 PM PDT 24
Finished Jul 11 05:36:11 PM PDT 24
Peak memory 206956 kb
Host smart-18c09e06-05f3-46e0-bb5a-e0b2b58ee4e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622520869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3622520869
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3488469054
Short name T711
Test name
Test status
Simulation time 137951235 ps
CPU time 2.36 seconds
Started Jul 11 05:36:16 PM PDT 24
Finished Jul 11 05:36:21 PM PDT 24
Peak memory 215584 kb
Host smart-31c02c6e-432f-42e3-af92-1d69eb9ac893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488469054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3488469054
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1965174466
Short name T17
Test name
Test status
Simulation time 246055761 ps
CPU time 3.07 seconds
Started Jul 11 05:36:03 PM PDT 24
Finished Jul 11 05:36:10 PM PDT 24
Peak memory 207504 kb
Host smart-b8b288ed-3e5c-4833-9a71-d1510d0edcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965174466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1965174466
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1502303004
Short name T325
Test name
Test status
Simulation time 839409585 ps
CPU time 31.82 seconds
Started Jul 11 05:36:21 PM PDT 24
Finished Jul 11 05:36:56 PM PDT 24
Peak memory 215980 kb
Host smart-ca5bc306-e39f-4243-849e-5c51abd51952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502303004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1502303004
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2873987466
Short name T183
Test name
Test status
Simulation time 400115394 ps
CPU time 14.82 seconds
Started Jul 11 05:36:16 PM PDT 24
Finished Jul 11 05:36:34 PM PDT 24
Peak memory 222628 kb
Host smart-9943d544-786b-489a-8892-a230b309caec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873987466 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2873987466
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.318924701
Short name T618
Test name
Test status
Simulation time 149006509 ps
CPU time 3.65 seconds
Started Jul 11 05:36:29 PM PDT 24
Finished Jul 11 05:36:37 PM PDT 24
Peak memory 207464 kb
Host smart-6742bdf3-ffd5-445a-b731-27ed8a7a1976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318924701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.318924701
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1446991566
Short name T826
Test name
Test status
Simulation time 885214238 ps
CPU time 2.18 seconds
Started Jul 11 05:36:16 PM PDT 24
Finished Jul 11 05:36:21 PM PDT 24
Peak memory 210540 kb
Host smart-59b31cf2-bf70-492e-95a7-c5cec352bca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446991566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1446991566
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1568324572
Short name T535
Test name
Test status
Simulation time 59447089 ps
CPU time 0.88 seconds
Started Jul 11 05:36:16 PM PDT 24
Finished Jul 11 05:36:20 PM PDT 24
Peak memory 205988 kb
Host smart-44d99715-12cd-43f1-9776-e8642517c2de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568324572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1568324572
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3498973419
Short name T326
Test name
Test status
Simulation time 378547726 ps
CPU time 3.35 seconds
Started Jul 11 05:36:17 PM PDT 24
Finished Jul 11 05:36:24 PM PDT 24
Peak memory 214396 kb
Host smart-31659a8a-e9c9-49bf-a762-fa941ac82ec3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498973419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3498973419
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3792811194
Short name T894
Test name
Test status
Simulation time 680534569 ps
CPU time 5.85 seconds
Started Jul 11 05:36:15 PM PDT 24
Finished Jul 11 05:36:23 PM PDT 24
Peak memory 222968 kb
Host smart-130d5f51-d6d1-4ad6-8d86-37f8e3d0a772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792811194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3792811194
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.498749883
Short name T561
Test name
Test status
Simulation time 87560918 ps
CPU time 3.45 seconds
Started Jul 11 05:36:17 PM PDT 24
Finished Jul 11 05:36:23 PM PDT 24
Peak memory 214340 kb
Host smart-8ecf1af8-523a-4687-8658-afe785f6c1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498749883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.498749883
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3855355622
Short name T386
Test name
Test status
Simulation time 247907999 ps
CPU time 8.09 seconds
Started Jul 11 05:36:22 PM PDT 24
Finished Jul 11 05:36:33 PM PDT 24
Peak memory 214344 kb
Host smart-79fac724-ca81-4f76-9ac9-0c0eb9cd931f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855355622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3855355622
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2249852509
Short name T918
Test name
Test status
Simulation time 51686448 ps
CPU time 2.77 seconds
Started Jul 11 05:36:07 PM PDT 24
Finished Jul 11 05:36:12 PM PDT 24
Peak memory 214340 kb
Host smart-a80e0001-1538-4c5a-a471-5f6d015e78e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249852509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2249852509
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3320052634
Short name T817
Test name
Test status
Simulation time 997479273 ps
CPU time 7.49 seconds
Started Jul 11 05:36:13 PM PDT 24
Finished Jul 11 05:36:22 PM PDT 24
Peak memory 215496 kb
Host smart-07d9dd31-99af-4c8a-bd87-3a4f91aad2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320052634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3320052634
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3297327964
Short name T89
Test name
Test status
Simulation time 276332555 ps
CPU time 4.46 seconds
Started Jul 11 05:36:17 PM PDT 24
Finished Jul 11 05:36:25 PM PDT 24
Peak memory 209628 kb
Host smart-aa2a39a8-a651-4f7f-b13c-ac477825dbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297327964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3297327964
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3489747681
Short name T484
Test name
Test status
Simulation time 111200715 ps
CPU time 4.36 seconds
Started Jul 11 05:36:29 PM PDT 24
Finished Jul 11 05:36:38 PM PDT 24
Peak memory 206772 kb
Host smart-b12cb939-e802-4b3c-a221-b51100fd8793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489747681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3489747681
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.96758668
Short name T640
Test name
Test status
Simulation time 81682036 ps
CPU time 3.65 seconds
Started Jul 11 05:36:14 PM PDT 24
Finished Jul 11 05:36:20 PM PDT 24
Peak memory 208216 kb
Host smart-9e984d60-4f65-483e-afa0-df02b814317b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96758668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.96758668
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3260262925
Short name T295
Test name
Test status
Simulation time 68011370 ps
CPU time 3.57 seconds
Started Jul 11 05:36:02 PM PDT 24
Finished Jul 11 05:36:09 PM PDT 24
Peak memory 209028 kb
Host smart-618fddd1-36ef-482f-a965-1991abcd438d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260262925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3260262925
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1716074337
Short name T120
Test name
Test status
Simulation time 1618535983 ps
CPU time 9.79 seconds
Started Jul 11 05:36:04 PM PDT 24
Finished Jul 11 05:36:17 PM PDT 24
Peak memory 208208 kb
Host smart-13917e57-0271-4cd0-abc6-55c1db9aa62d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716074337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1716074337
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2719960737
Short name T760
Test name
Test status
Simulation time 120176392 ps
CPU time 1.92 seconds
Started Jul 11 05:36:13 PM PDT 24
Finished Jul 11 05:36:17 PM PDT 24
Peak memory 209628 kb
Host smart-9a61b38b-6067-4759-9e0e-e99d8ff9e969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719960737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2719960737
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1657059031
Short name T88
Test name
Test status
Simulation time 416208860 ps
CPU time 4.47 seconds
Started Jul 11 05:36:15 PM PDT 24
Finished Jul 11 05:36:23 PM PDT 24
Peak memory 206852 kb
Host smart-26a88eb0-86b7-4976-a531-74ebb06b8178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657059031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1657059031
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2264894303
Short name T231
Test name
Test status
Simulation time 4919236803 ps
CPU time 44.1 seconds
Started Jul 11 05:36:12 PM PDT 24
Finished Jul 11 05:36:57 PM PDT 24
Peak memory 215952 kb
Host smart-1afbfe41-4d5e-4910-8da4-4d8674ea6469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264894303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2264894303
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3274278777
Short name T825
Test name
Test status
Simulation time 286287452 ps
CPU time 4.5 seconds
Started Jul 11 05:36:05 PM PDT 24
Finished Jul 11 05:36:12 PM PDT 24
Peak memory 214496 kb
Host smart-de5015b3-717c-471e-86e9-744429fdab06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274278777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3274278777
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.4069492362
Short name T881
Test name
Test status
Simulation time 328496597 ps
CPU time 2.6 seconds
Started Jul 11 05:36:05 PM PDT 24
Finished Jul 11 05:36:11 PM PDT 24
Peak memory 210424 kb
Host smart-f57fb6bf-fdf5-41da-beb6-c221555d9de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069492362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.4069492362
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.4214600402
Short name T687
Test name
Test status
Simulation time 13865375 ps
CPU time 0.86 seconds
Started Jul 11 05:36:21 PM PDT 24
Finished Jul 11 05:36:25 PM PDT 24
Peak memory 206012 kb
Host smart-1b5fbd8c-4bc0-4c24-9506-f9f11ae20f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214600402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.4214600402
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2413045766
Short name T333
Test name
Test status
Simulation time 53954356 ps
CPU time 3.58 seconds
Started Jul 11 05:36:20 PM PDT 24
Finished Jul 11 05:36:27 PM PDT 24
Peak memory 215028 kb
Host smart-9ac5222e-8ab5-4a36-8da1-fe04ce6b20c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413045766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2413045766
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.4001899606
Short name T610
Test name
Test status
Simulation time 491372107 ps
CPU time 7.89 seconds
Started Jul 11 05:36:16 PM PDT 24
Finished Jul 11 05:36:27 PM PDT 24
Peak memory 208056 kb
Host smart-155b6a5e-c54e-4199-b4fa-cac1c2f2af4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001899606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.4001899606
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1590289780
Short name T595
Test name
Test status
Simulation time 120966678 ps
CPU time 3.34 seconds
Started Jul 11 05:36:04 PM PDT 24
Finished Jul 11 05:36:10 PM PDT 24
Peak memory 209860 kb
Host smart-bd29192a-9420-4a31-9154-04d7ec188932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590289780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1590289780
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3995716723
Short name T750
Test name
Test status
Simulation time 207030328 ps
CPU time 3.56 seconds
Started Jul 11 05:36:16 PM PDT 24
Finished Jul 11 05:36:23 PM PDT 24
Peak memory 206948 kb
Host smart-0d773e7c-c4ea-415f-8582-474edfdaf8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995716723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3995716723
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.504140372
Short name T870
Test name
Test status
Simulation time 203836916 ps
CPU time 5.73 seconds
Started Jul 11 05:36:06 PM PDT 24
Finished Jul 11 05:36:14 PM PDT 24
Peak memory 206884 kb
Host smart-47378927-0127-467f-8331-23644e603e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504140372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.504140372
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.506560811
Short name T804
Test name
Test status
Simulation time 494554958 ps
CPU time 15.45 seconds
Started Jul 11 05:36:12 PM PDT 24
Finished Jul 11 05:36:29 PM PDT 24
Peak memory 208352 kb
Host smart-d93eeb4f-c186-4599-ac41-4b15f8f87094
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506560811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.506560811
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3560275136
Short name T566
Test name
Test status
Simulation time 103679379 ps
CPU time 2.94 seconds
Started Jul 11 05:36:22 PM PDT 24
Finished Jul 11 05:36:28 PM PDT 24
Peak memory 207020 kb
Host smart-2ae56054-96b5-4e5b-a449-2ef37c084b67
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560275136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3560275136
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1003982103
Short name T782
Test name
Test status
Simulation time 368202678 ps
CPU time 5.76 seconds
Started Jul 11 05:36:02 PM PDT 24
Finished Jul 11 05:36:11 PM PDT 24
Peak memory 209108 kb
Host smart-37717ae0-0d2f-42d0-9466-56d9e0902f59
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003982103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1003982103
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3912674683
Short name T218
Test name
Test status
Simulation time 34086818 ps
CPU time 2.38 seconds
Started Jul 11 05:36:29 PM PDT 24
Finished Jul 11 05:36:36 PM PDT 24
Peak memory 214236 kb
Host smart-4133e934-8dd2-49bc-890e-856c7aa45880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912674683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3912674683
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.485755627
Short name T487
Test name
Test status
Simulation time 595931460 ps
CPU time 2.48 seconds
Started Jul 11 05:36:29 PM PDT 24
Finished Jul 11 05:36:36 PM PDT 24
Peak memory 206796 kb
Host smart-5715e0ae-dcb2-4739-842e-e18185e1b411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485755627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.485755627
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2801201758
Short name T230
Test name
Test status
Simulation time 10648237793 ps
CPU time 171.28 seconds
Started Jul 11 05:36:16 PM PDT 24
Finished Jul 11 05:39:10 PM PDT 24
Peak memory 216664 kb
Host smart-b1899c7c-9631-46c9-8068-470dac43a7f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801201758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2801201758
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.539442355
Short name T310
Test name
Test status
Simulation time 1213749228 ps
CPU time 6.57 seconds
Started Jul 11 05:36:13 PM PDT 24
Finished Jul 11 05:36:21 PM PDT 24
Peak memory 218212 kb
Host smart-a65dcc39-5dd7-413a-8d9f-f04eb370a9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539442355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.539442355
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1432248847
Short name T660
Test name
Test status
Simulation time 396070230 ps
CPU time 10.54 seconds
Started Jul 11 05:36:07 PM PDT 24
Finished Jul 11 05:36:19 PM PDT 24
Peak memory 210776 kb
Host smart-e7feba4b-a51c-43fa-80e8-6e2d0893ebf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432248847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1432248847
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2825925922
Short name T204
Test name
Test status
Simulation time 58308194 ps
CPU time 0.83 seconds
Started Jul 11 05:36:11 PM PDT 24
Finished Jul 11 05:36:13 PM PDT 24
Peak memory 206008 kb
Host smart-d058f426-ab78-43cd-a3b6-ba7455c79d62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825925922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2825925922
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3251847563
Short name T36
Test name
Test status
Simulation time 136516678 ps
CPU time 2.26 seconds
Started Jul 11 05:36:19 PM PDT 24
Finished Jul 11 05:36:24 PM PDT 24
Peak memory 208848 kb
Host smart-200825eb-8c01-447a-8304-22c73c568d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251847563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3251847563
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.254071454
Short name T829
Test name
Test status
Simulation time 342531377 ps
CPU time 4.28 seconds
Started Jul 11 05:36:11 PM PDT 24
Finished Jul 11 05:36:16 PM PDT 24
Peak memory 209144 kb
Host smart-70904f07-e9c2-4037-8f68-4be39dd15362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254071454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.254071454
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2797354141
Short name T94
Test name
Test status
Simulation time 104349504 ps
CPU time 5.31 seconds
Started Jul 11 05:36:08 PM PDT 24
Finished Jul 11 05:36:15 PM PDT 24
Peak memory 209220 kb
Host smart-e14d17a9-105d-4b0c-908a-088080c27d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797354141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2797354141
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.602745564
Short name T321
Test name
Test status
Simulation time 345227520 ps
CPU time 4.1 seconds
Started Jul 11 05:36:18 PM PDT 24
Finished Jul 11 05:36:25 PM PDT 24
Peak memory 220728 kb
Host smart-900f4ca6-8c45-454f-ac28-94e6935292fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602745564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.602745564
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.4106191616
Short name T792
Test name
Test status
Simulation time 317787515 ps
CPU time 3.06 seconds
Started Jul 11 05:36:31 PM PDT 24
Finished Jul 11 05:36:39 PM PDT 24
Peak memory 209256 kb
Host smart-263cf150-4657-4def-beab-b3638fb0b373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106191616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.4106191616
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1435011822
Short name T250
Test name
Test status
Simulation time 409808630 ps
CPU time 4.51 seconds
Started Jul 11 05:36:32 PM PDT 24
Finished Jul 11 05:36:41 PM PDT 24
Peak memory 206816 kb
Host smart-acf4d27a-7b99-4d2d-97b5-432d7ad495f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435011822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1435011822
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.4134126580
Short name T572
Test name
Test status
Simulation time 42096350 ps
CPU time 2.33 seconds
Started Jul 11 05:36:17 PM PDT 24
Finished Jul 11 05:36:23 PM PDT 24
Peak memory 206932 kb
Host smart-c348eab4-4ae1-4f71-885f-4faadf5cd2d3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134126580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.4134126580
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3580618653
Short name T399
Test name
Test status
Simulation time 66273793 ps
CPU time 3.31 seconds
Started Jul 11 05:36:14 PM PDT 24
Finished Jul 11 05:36:19 PM PDT 24
Peak memory 206868 kb
Host smart-75822e34-3fb1-407c-ab5c-899957257d9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580618653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3580618653
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2500429023
Short name T511
Test name
Test status
Simulation time 1535891533 ps
CPU time 15.54 seconds
Started Jul 11 05:36:24 PM PDT 24
Finished Jul 11 05:36:42 PM PDT 24
Peak memory 208700 kb
Host smart-1d8302e4-d499-4702-aa97-11786efa5c31
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500429023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2500429023
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3457651774
Short name T721
Test name
Test status
Simulation time 112770187 ps
CPU time 2.8 seconds
Started Jul 11 05:36:15 PM PDT 24
Finished Jul 11 05:36:20 PM PDT 24
Peak memory 208772 kb
Host smart-a43ba9d2-029d-4f67-8e38-c351e78e8320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457651774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3457651774
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2538940761
Short name T893
Test name
Test status
Simulation time 180537788 ps
CPU time 4.72 seconds
Started Jul 11 05:36:23 PM PDT 24
Finished Jul 11 05:36:31 PM PDT 24
Peak memory 208356 kb
Host smart-048648d0-9a98-484c-8b27-0ec290c34347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538940761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2538940761
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2472945984
Short name T648
Test name
Test status
Simulation time 1320322200 ps
CPU time 22.15 seconds
Started Jul 11 05:36:12 PM PDT 24
Finished Jul 11 05:36:35 PM PDT 24
Peak memory 222528 kb
Host smart-ac578766-cf04-4a50-abea-c34657b8ab25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472945984 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2472945984
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.961695541
Short name T122
Test name
Test status
Simulation time 378035927 ps
CPU time 4.94 seconds
Started Jul 11 05:36:19 PM PDT 24
Finished Jul 11 05:36:27 PM PDT 24
Peak memory 218392 kb
Host smart-69e76a0b-cae9-4805-84d6-4b4cbb764173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961695541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.961695541
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2471302890
Short name T701
Test name
Test status
Simulation time 89396773 ps
CPU time 2.78 seconds
Started Jul 11 05:36:13 PM PDT 24
Finished Jul 11 05:36:18 PM PDT 24
Peak memory 210256 kb
Host smart-b67d718f-1293-48b4-a900-c047f158c025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471302890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2471302890
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3483420110
Short name T722
Test name
Test status
Simulation time 10592234 ps
CPU time 0.95 seconds
Started Jul 11 05:36:14 PM PDT 24
Finished Jul 11 05:36:17 PM PDT 24
Peak memory 205900 kb
Host smart-f9c8a65c-b850-4530-affe-9c473af187e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483420110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3483420110
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.4137893922
Short name T264
Test name
Test status
Simulation time 95230536 ps
CPU time 5.72 seconds
Started Jul 11 05:36:31 PM PDT 24
Finished Jul 11 05:36:42 PM PDT 24
Peak memory 222496 kb
Host smart-d748ef7a-7529-4cd6-bd53-922d7e9ecdb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4137893922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.4137893922
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.510322994
Short name T695
Test name
Test status
Simulation time 129461477 ps
CPU time 3.17 seconds
Started Jul 11 05:36:10 PM PDT 24
Finished Jul 11 05:36:14 PM PDT 24
Peak memory 219452 kb
Host smart-d68039b3-39f3-4853-8aac-81a0e748af73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510322994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.510322994
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2635408171
Short name T16
Test name
Test status
Simulation time 71773410 ps
CPU time 2.4 seconds
Started Jul 11 05:36:24 PM PDT 24
Finished Jul 11 05:36:29 PM PDT 24
Peak memory 209152 kb
Host smart-4f676777-707c-47d2-9358-31e3298b3b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635408171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2635408171
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1288765106
Short name T317
Test name
Test status
Simulation time 357717523 ps
CPU time 4.25 seconds
Started Jul 11 05:36:24 PM PDT 24
Finished Jul 11 05:36:31 PM PDT 24
Peak memory 221280 kb
Host smart-e7c8e80b-c8b2-452d-9708-1087916840e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288765106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1288765106
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2124519036
Short name T482
Test name
Test status
Simulation time 25545084 ps
CPU time 1.43 seconds
Started Jul 11 05:36:17 PM PDT 24
Finished Jul 11 05:36:22 PM PDT 24
Peak memory 206184 kb
Host smart-942339bd-6e45-4a8f-8d83-14e287747f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124519036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2124519036
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3453995341
Short name T767
Test name
Test status
Simulation time 319832809 ps
CPU time 8.26 seconds
Started Jul 11 05:36:18 PM PDT 24
Finished Jul 11 05:36:30 PM PDT 24
Peak memory 209772 kb
Host smart-f120f7c6-3595-4a36-a9d6-64f6b3863ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453995341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3453995341
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3716303286
Short name T570
Test name
Test status
Simulation time 1611064242 ps
CPU time 11.44 seconds
Started Jul 11 05:36:19 PM PDT 24
Finished Jul 11 05:36:33 PM PDT 24
Peak memory 208028 kb
Host smart-d32d50c8-afbd-4281-9072-05f62fe4d7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716303286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3716303286
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.955719462
Short name T605
Test name
Test status
Simulation time 276669268 ps
CPU time 3.14 seconds
Started Jul 11 05:36:24 PM PDT 24
Finished Jul 11 05:36:30 PM PDT 24
Peak memory 206892 kb
Host smart-fb8d443d-4e71-4535-8064-e386c9b9ae2d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955719462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.955719462
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2064156527
Short name T593
Test name
Test status
Simulation time 456482445 ps
CPU time 4.2 seconds
Started Jul 11 05:36:31 PM PDT 24
Finished Jul 11 05:36:40 PM PDT 24
Peak memory 208632 kb
Host smart-3d4a67ea-c3d8-457b-b66f-5d3079f0cae7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064156527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2064156527
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1698844850
Short name T536
Test name
Test status
Simulation time 71631143 ps
CPU time 2.07 seconds
Started Jul 11 05:36:29 PM PDT 24
Finished Jul 11 05:36:35 PM PDT 24
Peak memory 208684 kb
Host smart-a6b250b1-4143-4b2f-be03-5ea03720e797
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698844850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1698844850
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.563890252
Short name T371
Test name
Test status
Simulation time 208637214 ps
CPU time 4.55 seconds
Started Jul 11 05:36:25 PM PDT 24
Finished Jul 11 05:36:33 PM PDT 24
Peak memory 210304 kb
Host smart-55691f84-6bea-44c9-a729-5bd3aa7f2135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563890252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.563890252
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3871092549
Short name T624
Test name
Test status
Simulation time 171437070 ps
CPU time 2.28 seconds
Started Jul 11 05:36:12 PM PDT 24
Finished Jul 11 05:36:16 PM PDT 24
Peak memory 208456 kb
Host smart-f8a52558-963d-4d47-ad93-323397c597cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871092549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3871092549
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3708334136
Short name T346
Test name
Test status
Simulation time 1157571826 ps
CPU time 29.21 seconds
Started Jul 11 05:36:25 PM PDT 24
Finished Jul 11 05:36:58 PM PDT 24
Peak memory 215032 kb
Host smart-6392e0e2-df63-486a-b239-b3a4e855f4ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708334136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3708334136
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3749184233
Short name T187
Test name
Test status
Simulation time 484095999 ps
CPU time 17.57 seconds
Started Jul 11 05:36:11 PM PDT 24
Finished Jul 11 05:36:29 PM PDT 24
Peak memory 222632 kb
Host smart-3e4a2c2b-aa8b-4da4-809a-023d193e557a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749184233 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3749184233
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.92166416
Short name T786
Test name
Test status
Simulation time 526837524 ps
CPU time 6.71 seconds
Started Jul 11 05:36:08 PM PDT 24
Finished Jul 11 05:36:17 PM PDT 24
Peak memory 218412 kb
Host smart-af3d62af-73f3-4066-8465-8177cc210e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92166416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.92166416
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2652712836
Short name T552
Test name
Test status
Simulation time 104251388 ps
CPU time 3.85 seconds
Started Jul 11 05:36:13 PM PDT 24
Finished Jul 11 05:36:18 PM PDT 24
Peak memory 210340 kb
Host smart-bc386557-c93b-4398-ac5f-123d90a669a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652712836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2652712836
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.4142515697
Short name T433
Test name
Test status
Simulation time 15805213 ps
CPU time 0.8 seconds
Started Jul 11 05:36:21 PM PDT 24
Finished Jul 11 05:36:25 PM PDT 24
Peak memory 205976 kb
Host smart-4ba76caa-9cd8-4b55-b430-a33b4dcaf8fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142515697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.4142515697
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.852374553
Short name T73
Test name
Test status
Simulation time 715738202 ps
CPU time 16.5 seconds
Started Jul 11 05:36:18 PM PDT 24
Finished Jul 11 05:36:38 PM PDT 24
Peak memory 209888 kb
Host smart-789648a8-b0b6-4d16-b7c9-b1eff96d745f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852374553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.852374553
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.103550262
Short name T904
Test name
Test status
Simulation time 71891038 ps
CPU time 2.08 seconds
Started Jul 11 05:36:16 PM PDT 24
Finished Jul 11 05:36:22 PM PDT 24
Peak memory 209248 kb
Host smart-94c9b08b-c1b9-4595-8776-3d3406ebd0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103550262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.103550262
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3545898553
Short name T547
Test name
Test status
Simulation time 72031027 ps
CPU time 2.68 seconds
Started Jul 11 05:36:27 PM PDT 24
Finished Jul 11 05:36:32 PM PDT 24
Peak memory 221540 kb
Host smart-fcf70c97-9cf6-4267-a19e-d772e571172f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545898553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3545898553
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.161061498
Short name T292
Test name
Test status
Simulation time 301295110 ps
CPU time 4.5 seconds
Started Jul 11 05:36:22 PM PDT 24
Finished Jul 11 05:36:29 PM PDT 24
Peak memory 222448 kb
Host smart-80c75237-a4a8-4963-890a-2e065032450e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161061498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.161061498
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.4055171843
Short name T859
Test name
Test status
Simulation time 142505427 ps
CPU time 4.53 seconds
Started Jul 11 05:36:18 PM PDT 24
Finished Jul 11 05:36:26 PM PDT 24
Peak memory 210024 kb
Host smart-d874e61b-0a31-435b-9677-3812e0858eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055171843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.4055171843
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3317149556
Short name T692
Test name
Test status
Simulation time 318525392 ps
CPU time 4.88 seconds
Started Jul 11 05:36:38 PM PDT 24
Finished Jul 11 05:36:45 PM PDT 24
Peak memory 214324 kb
Host smart-3f8020a8-3746-4727-b17f-6ec4dc590683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317149556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3317149556
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2793866874
Short name T637
Test name
Test status
Simulation time 38294163 ps
CPU time 2.61 seconds
Started Jul 11 05:36:16 PM PDT 24
Finished Jul 11 05:36:22 PM PDT 24
Peak memory 208640 kb
Host smart-3dd64f83-8ab4-4fa1-a0a4-fd900e167335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793866874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2793866874
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1490122392
Short name T704
Test name
Test status
Simulation time 100834993 ps
CPU time 2.82 seconds
Started Jul 11 05:36:25 PM PDT 24
Finished Jul 11 05:36:30 PM PDT 24
Peak memory 206972 kb
Host smart-e5249996-29b6-493c-9c17-041a13f4790c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490122392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1490122392
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1374432892
Short name T885
Test name
Test status
Simulation time 93026002 ps
CPU time 1.99 seconds
Started Jul 11 05:36:22 PM PDT 24
Finished Jul 11 05:36:27 PM PDT 24
Peak memory 208772 kb
Host smart-910352f5-a168-40d7-b758-e583041be3d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374432892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1374432892
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1650660887
Short name T849
Test name
Test status
Simulation time 39794804 ps
CPU time 2.48 seconds
Started Jul 11 05:36:19 PM PDT 24
Finished Jul 11 05:36:25 PM PDT 24
Peak memory 207388 kb
Host smart-d4afad8a-a153-44c4-8c50-ff52e736d253
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650660887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1650660887
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1951748769
Short name T426
Test name
Test status
Simulation time 64002259 ps
CPU time 2.12 seconds
Started Jul 11 05:36:39 PM PDT 24
Finished Jul 11 05:36:43 PM PDT 24
Peak memory 208132 kb
Host smart-4750565a-7470-4c39-b274-7d21436cc0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951748769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1951748769
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1253430403
Short name T503
Test name
Test status
Simulation time 152137848 ps
CPU time 3.81 seconds
Started Jul 11 05:36:16 PM PDT 24
Finished Jul 11 05:36:22 PM PDT 24
Peak memory 206828 kb
Host smart-b2dac7a8-936d-427f-b60e-0ffc9f66d679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253430403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1253430403
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2368854922
Short name T848
Test name
Test status
Simulation time 1822496266 ps
CPU time 32.33 seconds
Started Jul 11 05:36:28 PM PDT 24
Finished Jul 11 05:37:03 PM PDT 24
Peak memory 222500 kb
Host smart-6b7c2436-185c-42c7-bf72-9f8156bc10e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368854922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2368854922
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2643485229
Short name T355
Test name
Test status
Simulation time 465796183 ps
CPU time 7.83 seconds
Started Jul 11 05:36:27 PM PDT 24
Finished Jul 11 05:36:37 PM PDT 24
Peak memory 222648 kb
Host smart-8e5dfcc4-0331-453e-a1df-54050f72bbd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643485229 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2643485229
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.819857543
Short name T742
Test name
Test status
Simulation time 161686473 ps
CPU time 4.75 seconds
Started Jul 11 05:36:22 PM PDT 24
Finished Jul 11 05:36:30 PM PDT 24
Peak memory 207636 kb
Host smart-8d27b58d-7c6c-48e8-a977-67130057ff77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819857543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.819857543
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1184163665
Short name T395
Test name
Test status
Simulation time 205493884 ps
CPU time 2.23 seconds
Started Jul 11 05:36:18 PM PDT 24
Finished Jul 11 05:36:23 PM PDT 24
Peak memory 210028 kb
Host smart-ac402a96-ae62-4cb1-af28-7b5e5850c8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184163665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1184163665
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.810603762
Short name T617
Test name
Test status
Simulation time 9246310 ps
CPU time 0.72 seconds
Started Jul 11 05:36:20 PM PDT 24
Finished Jul 11 05:36:24 PM PDT 24
Peak memory 205892 kb
Host smart-e9704e8d-c1e0-42f0-8b4f-8ca1ba3838ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810603762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.810603762
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.433176158
Short name T42
Test name
Test status
Simulation time 141564200 ps
CPU time 3.41 seconds
Started Jul 11 05:36:30 PM PDT 24
Finished Jul 11 05:36:38 PM PDT 24
Peak memory 219604 kb
Host smart-1475ff13-bba1-48a5-baae-74f8a61f23a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433176158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.433176158
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3951326362
Short name T370
Test name
Test status
Simulation time 20516707 ps
CPU time 1.7 seconds
Started Jul 11 05:36:19 PM PDT 24
Finished Jul 11 05:36:24 PM PDT 24
Peak memory 207932 kb
Host smart-e545dae3-6a2d-4af6-a2a6-a2e3bb8aa354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951326362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3951326362
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1762904573
Short name T48
Test name
Test status
Simulation time 165225337 ps
CPU time 2.05 seconds
Started Jul 11 05:36:21 PM PDT 24
Finished Jul 11 05:36:26 PM PDT 24
Peak memory 214340 kb
Host smart-eef0b98c-219c-43af-955f-98a2ea78199e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762904573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1762904573
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2067613186
Short name T43
Test name
Test status
Simulation time 109625883 ps
CPU time 5.09 seconds
Started Jul 11 05:36:30 PM PDT 24
Finished Jul 11 05:36:39 PM PDT 24
Peak memory 222412 kb
Host smart-bf68a056-81a1-4ef6-8122-e36797e30ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067613186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2067613186
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.962747028
Short name T600
Test name
Test status
Simulation time 95839776 ps
CPU time 4.14 seconds
Started Jul 11 05:36:39 PM PDT 24
Finished Jul 11 05:36:45 PM PDT 24
Peak memory 214336 kb
Host smart-f567f937-9b61-4885-880a-b3b51126d0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962747028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.962747028
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3706391886
Short name T902
Test name
Test status
Simulation time 124878853 ps
CPU time 5.73 seconds
Started Jul 11 05:36:26 PM PDT 24
Finished Jul 11 05:36:34 PM PDT 24
Peak memory 218348 kb
Host smart-7357b3e9-380a-4e75-ae87-56fafd4ce80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706391886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3706391886
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3659323809
Short name T459
Test name
Test status
Simulation time 106220923 ps
CPU time 2.74 seconds
Started Jul 11 05:36:29 PM PDT 24
Finished Jul 11 05:36:36 PM PDT 24
Peak memory 206876 kb
Host smart-dff01834-f7a1-4169-8fa1-2b23426f2880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659323809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3659323809
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3482898683
Short name T832
Test name
Test status
Simulation time 144034655 ps
CPU time 4.31 seconds
Started Jul 11 05:36:15 PM PDT 24
Finished Jul 11 05:36:21 PM PDT 24
Peak memory 208532 kb
Host smart-6b2730c7-0680-4cfc-917f-b7f67b5aaa31
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482898683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3482898683
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.923863137
Short name T263
Test name
Test status
Simulation time 70755112 ps
CPU time 3.14 seconds
Started Jul 11 05:36:21 PM PDT 24
Finished Jul 11 05:36:27 PM PDT 24
Peak memory 208436 kb
Host smart-6f219a57-4352-4518-948a-42592f1d14a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923863137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.923863137
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2574680795
Short name T207
Test name
Test status
Simulation time 378255495 ps
CPU time 3.03 seconds
Started Jul 11 05:36:26 PM PDT 24
Finished Jul 11 05:36:32 PM PDT 24
Peak memory 209024 kb
Host smart-bd757945-f466-4773-8420-1e1484c18b45
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574680795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2574680795
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.474194365
Short name T506
Test name
Test status
Simulation time 176652459 ps
CPU time 2.43 seconds
Started Jul 11 05:36:23 PM PDT 24
Finished Jul 11 05:36:29 PM PDT 24
Peak memory 209608 kb
Host smart-6ee54e75-6e1a-43e8-ac74-d4bb479a0689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474194365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.474194365
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.4246990223
Short name T835
Test name
Test status
Simulation time 635780040 ps
CPU time 3.29 seconds
Started Jul 11 05:36:19 PM PDT 24
Finished Jul 11 05:36:25 PM PDT 24
Peak memory 208800 kb
Host smart-6eb4736d-f4d7-4664-928a-63a14b9734b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246990223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.4246990223
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3054240633
Short name T100
Test name
Test status
Simulation time 267819399 ps
CPU time 9.89 seconds
Started Jul 11 05:36:25 PM PDT 24
Finished Jul 11 05:36:38 PM PDT 24
Peak memory 219660 kb
Host smart-fafb153d-978d-4d55-adcb-b9c835819ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054240633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3054240633
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1780588953
Short name T72
Test name
Test status
Simulation time 2431707623 ps
CPU time 7.05 seconds
Started Jul 11 05:36:25 PM PDT 24
Finished Jul 11 05:36:35 PM PDT 24
Peak memory 222748 kb
Host smart-ac237257-d8df-4fd9-8904-f3d37f4d7993
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780588953 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1780588953
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1823831808
Short name T516
Test name
Test status
Simulation time 128163409 ps
CPU time 3.4 seconds
Started Jul 11 05:36:24 PM PDT 24
Finished Jul 11 05:36:30 PM PDT 24
Peak memory 208620 kb
Host smart-202b53c4-994d-4cd9-a1e0-e10189e6ecd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823831808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1823831808
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2548068242
Short name T208
Test name
Test status
Simulation time 127629613 ps
CPU time 2.23 seconds
Started Jul 11 05:36:27 PM PDT 24
Finished Jul 11 05:36:32 PM PDT 24
Peak memory 210136 kb
Host smart-5d9ccfb8-ad49-4d65-ba10-f1d68d609d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548068242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2548068242
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2510544967
Short name T448
Test name
Test status
Simulation time 53218654 ps
CPU time 0.88 seconds
Started Jul 11 05:33:40 PM PDT 24
Finished Jul 11 05:33:43 PM PDT 24
Peak memory 205996 kb
Host smart-51d4247a-3b22-4584-b11b-06608b951b8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510544967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2510544967
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2582057448
Short name T396
Test name
Test status
Simulation time 919452828 ps
CPU time 12.04 seconds
Started Jul 11 05:33:36 PM PDT 24
Finished Jul 11 05:33:51 PM PDT 24
Peak memory 214844 kb
Host smart-7da3d876-e78a-43a1-b5c4-1d6785a7935b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2582057448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2582057448
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3031878520
Short name T25
Test name
Test status
Simulation time 462956872 ps
CPU time 3.32 seconds
Started Jul 11 05:33:32 PM PDT 24
Finished Jul 11 05:33:38 PM PDT 24
Peak memory 214604 kb
Host smart-9f86cfcd-29e0-46c4-8d25-4c03946f7996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031878520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3031878520
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2201576457
Short name T290
Test name
Test status
Simulation time 85725194 ps
CPU time 3.88 seconds
Started Jul 11 05:33:37 PM PDT 24
Finished Jul 11 05:33:44 PM PDT 24
Peak memory 218404 kb
Host smart-27ef51ba-a249-498b-af0f-b3a47358db6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201576457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2201576457
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3940777481
Short name T632
Test name
Test status
Simulation time 70179899 ps
CPU time 3.77 seconds
Started Jul 11 05:33:34 PM PDT 24
Finished Jul 11 05:33:40 PM PDT 24
Peak memory 214340 kb
Host smart-98248dc3-979a-4fb7-9be9-1ef82c9447ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940777481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3940777481
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1832911171
Short name T381
Test name
Test status
Simulation time 364281753 ps
CPU time 5.59 seconds
Started Jul 11 05:33:35 PM PDT 24
Finished Jul 11 05:33:43 PM PDT 24
Peak memory 215384 kb
Host smart-70510ab6-4c32-43ca-84bf-3de674665d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832911171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1832911171
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.133399889
Short name T573
Test name
Test status
Simulation time 129503370 ps
CPU time 3.65 seconds
Started Jul 11 05:33:34 PM PDT 24
Finished Jul 11 05:33:40 PM PDT 24
Peak memory 219568 kb
Host smart-d9bf5eee-cb1c-47ce-ae11-20bde9d67d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133399889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.133399889
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1031869866
Short name T515
Test name
Test status
Simulation time 275348768 ps
CPU time 3.37 seconds
Started Jul 11 05:33:36 PM PDT 24
Finished Jul 11 05:33:43 PM PDT 24
Peak memory 214332 kb
Host smart-0e4d11e4-e507-447b-bd97-94e62893b75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031869866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1031869866
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2621494709
Short name T758
Test name
Test status
Simulation time 122469207 ps
CPU time 3.66 seconds
Started Jul 11 05:33:35 PM PDT 24
Finished Jul 11 05:33:41 PM PDT 24
Peak memory 208140 kb
Host smart-695c777c-b67e-4349-b7f2-5edc264f2259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621494709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2621494709
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2611899152
Short name T316
Test name
Test status
Simulation time 56729760 ps
CPU time 3.04 seconds
Started Jul 11 05:33:33 PM PDT 24
Finished Jul 11 05:33:38 PM PDT 24
Peak memory 206864 kb
Host smart-1b7063e2-43ee-4242-afa0-6930334a881b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611899152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2611899152
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.4281220402
Short name T254
Test name
Test status
Simulation time 12647484904 ps
CPU time 46.9 seconds
Started Jul 11 05:33:37 PM PDT 24
Finished Jul 11 05:34:26 PM PDT 24
Peak memory 209296 kb
Host smart-7e3a4207-89e0-4aef-b352-5459c0934382
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281220402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.4281220402
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2347135581
Short name T808
Test name
Test status
Simulation time 2069286105 ps
CPU time 14.94 seconds
Started Jul 11 05:33:35 PM PDT 24
Finished Jul 11 05:33:53 PM PDT 24
Peak memory 208008 kb
Host smart-a14e2623-cc8f-4fdc-b57d-67d65daa5c3c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347135581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2347135581
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.4132059018
Short name T644
Test name
Test status
Simulation time 619480090 ps
CPU time 2.72 seconds
Started Jul 11 05:33:37 PM PDT 24
Finished Jul 11 05:33:43 PM PDT 24
Peak memory 214224 kb
Host smart-c8c6d74f-c10e-4e10-b826-d4da58977e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132059018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.4132059018
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.639128497
Short name T629
Test name
Test status
Simulation time 1013626556 ps
CPU time 2.98 seconds
Started Jul 11 05:33:34 PM PDT 24
Finished Jul 11 05:33:39 PM PDT 24
Peak memory 206680 kb
Host smart-c56b91ce-631f-490f-b980-be7ad2c9850d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639128497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.639128497
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.320536212
Short name T197
Test name
Test status
Simulation time 1062728380 ps
CPU time 27.12 seconds
Started Jul 11 05:33:49 PM PDT 24
Finished Jul 11 05:34:21 PM PDT 24
Peak memory 220692 kb
Host smart-15a15263-53b3-428e-a571-0e537f386a9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320536212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.320536212
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2459470732
Short name T232
Test name
Test status
Simulation time 229991004 ps
CPU time 7.61 seconds
Started Jul 11 05:33:43 PM PDT 24
Finished Jul 11 05:33:53 PM PDT 24
Peak memory 222600 kb
Host smart-2242313e-1c19-42d3-ba98-709d6ee7a95b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459470732 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2459470732
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3134655097
Short name T334
Test name
Test status
Simulation time 1322009356 ps
CPU time 30.3 seconds
Started Jul 11 05:33:33 PM PDT 24
Finished Jul 11 05:34:06 PM PDT 24
Peak memory 210292 kb
Host smart-7343ef3f-32e0-4f9d-8a50-6ff01fa743d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134655097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3134655097
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1399200625
Short name T700
Test name
Test status
Simulation time 102074956 ps
CPU time 2.04 seconds
Started Jul 11 05:33:47 PM PDT 24
Finished Jul 11 05:33:52 PM PDT 24
Peak memory 209856 kb
Host smart-03e7dd7c-dedf-4594-8d9a-89f8ad80fe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399200625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1399200625
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3197475775
Short name T559
Test name
Test status
Simulation time 9033388 ps
CPU time 0.72 seconds
Started Jul 11 05:33:39 PM PDT 24
Finished Jul 11 05:33:42 PM PDT 24
Peak memory 205892 kb
Host smart-1a8b5a1e-8093-4ab9-9847-c01a8228022a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197475775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3197475775
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.245034415
Short name T872
Test name
Test status
Simulation time 241450912 ps
CPU time 3.18 seconds
Started Jul 11 05:33:41 PM PDT 24
Finished Jul 11 05:33:47 PM PDT 24
Peak memory 216400 kb
Host smart-bb4f3f29-4b3b-4703-a17b-2e569cf3cd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245034415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.245034415
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3112420067
Short name T314
Test name
Test status
Simulation time 563609545 ps
CPU time 3.86 seconds
Started Jul 11 05:33:46 PM PDT 24
Finished Jul 11 05:33:53 PM PDT 24
Peak memory 218048 kb
Host smart-6b22b532-d16a-4ea9-9451-c4c607811cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112420067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3112420067
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2468493725
Short name T345
Test name
Test status
Simulation time 71374297 ps
CPU time 2.5 seconds
Started Jul 11 05:33:39 PM PDT 24
Finished Jul 11 05:33:44 PM PDT 24
Peak memory 206108 kb
Host smart-217536d7-1d07-4a3f-be14-941816d84534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468493725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2468493725
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.4037351197
Short name T824
Test name
Test status
Simulation time 46977415 ps
CPU time 2.39 seconds
Started Jul 11 05:33:42 PM PDT 24
Finished Jul 11 05:33:47 PM PDT 24
Peak memory 214256 kb
Host smart-08a4218d-e355-452c-9ca9-c5741deb7386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037351197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.4037351197
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2669838373
Short name T740
Test name
Test status
Simulation time 37543020 ps
CPU time 1.53 seconds
Started Jul 11 05:33:42 PM PDT 24
Finished Jul 11 05:33:47 PM PDT 24
Peak memory 206148 kb
Host smart-8fe49396-6f5e-4254-854f-a400861bcfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669838373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2669838373
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1875021483
Short name T598
Test name
Test status
Simulation time 88284211 ps
CPU time 1.87 seconds
Started Jul 11 05:33:50 PM PDT 24
Finished Jul 11 05:33:58 PM PDT 24
Peak memory 208620 kb
Host smart-b227f2ae-05c9-44a4-b678-c8be0fafa70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875021483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1875021483
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3809737186
Short name T480
Test name
Test status
Simulation time 448297168 ps
CPU time 3.92 seconds
Started Jul 11 05:33:38 PM PDT 24
Finished Jul 11 05:33:45 PM PDT 24
Peak memory 206692 kb
Host smart-a20ab7ab-b301-4327-b093-db94a1d2514d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809737186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3809737186
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3881857901
Short name T305
Test name
Test status
Simulation time 2676488464 ps
CPU time 13.7 seconds
Started Jul 11 05:33:39 PM PDT 24
Finished Jul 11 05:33:55 PM PDT 24
Peak memory 208344 kb
Host smart-890c4bb1-cfa3-4cc3-911b-9863a55c459f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881857901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3881857901
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3121115491
Short name T753
Test name
Test status
Simulation time 474638033 ps
CPU time 8.49 seconds
Started Jul 11 05:33:39 PM PDT 24
Finished Jul 11 05:33:50 PM PDT 24
Peak memory 206996 kb
Host smart-8e0807ab-586b-456c-881f-f2720f94cd69
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121115491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3121115491
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1757556608
Short name T221
Test name
Test status
Simulation time 16974830 ps
CPU time 1.48 seconds
Started Jul 11 05:33:49 PM PDT 24
Finished Jul 11 05:33:57 PM PDT 24
Peak memory 207060 kb
Host smart-9a4ec6be-f4f2-46c6-bee1-845c1f30b64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757556608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1757556608
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2349343920
Short name T550
Test name
Test status
Simulation time 260513939 ps
CPU time 2.88 seconds
Started Jul 11 05:33:40 PM PDT 24
Finished Jul 11 05:33:45 PM PDT 24
Peak memory 207896 kb
Host smart-ab10abdd-589e-46e5-b93b-30763327751b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349343920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2349343920
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3371327765
Short name T353
Test name
Test status
Simulation time 1116286409 ps
CPU time 12.64 seconds
Started Jul 11 05:33:38 PM PDT 24
Finished Jul 11 05:33:53 PM PDT 24
Peak memory 222568 kb
Host smart-8f38aa93-8866-4680-9898-f5a5e9c2ad04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371327765 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3371327765
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2056755796
Short name T257
Test name
Test status
Simulation time 235788998 ps
CPU time 7.15 seconds
Started Jul 11 05:33:37 PM PDT 24
Finished Jul 11 05:33:47 PM PDT 24
Peak memory 207548 kb
Host smart-09756a8d-7328-456b-ae53-96f08316c4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056755796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2056755796
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4086179354
Short name T702
Test name
Test status
Simulation time 105154596 ps
CPU time 1.52 seconds
Started Jul 11 05:33:47 PM PDT 24
Finished Jul 11 05:33:52 PM PDT 24
Peak memory 209560 kb
Host smart-b91867e1-5b72-4442-a50d-2bbb68239e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086179354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4086179354
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3310868316
Short name T677
Test name
Test status
Simulation time 9955585 ps
CPU time 0.68 seconds
Started Jul 11 05:33:48 PM PDT 24
Finished Jul 11 05:33:53 PM PDT 24
Peak memory 205928 kb
Host smart-903621fc-a2d9-47ee-9ef3-5e77036c78af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310868316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3310868316
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.438442726
Short name T304
Test name
Test status
Simulation time 50668059 ps
CPU time 3.89 seconds
Started Jul 11 05:33:46 PM PDT 24
Finished Jul 11 05:33:53 PM PDT 24
Peak memory 214784 kb
Host smart-ff18151e-aeb2-4c02-9482-bd7e12bc1e3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438442726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.438442726
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.354001242
Short name T779
Test name
Test status
Simulation time 93828402 ps
CPU time 1.45 seconds
Started Jul 11 05:33:46 PM PDT 24
Finished Jul 11 05:33:51 PM PDT 24
Peak memory 209660 kb
Host smart-421480d0-38b9-47a5-a86b-ca5f03e8d5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354001242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.354001242
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.629000505
Short name T568
Test name
Test status
Simulation time 172625139 ps
CPU time 5.63 seconds
Started Jul 11 05:33:48 PM PDT 24
Finished Jul 11 05:33:57 PM PDT 24
Peak memory 209264 kb
Host smart-02c905c2-b119-4ba4-bfc9-b502a1f56c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629000505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.629000505
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1065836365
Short name T713
Test name
Test status
Simulation time 752713980 ps
CPU time 5.36 seconds
Started Jul 11 05:33:42 PM PDT 24
Finished Jul 11 05:33:50 PM PDT 24
Peak memory 209504 kb
Host smart-95eaefff-2d36-449b-afb0-fa2bb2879317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065836365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1065836365
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3161106484
Short name T340
Test name
Test status
Simulation time 114206805 ps
CPU time 1.65 seconds
Started Jul 11 05:33:48 PM PDT 24
Finished Jul 11 05:33:54 PM PDT 24
Peak memory 214304 kb
Host smart-72109192-729e-402d-b5e5-8df4ec660dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161106484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3161106484
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1170189174
Short name T769
Test name
Test status
Simulation time 168023053 ps
CPU time 3.47 seconds
Started Jul 11 05:33:43 PM PDT 24
Finished Jul 11 05:33:49 PM PDT 24
Peak memory 215148 kb
Host smart-e8b23c34-6d7d-4325-9422-ea14b6141027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170189174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1170189174
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2239879354
Short name T354
Test name
Test status
Simulation time 80706568 ps
CPU time 4.06 seconds
Started Jul 11 05:33:43 PM PDT 24
Finished Jul 11 05:33:50 PM PDT 24
Peak memory 207528 kb
Host smart-e2b48acd-1b07-46b5-808d-4e66f03ffd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239879354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2239879354
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2624665396
Short name T847
Test name
Test status
Simulation time 167836604 ps
CPU time 5.22 seconds
Started Jul 11 05:33:40 PM PDT 24
Finished Jul 11 05:33:47 PM PDT 24
Peak memory 208592 kb
Host smart-9710c87e-b448-4a8f-adce-2305483dba2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624665396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2624665396
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2094288526
Short name T810
Test name
Test status
Simulation time 407403748 ps
CPU time 3.32 seconds
Started Jul 11 05:33:41 PM PDT 24
Finished Jul 11 05:33:46 PM PDT 24
Peak memory 206932 kb
Host smart-ad8b365a-456f-4740-b859-3a7ef96169c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094288526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2094288526
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2068317840
Short name T866
Test name
Test status
Simulation time 211404807 ps
CPU time 3.01 seconds
Started Jul 11 05:33:39 PM PDT 24
Finished Jul 11 05:33:44 PM PDT 24
Peak memory 206712 kb
Host smart-cd216079-b293-431b-8dc3-9c0cd107fcd0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068317840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2068317840
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3728262361
Short name T609
Test name
Test status
Simulation time 39694993 ps
CPU time 1.72 seconds
Started Jul 11 05:33:45 PM PDT 24
Finished Jul 11 05:33:50 PM PDT 24
Peak memory 206984 kb
Host smart-e95a83a4-7a71-4a6a-9964-ad05bd4fd981
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728262361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3728262361
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3885543789
Short name T583
Test name
Test status
Simulation time 364261353 ps
CPU time 4.37 seconds
Started Jul 11 05:33:46 PM PDT 24
Finished Jul 11 05:33:54 PM PDT 24
Peak memory 214348 kb
Host smart-02ebd193-5448-4334-a052-31bf5ee8a8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885543789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3885543789
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3248589398
Short name T491
Test name
Test status
Simulation time 69880552 ps
CPU time 2.03 seconds
Started Jul 11 05:33:46 PM PDT 24
Finished Jul 11 05:33:51 PM PDT 24
Peak memory 206792 kb
Host smart-819cd2c9-b1f2-4684-bc2f-2fdd0c4e2cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248589398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3248589398
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1637951013
Short name T620
Test name
Test status
Simulation time 1316240136 ps
CPU time 5.33 seconds
Started Jul 11 05:33:53 PM PDT 24
Finished Jul 11 05:34:07 PM PDT 24
Peak memory 209056 kb
Host smart-3f84ad14-44e3-4322-ae7c-72eede0b12a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637951013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1637951013
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.155091975
Short name T564
Test name
Test status
Simulation time 246634198 ps
CPU time 1.55 seconds
Started Jul 11 05:33:48 PM PDT 24
Finished Jul 11 05:33:53 PM PDT 24
Peak memory 209936 kb
Host smart-98eecbd8-badd-44bb-94ef-d459299af1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155091975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.155091975
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3134212797
Short name T664
Test name
Test status
Simulation time 14117418 ps
CPU time 0.9 seconds
Started Jul 11 05:33:47 PM PDT 24
Finished Jul 11 05:33:51 PM PDT 24
Peak memory 206156 kb
Host smart-a199fc22-ee25-44bd-a9c4-d72705a947c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134212797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3134212797
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2580164504
Short name T416
Test name
Test status
Simulation time 47050169 ps
CPU time 3.28 seconds
Started Jul 11 05:33:40 PM PDT 24
Finished Jul 11 05:33:46 PM PDT 24
Peak memory 214368 kb
Host smart-c7208f69-9f8e-4c50-967a-ac5850abb45f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2580164504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2580164504
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.437565740
Short name T400
Test name
Test status
Simulation time 59889346 ps
CPU time 3.21 seconds
Started Jul 11 05:33:46 PM PDT 24
Finished Jul 11 05:33:52 PM PDT 24
Peak memory 221816 kb
Host smart-c006e527-592f-47f4-9df6-e584fccb203c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437565740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.437565740
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1172166013
Short name T77
Test name
Test status
Simulation time 2881907681 ps
CPU time 6.79 seconds
Started Jul 11 05:33:40 PM PDT 24
Finished Jul 11 05:33:49 PM PDT 24
Peak memory 209572 kb
Host smart-1d50cd49-3915-4826-b713-400ca20f097c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172166013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1172166013
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.22433014
Short name T671
Test name
Test status
Simulation time 136633342 ps
CPU time 5.51 seconds
Started Jul 11 05:33:42 PM PDT 24
Finished Jul 11 05:33:51 PM PDT 24
Peak memory 222488 kb
Host smart-1dc385ac-4cbb-46bc-8672-2222a67a6b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22433014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.22433014
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.116682531
Short name T619
Test name
Test status
Simulation time 220854122 ps
CPU time 4.39 seconds
Started Jul 11 05:33:44 PM PDT 24
Finished Jul 11 05:33:52 PM PDT 24
Peak memory 222448 kb
Host smart-588a6b21-147e-4a73-9c86-caccc3904e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116682531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.116682531
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.303426701
Short name T495
Test name
Test status
Simulation time 293741703 ps
CPU time 2.93 seconds
Started Jul 11 05:33:43 PM PDT 24
Finished Jul 11 05:33:49 PM PDT 24
Peak memory 209744 kb
Host smart-e7940de7-e373-465d-ae9e-a88f1f51db8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303426701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.303426701
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3630698784
Short name T509
Test name
Test status
Simulation time 374925744 ps
CPU time 7.27 seconds
Started Jul 11 05:33:42 PM PDT 24
Finished Jul 11 05:33:52 PM PDT 24
Peak memory 208480 kb
Host smart-08f49548-e160-4668-952c-d09d26470878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630698784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3630698784
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.4199976166
Short name T906
Test name
Test status
Simulation time 51738531 ps
CPU time 2.74 seconds
Started Jul 11 05:33:40 PM PDT 24
Finished Jul 11 05:33:45 PM PDT 24
Peak memory 208492 kb
Host smart-8070f216-cd30-4f94-927f-95c96f39083b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199976166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.4199976166
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3463601265
Short name T119
Test name
Test status
Simulation time 62395262 ps
CPU time 2.96 seconds
Started Jul 11 05:33:43 PM PDT 24
Finished Jul 11 05:33:49 PM PDT 24
Peak memory 208228 kb
Host smart-f00083cc-90f0-421f-8860-e11b4a131f5b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463601265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3463601265
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2365772734
Short name T833
Test name
Test status
Simulation time 340447871 ps
CPU time 4.38 seconds
Started Jul 11 05:33:45 PM PDT 24
Finished Jul 11 05:33:53 PM PDT 24
Peak memory 207020 kb
Host smart-ad110202-e7c8-4069-9032-a8204f1b6a9d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365772734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2365772734
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.332168398
Short name T890
Test name
Test status
Simulation time 302778845 ps
CPU time 3.13 seconds
Started Jul 11 05:33:39 PM PDT 24
Finished Jul 11 05:33:44 PM PDT 24
Peak memory 207456 kb
Host smart-dbd9660d-1801-4ccd-8d7d-b791e7c7bda5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332168398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.332168398
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2388773867
Short name T528
Test name
Test status
Simulation time 209426735 ps
CPU time 4.11 seconds
Started Jul 11 05:33:53 PM PDT 24
Finished Jul 11 05:34:05 PM PDT 24
Peak memory 208204 kb
Host smart-58cbe9da-4d77-4157-8c95-6fa537b4b114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388773867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2388773867
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.457231632
Short name T441
Test name
Test status
Simulation time 103117590 ps
CPU time 2.24 seconds
Started Jul 11 05:33:40 PM PDT 24
Finished Jul 11 05:33:45 PM PDT 24
Peak memory 206672 kb
Host smart-a25e6295-c234-469c-a497-3e600d7e9cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457231632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.457231632
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3825571665
Short name T198
Test name
Test status
Simulation time 490279056 ps
CPU time 18.88 seconds
Started Jul 11 05:34:24 PM PDT 24
Finished Jul 11 05:34:54 PM PDT 24
Peak memory 219720 kb
Host smart-00669261-0c3f-4e77-b809-4bdd5e37afc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825571665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3825571665
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3967396206
Short name T309
Test name
Test status
Simulation time 113886432 ps
CPU time 2.54 seconds
Started Jul 11 05:33:46 PM PDT 24
Finished Jul 11 05:33:52 PM PDT 24
Peak memory 207856 kb
Host smart-1dfa4ac8-19bd-4548-94f8-fcca2043a3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967396206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3967396206
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1469086250
Short name T177
Test name
Test status
Simulation time 66766041 ps
CPU time 3.33 seconds
Started Jul 11 05:33:55 PM PDT 24
Finished Jul 11 05:34:07 PM PDT 24
Peak memory 210796 kb
Host smart-4c50cd44-745a-454a-ba60-66770d5c111f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469086250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1469086250
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2434638477
Short name T873
Test name
Test status
Simulation time 27845115 ps
CPU time 0.78 seconds
Started Jul 11 05:33:50 PM PDT 24
Finished Jul 11 05:33:57 PM PDT 24
Peak memory 205984 kb
Host smart-c36c3564-383f-48aa-a671-16fe34348b7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434638477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2434638477
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1202909683
Short name T412
Test name
Test status
Simulation time 423926277 ps
CPU time 12.59 seconds
Started Jul 11 05:33:47 PM PDT 24
Finished Jul 11 05:34:03 PM PDT 24
Peak memory 214988 kb
Host smart-44deba7c-cb44-4e65-83df-053b2456457e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1202909683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1202909683
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2382623973
Short name T763
Test name
Test status
Simulation time 200882386 ps
CPU time 2.42 seconds
Started Jul 11 05:33:54 PM PDT 24
Finished Jul 11 05:34:06 PM PDT 24
Peak memory 214316 kb
Host smart-07e8b574-22a5-49b9-97fc-d37582640508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382623973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2382623973
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.4003499093
Short name T858
Test name
Test status
Simulation time 193108180 ps
CPU time 2.93 seconds
Started Jul 11 05:33:45 PM PDT 24
Finished Jul 11 05:33:51 PM PDT 24
Peak memory 214268 kb
Host smart-3f8c1592-1982-413a-a5c0-4c3d7c66ee57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003499093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.4003499093
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1228300420
Short name T278
Test name
Test status
Simulation time 119266233 ps
CPU time 5.07 seconds
Started Jul 11 05:33:47 PM PDT 24
Finished Jul 11 05:33:56 PM PDT 24
Peak memory 220472 kb
Host smart-9398a3ec-5da9-446e-adb6-ba360f4fcec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228300420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1228300420
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3425960528
Short name T382
Test name
Test status
Simulation time 150496716 ps
CPU time 2.93 seconds
Started Jul 11 05:33:47 PM PDT 24
Finished Jul 11 05:33:53 PM PDT 24
Peak memory 214248 kb
Host smart-1768dd78-9d29-4693-8cd8-5d5c711b7d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425960528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3425960528
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_random.1976097623
Short name T914
Test name
Test status
Simulation time 42437308 ps
CPU time 3.14 seconds
Started Jul 11 05:33:52 PM PDT 24
Finished Jul 11 05:34:02 PM PDT 24
Peak memory 214540 kb
Host smart-f19f0e3d-a2cb-4ad7-981c-aca961ca8b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976097623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1976097623
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3614792274
Short name T861
Test name
Test status
Simulation time 392182178 ps
CPU time 8.12 seconds
Started Jul 11 05:33:45 PM PDT 24
Finished Jul 11 05:33:56 PM PDT 24
Peak memory 208876 kb
Host smart-8f1c7373-ff29-480b-bbf0-ade0538afbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614792274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3614792274
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3342876640
Short name T206
Test name
Test status
Simulation time 45304494 ps
CPU time 2.72 seconds
Started Jul 11 05:33:53 PM PDT 24
Finished Jul 11 05:34:03 PM PDT 24
Peak memory 206944 kb
Host smart-1363be5b-15f7-4d76-901c-9cbdf58ea7b9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342876640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3342876640
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3154875960
Short name T217
Test name
Test status
Simulation time 158876395 ps
CPU time 3.84 seconds
Started Jul 11 05:33:49 PM PDT 24
Finished Jul 11 05:33:59 PM PDT 24
Peak memory 208348 kb
Host smart-0a9281cb-4d90-4680-aaa5-f5f84a00fd86
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154875960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3154875960
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1245476823
Short name T582
Test name
Test status
Simulation time 308860254 ps
CPU time 3.44 seconds
Started Jul 11 05:33:50 PM PDT 24
Finished Jul 11 05:34:00 PM PDT 24
Peak memory 208696 kb
Host smart-23972113-e574-4bbc-af22-fb1cfc5719a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245476823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1245476823
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2485902905
Short name T447
Test name
Test status
Simulation time 132107016 ps
CPU time 2.01 seconds
Started Jul 11 05:33:45 PM PDT 24
Finished Jul 11 05:33:51 PM PDT 24
Peak memory 215736 kb
Host smart-bc73c80a-56ac-4505-82ea-8844cf8e534f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485902905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2485902905
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1567352989
Short name T903
Test name
Test status
Simulation time 95938893 ps
CPU time 2.87 seconds
Started Jul 11 05:33:49 PM PDT 24
Finished Jul 11 05:33:58 PM PDT 24
Peak memory 208176 kb
Host smart-c938c325-1afb-4efe-b586-f8605c6830c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567352989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1567352989
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3367182060
Short name T843
Test name
Test status
Simulation time 3549230309 ps
CPU time 34.41 seconds
Started Jul 11 05:33:45 PM PDT 24
Finished Jul 11 05:34:23 PM PDT 24
Peak memory 216044 kb
Host smart-eaf990c0-25fc-4f39-8c08-4fc7ec42014b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367182060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3367182060
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.4223507084
Short name T698
Test name
Test status
Simulation time 147391208 ps
CPU time 5.72 seconds
Started Jul 11 05:33:51 PM PDT 24
Finished Jul 11 05:34:04 PM PDT 24
Peak memory 208908 kb
Host smart-87bb951b-9e43-42ab-a29f-1abfb8333c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223507084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.4223507084
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.516005457
Short name T665
Test name
Test status
Simulation time 397053675 ps
CPU time 3.01 seconds
Started Jul 11 05:33:50 PM PDT 24
Finished Jul 11 05:34:00 PM PDT 24
Peak memory 210548 kb
Host smart-4e7b371d-b42c-4e7f-9b3c-b394c6760f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516005457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.516005457
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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