Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	17	32	65.31

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	16	19	54.29	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	61	1			T44	1		T45	1		T4	1
auto[OpGenId]	9	1			T229	1		T230	1		T68	1
auto[OpGenSwOut]	22	1			T63	1		T231	1		T232	1
auto[OpGenHwOut]	21	1			T4	1		T6	1		T46	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1582	1			T3	3		T44	1		T4	2
auto[StInit]	86	1			T36	1		T22	1		T4	1
auto[StCreatorRootKey]	69	1			T54	1		T44	1		T40	1
auto[StOwnerIntKey]	47	1			T13	1		T14	1		T44	2
auto[StOwnerKey]	36	1			T32	1		T45	1		T61	1
auto[StDisabled]	460	1			T3	15		T44	1		T100	2
auto[StInvalid]	50	1			T33	1		T34	1		T35	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3305

1

T1

1

T2

1

T3

19

auto[1]

113

1

T44

1

T45

1

T4

2

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1577	1			T3	3		T44	1		T4	2
auto[StReset]	auto[1]	5	1			T48	1		T49	1		T50	1
auto[StInit]	auto[0]	43	1			T36	1		T22	1		T233	1
auto[StInit]	auto[1]	43	1			T4	1		T52	1		T63	1
auto[StCreatorRootKey]	auto[0]	33	1			T54	1		T44	1		T40	1
auto[StCreatorRootKey]	auto[1]	36	1			T57	1		T5	1		T225	1
auto[StOwnerIntKey]	auto[0]	33	1			T13	1		T14	1		T44	1
auto[StOwnerIntKey]	auto[1]	14	1			T44	1		T4	1		T58	1
auto[StOwnerKey]	auto[0]	30	1			T32	1		T61	1		T57	1
auto[StOwnerKey]	auto[1]	6	1			T45	1		T63	1		T231	1
auto[StDisabled]	auto[0]	451	1			T3	15		T44	1		T100	2
auto[StDisabled]	auto[1]	9	1			T46	1		T123	1		T234	1
auto[StInvalid]	auto[0]	50	1			T33	1		T34	1		T35	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	16	19	54.29	16

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	5	1			T48	1		T49	1		T50	1
auto[StInit]	auto[OpAdvance]	27	1			T4	1		T52	1		T63	1
auto[StInit]	auto[OpGenId]	2	1			T229	1		T230	1		-	-
auto[StInit]	auto[OpGenSwOut]	7	1			T232	1		T235	1		T236	1
auto[StInit]	auto[OpGenHwOut]	7	1			T6	1		T237	1		T238	1
auto[StCreatorRootKey]	auto[OpAdvance]	16	1			T57	1		T5	1		T225	1
auto[StCreatorRootKey]	auto[OpGenId]	2	1			T239	1		T240	1		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T241	1		T242	1		T243	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	8	1			T62	1		T241	1		T244	1
auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T44	1		T58	1		T28	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T245	1		T246	1		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	3	1			T4	1		T247	1		T239	1
auto[StOwnerKey]	auto[OpAdvance]	2	1			T45	1		T248	1		-	-
auto[StOwnerKey]	auto[OpGenId]	1	1			T68	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T63	1		T231	1		T249	1
auto[StDisabled]	auto[OpAdvance]	2	1			T205	1		T171	1		-	-
auto[StDisabled]	auto[OpGenId]	2	1			T234	1		T250	1		-	-
auto[StDisabled]	auto[OpGenSwOut]	2	1			T251	1		T252	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	3	1			T46	1		T123	1		T239	1