Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.05	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	76	254	76.97

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	57	223	79.64	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4950

1

T1

4

T3

71

T13

1

auto[1]

511

1

T1

1

T3

6

T15

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4950

1

T1

4

T3

71

T13

1

auto[1]

511

1

T1

1

T3

6

T15

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4896

1

T1

5

T3

69

T15

8

auto[1]

565

1

T3

8

T13

1

T76

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4896

1

T1

5

T3

69

T15

8

auto[1]

565

1

T3

8

T13

1

T76

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	450	1			T1	2		T3	17		T18	3
auto[OpGenId]	1199	1			T3	19		T17	2		T18	1
auto[OpGenSwOut]	1204	1			T1	2		T3	15		T16	1
auto[OpGenHwOut]	2538	1			T1	1		T3	24		T13	1
auto[OpDisable]	70	1			T3	2		T17	1		T19	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	450	1			T1	2		T3	17		T18	3
auto[OpGenId]	1199	1			T3	19		T17	2		T18	1
auto[OpGenSwOut]	1204	1			T1	2		T3	15		T16	1
auto[OpGenHwOut]	2538	1			T1	1		T3	24		T13	1
auto[OpDisable]	70	1			T3	2		T17	1		T19	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4934

1

T1

4

T3

67

T13

1

auto[1]

527

1

T1

1

T3

10

T19

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4934

1

T1

4

T3

67

T13

1

auto[1]

527

1

T1

1

T3

10

T19

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5160

1

T1

4

T3

77

T13

1

auto[1]

301

1

T1

1

T146

2

T148

7

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1895	1			T1	2		T3	27		T13	1
auto[1]	715	1			T3	12		T15	1		T18	1
auto[2]	721	1			T1	1		T3	10		T75	5
auto[3]	713	1			T1	1		T3	11		T15	1
auto[4]	359	1			T3	3		T15	1		T76	1
auto[5]	355	1			T1	1		T3	4		T15	3
auto[6]	345	1			T3	5		T18	2		T19	2
auto[7]	358	1			T3	5		T75	1		T27	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1417	1			T1	1		T3	17		T15	4
clear_one[1]	715	1			T3	12		T15	1		T18	1
clear_one[2]	721	1			T1	1		T3	10		T75	5
clear_one[3]	713	1			T1	1		T3	11		T15	1
clear_none	1895	1			T1	2		T3	27		T13	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1020	1			T3	8		T17	2		T19	1
auto[StInit]	650	1			T1	1		T3	10		T15	1
auto[StCreatorRootKey]	571	1			T3	8		T13	1		T15	1
auto[StOwnerIntKey]	497	1			T1	1		T3	6		T15	1
auto[StOwnerKey]	477	1			T1	1		T3	6		T15	1
auto[StDisabled]	1940	1			T1	2		T3	39		T15	4
auto[StInvalid]	306	1			T33	2		T34	2		T35	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1020	1			T3	8		T17	2		T19	1
auto[StInit]	650	1			T1	1		T3	10		T15	1
auto[StCreatorRootKey]	571	1			T3	8		T13	1		T15	1
auto[StOwnerIntKey]	497	1			T1	1		T3	6		T15	1
auto[StOwnerKey]	477	1			T1	1		T3	6		T15	1
auto[StDisabled]	1940	1			T1	2		T3	39		T15	4
auto[StInvalid]	306	1			T33	2		T34	2		T35	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	57	223	79.64	57

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[0] - auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[2]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StCreatorRootKey]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[5]]	[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[7]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[7]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	2
[auto[7]]	[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	5	1			T253	1		T254	1		T255	1
auto[0]	auto[StReset]	auto[OpGenId]	175	1			T3	2		T17	1		T43	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	159	1			T3	2		T17	1		T19	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	255	1			T3	1		T228	2		T128	2
auto[0]	auto[StInit]	auto[OpAdvance]	44	1			T3	5		T18	1		T55	1
auto[0]	auto[StInit]	auto[OpGenId]	85	1			T54	1		T4	1		T104	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	83	1			T1	1		T3	1		T16	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	193	1			T3	3		T15	1		T75	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	27	1			T3	1		T76	1		T45	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	58	1			T3	1		T221	1		T4	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	51	1			T27	1		T44	1		T20	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	86	1			T13	1		T77	1		T228	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T100	1		T104	1		T7	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	29	1			T3	2		T222	1		T100	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	43	1			T3	2		T221	1		T44	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	52	1			T77	1		T256	1		T257	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T3	1		T146	1		T49	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	30	1			T88	1		T130	1		T4	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	30	1			T1	1		T258	1		T231	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	36	1			T3	1		T77	1		T128	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	40	1			T4	1		T104	2		T258	1
auto[0]	auto[StDisabled]	auto[OpGenId]	62	1			T3	3		T17	1		T146	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	73	1			T27	1		T104	1		T57	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T3	2		T15	1		T77	1
auto[0]	auto[StDisabled]	auto[OpDisable]	20	1			T259	1		T66	1		T260	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	11	1			T33	1		T47	1		T261	1
auto[0]	auto[StInvalid]	auto[OpGenId]	32	1			T101	1		T81	1		T99	2
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	23	1			T34	1		T56	1		T101	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	23	1			T34	1		T35	1		T262	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T263	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	24	1			T57	1		T264	1		T265	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	25	1			T53	1		T99	1		T107	2
auto[1]	auto[StReset]	auto[OpGenHwOut]	42	1			T3	1		T228	1		T4	1
auto[1]	auto[StInit]	auto[OpAdvance]	7	1			T266	1		T267	1		T268	1
auto[1]	auto[StInit]	auto[OpGenId]	13	1			T100	1		T225	1		T62	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	11	1			T269	1		T270	1		T242	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	19	1			T271	1		T272	1		T273	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T3	1		T274	1		T275	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T19	1		T53	1		T276	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	16	1			T55	1		T68	1		T127	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	30	1			T131	1		T277	1		T278	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T231	1		T67	1		T239	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T53	1		T125	1		T279	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	21	1			T4	1		T111	2		T53	2
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	33	1			T131	1		T108	1		T280	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T281	1		T282	1		T255	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	18	1			T4	1		T231	1		T283	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T3	1		T221	1		T111	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T15	1		T19	1		T131	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	32	1			T3	1		T88	1		T100	1
auto[1]	auto[StDisabled]	auto[OpGenId]	61	1			T3	2		T100	1		T106	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	73	1			T3	3		T18	1		T19	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	146	1			T3	2		T228	2		T222	1
auto[1]	auto[StDisabled]	auto[OpDisable]	5	1			T3	1		T68	1		T284	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	2	1			T285	1		T286	1		-	-
auto[1]	auto[StInvalid]	auto[OpGenId]	7	1			T262	1		T81	1		T287	2
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T101	1		T83	1		T288	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	22	1			T33	1		T35	1		T83	1
auto[2]	auto[StReset]	auto[OpGenId]	19	1			T262	1		T81	1		T289	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	22	1			T57	1		T235	1		T265	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	35	1			T228	1		T44	1		T81	1
auto[2]	auto[StInit]	auto[OpAdvance]	3	1			T4	1		T290	1		T291	1
auto[2]	auto[StInit]	auto[OpGenId]	11	1			T63	1		T64	1		T292	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	12	1			T212	1		T293	1		T294	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	20	1			T134	1		T295	1		T296	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T88	1		T134	1		T297	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T53	1		T25	1		T298	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T3	1		T53	1		T231	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	49	1			T3	1		T226	1		T128	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T106	1		T63	1		T291	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T100	1		T57	1		T278	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	23	1			T147	1		T298	1		T270	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T75	1		T226	1		T128	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T100	1		T148	1		T225	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	23	1			T53	1		T57	1		T269	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T100	1		T106	1		T278	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T106	1		T109	1		T299	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	34	1			T1	1		T3	2		T53	1
auto[2]	auto[StDisabled]	auto[OpGenId]	51	1			T3	2		T100	1		T223	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T3	2		T111	1		T55	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	154	1			T3	2		T75	4		T77	1
auto[2]	auto[StDisabled]	auto[OpDisable]	9	1			T134	1		T300	1		T67	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	8	1			T35	1		T261	1		T301	1
auto[2]	auto[StInvalid]	auto[OpGenId]	10	1			T56	1		T105	1		T302	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	16	1			T47	1		T101	1		T41	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T56	1		T99	1		T303	1
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T304	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	18	1			T4	1		T225	1		T305	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	24	1			T100	1		T57	1		T306	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	44	1			T3	1		T44	1		T307	1
auto[3]	auto[StInit]	auto[OpAdvance]	3	1			T308	1		T309	1		T291	1
auto[3]	auto[StInit]	auto[OpGenId]	9	1			T310	1		T311	1		T176	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	8	1			T264	1		T304	1		T26	2
auto[3]	auto[StInit]	auto[OpGenHwOut]	24	1			T228	1		T109	1		T312	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T3	1		T100	1		T61	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T66	1		T134	1		T300	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T63	1		T313	1		T314	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T3	1		T75	1		T280	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T1	1		T3	2		T18	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T53	1		T315	1		T316	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T55	1		T231	1		T274	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	45	1			T76	1		T107	1		T63	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T55	1		T258	1		T317	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	13	1			T4	1		T55	1		T53	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T17	1		T107	1		T63	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	33	1			T3	1		T226	1		T220	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	21	1			T3	2		T18	1		T146	1
auto[3]	auto[StDisabled]	auto[OpGenId]	62	1			T4	1		T231	1		T318	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	55	1			T220	1		T4	1		T53	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	167	1			T3	3		T15	1		T77	2
auto[3]	auto[StDisabled]	auto[OpDisable]	12	1			T17	1		T134	1		T319	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	8	1			T82	1		T288	1		T320	1
auto[3]	auto[StInvalid]	auto[OpGenId]	14	1			T35	1		T81	1		T302	2
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T81	1		T41	1		T301	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T307	1		T82	1		T321	1
auto[4]	auto[StReset]	auto[OpGenId]	7	1			T264	1		T235	1		T322	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	6	1			T21	1		T298	1		T323	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	22	1			T312	1		T324	1		T62	1
auto[4]	auto[StInit]	auto[OpAdvance]	9	1			T106	1		T325	1		T26	1
auto[4]	auto[StInit]	auto[OpGenId]	6	1			T134	1		T241	1		T242	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	7	1			T111	1		T37	1		T69	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	10	1			T3	1		T128	1		T326	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T3	1		T325	1		T304	2
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T106	1		T304	1		T327	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T227	1		T316	1		T328	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T329	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T57	1		T330	1		T331	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T57	1		T332	1		T333	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	15	1			T109	1		T334	1		T328	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T269	1		-	-		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	12	1			T3	1		T55	1		T231	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T335	1		T336	1		T337	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T256	1		T53	1		T277	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	22	1			T258	1		T269	1		T315	1
auto[4]	auto[StDisabled]	auto[OpGenId]	23	1			T57	1		T258	1		T231	2
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	22	1			T221	1		T111	1		T55	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	98	1			T15	1		T76	1		T128	1
auto[4]	auto[StDisabled]	auto[OpDisable]	7	1			T67	1		T125	1		T338	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T47	1		T307	1		T339	1
auto[4]	auto[StInvalid]	auto[OpGenId]	10	1			T302	1		T340	1		T341	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T41	1		T79	1		T342	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T262	1		T81	1		T82	1
auto[5]	auto[StReset]	auto[OpGenId]	10	1			T3	1		T266	1		T343	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	19	1			T57	1		T258	1		T259	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	21	1			T4	1		T262	1		T278	1
auto[5]	auto[StInit]	auto[OpAdvance]	1	1			T205	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenId]	7	1			T100	1		T316	1		T322	2
auto[5]	auto[StInit]	auto[OpGenSwOut]	6	1			T57	1		T306	1		T322	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	15	1			T53	1		T299	1		T259	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T344	1		T253	1		T345	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T295	1		T308	1		T346	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T134	1		T73	1		T347	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	26	1			T15	1		T43	1		T57	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T55	1		T198	1		T348	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T63	1		T349	1		T314	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T350	1		T351	1		T352	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T15	1		T17	1		T353	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T3	1		T253	2		T347	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T134	1		T125	1		T253	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T354	1		T355	1		T124	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	10	1			T148	1		T297	2		T293	1
auto[5]	auto[StDisabled]	auto[OpGenId]	32	1			T111	2		T231	2		T134	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	21	1			T3	1		T57	2		T134	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	79	1			T1	1		T3	1		T15	1
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T63	1		T356	1		T245	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	5	1			T357	1		T287	1		T358	1
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T105	1		T359	1		T360	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T81	1		T83	1		T78	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T81	1		T99	1		T361	1
auto[6]	auto[StReset]	auto[OpGenId]	10	1			T88	1		T69	1		T362	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	10	1			T53	1		T57	1		T363	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	16	1			T109	2		T82	1		T292	1
auto[6]	auto[StInit]	auto[OpAdvance]	7	1			T364	2		T365	1		T338	1
auto[6]	auto[StInit]	auto[OpGenId]	8	1			T4	1		T26	1		T364	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	2	1			T236	1		T284	1		-	-
auto[6]	auto[StInit]	auto[OpGenHwOut]	8	1			T366	1		T210	1		T367	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T108	1		-	-		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T271	1		T310	1		T234	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T134	1		T236	1		T242	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T57	1		T109	1		T353	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T325	1		T364	1		T89	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T127	1		T239	1		T368	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T134	1		T300	1		T369	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T19	1		T228	1		T370	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T364	1		T263	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	8	1			T371	1		T372	1		T373	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T374	1		T375	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T18	1		T228	1		T325	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	17	1			T290	1		T297	1		T327	1
auto[6]	auto[StDisabled]	auto[OpGenId]	39	1			T3	2		T18	1		T298	2
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	41	1			T3	2		T27	1		T231	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	74	1			T3	1		T226	1		T227	1
auto[6]	auto[StDisabled]	auto[OpDisable]	2	1			T19	1		T198	1		-	-
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T288	1		T376	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	6	1			T285	1		T94	1		T365	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T362	1		T377	1		T361	2
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T82	1		T357	1		T378	1
auto[7]	auto[StReset]	auto[OpGenId]	15	1			T276	1		T21	1		T231	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	14	1			T35	1		T276	1		T379	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	21	1			T53	1		T299	1		T298	1
auto[7]	auto[StInit]	auto[OpGenId]	5	1			T380	1		T381	1		T238	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	3	1			T64	1		T323	1		T382	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	11	1			T53	1		T383	1		T384	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T385	1		T29	1		T386	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T148	2		T63	1		T241	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T55	1		T306	1		T309	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	10	1			T63	1		T387	1		T367	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T231	1		T178	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T385	1		T241	1		T239	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T67	1		T388	1		T69	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T227	1		T299	1		T389	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	9	1			T45	1		T298	1		T124	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T184	1		T390	1		T391	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T75	1		T63	1		T46	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	18	1			T3	1		T27	1		T148	1
auto[7]	auto[StDisabled]	auto[OpGenId]	34	1			T3	1		T278	1		T64	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T100	1		T53	1		T231	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T3	2		T88	1		T53	1
auto[7]	auto[StDisabled]	auto[OpDisable]	10	1			T3	1		T67	1		T392	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T307	2		T393	1		T394	1
auto[7]	auto[StInvalid]	auto[OpGenId]	3	1			T35	1		T285	1		T320	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T47	1		T285	1		T320	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T105	2		T83	1		T395	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1417

1

T1

1

T3

17

T15

4

clear_one[1]

auto[0]

auto[0]

auto[0]

437

1

T3

5

T15

1

T18

1

clear_one[1]

auto[0]

auto[0]

auto[1]

110

1

T3

3

T19

1

T228

2

clear_one[1]

auto[0]

auto[1]

auto[0]

131

1

T3

4

T128

1

T130

1

clear_one[1]

auto[0]

auto[1]

auto[1]

37

1

T134

1

T225

1

T67

1

clear_one[2]

auto[0]

auto[0]

auto[0]

418

1

T3

4

T228

1

T88

1

clear_one[2]

auto[0]

auto[0]

auto[1]

152

1

T3

3

T75

5

T77

1

clear_one[2]

auto[1]

auto[0]

auto[0]

130

1

T3

3

T226

2

T44

1

clear_one[2]

auto[1]

auto[0]

auto[1]

21

1

T1

1

T225

2

T46

1

clear_one[3]

auto[0]

auto[0]

auto[0]

428

1

T1

1

T3

10

T17

2

clear_one[3]

auto[0]

auto[1]

auto[0]

119

1

T3

1

T76

1

T220

1

clear_one[3]

auto[1]

auto[0]

auto[0]

125

1

T15

1

T226

1

T4

1

clear_one[3]

auto[1]

auto[1]

auto[0]

41

1

T220

1

T111

1

T55

1

clear_none

auto[0]

auto[0]

auto[0]

1374

1

T1

2

T3

21

T15

1

clear_none

auto[0]

auto[0]

auto[1]

131

1

T3

2

T77

4

T228

1

clear_none

auto[0]

auto[1]

auto[0]

156

1

T13

1

T44

1

T128

1

clear_none

auto[0]

auto[1]

auto[1]

40

1

T3

1

T134

1

T46

2

clear_none

auto[1]

auto[0]

auto[0]

131

1

T15

1

T27

2

T222

1

clear_none

auto[1]

auto[0]

auto[1]

22

1

T3

1

T53

1

T134

1

clear_none

auto[1]

auto[1]

auto[0]

27

1

T3

2

T53

1

T64

1

clear_none

auto[1]

auto[1]

auto[1]

14

1

T55

1

T107

1

T125

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1327	1			T1	1		T3	17		T15	4
clear_all	auto[1]	90	1			T148	1		T104	3		T106	1
clear_one[1]	auto[0]	665	1			T3	12		T15	1		T18	1
clear_one[1]	auto[1]	50	1			T148	6		T106	1		T325	1
clear_one[2]	auto[0]	677	1			T3	10		T75	5		T77	1
clear_one[2]	auto[1]	44	1			T1	1		T106	2		T135	1
clear_one[3]	auto[0]	688	1			T1	1		T3	11		T15	1
clear_one[3]	auto[1]	25	1			T146	1		T304	2		T317	2
clear_none	auto[0]	1803	1			T1	2		T3	27		T13	1
clear_none	auto[1]	92	1			T146	1		T104	8		T136	6