Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11384

1

T1

8

T2

4

T3

160

auto[Attestation]

7865

1

T1

6

T2

2

T3

139

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2793	1			T3	41		T16	1		T17	5
auto[Aes]	3416	1			T1	6		T2	2		T3	40
auto[Kmac]	3526	1			T1	4		T2	1		T3	52
auto[Otbn]	3429	1			T1	3		T2	3		T3	60

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7764	1			T1	8		T2	3		T3	112
auto[OpGenId]	6085	1			T1	1		T3	106		T13	2
auto[OpGenSwOut]	6169	1			T1	6		T2	1		T3	91
auto[OpGenHwOut]	6995	1			T1	7		T2	5		T3	102
auto[OpDisable]	133	1			T3	3		T17	1		T19	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10781

1

T1

7

T2

9

T3

158

auto[OpDoneFail]

16365

1

T1

15

T3

256

T13

2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6769	1			T1	1		T2	1		T3	52
auto[StInit]	3790	1			T1	4		T2	1		T3	47
auto[StCreatorRootKey]	3222	1			T1	2		T2	1		T3	45
auto[StOwnerIntKey]	2824	1			T1	1		T2	6		T3	48
auto[StOwnerKey]	2484	1			T1	2		T3	40		T15	2
auto[StDisabled]	8057	1			T1	12		T3	182		T15	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	349	1			T3	1		T17	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	103	1			T45	1		T111	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	87	1			T220	1		T100	1		T111	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	74	1			T3	2		T100	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	73	1			T3	1		T27	1		T100	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	232	1			T3	8		T17	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	316	1			T3	2		T14	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	87	1			T3	1		T4	1		T147	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	96	1			T1	1		T3	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	61	1			T3	1		T220	1		T221	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	55	1			T18	1		T222	1		T100	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	202	1			T1	1		T3	2		T76	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	372	1			T17	2		T43	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	112	1			T16	2		T221	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	104	1			T3	1		T14	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	75	1			T2	1		T3	1		T4	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	64	1			T3	1		T220	1		T223	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	207	1			T3	3		T19	1		T76	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	382	1			T3	1		T17	1		T19	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	111	1			T100	1		T51	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	71	1			T13	1		T4	1		T104	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T3	2		T17	1		T224	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	55	1			T17	1		T27	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	206	1			T3	12		T18	1		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	78	1			T111	1		T53	3		T225	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	94	1			T3	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	82	1			T3	1		T17	1		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	73	1			T44	2		T45	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	56	1			T3	1		T32	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	230	1			T3	6		T222	1		T220	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	103	1			T35	3		T4	2		T55	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	99	1			T1	1		T3	1		T130	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	102	1			T3	2		T54	2		T44	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	74	1			T3	2		T32	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	74	1			T1	1		T27	1		T220	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	244	1			T3	2		T27	2		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	81	1			T3	2		T44	3		T4	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	107	1			T3	3		T19	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	95	1			T16	1		T27	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T3	1		T53	1		T147	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	63	1			T3	1		T130	1		T146	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	231	1			T1	1		T3	11		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	77	1			T3	4		T44	4		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	112	1			T3	2		T43	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T3	1		T17	1		T220	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	84	1			T3	1		T43	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	59	1			T18	1		T224	1		T221	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	213	1			T1	1		T3	9		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	284	1			T43	1		T35	1		T51	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	105	1			T3	3		T220	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	66	1			T3	1		T18	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	64	1			T3	1		T44	1		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	62	1			T3	3		T18	1		T220	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	185	1			T3	4		T76	2		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	423	1			T3	2		T17	1		T47	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	115	1			T3	2		T19	1		T226	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	111	1			T3	1		T15	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	91	1			T13	1		T14	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	86	1			T3	2		T76	1		T226	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	278	1			T3	9		T15	2		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	484	1			T3	5		T43	2		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	136	1			T1	2		T3	3		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	119	1			T3	1		T13	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	94	1			T3	2		T227	1		T223	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	94	1			T3	1		T18	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	265	1			T1	1		T3	7		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	477	1			T3	1		T17	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	132	1			T3	4		T228	1		T131	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	106	1			T3	3		T17	1		T77	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	98	1			T2	3		T3	2		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	83	1			T19	1		T77	1		T228	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	288	1			T1	2		T3	5		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	66	1			T3	1		T44	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	69	1			T3	2		T43	1		T111	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	77	1			T54	1		T222	1		T220	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	57	1			T17	1		T27	1		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	41	1			T3	1		T100	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	186	1			T3	4		T27	3		T220	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	79	1			T3	2		T44	2		T35	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	122	1			T15	1		T130	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	107	1			T3	2		T27	1		T226	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	95	1			T2	2		T3	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	79	1			T3	2		T15	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	317	1			T1	2		T3	3		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	45	1			T3	3		T44	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	136	1			T3	2		T88	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	94	1			T3	1		T227	1		T95	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	105	1			T3	1		T19	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	87	1			T220	1		T55	1		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	269	1			T3	2		T16	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	62	1			T3	1		T44	3		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	108	1			T75	1		T77	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	101	1			T3	2		T16	1		T75	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	107	1			T3	2		T77	1		T228	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	66	1			T3	2		T75	1		T55	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	274	1			T3	6		T16	1		T75	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	219	1			T3	3		T27	1		T220	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	699	1			T3	9		T17	2		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	196	1			T1	1		T3	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	621	1			T1	1		T3	6		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	224	1			T2	1		T3	3		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	710	1			T3	3		T16	2		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	189	1			T3	2		T13	1		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	708	1			T3	13		T17	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	198	1			T3	1		T17	1		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	415	1			T3	8		T16	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	231	1			T1	1		T3	4		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	465	1			T1	1		T3	3		T27	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	220	1			T3	2		T16	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	444	1			T1	1		T3	16		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	216	1			T3	2		T17	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	414	1			T1	1		T3	15		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	172	1			T3	5		T18	2		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	594	1			T3	7		T43	1		T76	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	269	1			T3	3		T13	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	835	1			T3	13		T15	2		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	288	1			T3	4		T13	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	904	1			T1	3		T3	15		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	277	1			T2	3		T3	5		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	907	1			T1	2		T3	10		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	163	1			T3	1		T17	1		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	333	1			T3	7		T43	1		T27	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	270	1			T2	2		T3	4		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	529	1			T1	2		T3	6		T15	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	276	1			T3	1		T19	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	460	1			T3	8		T16	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	247	1			T3	3		T16	1		T75	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	471	1			T3	10		T16	1		T75	3