Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7294

1

T1

4

T3

149

T13

2

auto[1]

298

1

T1

3

T146

1

T148

13

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	3072	1			T1	3		T3	56		T16	4
auto[134217728:268435455]	185	1			T3	5		T220	1		T44	1
auto[268435456:402653183]	157	1			T3	1		T43	1		T27	1
auto[402653184:536870911]	170	1			T3	4		T18	1		T27	1
auto[536870912:671088639]	162	1			T3	6		T17	1		T19	1
auto[671088640:805306367]	160	1			T3	4		T13	1		T17	1
auto[805306368:939524095]	149	1			T3	3		T27	2		T88	1
auto[939524096:1073741823]	146	1			T27	1		T88	1		T35	1
auto[1073741824:1207959551]	168	1			T3	5		T43	1		T220	1
auto[1207959552:1342177279]	127	1			T1	1		T3	3		T27	2
auto[1342177280:1476395007]	151	1			T3	6		T88	1		T44	1
auto[1476395008:1610612735]	135	1			T43	1		T34	1		T220	1
auto[1610612736:1744830463]	142	1			T3	3		T16	1		T19	1
auto[1744830464:1879048191]	153	1			T1	1		T3	1		T43	1
auto[1879048192:2013265919]	156	1			T3	4		T43	1		T27	1
auto[2013265920:2147483647]	147	1			T3	1		T33	2		T88	1
auto[2147483648:2281701375]	126	1			T3	3		T220	2		T4	1
auto[2281701376:2415919103]	132	1			T3	2		T16	2		T220	1
auto[2415919104:2550136831]	138	1			T3	1		T44	1		T4	2
auto[2550136832:2684354559]	148	1			T3	1		T43	1		T44	1
auto[2684354560:2818572287]	146	1			T3	1		T88	1		T44	2
auto[2818572288:2952790015]	125	1			T3	5		T16	1		T220	1
auto[2952790016:3087007743]	146	1			T3	7		T17	1		T27	1
auto[3087007744:3221225471]	123	1			T3	4		T16	1		T88	1
auto[3221225472:3355443199]	133	1			T76	1		T4	1		T20	1
auto[3355443200:3489660927]	133	1			T3	2		T220	1		T47	1
auto[3489660928:3623878655]	121	1			T3	3		T16	1		T35	1
auto[3623878656:3758096383]	133	1			T3	4		T43	1		T33	1
auto[3758096384:3892314111]	164	1			T1	1		T3	2		T18	1
auto[3892314112:4026531839]	129	1			T3	4		T17	1		T27	1
auto[4026531840:4160749567]	157	1			T1	1		T3	4		T13	1
auto[4160749568:4294967295]	158	1			T3	4		T88	1		T47	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	3060	1			T1	2		T3	56		T16	4
auto[0:134217727]	auto[1]	12	1			T1	1		T325	1		T269	1
auto[134217728:268435455]	auto[0]	176	1			T3	5		T220	1		T44	1
auto[134217728:268435455]	auto[1]	9	1			T148	2		T297	1		T253	1
auto[268435456:402653183]	auto[0]	150	1			T3	1		T43	1		T27	1
auto[268435456:402653183]	auto[1]	7	1			T135	1		T136	1		T291	1
auto[402653184:536870911]	auto[0]	163	1			T3	4		T18	1		T27	1
auto[402653184:536870911]	auto[1]	7	1			T104	1		T325	1		T253	1
auto[536870912:671088639]	auto[0]	157	1			T3	6		T17	1		T19	1
auto[536870912:671088639]	auto[1]	5	1			T406	1		T253	1		T263	1
auto[671088640:805306367]	auto[0]	152	1			T3	4		T13	1		T17	1
auto[671088640:805306367]	auto[1]	8	1			T106	1		T325	1		T253	1
auto[805306368:939524095]	auto[0]	135	1			T3	3		T27	2		T88	1
auto[805306368:939524095]	auto[1]	14	1			T148	1		T136	1		T325	2
auto[939524096:1073741823]	auto[0]	139	1			T27	1		T88	1		T35	1
auto[939524096:1073741823]	auto[1]	7	1			T325	1		T406	1		T253	1
auto[1073741824:1207959551]	auto[0]	155	1			T3	5		T43	1		T220	1
auto[1073741824:1207959551]	auto[1]	13	1			T148	1		T104	1		T325	1
auto[1207959552:1342177279]	auto[0]	119	1			T1	1		T3	3		T27	2
auto[1207959552:1342177279]	auto[1]	8	1			T269	1		T297	1		T182	1
auto[1342177280:1476395007]	auto[0]	140	1			T3	6		T88	1		T44	1
auto[1342177280:1476395007]	auto[1]	11	1			T104	1		T253	1		T322	1
auto[1476395008:1610612735]	auto[0]	124	1			T43	1		T34	1		T220	1
auto[1476395008:1610612735]	auto[1]	11	1			T136	1		T327	1		T407	1
auto[1610612736:1744830463]	auto[0]	134	1			T3	3		T16	1		T19	1
auto[1610612736:1744830463]	auto[1]	8	1			T148	1		T135	1		T297	1
auto[1744830464:1879048191]	auto[0]	141	1			T3	1		T43	1		T88	1
auto[1744830464:1879048191]	auto[1]	12	1			T1	1		T269	2		T327	1
auto[1879048192:2013265919]	auto[0]	146	1			T3	4		T43	1		T27	1
auto[1879048192:2013265919]	auto[1]	10	1			T135	1		T291	2		T368	1
auto[2013265920:2147483647]	auto[0]	138	1			T3	1		T33	2		T88	1
auto[2013265920:2147483647]	auto[1]	9	1			T406	1		T311	1		T405	1
auto[2147483648:2281701375]	auto[0]	113	1			T3	3		T220	2		T4	1
auto[2147483648:2281701375]	auto[1]	13	1			T106	1		T297	1		T406	1
auto[2281701376:2415919103]	auto[0]	118	1			T3	2		T16	2		T220	1
auto[2281701376:2415919103]	auto[1]	14	1			T304	1		T269	1		T317	1
auto[2415919104:2550136831]	auto[0]	132	1			T3	1		T44	1		T4	2
auto[2415919104:2550136831]	auto[1]	6	1			T325	1		T182	1		T263	1
auto[2550136832:2684354559]	auto[0]	141	1			T3	1		T43	1		T44	1
auto[2550136832:2684354559]	auto[1]	7	1			T148	1		T253	1		T311	1
auto[2684354560:2818572287]	auto[0]	139	1			T3	1		T88	1		T44	2
auto[2684354560:2818572287]	auto[1]	7	1			T135	1		T407	1		T369	1
auto[2818572288:2952790015]	auto[0]	119	1			T3	5		T16	1		T220	1
auto[2818572288:2952790015]	auto[1]	6	1			T304	1		T348	1		T182	1
auto[2952790016:3087007743]	auto[0]	138	1			T3	7		T17	1		T27	1
auto[2952790016:3087007743]	auto[1]	8	1			T148	1		T136	1		T297	1
auto[3087007744:3221225471]	auto[0]	110	1			T3	4		T16	1		T88	1
auto[3087007744:3221225471]	auto[1]	13	1			T148	1		T297	1		T407	2
auto[3221225472:3355443199]	auto[0]	119	1			T76	1		T4	1		T20	1
auto[3221225472:3355443199]	auto[1]	14	1			T146	1		T136	1		T327	1
auto[3355443200:3489660927]	auto[0]	123	1			T3	2		T220	1		T47	1
auto[3355443200:3489660927]	auto[1]	10	1			T269	1		T327	1		T253	1
auto[3489660928:3623878655]	auto[0]	113	1			T3	3		T16	1		T35	1
auto[3489660928:3623878655]	auto[1]	8	1			T253	1		T291	1		T424	2
auto[3623878656:3758096383]	auto[0]	129	1			T3	4		T43	1		T33	1
auto[3623878656:3758096383]	auto[1]	4	1			T148	2		T407	1		T253	1
auto[3758096384:3892314111]	auto[0]	153	1			T3	2		T18	1		T76	1
auto[3758096384:3892314111]	auto[1]	11	1			T1	1		T325	1		T407	1
auto[3892314112:4026531839]	auto[0]	121	1			T3	4		T17	1		T27	1
auto[3892314112:4026531839]	auto[1]	8	1			T148	1		T317	2		T254	1
auto[4026531840:4160749567]	auto[0]	146	1			T1	1		T3	4		T13	1
auto[4026531840:4160749567]	auto[1]	11	1			T148	2		T104	1		T106	1
auto[4160749568:4294967295]	auto[0]	151	1			T3	4		T88	1		T47	1
auto[4160749568:4294967295]	auto[1]	7	1			T322	1		T291	2		T182	2