Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.04 97.99 98.49 100.00 99.02 98.41 91.09


Total test records in report: 1088
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1003 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1223719941 Jul 12 06:44:14 PM PDT 24 Jul 12 06:44:17 PM PDT 24 9536423 ps
T1004 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.37593990 Jul 12 06:45:10 PM PDT 24 Jul 12 06:45:20 PM PDT 24 342379614 ps
T1005 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3736748904 Jul 12 06:44:35 PM PDT 24 Jul 12 06:44:44 PM PDT 24 361516455 ps
T1006 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1084946403 Jul 12 06:44:31 PM PDT 24 Jul 12 06:44:36 PM PDT 24 314826472 ps
T1007 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3777079381 Jul 12 06:44:08 PM PDT 24 Jul 12 06:44:16 PM PDT 24 188870858 ps
T1008 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.132463595 Jul 12 06:44:08 PM PDT 24 Jul 12 06:44:15 PM PDT 24 147073762 ps
T1009 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1152831019 Jul 12 06:44:21 PM PDT 24 Jul 12 06:44:24 PM PDT 24 40703219 ps
T1010 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1092595103 Jul 12 06:44:19 PM PDT 24 Jul 12 06:44:23 PM PDT 24 90533166 ps
T1011 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4190309681 Jul 12 06:44:15 PM PDT 24 Jul 12 06:44:21 PM PDT 24 214585905 ps
T1012 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3071695622 Jul 12 06:44:35 PM PDT 24 Jul 12 06:44:37 PM PDT 24 19287413 ps
T1013 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.387322948 Jul 12 06:44:40 PM PDT 24 Jul 12 06:44:41 PM PDT 24 58931931 ps
T1014 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2663215167 Jul 12 06:44:48 PM PDT 24 Jul 12 06:44:53 PM PDT 24 221484016 ps
T1015 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1518536022 Jul 12 06:44:32 PM PDT 24 Jul 12 06:44:35 PM PDT 24 43193689 ps
T1016 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2696625850 Jul 12 06:44:45 PM PDT 24 Jul 12 06:44:54 PM PDT 24 164175518 ps
T1017 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2870534934 Jul 12 06:44:37 PM PDT 24 Jul 12 06:44:38 PM PDT 24 19996319 ps
T1018 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.4263971667 Jul 12 06:44:29 PM PDT 24 Jul 12 06:44:32 PM PDT 24 29922445 ps
T1019 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3793332092 Jul 12 06:44:18 PM PDT 24 Jul 12 06:44:20 PM PDT 24 20160326 ps
T1020 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3649063942 Jul 12 06:44:44 PM PDT 24 Jul 12 06:44:55 PM PDT 24 667094835 ps
T1021 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2511660622 Jul 12 06:44:42 PM PDT 24 Jul 12 06:44:47 PM PDT 24 328111117 ps
T1022 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1736408780 Jul 12 06:44:31 PM PDT 24 Jul 12 06:44:33 PM PDT 24 42192430 ps
T1023 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2332571370 Jul 12 06:44:22 PM PDT 24 Jul 12 06:44:24 PM PDT 24 377312210 ps
T1024 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3765637315 Jul 12 06:44:30 PM PDT 24 Jul 12 06:44:34 PM PDT 24 151127815 ps
T1025 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3737596006 Jul 12 06:44:12 PM PDT 24 Jul 12 06:44:15 PM PDT 24 25661794 ps
T1026 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3721526640 Jul 12 06:44:28 PM PDT 24 Jul 12 06:44:31 PM PDT 24 28965611 ps
T1027 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2884776196 Jul 12 06:44:12 PM PDT 24 Jul 12 06:44:27 PM PDT 24 851361272 ps
T1028 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3248987958 Jul 12 06:44:35 PM PDT 24 Jul 12 06:44:36 PM PDT 24 49339312 ps
T1029 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2788422914 Jul 12 06:44:29 PM PDT 24 Jul 12 06:44:33 PM PDT 24 18569013 ps
T1030 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.694812768 Jul 12 06:44:26 PM PDT 24 Jul 12 06:44:30 PM PDT 24 199237644 ps
T1031 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1521323127 Jul 12 06:44:51 PM PDT 24 Jul 12 06:44:55 PM PDT 24 53673492 ps
T1032 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3114731195 Jul 12 06:44:39 PM PDT 24 Jul 12 06:44:41 PM PDT 24 19854982 ps
T1033 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3226889145 Jul 12 06:44:15 PM PDT 24 Jul 12 06:44:30 PM PDT 24 799017022 ps
T1034 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.4252714594 Jul 12 06:44:16 PM PDT 24 Jul 12 06:44:19 PM PDT 24 9786563 ps
T1035 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.351372161 Jul 12 06:44:21 PM PDT 24 Jul 12 06:44:26 PM PDT 24 139793663 ps
T1036 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2671531363 Jul 12 06:44:54 PM PDT 24 Jul 12 06:44:57 PM PDT 24 17289223 ps
T1037 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2875870790 Jul 12 06:44:12 PM PDT 24 Jul 12 06:44:17 PM PDT 24 36003833 ps
T1038 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2524067105 Jul 12 06:44:24 PM PDT 24 Jul 12 06:44:26 PM PDT 24 10793103 ps
T1039 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2424141300 Jul 12 06:44:33 PM PDT 24 Jul 12 06:44:37 PM PDT 24 117916848 ps
T1040 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.372853663 Jul 12 06:44:11 PM PDT 24 Jul 12 06:44:15 PM PDT 24 72639707 ps
T1041 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.557143433 Jul 12 06:44:27 PM PDT 24 Jul 12 06:44:30 PM PDT 24 152402309 ps
T1042 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3571667517 Jul 12 06:44:33 PM PDT 24 Jul 12 06:44:36 PM PDT 24 855934657 ps
T158 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2314427722 Jul 12 06:44:29 PM PDT 24 Jul 12 06:44:36 PM PDT 24 1066111527 ps
T1043 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3022828980 Jul 12 06:44:45 PM PDT 24 Jul 12 06:44:49 PM PDT 24 30889367 ps
T1044 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3621601681 Jul 12 06:44:57 PM PDT 24 Jul 12 06:44:59 PM PDT 24 18042173 ps
T1045 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3717760061 Jul 12 06:44:28 PM PDT 24 Jul 12 06:44:39 PM PDT 24 345961771 ps
T1046 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1018196133 Jul 12 06:44:38 PM PDT 24 Jul 12 06:44:39 PM PDT 24 10622360 ps
T163 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2928470319 Jul 12 06:44:26 PM PDT 24 Jul 12 06:44:32 PM PDT 24 128435138 ps
T1047 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.583125155 Jul 12 06:44:32 PM PDT 24 Jul 12 06:44:35 PM PDT 24 550941667 ps
T1048 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4100555024 Jul 12 06:44:35 PM PDT 24 Jul 12 06:44:39 PM PDT 24 120260493 ps
T1049 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3440028900 Jul 12 06:44:40 PM PDT 24 Jul 12 06:44:42 PM PDT 24 13296226 ps
T1050 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3227287934 Jul 12 06:44:27 PM PDT 24 Jul 12 06:44:29 PM PDT 24 13307392 ps
T1051 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1565857511 Jul 12 06:44:10 PM PDT 24 Jul 12 06:44:15 PM PDT 24 353142998 ps
T1052 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2086313252 Jul 12 06:44:27 PM PDT 24 Jul 12 06:44:31 PM PDT 24 24936592 ps
T1053 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1232312750 Jul 12 06:44:41 PM PDT 24 Jul 12 06:44:43 PM PDT 24 10357750 ps
T1054 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3156142297 Jul 12 06:44:46 PM PDT 24 Jul 12 06:44:50 PM PDT 24 24822360 ps
T1055 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3645181015 Jul 12 06:44:39 PM PDT 24 Jul 12 06:44:41 PM PDT 24 21823022 ps
T1056 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2737039530 Jul 12 06:44:48 PM PDT 24 Jul 12 06:44:53 PM PDT 24 320129727 ps
T1057 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.17398225 Jul 12 06:44:25 PM PDT 24 Jul 12 06:44:30 PM PDT 24 206073670 ps
T1058 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3267180368 Jul 12 06:44:28 PM PDT 24 Jul 12 06:44:31 PM PDT 24 45513380 ps
T1059 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.666248336 Jul 12 06:44:25 PM PDT 24 Jul 12 06:44:27 PM PDT 24 133720083 ps
T1060 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2630590558 Jul 12 06:44:34 PM PDT 24 Jul 12 06:44:36 PM PDT 24 82483585 ps
T1061 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2446358332 Jul 12 06:44:20 PM PDT 24 Jul 12 06:44:31 PM PDT 24 496635679 ps
T1062 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.4026071263 Jul 12 06:44:16 PM PDT 24 Jul 12 06:44:20 PM PDT 24 56977660 ps
T1063 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.780913953 Jul 12 06:44:23 PM PDT 24 Jul 12 06:44:31 PM PDT 24 575904164 ps
T1064 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.179913365 Jul 12 06:44:23 PM PDT 24 Jul 12 06:44:24 PM PDT 24 18543167 ps
T1065 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3199071402 Jul 12 06:44:14 PM PDT 24 Jul 12 06:44:28 PM PDT 24 1325744012 ps
T1066 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1864226499 Jul 12 06:44:10 PM PDT 24 Jul 12 06:44:15 PM PDT 24 171216196 ps
T1067 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1123656817 Jul 12 06:44:51 PM PDT 24 Jul 12 06:44:59 PM PDT 24 349805946 ps
T1068 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2452214199 Jul 12 06:44:21 PM PDT 24 Jul 12 06:44:23 PM PDT 24 262082869 ps
T1069 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2334926840 Jul 12 06:44:55 PM PDT 24 Jul 12 06:44:58 PM PDT 24 23882293 ps
T1070 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3682907861 Jul 12 06:44:39 PM PDT 24 Jul 12 06:44:41 PM PDT 24 35824579 ps
T1071 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3978755892 Jul 12 06:44:27 PM PDT 24 Jul 12 06:44:31 PM PDT 24 179670481 ps
T1072 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3353335148 Jul 12 06:44:10 PM PDT 24 Jul 12 06:44:18 PM PDT 24 321900370 ps
T1073 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1682678589 Jul 12 06:44:48 PM PDT 24 Jul 12 06:44:52 PM PDT 24 38022388 ps
T1074 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3065229449 Jul 12 06:44:49 PM PDT 24 Jul 12 06:44:55 PM PDT 24 250562782 ps
T1075 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.462963484 Jul 12 06:44:15 PM PDT 24 Jul 12 06:44:23 PM PDT 24 2952026858 ps
T1076 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2099593370 Jul 12 06:44:09 PM PDT 24 Jul 12 06:44:14 PM PDT 24 31976579 ps
T1077 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1341670486 Jul 12 06:44:17 PM PDT 24 Jul 12 06:44:21 PM PDT 24 179650780 ps
T1078 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3401411558 Jul 12 06:44:50 PM PDT 24 Jul 12 06:45:08 PM PDT 24 993279547 ps
T1079 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.904621676 Jul 12 06:48:49 PM PDT 24 Jul 12 06:48:51 PM PDT 24 25467841 ps
T1080 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4046142969 Jul 12 06:44:18 PM PDT 24 Jul 12 06:44:20 PM PDT 24 38946362 ps
T1081 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2044794906 Jul 12 06:44:32 PM PDT 24 Jul 12 06:44:34 PM PDT 24 95759189 ps
T1082 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.736627293 Jul 12 06:44:15 PM PDT 24 Jul 12 06:44:34 PM PDT 24 1280787257 ps
T1083 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1070911240 Jul 12 06:44:06 PM PDT 24 Jul 12 06:44:15 PM PDT 24 71542036 ps
T1084 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2673157688 Jul 12 06:44:19 PM PDT 24 Jul 12 06:44:28 PM PDT 24 229682866 ps
T1085 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.293045605 Jul 12 06:44:27 PM PDT 24 Jul 12 06:44:30 PM PDT 24 32016330 ps
T1086 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1974812528 Jul 12 06:44:33 PM PDT 24 Jul 12 06:44:45 PM PDT 24 1342992251 ps
T1087 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3577310319 Jul 12 06:44:21 PM PDT 24 Jul 12 06:44:23 PM PDT 24 27535109 ps
T1088 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2316718831 Jul 12 06:44:32 PM PDT 24 Jul 12 06:44:36 PM PDT 24 73244715 ps

Test location /workspace/coverage/default/34.keymgr_stress_all.2428411506
Short name T3
Test name
Test status
Simulation time 1372951925 ps
CPU time 51.79 seconds
Started Jul 12 06:41:30 PM PDT 24
Finished Jul 12 06:42:25 PM PDT 24
Peak memory 222500 kb
Host smart-ddbfdcf3-45dd-460a-820e-9be80e97d63d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428411506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2428411506
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2600821059
Short name T44
Test name
Test status
Simulation time 1260627053 ps
CPU time 9.7 seconds
Started Jul 12 06:40:16 PM PDT 24
Finished Jul 12 06:40:30 PM PDT 24
Peak memory 222596 kb
Host smart-d332e9d7-dba2-4972-9cf9-1d44907e506e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600821059 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2600821059
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.769928537
Short name T4
Test name
Test status
Simulation time 1767478204 ps
CPU time 22.97 seconds
Started Jul 12 06:42:02 PM PDT 24
Finished Jul 12 06:42:27 PM PDT 24
Peak memory 220580 kb
Host smart-0ad81164-e883-4427-98d5-8062d7bcad06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769928537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.769928537
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2298697281
Short name T10
Test name
Test status
Simulation time 345861441 ps
CPU time 7.71 seconds
Started Jul 12 06:39:50 PM PDT 24
Finished Jul 12 06:39:59 PM PDT 24
Peak memory 233788 kb
Host smart-e56e2862-b6fa-4bfd-9413-53dec82fe0e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298697281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2298697281
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.97925600
Short name T57
Test name
Test status
Simulation time 25657234398 ps
CPU time 55.92 seconds
Started Jul 12 06:42:11 PM PDT 24
Finished Jul 12 06:43:10 PM PDT 24
Peak memory 222524 kb
Host smart-23ae25eb-ff56-4238-aeac-f2f547c673da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97925600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.97925600
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.887454124
Short name T149
Test name
Test status
Simulation time 144425992 ps
CPU time 5.64 seconds
Started Jul 12 06:44:48 PM PDT 24
Finished Jul 12 06:44:57 PM PDT 24
Peak memory 205832 kb
Host smart-91c1c9e8-ea5c-4a18-b3b1-0b3e4927f916
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887454124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.887454124
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2567530733
Short name T1
Test name
Test status
Simulation time 41511157 ps
CPU time 3.34 seconds
Started Jul 12 06:41:15 PM PDT 24
Finished Jul 12 06:41:21 PM PDT 24
Peak memory 214384 kb
Host smart-78e1f75e-a426-444f-bace-2c107ab0f8eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2567530733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2567530733
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3271743465
Short name T33
Test name
Test status
Simulation time 180696079 ps
CPU time 4.53 seconds
Started Jul 12 06:41:10 PM PDT 24
Finished Jul 12 06:41:18 PM PDT 24
Peak memory 214256 kb
Host smart-b7b0c967-d7c9-4bb4-9ec6-f87b548e3dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271743465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3271743465
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.131326942
Short name T7
Test name
Test status
Simulation time 124188607 ps
CPU time 2.13 seconds
Started Jul 12 06:42:22 PM PDT 24
Finished Jul 12 06:42:28 PM PDT 24
Peak memory 210140 kb
Host smart-449b8b26-4129-4bca-8391-03642728d397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131326942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.131326942
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.962834443
Short name T253
Test name
Test status
Simulation time 1597182303 ps
CPU time 41.5 seconds
Started Jul 12 06:41:02 PM PDT 24
Finished Jul 12 06:41:44 PM PDT 24
Peak memory 214656 kb
Host smart-ec251ecc-0bca-4551-ab5a-8254cc50ade9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=962834443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.962834443
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.2727247484
Short name T63
Test name
Test status
Simulation time 2721939984 ps
CPU time 21.05 seconds
Started Jul 12 06:41:59 PM PDT 24
Finished Jul 12 06:42:22 PM PDT 24
Peak memory 222772 kb
Host smart-536be2fd-5e5d-408c-ba43-eae76ae9015a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727247484 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.2727247484
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1982818160
Short name T53
Test name
Test status
Simulation time 1124384975 ps
CPU time 17.08 seconds
Started Jul 12 06:40:42 PM PDT 24
Finished Jul 12 06:41:01 PM PDT 24
Peak memory 222612 kb
Host smart-2767cf69-88f4-4d38-9b63-95a5d17db04b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982818160 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1982818160
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1952290711
Short name T119
Test name
Test status
Simulation time 58077186 ps
CPU time 2.1 seconds
Started Jul 12 06:44:28 PM PDT 24
Finished Jul 12 06:44:32 PM PDT 24
Peak memory 214028 kb
Host smart-be0ed883-c180-47e5-ab2d-1b110e253ea5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952290711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1952290711
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.264544148
Short name T263
Test name
Test status
Simulation time 540813316 ps
CPU time 22.9 seconds
Started Jul 12 06:40:18 PM PDT 24
Finished Jul 12 06:40:47 PM PDT 24
Peak memory 215568 kb
Host smart-85ae1de8-9fe5-4521-b160-1d1eefa0e825
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=264544148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.264544148
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2438403817
Short name T40
Test name
Test status
Simulation time 69730093 ps
CPU time 1.91 seconds
Started Jul 12 06:40:18 PM PDT 24
Finished Jul 12 06:40:26 PM PDT 24
Peak memory 209976 kb
Host smart-3f507181-b9c3-4f04-a599-89d41b1a4f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438403817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2438403817
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.400353927
Short name T134
Test name
Test status
Simulation time 890753760 ps
CPU time 30.25 seconds
Started Jul 12 06:40:59 PM PDT 24
Finished Jul 12 06:41:30 PM PDT 24
Peak memory 222500 kb
Host smart-4abde3f4-d52d-4232-b5b6-256d67737432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400353927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.400353927
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3976368496
Short name T87
Test name
Test status
Simulation time 471366447 ps
CPU time 4.06 seconds
Started Jul 12 06:40:51 PM PDT 24
Finished Jul 12 06:40:58 PM PDT 24
Peak memory 214320 kb
Host smart-b0eb967c-ded5-44e0-9f4c-ca9c3b1102f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976368496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3976368496
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3112836319
Short name T348
Test name
Test status
Simulation time 537597082 ps
CPU time 26.79 seconds
Started Jul 12 06:40:39 PM PDT 24
Finished Jul 12 06:41:06 PM PDT 24
Peak memory 214488 kb
Host smart-b1f8379a-3917-43c1-a26d-7a2fa0ba2563
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3112836319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3112836319
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1001834076
Short name T291
Test name
Test status
Simulation time 7055028490 ps
CPU time 49.71 seconds
Started Jul 12 06:42:09 PM PDT 24
Finished Jul 12 06:43:01 PM PDT 24
Peak memory 215812 kb
Host smart-4c086d67-a15e-4e60-8dd7-31029dce8b0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1001834076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1001834076
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.302684428
Short name T89
Test name
Test status
Simulation time 1195048395 ps
CPU time 10.72 seconds
Started Jul 12 06:41:43 PM PDT 24
Finished Jul 12 06:41:55 PM PDT 24
Peak memory 214328 kb
Host smart-fd222d95-0ba0-4cc1-be48-de4793df7ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302684428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.302684428
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2281864713
Short name T595
Test name
Test status
Simulation time 161182995 ps
CPU time 4.63 seconds
Started Jul 12 06:40:13 PM PDT 24
Finished Jul 12 06:40:21 PM PDT 24
Peak memory 209712 kb
Host smart-b17c7258-7afd-4621-ba1b-81b731029bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281864713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2281864713
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3894049108
Short name T231
Test name
Test status
Simulation time 4499542756 ps
CPU time 17.03 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:35 PM PDT 24
Peak memory 215300 kb
Host smart-dbafc29c-181d-4f15-9ed3-ea7f7a00be5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894049108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3894049108
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.4177296131
Short name T407
Test name
Test status
Simulation time 4582486738 ps
CPU time 12.36 seconds
Started Jul 12 06:40:46 PM PDT 24
Finished Jul 12 06:41:00 PM PDT 24
Peak memory 222484 kb
Host smart-62441313-1924-4c9f-b19f-056fd009b6f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4177296131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.4177296131
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1646944745
Short name T114
Test name
Test status
Simulation time 252728889 ps
CPU time 5.55 seconds
Started Jul 12 06:44:45 PM PDT 24
Finished Jul 12 06:44:54 PM PDT 24
Peak memory 214068 kb
Host smart-58006e39-8fa0-4cb2-93da-c3b74428504c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646944745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1646944745
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1123130804
Short name T43
Test name
Test status
Simulation time 86437742 ps
CPU time 4.06 seconds
Started Jul 12 06:41:51 PM PDT 24
Finished Jul 12 06:41:57 PM PDT 24
Peak memory 210496 kb
Host smart-96881a3c-9354-4e2f-9ecc-03a51a3054fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123130804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1123130804
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.251531554
Short name T172
Test name
Test status
Simulation time 628252095 ps
CPU time 4.44 seconds
Started Jul 12 06:42:10 PM PDT 24
Finished Jul 12 06:42:17 PM PDT 24
Peak memory 222592 kb
Host smart-098ea516-9663-43ef-b5ad-04ddf7197baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251531554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.251531554
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.4153908176
Short name T37
Test name
Test status
Simulation time 216616718 ps
CPU time 3.05 seconds
Started Jul 12 06:40:39 PM PDT 24
Finished Jul 12 06:40:43 PM PDT 24
Peak memory 210424 kb
Host smart-46ee865f-6579-4e1e-93f7-3772380d8660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153908176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.4153908176
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1752697909
Short name T205
Test name
Test status
Simulation time 813723852 ps
CPU time 28.66 seconds
Started Jul 12 06:40:51 PM PDT 24
Finished Jul 12 06:41:23 PM PDT 24
Peak memory 222400 kb
Host smart-dec252d3-c549-482b-a913-280341925c56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752697909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1752697909
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2903634912
Short name T755
Test name
Test status
Simulation time 159899496 ps
CPU time 2.08 seconds
Started Jul 12 06:39:57 PM PDT 24
Finished Jul 12 06:40:00 PM PDT 24
Peak memory 208632 kb
Host smart-87a47550-65f0-4f97-aa2d-c796ae0ee20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903634912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2903634912
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.393976678
Short name T238
Test name
Test status
Simulation time 62100817801 ps
CPU time 455.74 seconds
Started Jul 12 06:42:54 PM PDT 24
Finished Jul 12 06:50:32 PM PDT 24
Peak memory 222576 kb
Host smart-1727a928-b054-4b80-a3ec-7a3ff2ec3ccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393976678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.393976678
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3018029594
Short name T346
Test name
Test status
Simulation time 364393277 ps
CPU time 10.13 seconds
Started Jul 12 06:39:57 PM PDT 24
Finished Jul 12 06:40:08 PM PDT 24
Peak memory 215260 kb
Host smart-e929ea7c-23a0-47e3-8707-2e6c490d4c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3018029594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3018029594
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.4128342390
Short name T81
Test name
Test status
Simulation time 131919827 ps
CPU time 2.67 seconds
Started Jul 12 06:41:00 PM PDT 24
Finished Jul 12 06:41:04 PM PDT 24
Peak memory 214488 kb
Host smart-234ee56e-0fd1-41a3-ae4f-ad572a410d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128342390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4128342390
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.301388575
Short name T67
Test name
Test status
Simulation time 859845798 ps
CPU time 33.2 seconds
Started Jul 12 06:41:19 PM PDT 24
Finished Jul 12 06:41:54 PM PDT 24
Peak memory 219540 kb
Host smart-3a1a8120-fd91-4979-a010-708f4fa31cdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301388575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.301388575
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1151511603
Short name T148
Test name
Test status
Simulation time 1419074325 ps
CPU time 46.96 seconds
Started Jul 12 06:41:04 PM PDT 24
Finished Jul 12 06:41:53 PM PDT 24
Peak memory 215216 kb
Host smart-31e4e4c0-1cf2-4623-9541-f32f1bf9d200
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1151511603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1151511603
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3021989681
Short name T465
Test name
Test status
Simulation time 32209469 ps
CPU time 0.96 seconds
Started Jul 12 06:40:22 PM PDT 24
Finished Jul 12 06:40:27 PM PDT 24
Peak memory 206040 kb
Host smart-30d73a05-9619-43ce-9784-ed74be394fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021989681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3021989681
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2081265996
Short name T239
Test name
Test status
Simulation time 1424818747 ps
CPU time 36.27 seconds
Started Jul 12 06:41:45 PM PDT 24
Finished Jul 12 06:42:22 PM PDT 24
Peak memory 222472 kb
Host smart-0610e44f-b65b-48a6-89f5-8e43822b6a34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081265996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2081265996
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.969824054
Short name T101
Test name
Test status
Simulation time 116352746 ps
CPU time 2.23 seconds
Started Jul 12 06:41:22 PM PDT 24
Finished Jul 12 06:41:28 PM PDT 24
Peak memory 220676 kb
Host smart-731ac8b2-2feb-4e2f-b38d-be46750eb1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969824054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.969824054
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3324397303
Short name T153
Test name
Test status
Simulation time 258003393 ps
CPU time 4.93 seconds
Started Jul 12 06:44:24 PM PDT 24
Finished Jul 12 06:44:30 PM PDT 24
Peak memory 215268 kb
Host smart-e0cd9137-ec9c-4b55-ab81-7c375f3119f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324397303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3324397303
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1296404473
Short name T298
Test name
Test status
Simulation time 1858897081 ps
CPU time 36.07 seconds
Started Jul 12 06:41:33 PM PDT 24
Finished Jul 12 06:42:12 PM PDT 24
Peak memory 220620 kb
Host smart-5133ddb6-7ae0-4a9d-b02d-f27ae2f8cf06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296404473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1296404473
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3521717615
Short name T112
Test name
Test status
Simulation time 186567616 ps
CPU time 1.3 seconds
Started Jul 12 06:44:33 PM PDT 24
Finished Jul 12 06:44:36 PM PDT 24
Peak memory 214156 kb
Host smart-984b6fcd-5dfa-4b1b-8715-507e3cbc9e29
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521717615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3521717615
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1599125101
Short name T55
Test name
Test status
Simulation time 490958605 ps
CPU time 19.98 seconds
Started Jul 12 06:41:57 PM PDT 24
Finished Jul 12 06:42:19 PM PDT 24
Peak memory 216808 kb
Host smart-0f0d424c-481a-4895-a5e3-007d30d0c8b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599125101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1599125101
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2805207526
Short name T297
Test name
Test status
Simulation time 72704679 ps
CPU time 4.2 seconds
Started Jul 12 06:40:16 PM PDT 24
Finished Jul 12 06:40:26 PM PDT 24
Peak memory 214324 kb
Host smart-56b83a3f-526d-4c38-bd2b-02bc327bc8bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2805207526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2805207526
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3768197745
Short name T159
Test name
Test status
Simulation time 381089393 ps
CPU time 4.51 seconds
Started Jul 12 06:44:25 PM PDT 24
Finished Jul 12 06:44:31 PM PDT 24
Peak memory 205464 kb
Host smart-67a94069-7c2b-4886-8679-e10686b1043e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768197745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3768197745
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2224733226
Short name T26
Test name
Test status
Simulation time 186228018 ps
CPU time 5.91 seconds
Started Jul 12 06:41:41 PM PDT 24
Finished Jul 12 06:41:48 PM PDT 24
Peak memory 209368 kb
Host smart-d0fd4d2c-0307-4256-8ab9-2523664e6da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224733226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2224733226
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1839123926
Short name T175
Test name
Test status
Simulation time 279391924 ps
CPU time 5.3 seconds
Started Jul 12 06:41:37 PM PDT 24
Finished Jul 12 06:41:44 PM PDT 24
Peak memory 218496 kb
Host smart-d85fefac-403a-4e64-8ca9-8b2a267dcb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839123926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1839123926
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1704775831
Short name T82
Test name
Test status
Simulation time 33257344 ps
CPU time 2.49 seconds
Started Jul 12 06:40:17 PM PDT 24
Finished Jul 12 06:40:24 PM PDT 24
Peak memory 214796 kb
Host smart-ad9742d4-8428-431a-864d-c9737ff870d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704775831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1704775831
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.323088274
Short name T322
Test name
Test status
Simulation time 893275614 ps
CPU time 12.69 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:45 PM PDT 24
Peak memory 215264 kb
Host smart-f67b89ce-dc91-4ebe-b76c-9030ec565e8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=323088274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.323088274
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2314427722
Short name T158
Test name
Test status
Simulation time 1066111527 ps
CPU time 4.95 seconds
Started Jul 12 06:44:29 PM PDT 24
Finished Jul 12 06:44:36 PM PDT 24
Peak memory 215108 kb
Host smart-f945fd85-3b43-4a23-b0b6-54ce9cc46e1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314427722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2314427722
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1254151479
Short name T32
Test name
Test status
Simulation time 272375194 ps
CPU time 5.32 seconds
Started Jul 12 06:40:51 PM PDT 24
Finished Jul 12 06:41:00 PM PDT 24
Peak memory 210472 kb
Host smart-c93e52b9-0176-4a51-94db-595e8efaa69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254151479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1254151479
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3990478334
Short name T170
Test name
Test status
Simulation time 57873414 ps
CPU time 3.18 seconds
Started Jul 12 06:41:03 PM PDT 24
Finished Jul 12 06:41:07 PM PDT 24
Peak memory 218044 kb
Host smart-88df3971-a5fc-4652-b68f-404dbf15fe4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990478334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3990478334
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.823343820
Short name T69
Test name
Test status
Simulation time 591368550 ps
CPU time 28.26 seconds
Started Jul 12 06:40:24 PM PDT 24
Finished Jul 12 06:40:56 PM PDT 24
Peak memory 220956 kb
Host smart-b88dd8ea-2fc6-4690-a613-07f1e8b7f9ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823343820 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.823343820
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1681102094
Short name T285
Test name
Test status
Simulation time 30367506 ps
CPU time 2.13 seconds
Started Jul 12 06:40:34 PM PDT 24
Finished Jul 12 06:40:39 PM PDT 24
Peak memory 214272 kb
Host smart-8d2c4e30-3e87-46fd-add1-15eac2fcdac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681102094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1681102094
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.183754234
Short name T358
Test name
Test status
Simulation time 104909240 ps
CPU time 1.9 seconds
Started Jul 12 06:40:40 PM PDT 24
Finished Jul 12 06:40:43 PM PDT 24
Peak memory 214360 kb
Host smart-0b10497d-a5e6-4087-acb2-4a04abaa5b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183754234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.183754234
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2233660388
Short name T164
Test name
Test status
Simulation time 108706073 ps
CPU time 4.54 seconds
Started Jul 12 06:44:35 PM PDT 24
Finished Jul 12 06:44:40 PM PDT 24
Peak memory 205576 kb
Host smart-7e432cf6-9ec1-4e8d-8024-7ce199c1be52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233660388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2233660388
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1270217938
Short name T156
Test name
Test status
Simulation time 1150898067 ps
CPU time 7.2 seconds
Started Jul 12 06:44:49 PM PDT 24
Finished Jul 12 06:44:59 PM PDT 24
Peak memory 205612 kb
Host smart-dbdac7c3-c5e4-44a8-b2b2-0927ca4b7bc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270217938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1270217938
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.812334341
Short name T11
Test name
Test status
Simulation time 3814073021 ps
CPU time 18.26 seconds
Started Jul 12 06:39:55 PM PDT 24
Finished Jul 12 06:40:15 PM PDT 24
Peak memory 235440 kb
Host smart-e27d428d-2446-422c-8ad2-feb400968bb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812334341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.812334341
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.564068962
Short name T86
Test name
Test status
Simulation time 236492016 ps
CPU time 3.7 seconds
Started Jul 12 06:41:22 PM PDT 24
Finished Jul 12 06:41:30 PM PDT 24
Peak memory 220572 kb
Host smart-138ad159-0993-469d-8a30-3184047583ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564068962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.564068962
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3479816172
Short name T911
Test name
Test status
Simulation time 302360915 ps
CPU time 8.8 seconds
Started Jul 12 06:39:49 PM PDT 24
Finished Jul 12 06:40:00 PM PDT 24
Peak memory 215156 kb
Host smart-30984944-e8b4-46a0-8faf-df2100dcaccb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3479816172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3479816172
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.338615927
Short name T79
Test name
Test status
Simulation time 442507110 ps
CPU time 4.39 seconds
Started Jul 12 06:41:15 PM PDT 24
Finished Jul 12 06:41:23 PM PDT 24
Peak memory 215460 kb
Host smart-1b446e3e-0cec-4323-834d-c40f4c8df1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338615927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.338615927
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.926988325
Short name T638
Test name
Test status
Simulation time 373429986 ps
CPU time 5.57 seconds
Started Jul 12 06:41:30 PM PDT 24
Finished Jul 12 06:41:39 PM PDT 24
Peak memory 208792 kb
Host smart-4aa06924-e233-4d10-9da0-0c0185e6e5ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926988325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.926988325
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3080414825
Short name T173
Test name
Test status
Simulation time 124127114 ps
CPU time 5.97 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:31 PM PDT 24
Peak memory 218672 kb
Host smart-e32d123f-8e39-4436-b0e9-0a00166fb5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080414825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3080414825
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3378118902
Short name T171
Test name
Test status
Simulation time 2371615409 ps
CPU time 34.89 seconds
Started Jul 12 06:41:05 PM PDT 24
Finished Jul 12 06:41:42 PM PDT 24
Peak memory 218776 kb
Host smart-82647506-fac1-473d-8127-1357c0ea9fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378118902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3378118902
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3330445753
Short name T174
Test name
Test status
Simulation time 268349999 ps
CPU time 2.62 seconds
Started Jul 12 06:41:27 PM PDT 24
Finished Jul 12 06:41:33 PM PDT 24
Peak memory 222652 kb
Host smart-85766671-7d91-4bb1-9c0e-a60e2b49668e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330445753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3330445753
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.829945616
Short name T19
Test name
Test status
Simulation time 67173683 ps
CPU time 3.44 seconds
Started Jul 12 06:39:51 PM PDT 24
Finished Jul 12 06:39:55 PM PDT 24
Peak memory 218200 kb
Host smart-98682d4e-6c8d-45a8-8b5f-ab60eb2e632b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829945616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.829945616
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2232608540
Short name T494
Test name
Test status
Simulation time 887040829 ps
CPU time 27.9 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:41:00 PM PDT 24
Peak memory 208156 kb
Host smart-277ced18-d00d-44a4-88ad-892a9dc705b7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232608540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2232608540
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2179332102
Short name T248
Test name
Test status
Simulation time 4480892943 ps
CPU time 29.78 seconds
Started Jul 12 06:40:40 PM PDT 24
Finished Jul 12 06:41:11 PM PDT 24
Peak memory 216548 kb
Host smart-d83ae23e-1147-4e2c-8d8c-77644a193777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179332102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2179332102
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1155026215
Short name T307
Test name
Test status
Simulation time 150995289 ps
CPU time 3.14 seconds
Started Jul 12 06:41:00 PM PDT 24
Finished Jul 12 06:41:05 PM PDT 24
Peak memory 214316 kb
Host smart-6e6e939c-6fd7-4891-9136-7cde42e359b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155026215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1155026215
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2519500122
Short name T426
Test name
Test status
Simulation time 113157096 ps
CPU time 3.2 seconds
Started Jul 12 06:41:02 PM PDT 24
Finished Jul 12 06:41:06 PM PDT 24
Peak memory 214348 kb
Host smart-c6508909-0178-4a42-8564-e19556ddd789
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2519500122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2519500122
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.4213228155
Short name T396
Test name
Test status
Simulation time 245371575 ps
CPU time 4.29 seconds
Started Jul 12 06:41:11 PM PDT 24
Finished Jul 12 06:41:20 PM PDT 24
Peak memory 214324 kb
Host smart-7badfbc6-2199-4a78-907f-def041de2909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213228155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.4213228155
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.336828684
Short name T869
Test name
Test status
Simulation time 125946788 ps
CPU time 5.53 seconds
Started Jul 12 06:41:16 PM PDT 24
Finished Jul 12 06:41:24 PM PDT 24
Peak memory 222236 kb
Host smart-deb750fd-0533-4505-b265-9dce9e110030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336828684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.336828684
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2014174962
Short name T124
Test name
Test status
Simulation time 2502442290 ps
CPU time 26.73 seconds
Started Jul 12 06:42:15 PM PDT 24
Finished Jul 12 06:42:46 PM PDT 24
Peak memory 222612 kb
Host smart-0fbab760-5840-4d4b-8b7e-5c3fb1397de4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014174962 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2014174962
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1452479329
Short name T259
Test name
Test status
Simulation time 232246550 ps
CPU time 4.08 seconds
Started Jul 12 06:40:16 PM PDT 24
Finished Jul 12 06:40:25 PM PDT 24
Peak memory 209964 kb
Host smart-9ba28abf-2a6a-402b-8284-88bead744ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452479329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1452479329
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1626129446
Short name T161
Test name
Test status
Simulation time 204212724 ps
CPU time 6.01 seconds
Started Jul 12 06:44:08 PM PDT 24
Finished Jul 12 06:44:18 PM PDT 24
Peak memory 213748 kb
Host smart-d42c3055-1fca-4708-a526-ba5f9be88323
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626129446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1626129446
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.4116251814
Short name T154
Test name
Test status
Simulation time 212660466 ps
CPU time 6.22 seconds
Started Jul 12 06:44:11 PM PDT 24
Finished Jul 12 06:44:20 PM PDT 24
Peak memory 205524 kb
Host smart-510bcaa8-ba0e-4837-9d45-172576a597db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116251814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.4116251814
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.4155732945
Short name T23
Test name
Test status
Simulation time 65382967 ps
CPU time 1.78 seconds
Started Jul 12 06:39:55 PM PDT 24
Finished Jul 12 06:39:58 PM PDT 24
Peak memory 208172 kb
Host smart-7a4e5c0f-3d6d-49a6-acba-5c8b5f7923fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155732945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.4155732945
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3063154165
Short name T169
Test name
Test status
Simulation time 343422673 ps
CPU time 3.47 seconds
Started Jul 12 06:40:13 PM PDT 24
Finished Jul 12 06:40:20 PM PDT 24
Peak memory 217964 kb
Host smart-74621e1c-ac36-492c-8439-71073a665fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063154165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3063154165
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2498225063
Short name T65
Test name
Test status
Simulation time 21535045 ps
CPU time 1.45 seconds
Started Jul 12 06:42:08 PM PDT 24
Finished Jul 12 06:42:11 PM PDT 24
Peak memory 213236 kb
Host smart-be751fa2-f27d-488f-aad7-93df1f98f810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498225063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2498225063
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.557712858
Short name T180
Test name
Test status
Simulation time 2807573899 ps
CPU time 16.08 seconds
Started Jul 12 06:44:13 PM PDT 24
Finished Jul 12 06:44:31 PM PDT 24
Peak memory 205540 kb
Host smart-6c1e1e78-25a2-442e-9d09-6cb7a36e3730
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557712858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.557712858
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1598819280
Short name T395
Test name
Test status
Simulation time 108809014 ps
CPU time 2.13 seconds
Started Jul 12 06:39:59 PM PDT 24
Finished Jul 12 06:40:03 PM PDT 24
Peak memory 214260 kb
Host smart-a06f7e2b-fef8-400b-ac2c-006133e0f8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598819280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1598819280
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.335097563
Short name T251
Test name
Test status
Simulation time 223102960 ps
CPU time 3.73 seconds
Started Jul 12 06:40:19 PM PDT 24
Finished Jul 12 06:40:28 PM PDT 24
Peak memory 214324 kb
Host smart-65dafb6a-89d5-42a2-a30a-3323b7f377b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335097563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.335097563
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1383082723
Short name T304
Test name
Test status
Simulation time 244137971 ps
CPU time 5.1 seconds
Started Jul 12 06:40:30 PM PDT 24
Finished Jul 12 06:40:39 PM PDT 24
Peak memory 215420 kb
Host smart-a5b22e0d-fab5-4a1b-a1ed-2005b58a531f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383082723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1383082723
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.964655363
Short name T207
Test name
Test status
Simulation time 5982389227 ps
CPU time 41.15 seconds
Started Jul 12 06:40:30 PM PDT 24
Finished Jul 12 06:41:15 PM PDT 24
Peak memory 222528 kb
Host smart-7ac6a8ee-3a74-42cf-b827-15c9e095bf1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964655363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.964655363
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.447401108
Short name T254
Test name
Test status
Simulation time 16236270372 ps
CPU time 88.37 seconds
Started Jul 12 06:40:35 PM PDT 24
Finished Jul 12 06:42:06 PM PDT 24
Peak memory 215028 kb
Host smart-74de656a-b1d5-404a-8dce-95ca41036905
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=447401108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.447401108
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1311659197
Short name T351
Test name
Test status
Simulation time 475757816 ps
CPU time 20.09 seconds
Started Jul 12 06:40:33 PM PDT 24
Finished Jul 12 06:40:56 PM PDT 24
Peak memory 222528 kb
Host smart-39f2952a-4070-41a7-a4c5-e4530674ab93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311659197 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1311659197
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2581193459
Short name T234
Test name
Test status
Simulation time 202704843 ps
CPU time 9.43 seconds
Started Jul 12 06:40:42 PM PDT 24
Finished Jul 12 06:40:54 PM PDT 24
Peak memory 210040 kb
Host smart-ea04341e-696f-4f49-846a-b505f56e40f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581193459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2581193459
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1795960300
Short name T282
Test name
Test status
Simulation time 185838243 ps
CPU time 4.54 seconds
Started Jul 12 06:40:46 PM PDT 24
Finished Jul 12 06:40:52 PM PDT 24
Peak memory 214300 kb
Host smart-aa7210b6-6feb-47c3-b0d2-1fdb2d3bfda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795960300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1795960300
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3781930665
Short name T284
Test name
Test status
Simulation time 812750072 ps
CPU time 2.87 seconds
Started Jul 12 06:40:47 PM PDT 24
Finished Jul 12 06:40:52 PM PDT 24
Peak memory 208184 kb
Host smart-f551f0e9-f6bb-4318-9fe2-4724a7cd0ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781930665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3781930665
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2659625481
Short name T230
Test name
Test status
Simulation time 81900785 ps
CPU time 2.57 seconds
Started Jul 12 06:40:12 PM PDT 24
Finished Jul 12 06:40:17 PM PDT 24
Peak memory 208856 kb
Host smart-b227d254-1e86-4722-8330-3da092282d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659625481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2659625481
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1919319524
Short name T468
Test name
Test status
Simulation time 131716580 ps
CPU time 2.79 seconds
Started Jul 12 06:40:00 PM PDT 24
Finished Jul 12 06:40:05 PM PDT 24
Peak memory 209972 kb
Host smart-cd96eb08-dff0-4fa4-861e-5a2811795c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919319524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1919319524
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3403299185
Short name T377
Test name
Test status
Simulation time 525499082 ps
CPU time 4.04 seconds
Started Jul 12 06:40:53 PM PDT 24
Finished Jul 12 06:41:00 PM PDT 24
Peak memory 214236 kb
Host smart-3725eecd-5253-4da1-adcf-c21a2eeeb2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403299185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3403299185
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1484386406
Short name T29
Test name
Test status
Simulation time 834742451 ps
CPU time 6.56 seconds
Started Jul 12 06:41:01 PM PDT 24
Finished Jul 12 06:41:08 PM PDT 24
Peak memory 210484 kb
Host smart-3f0d86f5-a5a1-436d-af8c-72d45781a4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484386406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1484386406
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.4115515274
Short name T68
Test name
Test status
Simulation time 2774877478 ps
CPU time 32.21 seconds
Started Jul 12 06:41:04 PM PDT 24
Finished Jul 12 06:41:38 PM PDT 24
Peak memory 216484 kb
Host smart-2275a245-6594-4178-b075-ff315eae75b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115515274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.4115515274
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1705071413
Short name T246
Test name
Test status
Simulation time 328223237 ps
CPU time 11.94 seconds
Started Jul 12 06:41:05 PM PDT 24
Finished Jul 12 06:41:19 PM PDT 24
Peak memory 215640 kb
Host smart-d4b4fcda-5e49-40bf-8258-39f425c1403e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705071413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1705071413
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sideload.882463743
Short name T323
Test name
Test status
Simulation time 194632906 ps
CPU time 3.33 seconds
Started Jul 12 06:41:19 PM PDT 24
Finished Jul 12 06:41:24 PM PDT 24
Peak memory 208520 kb
Host smart-2e4e901e-0ead-4c64-8a6a-c3498c623c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882463743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.882463743
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2477524378
Short name T802
Test name
Test status
Simulation time 107440721 ps
CPU time 3.98 seconds
Started Jul 12 06:41:26 PM PDT 24
Finished Jul 12 06:41:33 PM PDT 24
Peak memory 214116 kb
Host smart-310a5a9a-7d5f-4d6e-a09d-6a88de5d0a42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2477524378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2477524378
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2717022572
Short name T329
Test name
Test status
Simulation time 128022073 ps
CPU time 3.42 seconds
Started Jul 12 06:41:46 PM PDT 24
Finished Jul 12 06:41:51 PM PDT 24
Peak memory 215560 kb
Host smart-e4ba3ece-93a2-4843-ae6b-85946bbff57a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2717022572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2717022572
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3709692002
Short name T375
Test name
Test status
Simulation time 900273878 ps
CPU time 7.04 seconds
Started Jul 12 06:40:03 PM PDT 24
Finished Jul 12 06:40:12 PM PDT 24
Peak memory 208700 kb
Host smart-385ae3b8-e942-49a4-98ec-5b8f50165524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709692002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3709692002
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2577938653
Short name T376
Test name
Test status
Simulation time 40870213 ps
CPU time 2.37 seconds
Started Jul 12 06:41:52 PM PDT 24
Finished Jul 12 06:41:57 PM PDT 24
Peak memory 215564 kb
Host smart-4aa9f4fb-8b17-4384-9b71-4e088d5e9717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577938653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2577938653
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2527404942
Short name T269
Test name
Test status
Simulation time 67084776 ps
CPU time 4.57 seconds
Started Jul 12 06:42:03 PM PDT 24
Finished Jul 12 06:42:10 PM PDT 24
Peak memory 214840 kb
Host smart-aa1069b9-cd6b-49a6-8c63-7a456125c5a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2527404942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2527404942
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.319764898
Short name T108
Test name
Test status
Simulation time 2397133680 ps
CPU time 8.67 seconds
Started Jul 12 06:40:15 PM PDT 24
Finished Jul 12 06:40:28 PM PDT 24
Peak memory 209968 kb
Host smart-9187de8a-e36d-4e00-88e5-9c5c86a803ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319764898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.319764898
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1070911240
Short name T1083
Test name
Test status
Simulation time 71542036 ps
CPU time 4.02 seconds
Started Jul 12 06:44:06 PM PDT 24
Finished Jul 12 06:44:15 PM PDT 24
Peak memory 205432 kb
Host smart-78db41ae-5b3a-4057-bbb0-6f9524e6e369
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070911240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
070911240
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.852170365
Short name T1002
Test name
Test status
Simulation time 27203338 ps
CPU time 0.98 seconds
Started Jul 12 06:44:04 PM PDT 24
Finished Jul 12 06:44:11 PM PDT 24
Peak memory 205440 kb
Host smart-52417727-768f-4a1e-949d-8b69870d04f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852170365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.852170365
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2099593370
Short name T1076
Test name
Test status
Simulation time 31976579 ps
CPU time 1.62 seconds
Started Jul 12 06:44:09 PM PDT 24
Finished Jul 12 06:44:14 PM PDT 24
Peak memory 205568 kb
Host smart-98ac4ede-fd7c-491a-92f4-fef6d15e16f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099593370 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2099593370
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1718765432
Short name T944
Test name
Test status
Simulation time 82223052 ps
CPU time 1.47 seconds
Started Jul 12 06:44:05 PM PDT 24
Finished Jul 12 06:44:12 PM PDT 24
Peak memory 205368 kb
Host smart-26594152-085c-48d8-81c7-8b62a4c96ffd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718765432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1718765432
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1879515505
Short name T996
Test name
Test status
Simulation time 81969774 ps
CPU time 0.88 seconds
Started Jul 12 06:44:12 PM PDT 24
Finished Jul 12 06:44:15 PM PDT 24
Peak memory 205356 kb
Host smart-cbfa5acf-5315-419e-aeb4-25afa06e38dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879515505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1879515505
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1152831019
Short name T1009
Test name
Test status
Simulation time 40703219 ps
CPU time 2.5 seconds
Started Jul 12 06:44:21 PM PDT 24
Finished Jul 12 06:44:24 PM PDT 24
Peak memory 205504 kb
Host smart-65aec6da-68ce-4426-bfc5-8daf0821b7c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152831019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1152831019
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3777079381
Short name T1007
Test name
Test status
Simulation time 188870858 ps
CPU time 4.62 seconds
Started Jul 12 06:44:08 PM PDT 24
Finished Jul 12 06:44:16 PM PDT 24
Peak memory 214048 kb
Host smart-978ad535-261b-46aa-8942-1117138c7fcc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777079381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3777079381
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1732533440
Short name T118
Test name
Test status
Simulation time 247898133 ps
CPU time 8.44 seconds
Started Jul 12 06:44:06 PM PDT 24
Finished Jul 12 06:44:19 PM PDT 24
Peak memory 214012 kb
Host smart-f27182a1-0347-4bb7-aab7-dad6c7e83c34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732533440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1732533440
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.132463595
Short name T1008
Test name
Test status
Simulation time 147073762 ps
CPU time 2.84 seconds
Started Jul 12 06:44:08 PM PDT 24
Finished Jul 12 06:44:15 PM PDT 24
Peak memory 213836 kb
Host smart-9c26569c-0c3c-4b3d-97a9-2ee0398b6938
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132463595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.132463595
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.981685447
Short name T155
Test name
Test status
Simulation time 442354644 ps
CPU time 9.26 seconds
Started Jul 12 06:44:12 PM PDT 24
Finished Jul 12 06:44:24 PM PDT 24
Peak memory 205592 kb
Host smart-a2a90b20-b083-45a1-94ee-4e40f663f09c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981685447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.981685447
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.109654210
Short name T934
Test name
Test status
Simulation time 510849655 ps
CPU time 14.97 seconds
Started Jul 12 06:44:12 PM PDT 24
Finished Jul 12 06:44:29 PM PDT 24
Peak memory 205560 kb
Host smart-28c57028-c648-439a-a8eb-484116e6e59a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109654210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.109654210
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2892766269
Short name T968
Test name
Test status
Simulation time 166008586 ps
CPU time 1.24 seconds
Started Jul 12 06:44:12 PM PDT 24
Finished Jul 12 06:44:16 PM PDT 24
Peak memory 205500 kb
Host smart-b359ca27-8d23-4f03-84b4-c53d7085e42a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892766269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
892766269
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1565857511
Short name T1051
Test name
Test status
Simulation time 353142998 ps
CPU time 2.15 seconds
Started Jul 12 06:44:10 PM PDT 24
Finished Jul 12 06:44:15 PM PDT 24
Peak memory 213828 kb
Host smart-6b3d310c-2496-46d9-ab7b-b8cc82b93033
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565857511 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1565857511
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.372853663
Short name T1040
Test name
Test status
Simulation time 72639707 ps
CPU time 0.96 seconds
Started Jul 12 06:44:11 PM PDT 24
Finished Jul 12 06:44:15 PM PDT 24
Peak memory 205464 kb
Host smart-acb63fb1-75fe-403c-8118-f5fde76af8e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372853663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.372853663
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1791055712
Short name T954
Test name
Test status
Simulation time 69934855 ps
CPU time 0.75 seconds
Started Jul 12 06:44:09 PM PDT 24
Finished Jul 12 06:44:13 PM PDT 24
Peak memory 205288 kb
Host smart-28766a0c-862f-433c-900d-6636b4e11ee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791055712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1791055712
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1864226499
Short name T1066
Test name
Test status
Simulation time 171216196 ps
CPU time 2.43 seconds
Started Jul 12 06:44:10 PM PDT 24
Finished Jul 12 06:44:15 PM PDT 24
Peak memory 205616 kb
Host smart-c7e78f49-cb3a-496a-afac-ec958fb240a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864226499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1864226499
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3162210913
Short name T113
Test name
Test status
Simulation time 249186618 ps
CPU time 1.81 seconds
Started Jul 12 06:44:15 PM PDT 24
Finished Jul 12 06:44:19 PM PDT 24
Peak memory 214000 kb
Host smart-cd845079-07fb-46bd-b531-30a300912bd1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162210913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3162210913
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3353335148
Short name T1072
Test name
Test status
Simulation time 321900370 ps
CPU time 4.71 seconds
Started Jul 12 06:44:10 PM PDT 24
Finished Jul 12 06:44:18 PM PDT 24
Peak memory 220136 kb
Host smart-d338af66-337d-43d3-a695-24e98bc9b407
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353335148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3353335148
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4190309681
Short name T1011
Test name
Test status
Simulation time 214585905 ps
CPU time 3.67 seconds
Started Jul 12 06:44:15 PM PDT 24
Finished Jul 12 06:44:21 PM PDT 24
Peak memory 215912 kb
Host smart-7aa2495e-25f7-4488-a020-1531f32f7d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190309681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4190309681
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.557143433
Short name T1041
Test name
Test status
Simulation time 152402309 ps
CPU time 1.35 seconds
Started Jul 12 06:44:27 PM PDT 24
Finished Jul 12 06:44:30 PM PDT 24
Peak memory 213916 kb
Host smart-272448f4-5c0d-4ec0-b3d8-caecc9942dc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557143433 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.557143433
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2044794906
Short name T1081
Test name
Test status
Simulation time 95759189 ps
CPU time 1.17 seconds
Started Jul 12 06:44:32 PM PDT 24
Finished Jul 12 06:44:34 PM PDT 24
Peak memory 205500 kb
Host smart-21d2a266-fedf-487e-81d0-f094df1d505c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044794906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2044794906
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3633477340
Short name T936
Test name
Test status
Simulation time 44013181 ps
CPU time 0.74 seconds
Started Jul 12 06:44:28 PM PDT 24
Finished Jul 12 06:44:31 PM PDT 24
Peak memory 205304 kb
Host smart-d87e0d8d-b30b-4de5-8ae8-d7d6a406345a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633477340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3633477340
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2871723054
Short name T966
Test name
Test status
Simulation time 123842007 ps
CPU time 1.97 seconds
Started Jul 12 06:44:26 PM PDT 24
Finished Jul 12 06:44:34 PM PDT 24
Peak memory 205512 kb
Host smart-9e31f29f-1fdd-4a44-857b-c525cde2c178
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871723054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2871723054
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1928177429
Short name T986
Test name
Test status
Simulation time 165818409 ps
CPU time 3.13 seconds
Started Jul 12 06:44:28 PM PDT 24
Finished Jul 12 06:44:34 PM PDT 24
Peak memory 213984 kb
Host smart-8633a901-8492-4e1e-9faf-d561c6db1a0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928177429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1928177429
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.389420634
Short name T121
Test name
Test status
Simulation time 220489731 ps
CPU time 7.6 seconds
Started Jul 12 06:44:37 PM PDT 24
Finished Jul 12 06:44:46 PM PDT 24
Peak memory 214012 kb
Host smart-102a54c6-e1f8-4cc3-a8bb-fc6b195da13f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389420634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.389420634
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2358244233
Short name T963
Test name
Test status
Simulation time 226146644 ps
CPU time 2.22 seconds
Started Jul 12 06:44:39 PM PDT 24
Finished Jul 12 06:44:42 PM PDT 24
Peak memory 213796 kb
Host smart-45f11db7-a5cb-405c-9637-00f0852289e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358244233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2358244233
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2928470319
Short name T163
Test name
Test status
Simulation time 128435138 ps
CPU time 4.96 seconds
Started Jul 12 06:44:26 PM PDT 24
Finished Jul 12 06:44:32 PM PDT 24
Peak memory 213736 kb
Host smart-802b1c68-b2d8-4059-b7f1-993c0084d6cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928470319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2928470319
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1518536022
Short name T1015
Test name
Test status
Simulation time 43193689 ps
CPU time 2.09 seconds
Started Jul 12 06:44:32 PM PDT 24
Finished Jul 12 06:44:35 PM PDT 24
Peak memory 213820 kb
Host smart-8d33b30b-bdb9-40e3-a1d8-ecebc504fc13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518536022 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1518536022
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2630590558
Short name T1060
Test name
Test status
Simulation time 82483585 ps
CPU time 1.18 seconds
Started Jul 12 06:44:34 PM PDT 24
Finished Jul 12 06:44:36 PM PDT 24
Peak memory 205516 kb
Host smart-20f02625-d6e5-448a-9187-0024a9554c2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630590558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2630590558
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2290546414
Short name T977
Test name
Test status
Simulation time 44594648 ps
CPU time 0.87 seconds
Started Jul 12 06:44:35 PM PDT 24
Finished Jul 12 06:44:37 PM PDT 24
Peak memory 205404 kb
Host smart-641596b3-2866-4523-863c-a3d438238d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290546414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2290546414
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3571811570
Short name T140
Test name
Test status
Simulation time 124744837 ps
CPU time 3.7 seconds
Started Jul 12 06:44:33 PM PDT 24
Finished Jul 12 06:44:38 PM PDT 24
Peak memory 205544 kb
Host smart-8e4b2cbe-2fa9-4ce9-baba-c4d0140d7ad5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571811570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3571811570
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3978755892
Short name T1071
Test name
Test status
Simulation time 179670481 ps
CPU time 2.96 seconds
Started Jul 12 06:44:27 PM PDT 24
Finished Jul 12 06:44:31 PM PDT 24
Peak memory 213964 kb
Host smart-068c467f-3f00-4f03-96df-0eb36ca5859c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978755892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3978755892
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3649063942
Short name T1020
Test name
Test status
Simulation time 667094835 ps
CPU time 8.01 seconds
Started Jul 12 06:44:44 PM PDT 24
Finished Jul 12 06:44:55 PM PDT 24
Peak memory 219956 kb
Host smart-ce233a24-a886-474c-a0b0-2c8bedfd52c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649063942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3649063942
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2130167604
Short name T933
Test name
Test status
Simulation time 269407344 ps
CPU time 2.1 seconds
Started Jul 12 06:44:26 PM PDT 24
Finished Jul 12 06:44:30 PM PDT 24
Peak memory 213776 kb
Host smart-4bbecb03-f551-49f0-814a-768d2a123cf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130167604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2130167604
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.927370936
Short name T988
Test name
Test status
Simulation time 92330562 ps
CPU time 1.53 seconds
Started Jul 12 06:44:26 PM PDT 24
Finished Jul 12 06:44:28 PM PDT 24
Peak memory 216588 kb
Host smart-1bf605d9-5dd2-4373-a704-0ee93915983b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927370936 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.927370936
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.41700852
Short name T1000
Test name
Test status
Simulation time 31506215 ps
CPU time 0.87 seconds
Started Jul 12 06:44:28 PM PDT 24
Finished Jul 12 06:44:31 PM PDT 24
Peak memory 205452 kb
Host smart-d12cf12c-53cc-4cfb-963c-d5e019b1f97f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41700852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.41700852
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.4275912782
Short name T937
Test name
Test status
Simulation time 32666770 ps
CPU time 0.81 seconds
Started Jul 12 06:44:26 PM PDT 24
Finished Jul 12 06:44:29 PM PDT 24
Peak memory 205300 kb
Host smart-73fab045-8777-4ea7-be2b-25033bfb61aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275912782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.4275912782
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3637836011
Short name T983
Test name
Test status
Simulation time 333571379 ps
CPU time 1.6 seconds
Started Jul 12 06:44:28 PM PDT 24
Finished Jul 12 06:44:32 PM PDT 24
Peak memory 205584 kb
Host smart-d389b391-0559-48af-9908-3b13b02f0bc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637836011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3637836011
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3717760061
Short name T1045
Test name
Test status
Simulation time 345961771 ps
CPU time 8.87 seconds
Started Jul 12 06:44:28 PM PDT 24
Finished Jul 12 06:44:39 PM PDT 24
Peak memory 214040 kb
Host smart-9860773b-2d8c-45de-8dc4-4343bd61965e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717760061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3717760061
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1465584158
Short name T938
Test name
Test status
Simulation time 39097951 ps
CPU time 1.45 seconds
Started Jul 12 06:44:39 PM PDT 24
Finished Jul 12 06:44:41 PM PDT 24
Peak memory 214900 kb
Host smart-60242061-d6cb-4e7a-a7e1-1b598a427cba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465584158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1465584158
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2363647206
Short name T958
Test name
Test status
Simulation time 52123268 ps
CPU time 2.62 seconds
Started Jul 12 06:44:28 PM PDT 24
Finished Jul 12 06:44:33 PM PDT 24
Peak memory 213792 kb
Host smart-e6e424cc-94e1-4ba0-8458-b6072aed030e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363647206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2363647206
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3448188291
Short name T942
Test name
Test status
Simulation time 69533256 ps
CPU time 1.36 seconds
Started Jul 12 06:44:29 PM PDT 24
Finished Jul 12 06:44:32 PM PDT 24
Peak memory 213772 kb
Host smart-52a98acd-ea0a-4e49-b59d-b5dbacabe8b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448188291 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3448188291
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3267180368
Short name T1058
Test name
Test status
Simulation time 45513380 ps
CPU time 1.33 seconds
Started Jul 12 06:44:28 PM PDT 24
Finished Jul 12 06:44:31 PM PDT 24
Peak memory 205588 kb
Host smart-467eeef5-9d46-4c30-a7f0-fd18d266c8fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267180368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3267180368
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.67929705
Short name T925
Test name
Test status
Simulation time 10947827 ps
CPU time 0.82 seconds
Started Jul 12 06:44:43 PM PDT 24
Finished Jul 12 06:44:46 PM PDT 24
Peak memory 205328 kb
Host smart-5ebd586c-86fc-41a5-9892-82f21ffd485a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67929705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.67929705
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.293045605
Short name T1085
Test name
Test status
Simulation time 32016330 ps
CPU time 2.37 seconds
Started Jul 12 06:44:27 PM PDT 24
Finished Jul 12 06:44:30 PM PDT 24
Peak memory 213708 kb
Host smart-2becb39e-c3e2-4a58-ba5a-57162ff9c795
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293045605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.293045605
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2316718831
Short name T1088
Test name
Test status
Simulation time 73244715 ps
CPU time 2.05 seconds
Started Jul 12 06:44:32 PM PDT 24
Finished Jul 12 06:44:36 PM PDT 24
Peak memory 214000 kb
Host smart-5b6aca25-12c5-4b9a-bc6e-1989a7ecf379
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316718831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2316718831
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.212807649
Short name T995
Test name
Test status
Simulation time 421840859 ps
CPU time 7.66 seconds
Started Jul 12 06:44:26 PM PDT 24
Finished Jul 12 06:44:36 PM PDT 24
Peak memory 220092 kb
Host smart-fe31ad54-c544-45db-b7ec-63550cb0b9bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212807649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.212807649
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2287631538
Short name T979
Test name
Test status
Simulation time 93172939 ps
CPU time 1.8 seconds
Started Jul 12 06:44:27 PM PDT 24
Finished Jul 12 06:44:31 PM PDT 24
Peak memory 213764 kb
Host smart-11740824-0638-4d04-9e02-9915ca02a95e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287631538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2287631538
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1465412847
Short name T991
Test name
Test status
Simulation time 189923668 ps
CPU time 5.55 seconds
Started Jul 12 06:44:30 PM PDT 24
Finished Jul 12 06:44:38 PM PDT 24
Peak memory 213752 kb
Host smart-dd20a3a2-7323-463a-a600-0e42b757779f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465412847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1465412847
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3479938845
Short name T201
Test name
Test status
Simulation time 631111994 ps
CPU time 2.25 seconds
Started Jul 12 06:44:29 PM PDT 24
Finished Jul 12 06:44:33 PM PDT 24
Peak memory 213840 kb
Host smart-fffda163-e973-479e-ae27-d3461faae67e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479938845 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3479938845
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3231492263
Short name T985
Test name
Test status
Simulation time 37847451 ps
CPU time 0.94 seconds
Started Jul 12 06:44:26 PM PDT 24
Finished Jul 12 06:44:29 PM PDT 24
Peak memory 205416 kb
Host smart-4d36a13e-3664-4231-9893-f416be7e288a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231492263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3231492263
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.4263971667
Short name T1018
Test name
Test status
Simulation time 29922445 ps
CPU time 0.78 seconds
Started Jul 12 06:44:29 PM PDT 24
Finished Jul 12 06:44:32 PM PDT 24
Peak memory 205376 kb
Host smart-24a29ff1-67e5-4779-9914-a123a9458ea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263971667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.4263971667
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2086313252
Short name T1052
Test name
Test status
Simulation time 24936592 ps
CPU time 1.43 seconds
Started Jul 12 06:44:27 PM PDT 24
Finished Jul 12 06:44:31 PM PDT 24
Peak memory 205544 kb
Host smart-a203e587-5663-4e8d-8512-21051686a592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086313252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2086313252
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1964087668
Short name T116
Test name
Test status
Simulation time 175767599 ps
CPU time 1.6 seconds
Started Jul 12 06:44:30 PM PDT 24
Finished Jul 12 06:44:34 PM PDT 24
Peak memory 214028 kb
Host smart-00c76f0a-8a4f-40c5-9af5-ed54a5729afc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964087668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1964087668
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.37593990
Short name T1004
Test name
Test status
Simulation time 342379614 ps
CPU time 7.74 seconds
Started Jul 12 06:45:10 PM PDT 24
Finished Jul 12 06:45:20 PM PDT 24
Peak memory 220120 kb
Host smart-264221db-efb3-4a20-91d6-8247ea1f47de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37593990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.k
eymgr_shadow_reg_errors_with_csr_rw.37593990
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3065229449
Short name T1074
Test name
Test status
Simulation time 250562782 ps
CPU time 2.84 seconds
Started Jul 12 06:44:49 PM PDT 24
Finished Jul 12 06:44:55 PM PDT 24
Peak memory 213800 kb
Host smart-fc001f9b-550f-4978-80c7-2a643be1a850
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065229449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3065229449
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1529631478
Short name T953
Test name
Test status
Simulation time 186941015 ps
CPU time 6.25 seconds
Started Jul 12 06:44:28 PM PDT 24
Finished Jul 12 06:44:36 PM PDT 24
Peak memory 213860 kb
Host smart-43e40bf9-e79e-42ff-a962-c385cd71ab83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529631478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1529631478
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.904621676
Short name T1079
Test name
Test status
Simulation time 25467841 ps
CPU time 1.9 seconds
Started Jul 12 06:48:49 PM PDT 24
Finished Jul 12 06:48:51 PM PDT 24
Peak memory 213796 kb
Host smart-874ee552-0f26-49af-8c54-564ea2e977ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904621676 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.904621676
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3114731195
Short name T1032
Test name
Test status
Simulation time 19854982 ps
CPU time 1.18 seconds
Started Jul 12 06:44:39 PM PDT 24
Finished Jul 12 06:44:41 PM PDT 24
Peak memory 205508 kb
Host smart-ab8c6cbe-b240-4fc5-9aac-871092a0e44e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114731195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3114731195
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2529978597
Short name T967
Test name
Test status
Simulation time 51850803 ps
CPU time 0.7 seconds
Started Jul 12 06:44:36 PM PDT 24
Finished Jul 12 06:44:38 PM PDT 24
Peak memory 205376 kb
Host smart-4e004f6f-896a-4503-beb2-a8fbd45ab52b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529978597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2529978597
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.26588148
Short name T138
Test name
Test status
Simulation time 126658612 ps
CPU time 1.97 seconds
Started Jul 12 06:44:47 PM PDT 24
Finished Jul 12 06:44:52 PM PDT 24
Peak memory 205556 kb
Host smart-6277e545-7c5a-4287-b497-4e2a719f9367
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26588148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sam
e_csr_outstanding.26588148
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2696625850
Short name T1016
Test name
Test status
Simulation time 164175518 ps
CPU time 4.76 seconds
Started Jul 12 06:44:45 PM PDT 24
Finished Jul 12 06:44:54 PM PDT 24
Peak memory 220248 kb
Host smart-7414875d-4450-4f1f-a70a-a61dd312e023
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696625850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2696625850
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3887278397
Short name T929
Test name
Test status
Simulation time 32356839 ps
CPU time 2.08 seconds
Started Jul 12 06:44:51 PM PDT 24
Finished Jul 12 06:44:57 PM PDT 24
Peak memory 213564 kb
Host smart-48639052-e44f-4f27-bf2b-be4803fd4997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887278397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3887278397
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1974812528
Short name T1086
Test name
Test status
Simulation time 1342992251 ps
CPU time 10.66 seconds
Started Jul 12 06:44:33 PM PDT 24
Finished Jul 12 06:44:45 PM PDT 24
Peak memory 213752 kb
Host smart-2b532210-ca31-4e07-a84d-ff8b1b110150
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974812528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1974812528
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2537664179
Short name T970
Test name
Test status
Simulation time 53946020 ps
CPU time 1.49 seconds
Started Jul 12 06:44:53 PM PDT 24
Finished Jul 12 06:44:57 PM PDT 24
Peak memory 213856 kb
Host smart-5973ca2d-fc63-4179-a482-5a6ee6b22ad3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537664179 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2537664179
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1682678589
Short name T1073
Test name
Test status
Simulation time 38022388 ps
CPU time 0.97 seconds
Started Jul 12 06:44:48 PM PDT 24
Finished Jul 12 06:44:52 PM PDT 24
Peak memory 205408 kb
Host smart-a03b651d-1709-41f2-b69c-f299ee7106da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682678589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1682678589
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1736408780
Short name T1022
Test name
Test status
Simulation time 42192430 ps
CPU time 0.72 seconds
Started Jul 12 06:44:31 PM PDT 24
Finished Jul 12 06:44:33 PM PDT 24
Peak memory 205300 kb
Host smart-d992a0d9-83ed-45cb-a326-90673550cd7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736408780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1736408780
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2640520882
Short name T969
Test name
Test status
Simulation time 94590109 ps
CPU time 1.56 seconds
Started Jul 12 06:44:52 PM PDT 24
Finished Jul 12 06:44:56 PM PDT 24
Peak memory 205508 kb
Host smart-adc1124b-0971-4242-8efd-81e14f8f42b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640520882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2640520882
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.583125155
Short name T1047
Test name
Test status
Simulation time 550941667 ps
CPU time 1.33 seconds
Started Jul 12 06:44:32 PM PDT 24
Finished Jul 12 06:44:35 PM PDT 24
Peak memory 213992 kb
Host smart-bad81a11-8446-43a9-b33d-f799b2497337
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583125155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.583125155
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3401411558
Short name T1078
Test name
Test status
Simulation time 993279547 ps
CPU time 15.36 seconds
Started Jul 12 06:44:50 PM PDT 24
Finished Jul 12 06:45:08 PM PDT 24
Peak memory 214296 kb
Host smart-0ee0cabd-27b0-4e3c-b23f-f4d0e549a2cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401411558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3401411558
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4100555024
Short name T1048
Test name
Test status
Simulation time 120260493 ps
CPU time 3.22 seconds
Started Jul 12 06:44:35 PM PDT 24
Finished Jul 12 06:44:39 PM PDT 24
Peak memory 213828 kb
Host smart-1de45ef1-a313-4115-a132-fa638989fd81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100555024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.4100555024
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3645181015
Short name T1055
Test name
Test status
Simulation time 21823022 ps
CPU time 1.61 seconds
Started Jul 12 06:44:39 PM PDT 24
Finished Jul 12 06:44:41 PM PDT 24
Peak memory 221936 kb
Host smart-0e0a1921-3684-42fb-875d-0159ace64a43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645181015 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3645181015
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2561508033
Short name T964
Test name
Test status
Simulation time 16560558 ps
CPU time 0.94 seconds
Started Jul 12 06:44:37 PM PDT 24
Finished Jul 12 06:44:39 PM PDT 24
Peak memory 205488 kb
Host smart-3bbd172e-3f94-40b3-bd64-691a37229013
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561508033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2561508033
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3248987958
Short name T1028
Test name
Test status
Simulation time 49339312 ps
CPU time 0.8 seconds
Started Jul 12 06:44:35 PM PDT 24
Finished Jul 12 06:44:36 PM PDT 24
Peak memory 205344 kb
Host smart-5158ffaa-b312-444c-a98c-68e79ecda573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248987958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3248987958
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3350170725
Short name T145
Test name
Test status
Simulation time 73921772 ps
CPU time 1.58 seconds
Started Jul 12 06:44:50 PM PDT 24
Finished Jul 12 06:44:55 PM PDT 24
Peak memory 205464 kb
Host smart-30d619ef-8f25-4b88-90f6-1c9c00870ef4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350170725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3350170725
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2511660622
Short name T1021
Test name
Test status
Simulation time 328111117 ps
CPU time 4.58 seconds
Started Jul 12 06:44:42 PM PDT 24
Finished Jul 12 06:44:47 PM PDT 24
Peak memory 218672 kb
Host smart-12f7edba-3dc4-44d0-8361-2de261126832
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511660622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2511660622
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3736748904
Short name T1005
Test name
Test status
Simulation time 361516455 ps
CPU time 8.77 seconds
Started Jul 12 06:44:35 PM PDT 24
Finished Jul 12 06:44:44 PM PDT 24
Peak memory 220208 kb
Host smart-31a4d073-9821-45d1-8106-a0019359cb9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736748904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3736748904
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1123656817
Short name T1067
Test name
Test status
Simulation time 349805946 ps
CPU time 4.94 seconds
Started Jul 12 06:44:51 PM PDT 24
Finished Jul 12 06:44:59 PM PDT 24
Peak memory 213832 kb
Host smart-ab039d38-7885-40c6-8583-a75598a6a21c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123656817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1123656817
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2987866945
Short name T181
Test name
Test status
Simulation time 91077235 ps
CPU time 1.53 seconds
Started Jul 12 06:44:53 PM PDT 24
Finished Jul 12 06:44:57 PM PDT 24
Peak memory 213756 kb
Host smart-77280782-bcf6-4349-98c1-b5b3f9c211ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987866945 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2987866945
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3151517139
Short name T144
Test name
Test status
Simulation time 73712392 ps
CPU time 1.6 seconds
Started Jul 12 06:44:53 PM PDT 24
Finished Jul 12 06:44:57 PM PDT 24
Peak memory 205540 kb
Host smart-d054a61b-640f-44d7-a986-36518015168d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151517139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3151517139
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.258989186
Short name T939
Test name
Test status
Simulation time 17603702 ps
CPU time 0.76 seconds
Started Jul 12 06:44:32 PM PDT 24
Finished Jul 12 06:44:34 PM PDT 24
Peak memory 205364 kb
Host smart-d63542d6-d147-4565-934b-207d675251a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258989186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.258989186
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2663215167
Short name T1014
Test name
Test status
Simulation time 221484016 ps
CPU time 2.41 seconds
Started Jul 12 06:44:48 PM PDT 24
Finished Jul 12 06:44:53 PM PDT 24
Peak memory 205464 kb
Host smart-e0ff528c-acd9-4bfe-870d-1edaa8082d3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663215167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2663215167
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1393842959
Short name T982
Test name
Test status
Simulation time 443816736 ps
CPU time 1.78 seconds
Started Jul 12 06:44:47 PM PDT 24
Finished Jul 12 06:44:51 PM PDT 24
Peak memory 214052 kb
Host smart-10792c4d-3593-44dd-a57a-e3b6b5a1ff1e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393842959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1393842959
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.156240229
Short name T120
Test name
Test status
Simulation time 1373530644 ps
CPU time 9.05 seconds
Started Jul 12 06:44:48 PM PDT 24
Finished Jul 12 06:45:00 PM PDT 24
Peak memory 213972 kb
Host smart-d925e95a-1af6-4900-9bf7-87e1b5cdbc00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156240229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.156240229
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.815999430
Short name T951
Test name
Test status
Simulation time 45611367 ps
CPU time 1.53 seconds
Started Jul 12 06:44:29 PM PDT 24
Finished Jul 12 06:44:33 PM PDT 24
Peak memory 205588 kb
Host smart-f9c19ccc-44e2-4f1a-aacb-e45e1d0a55cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815999430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.815999430
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1521323127
Short name T1031
Test name
Test status
Simulation time 53673492 ps
CPU time 1.56 seconds
Started Jul 12 06:44:51 PM PDT 24
Finished Jul 12 06:44:55 PM PDT 24
Peak memory 213760 kb
Host smart-e8d4e972-4ad0-4039-a6dc-8fdc085486b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521323127 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1521323127
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.293548939
Short name T137
Test name
Test status
Simulation time 45021277 ps
CPU time 1.13 seconds
Started Jul 12 06:44:39 PM PDT 24
Finished Jul 12 06:44:48 PM PDT 24
Peak memory 205612 kb
Host smart-0cb49a0f-0893-41e6-bc55-023c8289a5ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293548939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.293548939
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1079922989
Short name T959
Test name
Test status
Simulation time 42062571 ps
CPU time 0.91 seconds
Started Jul 12 06:44:35 PM PDT 24
Finished Jul 12 06:44:36 PM PDT 24
Peak memory 205396 kb
Host smart-23d36226-1f22-4101-9640-66b0ed7827f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079922989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1079922989
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.501255393
Short name T141
Test name
Test status
Simulation time 268057108 ps
CPU time 2.47 seconds
Started Jul 12 06:44:41 PM PDT 24
Finished Jul 12 06:44:44 PM PDT 24
Peak memory 205524 kb
Host smart-2376ceb0-f33e-4701-a0d4-05da96b15d9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501255393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.501255393
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3103328633
Short name T115
Test name
Test status
Simulation time 92296120 ps
CPU time 2.79 seconds
Started Jul 12 06:44:30 PM PDT 24
Finished Jul 12 06:44:35 PM PDT 24
Peak memory 214044 kb
Host smart-c0336208-c517-4b04-9d6b-ee8e9ce47d42
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103328633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3103328633
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.311367052
Short name T993
Test name
Test status
Simulation time 70672077 ps
CPU time 2.92 seconds
Started Jul 12 06:44:32 PM PDT 24
Finished Jul 12 06:44:36 PM PDT 24
Peak memory 213684 kb
Host smart-d5e817f2-05e8-465c-862a-262f73298519
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311367052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.311367052
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.4220957012
Short name T150
Test name
Test status
Simulation time 118173562 ps
CPU time 3.25 seconds
Started Jul 12 06:44:46 PM PDT 24
Finished Jul 12 06:44:52 PM PDT 24
Peak memory 213784 kb
Host smart-583b59e5-b316-444b-b42c-82b5d0044c9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220957012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.4220957012
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.462963484
Short name T1075
Test name
Test status
Simulation time 2952026858 ps
CPU time 6.47 seconds
Started Jul 12 06:44:15 PM PDT 24
Finished Jul 12 06:44:23 PM PDT 24
Peak memory 205628 kb
Host smart-2063a97e-bc51-4d87-84c0-81a17a3f25af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462963484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.462963484
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2884776196
Short name T1027
Test name
Test status
Simulation time 851361272 ps
CPU time 12.31 seconds
Started Jul 12 06:44:12 PM PDT 24
Finished Jul 12 06:44:27 PM PDT 24
Peak memory 205456 kb
Host smart-d9e29181-7d80-42f7-b2b7-7fe60c0a5877
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884776196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
884776196
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3968524391
Short name T218
Test name
Test status
Simulation time 23607331 ps
CPU time 1.37 seconds
Started Jul 12 06:44:13 PM PDT 24
Finished Jul 12 06:44:17 PM PDT 24
Peak memory 205584 kb
Host smart-c2af8e2a-9fd5-45dc-b4f0-f3c9a73e715b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968524391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
968524391
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.168927420
Short name T989
Test name
Test status
Simulation time 180291420 ps
CPU time 2.06 seconds
Started Jul 12 06:44:15 PM PDT 24
Finished Jul 12 06:44:20 PM PDT 24
Peak memory 213752 kb
Host smart-733c698a-5c51-4523-9f98-871c84c1608d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168927420 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.168927420
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1223719941
Short name T1003
Test name
Test status
Simulation time 9536423 ps
CPU time 0.89 seconds
Started Jul 12 06:44:14 PM PDT 24
Finished Jul 12 06:44:17 PM PDT 24
Peak memory 205444 kb
Host smart-8ccbffe7-3b8b-47bd-a981-8bc979918130
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223719941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1223719941
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3737596006
Short name T1025
Test name
Test status
Simulation time 25661794 ps
CPU time 0.75 seconds
Started Jul 12 06:44:12 PM PDT 24
Finished Jul 12 06:44:15 PM PDT 24
Peak memory 205380 kb
Host smart-0edc3c3e-fbde-484f-a888-501946136f14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737596006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3737596006
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2875870790
Short name T1037
Test name
Test status
Simulation time 36003833 ps
CPU time 2.04 seconds
Started Jul 12 06:44:12 PM PDT 24
Finished Jul 12 06:44:17 PM PDT 24
Peak memory 205516 kb
Host smart-2ab633d0-de49-4998-b6c2-1123de694812
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875870790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2875870790
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.408747484
Short name T122
Test name
Test status
Simulation time 2000447295 ps
CPU time 4.38 seconds
Started Jul 12 06:44:11 PM PDT 24
Finished Jul 12 06:44:18 PM PDT 24
Peak memory 213988 kb
Host smart-3f772f4f-5dfc-408f-ab5a-5834a4f411a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408747484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.408747484
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3226889145
Short name T1033
Test name
Test status
Simulation time 799017022 ps
CPU time 13.5 seconds
Started Jul 12 06:44:15 PM PDT 24
Finished Jul 12 06:44:30 PM PDT 24
Peak memory 214016 kb
Host smart-d84cbb0c-89a2-466f-a9bf-8004ab248fa4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226889145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3226889145
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3321674376
Short name T932
Test name
Test status
Simulation time 467760557 ps
CPU time 3.85 seconds
Started Jul 12 06:44:10 PM PDT 24
Finished Jul 12 06:44:17 PM PDT 24
Peak memory 216844 kb
Host smart-8dc724b4-908e-4151-83a9-f9c4d939b65e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321674376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3321674376
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.557071170
Short name T167
Test name
Test status
Simulation time 534633423 ps
CPU time 4.63 seconds
Started Jul 12 06:44:08 PM PDT 24
Finished Jul 12 06:44:17 PM PDT 24
Peak memory 213684 kb
Host smart-e483ee12-9ce8-4a99-b2bc-50849e3e368e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557071170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
557071170
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.375166668
Short name T926
Test name
Test status
Simulation time 23418146 ps
CPU time 0.87 seconds
Started Jul 12 06:44:52 PM PDT 24
Finished Jul 12 06:44:56 PM PDT 24
Peak memory 205300 kb
Host smart-4ae1c762-cbec-478c-b332-ea60d8feb356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375166668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.375166668
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1183994669
Short name T940
Test name
Test status
Simulation time 11589254 ps
CPU time 0.83 seconds
Started Jul 12 06:44:52 PM PDT 24
Finished Jul 12 06:44:56 PM PDT 24
Peak memory 205376 kb
Host smart-7a09b169-27a2-451d-baa7-a0b87dfdc448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183994669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1183994669
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1299814169
Short name T984
Test name
Test status
Simulation time 24676324 ps
CPU time 0.72 seconds
Started Jul 12 06:44:39 PM PDT 24
Finished Jul 12 06:44:41 PM PDT 24
Peak memory 205312 kb
Host smart-daeda674-465a-43f1-81fb-45e7d618be64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299814169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1299814169
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3419763717
Short name T999
Test name
Test status
Simulation time 18637714 ps
CPU time 0.79 seconds
Started Jul 12 06:44:37 PM PDT 24
Finished Jul 12 06:44:39 PM PDT 24
Peak memory 205336 kb
Host smart-9ef9cbbd-4a7c-4e40-b21b-0ba2a62895f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419763717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3419763717
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2334926840
Short name T1069
Test name
Test status
Simulation time 23882293 ps
CPU time 0.86 seconds
Started Jul 12 06:44:55 PM PDT 24
Finished Jul 12 06:44:58 PM PDT 24
Peak memory 205368 kb
Host smart-150c79f5-7d8b-40aa-b675-303f31a23787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334926840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2334926840
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3022828980
Short name T1043
Test name
Test status
Simulation time 30889367 ps
CPU time 0.86 seconds
Started Jul 12 06:44:45 PM PDT 24
Finished Jul 12 06:44:49 PM PDT 24
Peak memory 205360 kb
Host smart-0790c271-e60c-4172-b23a-5ad2d9a55c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022828980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3022828980
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3071695622
Short name T1012
Test name
Test status
Simulation time 19287413 ps
CPU time 0.74 seconds
Started Jul 12 06:44:35 PM PDT 24
Finished Jul 12 06:44:37 PM PDT 24
Peak memory 205268 kb
Host smart-c4396741-f7b5-4990-ac5e-05b15b8e7a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071695622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3071695622
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3867077594
Short name T957
Test name
Test status
Simulation time 11056269 ps
CPU time 0.81 seconds
Started Jul 12 06:44:38 PM PDT 24
Finished Jul 12 06:44:39 PM PDT 24
Peak memory 205284 kb
Host smart-2f638260-c462-4331-b83c-b555cd5ef38c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867077594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3867077594
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1148132444
Short name T994
Test name
Test status
Simulation time 73587049 ps
CPU time 0.85 seconds
Started Jul 12 06:44:39 PM PDT 24
Finished Jul 12 06:44:40 PM PDT 24
Peak memory 205280 kb
Host smart-37217916-6932-42ca-8f80-bfe859e82e8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148132444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1148132444
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3348359404
Short name T945
Test name
Test status
Simulation time 18351242 ps
CPU time 0.74 seconds
Started Jul 12 06:44:52 PM PDT 24
Finished Jul 12 06:44:56 PM PDT 24
Peak memory 205376 kb
Host smart-edb6d88c-6001-4498-80a5-1920009b9935
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348359404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3348359404
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2446358332
Short name T1061
Test name
Test status
Simulation time 496635679 ps
CPU time 10.15 seconds
Started Jul 12 06:44:20 PM PDT 24
Finished Jul 12 06:44:31 PM PDT 24
Peak memory 205572 kb
Host smart-43511255-b0d1-4067-83ef-62004790aeb2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446358332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
446358332
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2677199756
Short name T974
Test name
Test status
Simulation time 592186382 ps
CPU time 6.23 seconds
Started Jul 12 06:44:15 PM PDT 24
Finished Jul 12 06:44:23 PM PDT 24
Peak memory 205376 kb
Host smart-177e8c56-6b9c-4e48-9f0f-af192d553aa9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677199756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
677199756
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4046142969
Short name T1080
Test name
Test status
Simulation time 38946362 ps
CPU time 1.16 seconds
Started Jul 12 06:44:18 PM PDT 24
Finished Jul 12 06:44:20 PM PDT 24
Peak memory 205544 kb
Host smart-23e1acdd-d7e1-4045-8716-c387e8a0572b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046142969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4
046142969
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2875813801
Short name T973
Test name
Test status
Simulation time 175218520 ps
CPU time 1.52 seconds
Started Jul 12 06:44:13 PM PDT 24
Finished Jul 12 06:44:16 PM PDT 24
Peak memory 213748 kb
Host smart-e83d87ee-6319-4b82-bd6e-022a7aded24b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875813801 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2875813801
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3694783002
Short name T992
Test name
Test status
Simulation time 54866646 ps
CPU time 1.23 seconds
Started Jul 12 06:44:16 PM PDT 24
Finished Jul 12 06:44:19 PM PDT 24
Peak memory 205584 kb
Host smart-ab14aac9-4c30-441c-9f32-9a33da911dd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694783002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3694783002
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.4252714594
Short name T1034
Test name
Test status
Simulation time 9786563 ps
CPU time 0.8 seconds
Started Jul 12 06:44:16 PM PDT 24
Finished Jul 12 06:44:19 PM PDT 24
Peak memory 205276 kb
Host smart-8dbf18c0-9667-465d-9d63-99c345c929d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252714594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.4252714594
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2452214199
Short name T1068
Test name
Test status
Simulation time 262082869 ps
CPU time 1.88 seconds
Started Jul 12 06:44:21 PM PDT 24
Finished Jul 12 06:44:23 PM PDT 24
Peak memory 205724 kb
Host smart-38a92808-f2d5-4b59-b6ec-0acf4a52dcc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452214199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2452214199
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.29292246
Short name T980
Test name
Test status
Simulation time 292529668 ps
CPU time 3.33 seconds
Started Jul 12 06:44:12 PM PDT 24
Finished Jul 12 06:44:18 PM PDT 24
Peak memory 213960 kb
Host smart-08bf2852-7f95-4ad3-9941-4234bc56ad46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29292246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_
reg_errors.29292246
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.351372161
Short name T1035
Test name
Test status
Simulation time 139793663 ps
CPU time 4.29 seconds
Started Jul 12 06:44:21 PM PDT 24
Finished Jul 12 06:44:26 PM PDT 24
Peak memory 214076 kb
Host smart-43364872-52fe-4479-83d4-735d942f4b03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351372161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.351372161
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1436549095
Short name T990
Test name
Test status
Simulation time 257350364 ps
CPU time 3.14 seconds
Started Jul 12 06:44:18 PM PDT 24
Finished Jul 12 06:44:22 PM PDT 24
Peak memory 213788 kb
Host smart-db1edefd-8612-4e68-8ab0-6b68dd877615
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436549095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1436549095
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2988927404
Short name T403
Test name
Test status
Simulation time 54741694 ps
CPU time 3.08 seconds
Started Jul 12 06:44:28 PM PDT 24
Finished Jul 12 06:44:33 PM PDT 24
Peak memory 205488 kb
Host smart-2f2d826a-921d-425e-93e9-6053aa590413
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988927404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2988927404
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3156142297
Short name T1054
Test name
Test status
Simulation time 24822360 ps
CPU time 0.71 seconds
Started Jul 12 06:44:46 PM PDT 24
Finished Jul 12 06:44:50 PM PDT 24
Peak memory 205288 kb
Host smart-03bd0663-de1e-4574-9be9-3538ac089510
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156142297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3156142297
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2671531363
Short name T1036
Test name
Test status
Simulation time 17289223 ps
CPU time 0.79 seconds
Started Jul 12 06:44:54 PM PDT 24
Finished Jul 12 06:44:57 PM PDT 24
Peak memory 205380 kb
Host smart-37168dde-705d-477d-bbc7-f3a4b810b9af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671531363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2671531363
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1468943388
Short name T987
Test name
Test status
Simulation time 23123713 ps
CPU time 0.7 seconds
Started Jul 12 06:44:47 PM PDT 24
Finished Jul 12 06:44:51 PM PDT 24
Peak memory 205364 kb
Host smart-9f9cd2c0-d027-42f3-9c05-68a7c8924a62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468943388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1468943388
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.4077502829
Short name T931
Test name
Test status
Simulation time 23291176 ps
CPU time 0.9 seconds
Started Jul 12 06:44:50 PM PDT 24
Finished Jul 12 06:44:54 PM PDT 24
Peak memory 205388 kb
Host smart-e81c3280-c9e8-4660-923e-519c1455ad11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077502829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.4077502829
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1669238227
Short name T928
Test name
Test status
Simulation time 44139983 ps
CPU time 0.82 seconds
Started Jul 12 06:44:45 PM PDT 24
Finished Jul 12 06:44:49 PM PDT 24
Peak memory 205388 kb
Host smart-fa66008b-b1f5-4e91-94b1-020386708bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669238227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1669238227
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1232312750
Short name T1053
Test name
Test status
Simulation time 10357750 ps
CPU time 0.81 seconds
Started Jul 12 06:44:41 PM PDT 24
Finished Jul 12 06:44:43 PM PDT 24
Peak memory 205248 kb
Host smart-e922ff0c-49e5-436b-a3d0-09cf4806d425
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232312750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1232312750
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1018196133
Short name T1046
Test name
Test status
Simulation time 10622360 ps
CPU time 0.7 seconds
Started Jul 12 06:44:38 PM PDT 24
Finished Jul 12 06:44:39 PM PDT 24
Peak memory 205360 kb
Host smart-02ab12b1-c21c-45a0-b05b-a006f1a07b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018196133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1018196133
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.516696585
Short name T935
Test name
Test status
Simulation time 9944946 ps
CPU time 0.73 seconds
Started Jul 12 06:44:37 PM PDT 24
Finished Jul 12 06:44:39 PM PDT 24
Peak memory 205356 kb
Host smart-d3fd65d9-59ec-4440-bced-595f57731a27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516696585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.516696585
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1210866986
Short name T930
Test name
Test status
Simulation time 13347682 ps
CPU time 0.74 seconds
Started Jul 12 06:44:40 PM PDT 24
Finished Jul 12 06:44:42 PM PDT 24
Peak memory 205376 kb
Host smart-07897922-8fa7-47ca-84ab-9c309694193c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210866986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1210866986
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1794391735
Short name T927
Test name
Test status
Simulation time 22430736 ps
CPU time 0.83 seconds
Started Jul 12 06:44:39 PM PDT 24
Finished Jul 12 06:44:41 PM PDT 24
Peak memory 205388 kb
Host smart-bc5c1991-998c-4c4c-b485-4085ced77bf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794391735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1794391735
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.62929670
Short name T1001
Test name
Test status
Simulation time 1825814036 ps
CPU time 11.83 seconds
Started Jul 12 06:44:14 PM PDT 24
Finished Jul 12 06:44:29 PM PDT 24
Peak memory 205592 kb
Host smart-2d40d4de-e99e-4953-ac2a-fc3f7380afdc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62929670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.62929670
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.736627293
Short name T1082
Test name
Test status
Simulation time 1280787257 ps
CPU time 16.69 seconds
Started Jul 12 06:44:15 PM PDT 24
Finished Jul 12 06:44:34 PM PDT 24
Peak memory 205540 kb
Host smart-d0a6abc6-6651-4ea8-a374-f8330eada6bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736627293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.736627293
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3516540732
Short name T952
Test name
Test status
Simulation time 83730300 ps
CPU time 1.13 seconds
Started Jul 12 06:44:15 PM PDT 24
Finished Jul 12 06:44:22 PM PDT 24
Peak memory 205376 kb
Host smart-cebb2454-02e0-43ea-a8bd-f2e29c2c5403
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516540732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
516540732
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.30642616
Short name T955
Test name
Test status
Simulation time 209826221 ps
CPU time 1.75 seconds
Started Jul 12 06:44:23 PM PDT 24
Finished Jul 12 06:44:26 PM PDT 24
Peak memory 213828 kb
Host smart-d7b61874-780d-4b9c-bc04-a6fdc236c005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30642616 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.30642616
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1978479219
Short name T997
Test name
Test status
Simulation time 43567670 ps
CPU time 1.22 seconds
Started Jul 12 06:44:15 PM PDT 24
Finished Jul 12 06:44:18 PM PDT 24
Peak memory 205492 kb
Host smart-e1120614-08c8-4c5b-934b-c12d3265f902
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978479219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1978479219
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3793332092
Short name T1019
Test name
Test status
Simulation time 20160326 ps
CPU time 0.82 seconds
Started Jul 12 06:44:18 PM PDT 24
Finished Jul 12 06:44:20 PM PDT 24
Peak memory 205344 kb
Host smart-942ce9f4-bfdc-49c8-9a77-5b6c0ac3d09c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793332092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3793332092
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3863669931
Short name T142
Test name
Test status
Simulation time 46780219 ps
CPU time 1.61 seconds
Started Jul 12 06:44:16 PM PDT 24
Finished Jul 12 06:44:20 PM PDT 24
Peak memory 205436 kb
Host smart-66c8950e-31d9-427d-9110-4fa2b52177ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863669931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3863669931
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.4026071263
Short name T1062
Test name
Test status
Simulation time 56977660 ps
CPU time 1.64 seconds
Started Jul 12 06:44:16 PM PDT 24
Finished Jul 12 06:44:20 PM PDT 24
Peak memory 214124 kb
Host smart-b3a909ef-7e7c-47c9-a7b1-357ef797cc34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026071263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.4026071263
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3199071402
Short name T1065
Test name
Test status
Simulation time 1325744012 ps
CPU time 12.17 seconds
Started Jul 12 06:44:14 PM PDT 24
Finished Jul 12 06:44:28 PM PDT 24
Peak memory 214064 kb
Host smart-7e72fc22-597c-4b7d-9751-f53c9e7ca5ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199071402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3199071402
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1341670486
Short name T1077
Test name
Test status
Simulation time 179650780 ps
CPU time 2.35 seconds
Started Jul 12 06:44:17 PM PDT 24
Finished Jul 12 06:44:21 PM PDT 24
Peak memory 213780 kb
Host smart-56b83493-299d-49ea-b4e5-4e5da66d1a0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341670486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1341670486
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.275801583
Short name T404
Test name
Test status
Simulation time 176547269 ps
CPU time 3.01 seconds
Started Jul 12 06:44:17 PM PDT 24
Finished Jul 12 06:44:22 PM PDT 24
Peak memory 213760 kb
Host smart-a3d2c279-4ecd-48d5-a9fc-400c1d5f9cfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275801583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
275801583
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3682907861
Short name T1070
Test name
Test status
Simulation time 35824579 ps
CPU time 0.76 seconds
Started Jul 12 06:44:39 PM PDT 24
Finished Jul 12 06:44:41 PM PDT 24
Peak memory 205344 kb
Host smart-46075c67-735d-4813-9a15-32b20ffb3a27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682907861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3682907861
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3621601681
Short name T1044
Test name
Test status
Simulation time 18042173 ps
CPU time 0.76 seconds
Started Jul 12 06:44:57 PM PDT 24
Finished Jul 12 06:44:59 PM PDT 24
Peak memory 205376 kb
Host smart-3e81636d-7002-4f6a-a4df-33d10785f495
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621601681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3621601681
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3156536800
Short name T950
Test name
Test status
Simulation time 71804665 ps
CPU time 0.67 seconds
Started Jul 12 06:44:49 PM PDT 24
Finished Jul 12 06:44:52 PM PDT 24
Peak memory 205312 kb
Host smart-ab98108e-9d73-497d-92e2-636017639002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156536800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3156536800
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.387322948
Short name T1013
Test name
Test status
Simulation time 58931931 ps
CPU time 0.74 seconds
Started Jul 12 06:44:40 PM PDT 24
Finished Jul 12 06:44:41 PM PDT 24
Peak memory 205380 kb
Host smart-49fc850c-4655-4f2f-b220-17fc42894292
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387322948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.387322948
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2870534934
Short name T1017
Test name
Test status
Simulation time 19996319 ps
CPU time 0.73 seconds
Started Jul 12 06:44:37 PM PDT 24
Finished Jul 12 06:44:38 PM PDT 24
Peak memory 205328 kb
Host smart-b40f0db6-a64a-40c0-8595-5bf5ca69b817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870534934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2870534934
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3440028900
Short name T1049
Test name
Test status
Simulation time 13296226 ps
CPU time 0.77 seconds
Started Jul 12 06:44:40 PM PDT 24
Finished Jul 12 06:44:42 PM PDT 24
Peak memory 205376 kb
Host smart-518632d4-4565-49ad-9c5a-9022dcdb891b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440028900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3440028900
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1060309081
Short name T946
Test name
Test status
Simulation time 24414724 ps
CPU time 0.8 seconds
Started Jul 12 06:44:50 PM PDT 24
Finished Jul 12 06:44:54 PM PDT 24
Peak memory 205456 kb
Host smart-37e30b31-98f6-4839-9247-2699e72b82e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060309081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1060309081
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3618571241
Short name T948
Test name
Test status
Simulation time 12573043 ps
CPU time 0.71 seconds
Started Jul 12 06:44:44 PM PDT 24
Finished Jul 12 06:44:47 PM PDT 24
Peak memory 205312 kb
Host smart-59e93fe7-adab-4fa7-809d-1c8fe5eb808f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618571241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3618571241
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1723323494
Short name T965
Test name
Test status
Simulation time 58377216 ps
CPU time 0.78 seconds
Started Jul 12 06:44:36 PM PDT 24
Finished Jul 12 06:44:38 PM PDT 24
Peak memory 205320 kb
Host smart-c16941be-0b84-45c2-b812-f186c08051e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723323494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1723323494
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3131392357
Short name T971
Test name
Test status
Simulation time 17659151 ps
CPU time 0.91 seconds
Started Jul 12 06:44:41 PM PDT 24
Finished Jul 12 06:44:43 PM PDT 24
Peak memory 205364 kb
Host smart-89f02540-6918-48db-ad3e-aa7d6c565092
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131392357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3131392357
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3622652675
Short name T941
Test name
Test status
Simulation time 88839480 ps
CPU time 1.14 seconds
Started Jul 12 06:44:26 PM PDT 24
Finished Jul 12 06:44:29 PM PDT 24
Peak memory 205448 kb
Host smart-6e02979a-7b41-4f8d-8e3f-fbdb5dd30ad8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622652675 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3622652675
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3053837017
Short name T975
Test name
Test status
Simulation time 276417300 ps
CPU time 1.44 seconds
Started Jul 12 06:44:20 PM PDT 24
Finished Jul 12 06:44:22 PM PDT 24
Peak memory 205560 kb
Host smart-c3da3b45-be7c-4698-8b66-7aac0ad1be18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053837017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3053837017
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.179913365
Short name T1064
Test name
Test status
Simulation time 18543167 ps
CPU time 0.7 seconds
Started Jul 12 06:44:23 PM PDT 24
Finished Jul 12 06:44:24 PM PDT 24
Peak memory 205360 kb
Host smart-59fe330c-e574-4d24-bc1c-b4192ca90023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179913365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.179913365
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.694812768
Short name T1030
Test name
Test status
Simulation time 199237644 ps
CPU time 2.91 seconds
Started Jul 12 06:44:26 PM PDT 24
Finished Jul 12 06:44:30 PM PDT 24
Peak memory 205612 kb
Host smart-ac297cb3-fcc5-46f8-b5a7-dfe1ee6f28e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694812768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.694812768
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.307075039
Short name T117
Test name
Test status
Simulation time 308121191 ps
CPU time 2.34 seconds
Started Jul 12 06:44:17 PM PDT 24
Finished Jul 12 06:44:21 PM PDT 24
Peak memory 214064 kb
Host smart-af67cce4-7092-4d62-9169-d643fd48d420
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307075039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.307075039
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2673157688
Short name T1084
Test name
Test status
Simulation time 229682866 ps
CPU time 7.8 seconds
Started Jul 12 06:44:19 PM PDT 24
Finished Jul 12 06:44:28 PM PDT 24
Peak memory 219972 kb
Host smart-3b5e6612-228c-445d-9b65-afa72c5fe2b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673157688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2673157688
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.83486644
Short name T962
Test name
Test status
Simulation time 77970738 ps
CPU time 2.87 seconds
Started Jul 12 06:44:25 PM PDT 24
Finished Jul 12 06:44:28 PM PDT 24
Peak memory 213720 kb
Host smart-748d7872-036d-4306-a17d-d47a181da4e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83486644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.83486644
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.17398225
Short name T1057
Test name
Test status
Simulation time 206073670 ps
CPU time 4.54 seconds
Started Jul 12 06:44:25 PM PDT 24
Finished Jul 12 06:44:30 PM PDT 24
Peak memory 213672 kb
Host smart-93757988-28b8-480d-83ba-01bda05d9f12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17398225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.17398225
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1561944694
Short name T943
Test name
Test status
Simulation time 48214810 ps
CPU time 1.56 seconds
Started Jul 12 06:44:25 PM PDT 24
Finished Jul 12 06:44:28 PM PDT 24
Peak memory 213924 kb
Host smart-ae18d005-9322-47fa-858d-d64a52b0515a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561944694 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1561944694
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3231735396
Short name T139
Test name
Test status
Simulation time 119741733 ps
CPU time 1.15 seconds
Started Jul 12 06:44:43 PM PDT 24
Finished Jul 12 06:44:47 PM PDT 24
Peak memory 205624 kb
Host smart-4d61c8e5-ab51-4f25-be2f-0fc5c2c763f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231735396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3231735396
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2524067105
Short name T1038
Test name
Test status
Simulation time 10793103 ps
CPU time 0.84 seconds
Started Jul 12 06:44:24 PM PDT 24
Finished Jul 12 06:44:26 PM PDT 24
Peak memory 205364 kb
Host smart-142d0fed-2cb4-45db-a262-4dc149eec1fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524067105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2524067105
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.591185928
Short name T143
Test name
Test status
Simulation time 58923937 ps
CPU time 1.79 seconds
Started Jul 12 06:44:25 PM PDT 24
Finished Jul 12 06:44:28 PM PDT 24
Peak memory 205492 kb
Host smart-c76f5b15-f89f-4fc6-a961-f6b1652aff46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591185928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.591185928
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2332571370
Short name T1023
Test name
Test status
Simulation time 377312210 ps
CPU time 2.02 seconds
Started Jul 12 06:44:22 PM PDT 24
Finished Jul 12 06:44:24 PM PDT 24
Peak memory 214136 kb
Host smart-202963d2-80c6-453f-b3ba-d2f12481fc37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332571370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2332571370
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.42904780
Short name T961
Test name
Test status
Simulation time 175415071 ps
CPU time 8.68 seconds
Started Jul 12 06:44:25 PM PDT 24
Finished Jul 12 06:44:35 PM PDT 24
Peak memory 214204 kb
Host smart-b4e227a6-f3a5-4682-8598-52a1e6fa1ef1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42904780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.ke
ymgr_shadow_reg_errors_with_csr_rw.42904780
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2209869645
Short name T981
Test name
Test status
Simulation time 206860541 ps
CPU time 3.99 seconds
Started Jul 12 06:44:25 PM PDT 24
Finished Jul 12 06:44:30 PM PDT 24
Peak memory 213800 kb
Host smart-17db8430-a335-414b-9f83-e782a695c917
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209869645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2209869645
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3505967943
Short name T998
Test name
Test status
Simulation time 42356692 ps
CPU time 1.87 seconds
Started Jul 12 06:44:20 PM PDT 24
Finished Jul 12 06:44:22 PM PDT 24
Peak memory 205608 kb
Host smart-3f6986ed-eb1d-44fa-a7cc-4ba2e0e0e3e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505967943 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3505967943
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3227287934
Short name T1050
Test name
Test status
Simulation time 13307392 ps
CPU time 1.02 seconds
Started Jul 12 06:44:27 PM PDT 24
Finished Jul 12 06:44:29 PM PDT 24
Peak memory 205524 kb
Host smart-aef299dc-c3bc-4ef0-a310-cf6445187d7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227287934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3227287934
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.330408623
Short name T978
Test name
Test status
Simulation time 87808834 ps
CPU time 0.8 seconds
Started Jul 12 06:44:24 PM PDT 24
Finished Jul 12 06:44:25 PM PDT 24
Peak memory 205352 kb
Host smart-e9ec49a1-1a85-4018-9d24-a002cca33dea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330408623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.330408623
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2424141300
Short name T1039
Test name
Test status
Simulation time 117916848 ps
CPU time 2.75 seconds
Started Jul 12 06:44:33 PM PDT 24
Finished Jul 12 06:44:37 PM PDT 24
Peak memory 205508 kb
Host smart-42ae209f-45f6-4924-ab29-b3b33865878d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424141300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2424141300
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3784605044
Short name T972
Test name
Test status
Simulation time 77395381 ps
CPU time 2.44 seconds
Started Jul 12 06:44:44 PM PDT 24
Finished Jul 12 06:44:49 PM PDT 24
Peak memory 213996 kb
Host smart-ce22ac9d-a4e1-4dcd-bcf1-cc9c9b840c36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784605044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3784605044
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1092595103
Short name T1010
Test name
Test status
Simulation time 90533166 ps
CPU time 3.62 seconds
Started Jul 12 06:44:19 PM PDT 24
Finished Jul 12 06:44:23 PM PDT 24
Peak memory 214096 kb
Host smart-cb689b51-59ec-4d8c-aacf-2473d9dac8eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092595103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1092595103
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3577310319
Short name T1087
Test name
Test status
Simulation time 27535109 ps
CPU time 1.97 seconds
Started Jul 12 06:44:21 PM PDT 24
Finished Jul 12 06:44:23 PM PDT 24
Peak memory 213768 kb
Host smart-e95647f5-22a8-4ede-a440-8a466437c54e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577310319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3577310319
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.509701310
Short name T157
Test name
Test status
Simulation time 144444616 ps
CPU time 4.06 seconds
Started Jul 12 06:44:28 PM PDT 24
Finished Jul 12 06:44:34 PM PDT 24
Peak memory 214676 kb
Host smart-95b3068d-a88f-4bab-9cb8-bfc280a16084
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509701310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
509701310
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1963929536
Short name T949
Test name
Test status
Simulation time 58311194 ps
CPU time 1.34 seconds
Started Jul 12 06:44:44 PM PDT 24
Finished Jul 12 06:44:47 PM PDT 24
Peak memory 205456 kb
Host smart-f1ae5278-a40e-409f-8d60-74e17275f950
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963929536 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1963929536
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2139022222
Short name T960
Test name
Test status
Simulation time 21645861 ps
CPU time 1.41 seconds
Started Jul 12 06:44:38 PM PDT 24
Finished Jul 12 06:44:40 PM PDT 24
Peak memory 205596 kb
Host smart-343848c2-5bcc-4f28-990d-741ba5715f09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139022222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2139022222
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2231163591
Short name T947
Test name
Test status
Simulation time 10819013 ps
CPU time 0.71 seconds
Started Jul 12 06:44:24 PM PDT 24
Finished Jul 12 06:44:25 PM PDT 24
Peak memory 205292 kb
Host smart-b261b0f2-d4b1-4581-8d21-31a4bb685e70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231163591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2231163591
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3721526640
Short name T1026
Test name
Test status
Simulation time 28965611 ps
CPU time 1.34 seconds
Started Jul 12 06:44:28 PM PDT 24
Finished Jul 12 06:44:31 PM PDT 24
Peak memory 205540 kb
Host smart-dc68366f-e2a7-4408-9580-210a8022db46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721526640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3721526640
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.666248336
Short name T1059
Test name
Test status
Simulation time 133720083 ps
CPU time 1.8 seconds
Started Jul 12 06:44:25 PM PDT 24
Finished Jul 12 06:44:27 PM PDT 24
Peak memory 214112 kb
Host smart-0793ab4e-be90-4f0a-a08f-10666b80b591
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666248336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.666248336
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.780913953
Short name T1063
Test name
Test status
Simulation time 575904164 ps
CPU time 7.25 seconds
Started Jul 12 06:44:23 PM PDT 24
Finished Jul 12 06:44:31 PM PDT 24
Peak memory 213992 kb
Host smart-d1d0c0c6-42a9-4a4a-b48a-3739396e53bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780913953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.780913953
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2922349653
Short name T956
Test name
Test status
Simulation time 99016873 ps
CPU time 2.2 seconds
Started Jul 12 06:44:25 PM PDT 24
Finished Jul 12 06:44:28 PM PDT 24
Peak memory 215716 kb
Host smart-b6da7d62-96e1-4d3f-8381-f926626cd127
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922349653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2922349653
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2873568239
Short name T160
Test name
Test status
Simulation time 445640821 ps
CPU time 4.09 seconds
Started Jul 12 06:44:26 PM PDT 24
Finished Jul 12 06:44:31 PM PDT 24
Peak memory 213768 kb
Host smart-1f8edbbe-2176-43a8-a413-151de92f6ee1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873568239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2873568239
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3765637315
Short name T1024
Test name
Test status
Simulation time 151127815 ps
CPU time 1.37 seconds
Started Jul 12 06:44:30 PM PDT 24
Finished Jul 12 06:44:34 PM PDT 24
Peak memory 213852 kb
Host smart-affa134a-0027-40b4-981d-3c6a25e1ca1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765637315 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3765637315
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2788422914
Short name T1029
Test name
Test status
Simulation time 18569013 ps
CPU time 0.98 seconds
Started Jul 12 06:44:29 PM PDT 24
Finished Jul 12 06:44:33 PM PDT 24
Peak memory 205508 kb
Host smart-82ccbc76-a055-4fbc-968e-455223ac8b46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788422914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2788422914
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3832837979
Short name T976
Test name
Test status
Simulation time 19064947 ps
CPU time 0.78 seconds
Started Jul 12 06:44:50 PM PDT 24
Finished Jul 12 06:44:53 PM PDT 24
Peak memory 205276 kb
Host smart-ef2e5fd3-2c0d-4e7d-a7a5-7c48bab7a8ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832837979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3832837979
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2737039530
Short name T1056
Test name
Test status
Simulation time 320129727 ps
CPU time 2.24 seconds
Started Jul 12 06:44:48 PM PDT 24
Finished Jul 12 06:44:53 PM PDT 24
Peak memory 205636 kb
Host smart-3f90651d-554a-4f85-b64c-8a921907d7ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737039530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2737039530
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3571667517
Short name T1042
Test name
Test status
Simulation time 855934657 ps
CPU time 1.85 seconds
Started Jul 12 06:44:33 PM PDT 24
Finished Jul 12 06:44:36 PM PDT 24
Peak memory 214076 kb
Host smart-5b13d234-f808-43b3-af19-c6a2e89d5085
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571667517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3571667517
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1084946403
Short name T1006
Test name
Test status
Simulation time 314826472 ps
CPU time 3.6 seconds
Started Jul 12 06:44:31 PM PDT 24
Finished Jul 12 06:44:36 PM PDT 24
Peak memory 214112 kb
Host smart-24b0a3c7-aac5-4834-a539-6102e44bd01d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084946403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1084946403
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2771551506
Short name T179
Test name
Test status
Simulation time 333995903 ps
CPU time 3.31 seconds
Started Jul 12 06:44:28 PM PDT 24
Finished Jul 12 06:44:33 PM PDT 24
Peak memory 215960 kb
Host smart-3cb842e8-6b51-408b-a8e5-1c6b78577b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771551506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2771551506
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.4290076761
Short name T873
Test name
Test status
Simulation time 13532059 ps
CPU time 0.97 seconds
Started Jul 12 06:39:47 PM PDT 24
Finished Jul 12 06:39:50 PM PDT 24
Peak memory 206056 kb
Host smart-ad843b7e-3fc7-4e86-acd4-6e25dae87cdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290076761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.4290076761
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1234158474
Short name T341
Test name
Test status
Simulation time 528996683 ps
CPU time 2.91 seconds
Started Jul 12 06:39:48 PM PDT 24
Finished Jul 12 06:39:52 PM PDT 24
Peak memory 214312 kb
Host smart-253c2c98-8074-4240-ae3c-c41f53bc83b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234158474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1234158474
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.990834778
Short name T41
Test name
Test status
Simulation time 3964975170 ps
CPU time 13.52 seconds
Started Jul 12 06:39:48 PM PDT 24
Finished Jul 12 06:40:03 PM PDT 24
Peak memory 214504 kb
Host smart-29d0ebef-37fa-4967-9565-8ec3bacd8931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990834778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.990834778
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2842477047
Short name T742
Test name
Test status
Simulation time 684753117 ps
CPU time 5.41 seconds
Started Jul 12 06:39:56 PM PDT 24
Finished Jul 12 06:40:03 PM PDT 24
Peak memory 207788 kb
Host smart-149d7a26-20b2-4e3e-bf9b-465190748dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842477047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2842477047
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.64801430
Short name T290
Test name
Test status
Simulation time 113864308 ps
CPU time 3.57 seconds
Started Jul 12 06:39:53 PM PDT 24
Finished Jul 12 06:39:58 PM PDT 24
Peak memory 209872 kb
Host smart-8e644a61-03b3-4589-bab7-30855c245c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64801430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.64801430
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2517630068
Short name T539
Test name
Test status
Simulation time 640676035 ps
CPU time 2.67 seconds
Started Jul 12 06:39:50 PM PDT 24
Finished Jul 12 06:39:54 PM PDT 24
Peak memory 207496 kb
Host smart-4e4436c1-615f-4709-b1a4-8505236601b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517630068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2517630068
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.635246903
Short name T272
Test name
Test status
Simulation time 23216005 ps
CPU time 1.98 seconds
Started Jul 12 06:39:56 PM PDT 24
Finished Jul 12 06:40:00 PM PDT 24
Peak memory 208440 kb
Host smart-b82d475a-b226-4d2c-9c97-938dbdb37fc2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635246903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.635246903
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2428559432
Short name T854
Test name
Test status
Simulation time 823994532 ps
CPU time 11.72 seconds
Started Jul 12 06:39:49 PM PDT 24
Finished Jul 12 06:40:02 PM PDT 24
Peak memory 208772 kb
Host smart-254c6acd-f3c3-4385-865f-831537da6d1b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428559432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2428559432
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3163303108
Short name T296
Test name
Test status
Simulation time 130121335 ps
CPU time 2.04 seconds
Started Jul 12 06:39:48 PM PDT 24
Finished Jul 12 06:39:52 PM PDT 24
Peak memory 207712 kb
Host smart-ae376f31-4a75-4251-9d85-728a5c5e0796
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163303108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3163303108
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2749594257
Short name T309
Test name
Test status
Simulation time 259989865 ps
CPU time 3.22 seconds
Started Jul 12 06:39:55 PM PDT 24
Finished Jul 12 06:40:00 PM PDT 24
Peak memory 218260 kb
Host smart-aa73bc39-9f90-4cdc-a4ee-c7ffa694f058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749594257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2749594257
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1860793443
Short name T585
Test name
Test status
Simulation time 67220794 ps
CPU time 2.29 seconds
Started Jul 12 06:39:50 PM PDT 24
Finished Jul 12 06:39:54 PM PDT 24
Peak memory 207020 kb
Host smart-155a60a4-c0b9-4efd-9092-18288014c67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860793443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1860793443
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2865860438
Short name T270
Test name
Test status
Simulation time 519546605 ps
CPU time 12.64 seconds
Started Jul 12 06:39:49 PM PDT 24
Finished Jul 12 06:40:03 PM PDT 24
Peak memory 219772 kb
Host smart-7c8c31cd-32fc-4dc5-93d2-a05db9465efb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865860438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2865860438
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3834636484
Short name T194
Test name
Test status
Simulation time 382287170 ps
CPU time 8.97 seconds
Started Jul 12 06:39:49 PM PDT 24
Finished Jul 12 06:39:59 PM PDT 24
Peak memory 222456 kb
Host smart-df8ad997-1ef5-441d-b445-6855e86870b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834636484 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3834636484
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2511799825
Short name T220
Test name
Test status
Simulation time 33175296 ps
CPU time 2.5 seconds
Started Jul 12 06:39:54 PM PDT 24
Finished Jul 12 06:39:57 PM PDT 24
Peak memory 207500 kb
Host smart-0f1c169d-8e79-40a2-8b27-5739dd570db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511799825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2511799825
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3758700480
Short name T423
Test name
Test status
Simulation time 104822558 ps
CPU time 1.24 seconds
Started Jul 12 06:39:50 PM PDT 24
Finished Jul 12 06:39:53 PM PDT 24
Peak memory 209560 kb
Host smart-4f110ba2-5be6-47a2-8cc4-28d9d6c198a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758700480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3758700480
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2689105868
Short name T745
Test name
Test status
Simulation time 50783971 ps
CPU time 0.95 seconds
Started Jul 12 06:39:54 PM PDT 24
Finished Jul 12 06:39:57 PM PDT 24
Peak memory 205936 kb
Host smart-c6b19366-181d-458c-864f-c250e4309ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689105868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2689105868
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3063929685
Short name T425
Test name
Test status
Simulation time 68391343 ps
CPU time 2.96 seconds
Started Jul 12 06:39:53 PM PDT 24
Finished Jul 12 06:39:57 PM PDT 24
Peak memory 215076 kb
Host smart-984d6e12-4ee9-4fb5-b0d9-66668de09c40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3063929685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3063929685
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2908594740
Short name T197
Test name
Test status
Simulation time 104281491 ps
CPU time 4.56 seconds
Started Jul 12 06:39:56 PM PDT 24
Finished Jul 12 06:40:02 PM PDT 24
Peak memory 219224 kb
Host smart-a25e042b-b9ed-4ccf-9275-75e83b591888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908594740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2908594740
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.939294717
Short name T772
Test name
Test status
Simulation time 72497602 ps
CPU time 2.37 seconds
Started Jul 12 06:39:56 PM PDT 24
Finished Jul 12 06:40:00 PM PDT 24
Peak memory 209428 kb
Host smart-23ce8320-b4fb-4616-80ef-cd8fcc8e065c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939294717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.939294717
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2018642629
Short name T535
Test name
Test status
Simulation time 52399516 ps
CPU time 2.02 seconds
Started Jul 12 06:40:13 PM PDT 24
Finished Jul 12 06:40:19 PM PDT 24
Peak memory 214336 kb
Host smart-c2495ffe-4c58-4ab6-ba3a-7a10505c1bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018642629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2018642629
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3114388778
Short name T855
Test name
Test status
Simulation time 100874684 ps
CPU time 4.62 seconds
Started Jul 12 06:39:55 PM PDT 24
Finished Jul 12 06:40:01 PM PDT 24
Peak memory 210152 kb
Host smart-0de275d3-3f83-4515-bb0c-3aa7c21f2136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114388778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3114388778
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2532940685
Short name T825
Test name
Test status
Simulation time 2085722905 ps
CPU time 38.61 seconds
Started Jul 12 06:39:58 PM PDT 24
Finished Jul 12 06:40:37 PM PDT 24
Peak memory 214352 kb
Host smart-d4022f98-a377-4d16-96ad-f77f9eedae99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532940685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2532940685
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2102082145
Short name T371
Test name
Test status
Simulation time 131022487 ps
CPU time 4.26 seconds
Started Jul 12 06:39:56 PM PDT 24
Finished Jul 12 06:40:02 PM PDT 24
Peak memory 208624 kb
Host smart-880d4a3d-ea7a-4dd0-8d13-f827feb82149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102082145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2102082145
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.378357587
Short name T486
Test name
Test status
Simulation time 50604321 ps
CPU time 2.44 seconds
Started Jul 12 06:39:55 PM PDT 24
Finished Jul 12 06:39:59 PM PDT 24
Peak memory 207948 kb
Host smart-73713839-5768-4ad8-835f-c139b52ed5b8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378357587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.378357587
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.54749163
Short name T631
Test name
Test status
Simulation time 1571443912 ps
CPU time 26.12 seconds
Started Jul 12 06:39:52 PM PDT 24
Finished Jul 12 06:40:19 PM PDT 24
Peak memory 208952 kb
Host smart-1861c33d-5726-4aa0-9302-1aefc499306c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54749163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.54749163
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2128063169
Short name T565
Test name
Test status
Simulation time 64176877 ps
CPU time 2.42 seconds
Started Jul 12 06:40:13 PM PDT 24
Finished Jul 12 06:40:19 PM PDT 24
Peak memory 207324 kb
Host smart-a55bea85-14ba-401d-ae6d-7e6f9b8d1cee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128063169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2128063169
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2117134712
Short name T594
Test name
Test status
Simulation time 158668830 ps
CPU time 2.04 seconds
Started Jul 12 06:39:55 PM PDT 24
Finished Jul 12 06:39:58 PM PDT 24
Peak memory 209292 kb
Host smart-5a378d0f-4ac9-477e-8be3-8854630a473d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117134712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2117134712
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2633371376
Short name T529
Test name
Test status
Simulation time 346417569 ps
CPU time 3.62 seconds
Started Jul 12 06:39:51 PM PDT 24
Finished Jul 12 06:39:56 PM PDT 24
Peak memory 208820 kb
Host smart-b026f9fe-62d7-45b2-8c28-2ab0f83e6689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633371376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2633371376
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.122780171
Short name T536
Test name
Test status
Simulation time 1162463245 ps
CPU time 11.2 seconds
Started Jul 12 06:39:56 PM PDT 24
Finished Jul 12 06:40:09 PM PDT 24
Peak memory 214532 kb
Host smart-77e5c959-5af0-4cee-8e3b-c2e0ac0a41a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122780171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.122780171
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3798906064
Short name T795
Test name
Test status
Simulation time 345806844 ps
CPU time 13.72 seconds
Started Jul 12 06:39:55 PM PDT 24
Finished Jul 12 06:40:10 PM PDT 24
Peak memory 222624 kb
Host smart-4f8784d7-2ffc-4471-89da-ee2c0c95fceb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798906064 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3798906064
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2159829965
Short name T418
Test name
Test status
Simulation time 708111295 ps
CPU time 8.19 seconds
Started Jul 12 06:39:54 PM PDT 24
Finished Jul 12 06:40:04 PM PDT 24
Peak memory 207524 kb
Host smart-a6427321-4114-45c2-99e1-e3165dba5da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159829965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2159829965
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.224267032
Short name T731
Test name
Test status
Simulation time 115651665 ps
CPU time 2.9 seconds
Started Jul 12 06:39:56 PM PDT 24
Finished Jul 12 06:40:01 PM PDT 24
Peak memory 210328 kb
Host smart-04ed4700-1c11-44b9-a26d-089b0d3ea0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224267032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.224267032
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1288307311
Short name T653
Test name
Test status
Simulation time 26088625 ps
CPU time 0.7 seconds
Started Jul 12 06:40:24 PM PDT 24
Finished Jul 12 06:40:28 PM PDT 24
Peak memory 205988 kb
Host smart-d2425c0f-561e-4a89-bdbf-ee5c44ad1fe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288307311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1288307311
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3977534802
Short name T9
Test name
Test status
Simulation time 227236365 ps
CPU time 2.19 seconds
Started Jul 12 06:40:34 PM PDT 24
Finished Jul 12 06:40:39 PM PDT 24
Peak memory 220976 kb
Host smart-8d699a0b-a67b-4b42-9b7c-d79e40637889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977534802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3977534802
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.222324040
Short name T532
Test name
Test status
Simulation time 43953681 ps
CPU time 2.14 seconds
Started Jul 12 06:40:23 PM PDT 24
Finished Jul 12 06:40:29 PM PDT 24
Peak memory 210160 kb
Host smart-7169bcf0-0f30-428e-a6a5-497fba506a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222324040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.222324040
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3795636792
Short name T342
Test name
Test status
Simulation time 131069389 ps
CPU time 3.42 seconds
Started Jul 12 06:40:18 PM PDT 24
Finished Jul 12 06:40:27 PM PDT 24
Peak memory 214300 kb
Host smart-b0a102a1-38a4-44df-a525-5c4e93b8c165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795636792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3795636792
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.371988103
Short name T99
Test name
Test status
Simulation time 477396453 ps
CPU time 4.53 seconds
Started Jul 12 06:40:24 PM PDT 24
Finished Jul 12 06:40:32 PM PDT 24
Peak memory 222352 kb
Host smart-969256d3-c957-4804-816e-23ab9b8358db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371988103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.371988103
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.4075350510
Short name T840
Test name
Test status
Simulation time 121804864 ps
CPU time 3.69 seconds
Started Jul 12 06:40:29 PM PDT 24
Finished Jul 12 06:40:37 PM PDT 24
Peak memory 220172 kb
Host smart-d8d0db91-4ac1-4899-8bdf-1f7781b1f680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075350510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.4075350510
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.685490163
Short name T430
Test name
Test status
Simulation time 371339940 ps
CPU time 4.37 seconds
Started Jul 12 06:40:12 PM PDT 24
Finished Jul 12 06:40:20 PM PDT 24
Peak memory 207296 kb
Host smart-6c41a827-67f3-4947-9d42-7da6a37186e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685490163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.685490163
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2008108403
Short name T212
Test name
Test status
Simulation time 64688586 ps
CPU time 2.7 seconds
Started Jul 12 06:40:14 PM PDT 24
Finished Jul 12 06:40:21 PM PDT 24
Peak memory 208244 kb
Host smart-fa931729-e5f3-49a0-97db-e10df9155612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008108403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2008108403
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3380544145
Short name T542
Test name
Test status
Simulation time 62191704 ps
CPU time 3.28 seconds
Started Jul 12 06:40:20 PM PDT 24
Finished Jul 12 06:40:29 PM PDT 24
Peak memory 208632 kb
Host smart-4c29b5fb-0a61-4938-a2b5-1808d93e0f41
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380544145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3380544145
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.707053877
Short name T647
Test name
Test status
Simulation time 228669146 ps
CPU time 5.85 seconds
Started Jul 12 06:40:13 PM PDT 24
Finished Jul 12 06:40:23 PM PDT 24
Peak memory 208008 kb
Host smart-3626a7a7-3184-46b7-b33d-ddb4c1dbdc70
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707053877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.707053877
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2246835760
Short name T210
Test name
Test status
Simulation time 249494248 ps
CPU time 3.21 seconds
Started Jul 12 06:40:16 PM PDT 24
Finished Jul 12 06:40:24 PM PDT 24
Peak memory 208568 kb
Host smart-0dcb7123-1e8a-4e9a-b215-5e5bf98bea90
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246835760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2246835760
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.902521564
Short name T343
Test name
Test status
Simulation time 96898563 ps
CPU time 2.07 seconds
Started Jul 12 06:40:19 PM PDT 24
Finished Jul 12 06:40:26 PM PDT 24
Peak memory 214360 kb
Host smart-78f999c7-1dde-4ab3-ba3c-ad9fd445eff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902521564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.902521564
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3699885896
Short name T434
Test name
Test status
Simulation time 57984170 ps
CPU time 2.75 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:35 PM PDT 24
Peak memory 208672 kb
Host smart-fee67c22-65ed-4c00-bc4a-59243d22e947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699885896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3699885896
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1324624289
Short name T314
Test name
Test status
Simulation time 1243338606 ps
CPU time 34.54 seconds
Started Jul 12 06:40:33 PM PDT 24
Finished Jul 12 06:41:11 PM PDT 24
Peak memory 215984 kb
Host smart-32b6027f-39af-45ec-b2e0-a3021e0ab450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324624289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1324624289
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3959883602
Short name T857
Test name
Test status
Simulation time 90592714 ps
CPU time 4.25 seconds
Started Jul 12 06:40:29 PM PDT 24
Finished Jul 12 06:40:38 PM PDT 24
Peak memory 208780 kb
Host smart-12d979d0-b780-44e4-81c3-f44a5f07734c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959883602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3959883602
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2896003158
Short name T833
Test name
Test status
Simulation time 35617534 ps
CPU time 0.72 seconds
Started Jul 12 06:40:29 PM PDT 24
Finished Jul 12 06:40:34 PM PDT 24
Peak memory 205948 kb
Host smart-409ec800-408a-4349-8990-6c20b4ed07a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896003158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2896003158
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3602381122
Short name T311
Test name
Test status
Simulation time 216374309 ps
CPU time 3.85 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:37 PM PDT 24
Peak memory 215572 kb
Host smart-e90df191-f1fc-4588-ac80-425e6136242a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3602381122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3602381122
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.854678066
Short name T687
Test name
Test status
Simulation time 82363200 ps
CPU time 3.39 seconds
Started Jul 12 06:40:19 PM PDT 24
Finished Jul 12 06:40:28 PM PDT 24
Peak memory 214716 kb
Host smart-b097f617-123e-4625-a430-fc442088e52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854678066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.854678066
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.486327062
Short name T66
Test name
Test status
Simulation time 347204753 ps
CPU time 7.13 seconds
Started Jul 12 06:40:16 PM PDT 24
Finished Jul 12 06:40:28 PM PDT 24
Peak memory 208020 kb
Host smart-9a494608-145e-440e-ba7c-ba10f4153e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486327062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.486327062
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1178459000
Short name T378
Test name
Test status
Simulation time 226714560 ps
CPU time 4.34 seconds
Started Jul 12 06:40:33 PM PDT 24
Finished Jul 12 06:40:41 PM PDT 24
Peak memory 211236 kb
Host smart-3f1f1c0d-b859-4311-912f-c41316fc52bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178459000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1178459000
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.4056182254
Short name T45
Test name
Test status
Simulation time 76716968 ps
CPU time 2.88 seconds
Started Jul 12 06:40:33 PM PDT 24
Finished Jul 12 06:40:39 PM PDT 24
Peak memory 209836 kb
Host smart-cbe9b20f-9c25-447f-b671-ff965886f08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056182254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.4056182254
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2550626292
Short name T475
Test name
Test status
Simulation time 173772002 ps
CPU time 4.9 seconds
Started Jul 12 06:40:33 PM PDT 24
Finished Jul 12 06:40:41 PM PDT 24
Peak memory 218076 kb
Host smart-e30727c8-238d-47ca-9b7b-bc91101995c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550626292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2550626292
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2883747642
Short name T313
Test name
Test status
Simulation time 227162517 ps
CPU time 3.31 seconds
Started Jul 12 06:40:16 PM PDT 24
Finished Jul 12 06:40:24 PM PDT 24
Peak memory 208780 kb
Host smart-7bd460ba-0322-4cee-9fcd-6b46ca6274c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883747642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2883747642
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3212464365
Short name T447
Test name
Test status
Simulation time 803463223 ps
CPU time 5.92 seconds
Started Jul 12 06:40:33 PM PDT 24
Finished Jul 12 06:40:41 PM PDT 24
Peak memory 208004 kb
Host smart-b4af60ae-ea7e-413c-b1c1-50f11e7655b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212464365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3212464365
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.2874565295
Short name T633
Test name
Test status
Simulation time 215234977 ps
CPU time 6.12 seconds
Started Jul 12 06:40:24 PM PDT 24
Finished Jul 12 06:40:33 PM PDT 24
Peak memory 208180 kb
Host smart-879f9db4-672f-41ed-80ee-05a321d83cca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874565295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2874565295
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2112049845
Short name T670
Test name
Test status
Simulation time 62119390 ps
CPU time 2.27 seconds
Started Jul 12 06:40:17 PM PDT 24
Finished Jul 12 06:40:24 PM PDT 24
Peak memory 207416 kb
Host smart-69178e90-1ee4-442a-8b0a-7ad5302ee6b2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112049845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2112049845
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.222457456
Short name T879
Test name
Test status
Simulation time 411216956 ps
CPU time 3.17 seconds
Started Jul 12 06:40:27 PM PDT 24
Finished Jul 12 06:40:34 PM PDT 24
Peak memory 215756 kb
Host smart-222a93e9-e35a-479b-aa21-0f007d3a1842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222457456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.222457456
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3726624831
Short name T528
Test name
Test status
Simulation time 223751946 ps
CPU time 2.75 seconds
Started Jul 12 06:40:17 PM PDT 24
Finished Jul 12 06:40:24 PM PDT 24
Peak memory 207916 kb
Host smart-d4f9b7aa-d9ae-4676-99bc-107de9a03f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726624831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3726624831
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.4128072303
Short name T767
Test name
Test status
Simulation time 75656376729 ps
CPU time 344.14 seconds
Started Jul 12 06:40:27 PM PDT 24
Finished Jul 12 06:46:15 PM PDT 24
Peak memory 218296 kb
Host smart-f91e50ad-ad0b-45d5-b9f7-ec5d59fdc1d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128072303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.4128072303
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2076283619
Short name T862
Test name
Test status
Simulation time 655188497 ps
CPU time 5.46 seconds
Started Jul 12 06:40:33 PM PDT 24
Finished Jul 12 06:40:42 PM PDT 24
Peak memory 214304 kb
Host smart-2e8d64e4-9d58-4966-90c9-66e8a66e527f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076283619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2076283619
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1345830118
Short name T759
Test name
Test status
Simulation time 114319771 ps
CPU time 2.82 seconds
Started Jul 12 06:40:18 PM PDT 24
Finished Jul 12 06:40:25 PM PDT 24
Peak memory 210516 kb
Host smart-7ec4e988-af32-4c6e-9b69-907974fcdf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345830118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1345830118
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1939840759
Short name T8
Test name
Test status
Simulation time 57661531 ps
CPU time 2.14 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:35 PM PDT 24
Peak memory 214668 kb
Host smart-d18b063f-8dfb-40b4-b26f-0561a5585912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939840759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1939840759
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1813479749
Short name T185
Test name
Test status
Simulation time 66392042 ps
CPU time 1.77 seconds
Started Jul 12 06:40:29 PM PDT 24
Finished Jul 12 06:40:35 PM PDT 24
Peak memory 214268 kb
Host smart-4dd42e6d-e4f5-4cbd-886b-f655521f4bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813479749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1813479749
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1079220388
Short name T16
Test name
Test status
Simulation time 329403835 ps
CPU time 4.39 seconds
Started Jul 12 06:40:29 PM PDT 24
Finished Jul 12 06:40:37 PM PDT 24
Peak memory 209664 kb
Host smart-af19612e-9417-4bff-8f28-1d710ddb1577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079220388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1079220388
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1281879998
Short name T572
Test name
Test status
Simulation time 58497439 ps
CPU time 3.93 seconds
Started Jul 12 06:40:19 PM PDT 24
Finished Jul 12 06:40:28 PM PDT 24
Peak memory 214476 kb
Host smart-42ea711f-6163-45a7-84b9-1ece356f4b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281879998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1281879998
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.762362299
Short name T18
Test name
Test status
Simulation time 412877327 ps
CPU time 5.01 seconds
Started Jul 12 06:40:26 PM PDT 24
Finished Jul 12 06:40:34 PM PDT 24
Peak memory 207596 kb
Host smart-7400e07b-5178-4390-baf3-a19fb914fbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762362299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.762362299
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1026327943
Short name T318
Test name
Test status
Simulation time 282680588 ps
CPU time 2.47 seconds
Started Jul 12 06:40:23 PM PDT 24
Finished Jul 12 06:40:30 PM PDT 24
Peak memory 207336 kb
Host smart-c88d41b1-f5aa-4f45-9a6d-47db7c59b729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026327943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1026327943
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1820079600
Short name T505
Test name
Test status
Simulation time 23281379 ps
CPU time 1.86 seconds
Started Jul 12 06:40:33 PM PDT 24
Finished Jul 12 06:40:38 PM PDT 24
Peak memory 207036 kb
Host smart-d4c42661-ce60-4b37-8fba-7904c8f67114
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820079600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1820079600
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1640917154
Short name T610
Test name
Test status
Simulation time 142377223 ps
CPU time 4.42 seconds
Started Jul 12 06:40:17 PM PDT 24
Finished Jul 12 06:40:26 PM PDT 24
Peak memory 208748 kb
Host smart-66c612c5-35a6-42c2-83b6-3a9ee0aa460b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640917154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1640917154
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.576559109
Short name T712
Test name
Test status
Simulation time 480447951 ps
CPU time 5.23 seconds
Started Jul 12 06:40:22 PM PDT 24
Finished Jul 12 06:40:32 PM PDT 24
Peak memory 208488 kb
Host smart-556f66fc-21c4-4d77-84af-ae5597471836
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576559109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.576559109
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3652867178
Short name T305
Test name
Test status
Simulation time 32338417 ps
CPU time 2.3 seconds
Started Jul 12 06:40:23 PM PDT 24
Finished Jul 12 06:40:29 PM PDT 24
Peak memory 214388 kb
Host smart-5a630b55-c24c-4233-89c1-e1e6d7704e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652867178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3652867178
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2026464782
Short name T545
Test name
Test status
Simulation time 20524352 ps
CPU time 1.65 seconds
Started Jul 12 06:40:22 PM PDT 24
Finished Jul 12 06:40:28 PM PDT 24
Peak memory 206780 kb
Host smart-054957f2-38b6-45cd-9601-06803bf5e98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026464782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2026464782
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.4156042843
Short name T208
Test name
Test status
Simulation time 2405559957 ps
CPU time 56.64 seconds
Started Jul 12 06:40:29 PM PDT 24
Finished Jul 12 06:41:30 PM PDT 24
Peak memory 216824 kb
Host smart-5a95ed14-90f6-4410-b896-09e7f3c85bb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156042843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.4156042843
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.927733316
Short name T622
Test name
Test status
Simulation time 118527207 ps
CPU time 3.2 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:36 PM PDT 24
Peak memory 214328 kb
Host smart-e2eb2a2e-6f52-4c7e-ae58-889a4d5e30b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927733316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.927733316
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2575811557
Short name T162
Test name
Test status
Simulation time 316231436 ps
CPU time 2.46 seconds
Started Jul 12 06:40:26 PM PDT 24
Finished Jul 12 06:40:31 PM PDT 24
Peak memory 210004 kb
Host smart-844afa29-3043-4f5e-b2ee-7ea0e531de1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575811557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2575811557
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1765597633
Short name T444
Test name
Test status
Simulation time 69648605 ps
CPU time 0.88 seconds
Started Jul 12 06:40:23 PM PDT 24
Finished Jul 12 06:40:28 PM PDT 24
Peak memory 205864 kb
Host smart-9ed3ed3b-5a05-43df-9199-ce37e644b820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765597633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1765597633
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.334520519
Short name T146
Test name
Test status
Simulation time 38021427 ps
CPU time 3.02 seconds
Started Jul 12 06:40:24 PM PDT 24
Finished Jul 12 06:40:30 PM PDT 24
Peak memory 214748 kb
Host smart-cd13bc88-75e1-4fc5-a49c-01523177e921
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=334520519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.334520519
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1995052039
Short name T38
Test name
Test status
Simulation time 404658765 ps
CPU time 2.7 seconds
Started Jul 12 06:40:23 PM PDT 24
Finished Jul 12 06:40:30 PM PDT 24
Peak memory 220216 kb
Host smart-3829bab6-5def-412b-9600-43a1f952e9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995052039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1995052039
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3491383345
Short name T463
Test name
Test status
Simulation time 185526100 ps
CPU time 5.29 seconds
Started Jul 12 06:40:29 PM PDT 24
Finished Jul 12 06:40:38 PM PDT 24
Peak memory 214200 kb
Host smart-831ef12b-39e6-4b15-944a-14c27edafbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491383345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3491383345
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2925739329
Short name T793
Test name
Test status
Simulation time 397111027 ps
CPU time 5.16 seconds
Started Jul 12 06:40:27 PM PDT 24
Finished Jul 12 06:40:36 PM PDT 24
Peak memory 208064 kb
Host smart-80353569-cc17-40a5-ae70-9cad77537f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925739329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2925739329
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1203673713
Short name T600
Test name
Test status
Simulation time 141067659 ps
CPU time 3.66 seconds
Started Jul 12 06:40:27 PM PDT 24
Finished Jul 12 06:40:34 PM PDT 24
Peak memory 214312 kb
Host smart-3c833131-1636-4266-aa66-2081714cf1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203673713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1203673713
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.536764704
Short name T720
Test name
Test status
Simulation time 298939789 ps
CPU time 3.6 seconds
Started Jul 12 06:40:23 PM PDT 24
Finished Jul 12 06:40:30 PM PDT 24
Peak memory 222480 kb
Host smart-48e434b1-d5d1-4d25-a2c3-1ac641f26592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536764704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.536764704
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.950264910
Short name T702
Test name
Test status
Simulation time 64566530 ps
CPU time 2.59 seconds
Started Jul 12 06:40:22 PM PDT 24
Finished Jul 12 06:40:29 PM PDT 24
Peak memory 207428 kb
Host smart-ca6f2b9c-56b9-45d7-bb36-0591268276de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950264910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.950264910
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.208275962
Short name T838
Test name
Test status
Simulation time 111489289 ps
CPU time 2.53 seconds
Started Jul 12 06:40:26 PM PDT 24
Finished Jul 12 06:40:31 PM PDT 24
Peak memory 208788 kb
Host smart-fcf9a846-8c46-4466-827d-9c95ddc16a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208275962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.208275962
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1397755409
Short name T704
Test name
Test status
Simulation time 69735599 ps
CPU time 2.43 seconds
Started Jul 12 06:40:29 PM PDT 24
Finished Jul 12 06:40:35 PM PDT 24
Peak memory 206732 kb
Host smart-e77f35bc-22d9-403e-b566-b2c43b94dc60
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397755409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1397755409
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2266127094
Short name T521
Test name
Test status
Simulation time 1979539315 ps
CPU time 34.79 seconds
Started Jul 12 06:40:33 PM PDT 24
Finished Jul 12 06:41:11 PM PDT 24
Peak memory 209060 kb
Host smart-3605343f-2061-412c-9737-b354b628206c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266127094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2266127094
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3028051786
Short name T415
Test name
Test status
Simulation time 111276755 ps
CPU time 2.83 seconds
Started Jul 12 06:40:31 PM PDT 24
Finished Jul 12 06:40:38 PM PDT 24
Peak memory 207044 kb
Host smart-a9d3638d-f621-4135-9454-5077b85ad71b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028051786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3028051786
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.690694156
Short name T675
Test name
Test status
Simulation time 129731109 ps
CPU time 3.58 seconds
Started Jul 12 06:40:26 PM PDT 24
Finished Jul 12 06:40:32 PM PDT 24
Peak memory 209356 kb
Host smart-09aa36b7-2149-4465-9417-b20d17c59771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690694156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.690694156
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1912125242
Short name T554
Test name
Test status
Simulation time 41776983 ps
CPU time 2.25 seconds
Started Jul 12 06:40:24 PM PDT 24
Finished Jul 12 06:40:30 PM PDT 24
Peak memory 208452 kb
Host smart-cb434a65-81a0-43b4-bfb7-52e975acb7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912125242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1912125242
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3857726977
Short name T421
Test name
Test status
Simulation time 2391279543 ps
CPU time 18.27 seconds
Started Jul 12 06:40:23 PM PDT 24
Finished Jul 12 06:40:45 PM PDT 24
Peak memory 216640 kb
Host smart-81e307e0-aadf-41d0-8b6f-a82957fd7220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857726977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3857726977
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1326056566
Short name T344
Test name
Test status
Simulation time 134591621 ps
CPU time 5 seconds
Started Jul 12 06:41:23 PM PDT 24
Finished Jul 12 06:41:32 PM PDT 24
Peak memory 214320 kb
Host smart-4872a203-59a8-4ae5-8e6b-182942238bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326056566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1326056566
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1660864808
Short name T233
Test name
Test status
Simulation time 408771360 ps
CPU time 2.54 seconds
Started Jul 12 06:40:22 PM PDT 24
Finished Jul 12 06:40:29 PM PDT 24
Peak memory 209788 kb
Host smart-acf983b2-f61b-43c4-a52b-3c9d4fc3154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660864808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1660864808
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1466816503
Short name T886
Test name
Test status
Simulation time 14333528 ps
CPU time 0.88 seconds
Started Jul 12 06:40:33 PM PDT 24
Finished Jul 12 06:40:37 PM PDT 24
Peak memory 206112 kb
Host smart-063c28ca-0faa-4507-ab66-d52e9f114958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466816503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1466816503
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3834159974
Short name T567
Test name
Test status
Simulation time 488699043 ps
CPU time 5.93 seconds
Started Jul 12 06:40:31 PM PDT 24
Finished Jul 12 06:40:41 PM PDT 24
Peak memory 209048 kb
Host smart-8d85d625-a68a-4cf2-aaa5-9555fcf3d76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834159974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3834159974
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1451786294
Short name T260
Test name
Test status
Simulation time 29680447 ps
CPU time 1.54 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:33 PM PDT 24
Peak memory 207396 kb
Host smart-8f04ea2b-8014-4f9a-af8f-e6e2395d6938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451786294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1451786294
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2016906484
Short name T490
Test name
Test status
Simulation time 300463380 ps
CPU time 3.6 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:36 PM PDT 24
Peak memory 214372 kb
Host smart-1755b182-79e0-43f5-b28d-056b198da1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016906484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2016906484
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.266401109
Short name T240
Test name
Test status
Simulation time 420518078 ps
CPU time 3.38 seconds
Started Jul 12 06:40:31 PM PDT 24
Finished Jul 12 06:40:38 PM PDT 24
Peak memory 218000 kb
Host smart-b7541bce-605e-4e05-b493-098c9bdac922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266401109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.266401109
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3232504913
Short name T596
Test name
Test status
Simulation time 381776573 ps
CPU time 4 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:36 PM PDT 24
Peak memory 209748 kb
Host smart-c18da68f-b09f-428a-8931-5fe75eb6d5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232504913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3232504913
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2725438814
Short name T504
Test name
Test status
Simulation time 138151919 ps
CPU time 2.62 seconds
Started Jul 12 06:40:26 PM PDT 24
Finished Jul 12 06:40:31 PM PDT 24
Peak memory 206876 kb
Host smart-cf2bdd00-1cf5-42f3-bec8-6c79a73cd726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725438814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2725438814
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.718313213
Short name T518
Test name
Test status
Simulation time 49964661 ps
CPU time 2.66 seconds
Started Jul 12 06:40:24 PM PDT 24
Finished Jul 12 06:40:30 PM PDT 24
Peak memory 207000 kb
Host smart-816b9345-d2a9-4ea6-ac00-dbf647120ee0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718313213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.718313213
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2547622052
Short name T527
Test name
Test status
Simulation time 52447049 ps
CPU time 2.88 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:34 PM PDT 24
Peak memory 208780 kb
Host smart-e8d55fa3-fa43-413f-800a-40fb0e0ed810
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547622052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2547622052
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1690349140
Short name T550
Test name
Test status
Simulation time 180373492 ps
CPU time 2.28 seconds
Started Jul 12 06:40:29 PM PDT 24
Finished Jul 12 06:40:35 PM PDT 24
Peak memory 208612 kb
Host smart-998421b8-715a-4d86-9890-1f53864b5209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690349140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1690349140
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.115779143
Short name T195
Test name
Test status
Simulation time 232925929 ps
CPU time 2.8 seconds
Started Jul 12 06:40:34 PM PDT 24
Finished Jul 12 06:40:40 PM PDT 24
Peak memory 206864 kb
Host smart-cfc98bc6-2037-4abb-a141-93fb7cbadcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115779143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.115779143
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1143599167
Short name T46
Test name
Test status
Simulation time 463656229 ps
CPU time 17.2 seconds
Started Jul 12 06:40:30 PM PDT 24
Finished Jul 12 06:40:51 PM PDT 24
Peak memory 216632 kb
Host smart-caedd720-35e4-4d05-ba8b-47e68b7b58ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143599167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1143599167
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.4161669518
Short name T865
Test name
Test status
Simulation time 157793613 ps
CPU time 9.54 seconds
Started Jul 12 06:40:29 PM PDT 24
Finished Jul 12 06:40:43 PM PDT 24
Peak memory 222628 kb
Host smart-00042eac-f887-42ec-b0be-c4d2e6ca6921
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161669518 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.4161669518
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.870380604
Short name T213
Test name
Test status
Simulation time 800629821 ps
CPU time 12.16 seconds
Started Jul 12 06:40:29 PM PDT 24
Finished Jul 12 06:40:45 PM PDT 24
Peak memory 209116 kb
Host smart-531e4fec-dad6-47af-b4d0-d969d6958993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870380604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.870380604
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3162363144
Short name T166
Test name
Test status
Simulation time 2163023464 ps
CPU time 19.47 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:52 PM PDT 24
Peak memory 211028 kb
Host smart-20715d63-b9c7-4a97-adfa-7ace3f6d69f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162363144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3162363144
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2773493254
Short name T446
Test name
Test status
Simulation time 41195876 ps
CPU time 0.85 seconds
Started Jul 12 06:40:30 PM PDT 24
Finished Jul 12 06:40:34 PM PDT 24
Peak memory 205948 kb
Host smart-fc69836f-3470-4e01-9b79-66eae9450ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773493254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2773493254
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3870750534
Short name T644
Test name
Test status
Simulation time 265564526 ps
CPU time 5.61 seconds
Started Jul 12 06:40:30 PM PDT 24
Finished Jul 12 06:40:40 PM PDT 24
Peak memory 214712 kb
Host smart-b72be020-9147-4f73-8b19-2b695e4bee77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870750534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3870750534
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2597333394
Short name T73
Test name
Test status
Simulation time 183490998 ps
CPU time 3.97 seconds
Started Jul 12 06:40:27 PM PDT 24
Finished Jul 12 06:40:35 PM PDT 24
Peak memory 208620 kb
Host smart-e279e3b9-2ac7-47c0-9dda-27d31a4bb7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597333394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2597333394
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1631620179
Short name T485
Test name
Test status
Simulation time 138565969 ps
CPU time 3.74 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:36 PM PDT 24
Peak memory 214336 kb
Host smart-809569fd-e70e-4111-bd62-a77c2a6987fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631620179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1631620179
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1520838995
Short name T923
Test name
Test status
Simulation time 52614589 ps
CPU time 2.7 seconds
Started Jul 12 06:40:30 PM PDT 24
Finished Jul 12 06:40:37 PM PDT 24
Peak memory 214268 kb
Host smart-889b1f0c-bb90-4ce0-a45c-e8230e475672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520838995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1520838995
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.422681786
Short name T483
Test name
Test status
Simulation time 154194573 ps
CPU time 2.92 seconds
Started Jul 12 06:40:29 PM PDT 24
Finished Jul 12 06:40:36 PM PDT 24
Peak memory 219596 kb
Host smart-b74e2b4b-44a5-4cc5-8855-41e702198107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422681786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.422681786
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3407621491
Short name T618
Test name
Test status
Simulation time 180133096 ps
CPU time 5.74 seconds
Started Jul 12 06:40:34 PM PDT 24
Finished Jul 12 06:40:43 PM PDT 24
Peak memory 207596 kb
Host smart-b40af4fa-563b-4793-91e0-22299495f3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407621491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3407621491
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2702817965
Short name T846
Test name
Test status
Simulation time 30545389 ps
CPU time 2.2 seconds
Started Jul 12 06:40:32 PM PDT 24
Finished Jul 12 06:40:37 PM PDT 24
Peak memory 206672 kb
Host smart-55d75045-670b-469f-8744-fb926e54efc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702817965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2702817965
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2900400529
Short name T718
Test name
Test status
Simulation time 726781006 ps
CPU time 3.33 seconds
Started Jul 12 06:40:26 PM PDT 24
Finished Jul 12 06:40:32 PM PDT 24
Peak memory 206836 kb
Host smart-c1cca06a-500c-45af-b044-818b4c3b85ee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900400529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2900400529
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2062453697
Short name T676
Test name
Test status
Simulation time 46722502 ps
CPU time 2.57 seconds
Started Jul 12 06:40:32 PM PDT 24
Finished Jul 12 06:40:38 PM PDT 24
Peak memory 207028 kb
Host smart-2645ca55-7ccf-466c-ac70-945c8008177c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062453697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2062453697
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3782860027
Short name T257
Test name
Test status
Simulation time 312441560 ps
CPU time 4.76 seconds
Started Jul 12 06:40:32 PM PDT 24
Finished Jul 12 06:40:40 PM PDT 24
Peak memory 207924 kb
Host smart-7ff295be-3826-4153-9ec6-fa183b807357
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782860027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3782860027
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2426058048
Short name T661
Test name
Test status
Simulation time 876532515 ps
CPU time 9.66 seconds
Started Jul 12 06:40:29 PM PDT 24
Finished Jul 12 06:40:43 PM PDT 24
Peak memory 210556 kb
Host smart-7cc698ac-5eb6-4456-b3c7-d1e49f31f32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426058048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2426058048
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2946301961
Short name T679
Test name
Test status
Simulation time 44516877 ps
CPU time 2.22 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:34 PM PDT 24
Peak memory 206968 kb
Host smart-3722ad74-4aae-4ed7-9c3f-5af7bbf6b1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946301961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2946301961
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2843942331
Short name T177
Test name
Test status
Simulation time 1196885301 ps
CPU time 11.25 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:43 PM PDT 24
Peak memory 222592 kb
Host smart-80183e66-b556-42be-9ec0-565915995182
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843942331 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2843942331
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3621858128
Short name T130
Test name
Test status
Simulation time 575249137 ps
CPU time 10.08 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:42 PM PDT 24
Peak memory 208708 kb
Host smart-29618cad-cf9e-405a-bafe-100876f3bd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621858128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3621858128
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2230539423
Short name T791
Test name
Test status
Simulation time 84036884 ps
CPU time 2.24 seconds
Started Jul 12 06:40:27 PM PDT 24
Finished Jul 12 06:40:33 PM PDT 24
Peak memory 210788 kb
Host smart-f16b30cc-d52e-4f36-aad2-63221f33aabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230539423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2230539423
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.448214178
Short name T507
Test name
Test status
Simulation time 102057919 ps
CPU time 0.95 seconds
Started Jul 12 06:40:33 PM PDT 24
Finished Jul 12 06:40:37 PM PDT 24
Peak memory 206144 kb
Host smart-100bc73f-ae16-40fc-a91a-df865d2815c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448214178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.448214178
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2711561479
Short name T199
Test name
Test status
Simulation time 78043421 ps
CPU time 2.72 seconds
Started Jul 12 06:40:41 PM PDT 24
Finished Jul 12 06:40:46 PM PDT 24
Peak memory 222968 kb
Host smart-bea3b185-5798-4663-aac0-954f2868e5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711561479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2711561479
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2792979770
Short name T74
Test name
Test status
Simulation time 55971355 ps
CPU time 2.17 seconds
Started Jul 12 06:40:39 PM PDT 24
Finished Jul 12 06:40:42 PM PDT 24
Peak memory 208436 kb
Host smart-04a22151-e552-4acb-a0ba-e421fa45e043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792979770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2792979770
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1081031942
Short name T360
Test name
Test status
Simulation time 135648509 ps
CPU time 1.98 seconds
Started Jul 12 06:40:33 PM PDT 24
Finished Jul 12 06:40:38 PM PDT 24
Peak memory 214228 kb
Host smart-ec0add37-ae7d-4d9d-aad5-7d766dc6cb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081031942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1081031942
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.566657781
Short name T52
Test name
Test status
Simulation time 140794727 ps
CPU time 4.13 seconds
Started Jul 12 06:40:44 PM PDT 24
Finished Jul 12 06:40:51 PM PDT 24
Peak memory 218224 kb
Host smart-62549904-c823-4b41-9690-2cd1e098813e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566657781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.566657781
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2061398718
Short name T909
Test name
Test status
Simulation time 145281854 ps
CPU time 2.85 seconds
Started Jul 12 06:40:35 PM PDT 24
Finished Jul 12 06:40:40 PM PDT 24
Peak memory 209916 kb
Host smart-a899547e-5cea-4418-93b1-6589819f52af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061398718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2061398718
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.4074887482
Short name T283
Test name
Test status
Simulation time 223539181 ps
CPU time 2.9 seconds
Started Jul 12 06:40:35 PM PDT 24
Finished Jul 12 06:40:40 PM PDT 24
Peak memory 206872 kb
Host smart-4c156159-425b-463d-b5d9-f050f2eb3d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074887482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.4074887482
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1680558241
Short name T574
Test name
Test status
Simulation time 773801630 ps
CPU time 6.56 seconds
Started Jul 12 06:40:40 PM PDT 24
Finished Jul 12 06:40:47 PM PDT 24
Peak memory 208188 kb
Host smart-ef197c8d-6ad7-4166-ae33-5ee5d50f9d1f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680558241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1680558241
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1931951347
Short name T836
Test name
Test status
Simulation time 708490889 ps
CPU time 4.37 seconds
Started Jul 12 06:40:43 PM PDT 24
Finished Jul 12 06:40:50 PM PDT 24
Peak memory 207008 kb
Host smart-d946b7eb-36a5-48e7-8057-3b3b18b12344
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931951347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1931951347
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.4060680693
Short name T458
Test name
Test status
Simulation time 1216474648 ps
CPU time 8.34 seconds
Started Jul 12 06:40:37 PM PDT 24
Finished Jul 12 06:40:47 PM PDT 24
Peak memory 207948 kb
Host smart-99bc2a1e-45dd-4bb7-b365-5e686a9ede15
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060680693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.4060680693
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1229699287
Short name T858
Test name
Test status
Simulation time 153624518 ps
CPU time 3.48 seconds
Started Jul 12 06:40:34 PM PDT 24
Finished Jul 12 06:40:40 PM PDT 24
Peak memory 214388 kb
Host smart-411e5bae-271f-4396-830a-34066947f045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229699287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1229699287
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.761661365
Short name T808
Test name
Test status
Simulation time 4783623187 ps
CPU time 40.37 seconds
Started Jul 12 06:40:40 PM PDT 24
Finished Jul 12 06:41:21 PM PDT 24
Peak memory 209068 kb
Host smart-2e847818-1eaa-4607-8970-898ac8af83e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761661365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.761661365
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3909439240
Short name T559
Test name
Test status
Simulation time 64036039 ps
CPU time 3.56 seconds
Started Jul 12 06:40:37 PM PDT 24
Finished Jul 12 06:40:42 PM PDT 24
Peak memory 209968 kb
Host smart-feb9cacb-71db-468a-aa02-2b8359431e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909439240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3909439240
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.917840112
Short name T781
Test name
Test status
Simulation time 458140560 ps
CPU time 7.13 seconds
Started Jul 12 06:40:39 PM PDT 24
Finished Jul 12 06:40:47 PM PDT 24
Peak memory 210852 kb
Host smart-ee5133c7-bb06-49c4-8a50-04bad57eb2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917840112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.917840112
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1865521429
Short name T456
Test name
Test status
Simulation time 93818337 ps
CPU time 0.8 seconds
Started Jul 12 06:40:47 PM PDT 24
Finished Jul 12 06:40:50 PM PDT 24
Peak memory 205880 kb
Host smart-80dd884d-85cd-48cb-845c-9ee806b0d41d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865521429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1865521429
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2082328010
Short name T689
Test name
Test status
Simulation time 57379917 ps
CPU time 1.73 seconds
Started Jul 12 06:40:41 PM PDT 24
Finished Jul 12 06:40:44 PM PDT 24
Peak memory 214304 kb
Host smart-ff4335aa-e1b8-4316-ae94-d47cda705917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082328010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2082328010
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.142671303
Short name T287
Test name
Test status
Simulation time 29397510 ps
CPU time 2.24 seconds
Started Jul 12 06:40:41 PM PDT 24
Finished Jul 12 06:40:45 PM PDT 24
Peak memory 214284 kb
Host smart-5d8a69e5-8088-461f-9419-a70a5547076b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142671303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.142671303
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2531445987
Short name T345
Test name
Test status
Simulation time 4017782729 ps
CPU time 13.82 seconds
Started Jul 12 06:40:50 PM PDT 24
Finished Jul 12 06:41:04 PM PDT 24
Peak memory 215404 kb
Host smart-990dbcea-0e30-410c-9f59-502503386a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531445987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2531445987
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_random.3672852663
Short name T696
Test name
Test status
Simulation time 514083334 ps
CPU time 7.8 seconds
Started Jul 12 06:40:39 PM PDT 24
Finished Jul 12 06:40:48 PM PDT 24
Peak memory 209628 kb
Host smart-53593990-d756-4a0b-9614-21ab8dd5875d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672852663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3672852663
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1111839403
Short name T310
Test name
Test status
Simulation time 616455713 ps
CPU time 2.72 seconds
Started Jul 12 06:40:46 PM PDT 24
Finished Jul 12 06:40:51 PM PDT 24
Peak memory 208344 kb
Host smart-f09bf2c4-46d1-4eb9-ae00-f3773350f48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111839403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1111839403
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1604571824
Short name T706
Test name
Test status
Simulation time 1985043682 ps
CPU time 10.96 seconds
Started Jul 12 06:40:43 PM PDT 24
Finished Jul 12 06:40:55 PM PDT 24
Peak memory 208808 kb
Host smart-b65cab75-6dc1-4bf2-bfdf-b21216b1aee9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604571824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1604571824
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2786765850
Short name T192
Test name
Test status
Simulation time 52425343 ps
CPU time 2.89 seconds
Started Jul 12 06:40:51 PM PDT 24
Finished Jul 12 06:40:56 PM PDT 24
Peak memory 207024 kb
Host smart-acd03fb8-dc37-4c1d-8997-aaa0c995c2b1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786765850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2786765850
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.642702753
Short name T228
Test name
Test status
Simulation time 96321003 ps
CPU time 4.04 seconds
Started Jul 12 06:40:48 PM PDT 24
Finished Jul 12 06:40:53 PM PDT 24
Peak memory 208708 kb
Host smart-05b6229e-0faf-435a-a13b-0834b330d047
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642702753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.642702753
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.4156374841
Short name T837
Test name
Test status
Simulation time 290651919 ps
CPU time 8.53 seconds
Started Jul 12 06:40:48 PM PDT 24
Finished Jul 12 06:40:58 PM PDT 24
Peak memory 216180 kb
Host smart-f2074c85-3a8f-40dc-bed9-460ec0202e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156374841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.4156374841
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3913167151
Short name T215
Test name
Test status
Simulation time 2814207951 ps
CPU time 23.39 seconds
Started Jul 12 06:40:34 PM PDT 24
Finished Jul 12 06:41:00 PM PDT 24
Peak memory 208416 kb
Host smart-d74e176b-224a-4c94-b265-6f4b83e5adf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913167151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3913167151
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2616782881
Short name T209
Test name
Test status
Simulation time 1315119154 ps
CPU time 18.58 seconds
Started Jul 12 06:40:44 PM PDT 24
Finished Jul 12 06:41:05 PM PDT 24
Peak memory 209844 kb
Host smart-edc19cc8-9ff1-4e9c-bbbc-831f35875b6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616782881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2616782881
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3579739035
Short name T338
Test name
Test status
Simulation time 456049762 ps
CPU time 20.87 seconds
Started Jul 12 06:40:46 PM PDT 24
Finished Jul 12 06:41:08 PM PDT 24
Peak memory 222596 kb
Host smart-48919d09-43a0-44ad-8bb9-e197d0a177ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579739035 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3579739035
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2895024153
Short name T658
Test name
Test status
Simulation time 67913116 ps
CPU time 2.27 seconds
Started Jul 12 06:40:42 PM PDT 24
Finished Jul 12 06:40:46 PM PDT 24
Peak memory 209980 kb
Host smart-a1b7c098-f753-4e75-8606-125a2d2ba89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895024153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2895024153
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1398674009
Short name T834
Test name
Test status
Simulation time 44135806 ps
CPU time 0.76 seconds
Started Jul 12 06:40:43 PM PDT 24
Finished Jul 12 06:40:45 PM PDT 24
Peak memory 205972 kb
Host smart-7c8c3b6f-fb0d-4134-8eed-49a0f4c40fe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398674009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1398674009
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3124017885
Short name T106
Test name
Test status
Simulation time 31392511 ps
CPU time 2.68 seconds
Started Jul 12 06:40:39 PM PDT 24
Finished Jul 12 06:40:42 PM PDT 24
Peak memory 214300 kb
Host smart-a554bb20-cdc2-45c4-b3eb-71578039db6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3124017885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3124017885
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1021356757
Short name T39
Test name
Test status
Simulation time 767447618 ps
CPU time 6.09 seconds
Started Jul 12 06:40:47 PM PDT 24
Finished Jul 12 06:40:55 PM PDT 24
Peak memory 209544 kb
Host smart-fbc7453c-df0b-49ef-b3f3-568d125884de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021356757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1021356757
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.74396989
Short name T673
Test name
Test status
Simulation time 1007057878 ps
CPU time 2.62 seconds
Started Jul 12 06:40:52 PM PDT 24
Finished Jul 12 06:40:58 PM PDT 24
Peak memory 214292 kb
Host smart-f4b6aacd-5db6-48b3-ba87-0b6a9cbe290c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74396989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.74396989
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3012836495
Short name T707
Test name
Test status
Simulation time 53713071 ps
CPU time 2.32 seconds
Started Jul 12 06:40:43 PM PDT 24
Finished Jul 12 06:40:47 PM PDT 24
Peak memory 214240 kb
Host smart-8e98ee66-77c0-4537-8e92-206fc54ea90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012836495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3012836495
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3173927996
Short name T147
Test name
Test status
Simulation time 435221286 ps
CPU time 5.71 seconds
Started Jul 12 06:40:43 PM PDT 24
Finished Jul 12 06:40:51 PM PDT 24
Peak memory 222452 kb
Host smart-4a04ca37-c778-407a-a14d-d20c226dfcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173927996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3173927996
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3569682700
Short name T524
Test name
Test status
Simulation time 256315900 ps
CPU time 9.48 seconds
Started Jul 12 06:40:43 PM PDT 24
Finished Jul 12 06:40:55 PM PDT 24
Peak memory 218344 kb
Host smart-ed7e2f7d-5de8-46ac-be03-454299304962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569682700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3569682700
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3430283851
Short name T732
Test name
Test status
Simulation time 467434594 ps
CPU time 3.97 seconds
Started Jul 12 06:40:40 PM PDT 24
Finished Jul 12 06:40:45 PM PDT 24
Peak memory 207216 kb
Host smart-8f23e6ef-9f44-4d6d-8948-9529288e26dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430283851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3430283851
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3221959043
Short name T624
Test name
Test status
Simulation time 1419620832 ps
CPU time 37.75 seconds
Started Jul 12 06:40:41 PM PDT 24
Finished Jul 12 06:41:20 PM PDT 24
Peak memory 208828 kb
Host smart-e5953bac-8748-4570-8f59-b1bb8b81ae74
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221959043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3221959043
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3223065440
Short name T328
Test name
Test status
Simulation time 280443597 ps
CPU time 3.16 seconds
Started Jul 12 06:41:32 PM PDT 24
Finished Jul 12 06:41:38 PM PDT 24
Peak memory 209204 kb
Host smart-8579f481-62ae-45b3-9e79-f6be6f9f4345
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223065440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3223065440
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2526521311
Short name T668
Test name
Test status
Simulation time 773085616 ps
CPU time 4.95 seconds
Started Jul 12 06:40:41 PM PDT 24
Finished Jul 12 06:40:47 PM PDT 24
Peak memory 208880 kb
Host smart-f2c967a8-5e38-41fa-ab6f-213bcfe5b0e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526521311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2526521311
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.349849805
Short name T764
Test name
Test status
Simulation time 248141569 ps
CPU time 3.08 seconds
Started Jul 12 06:40:43 PM PDT 24
Finished Jul 12 06:40:48 PM PDT 24
Peak memory 218304 kb
Host smart-4b08da34-c3f5-4826-8108-49e8d7b3bf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349849805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.349849805
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3211008588
Short name T796
Test name
Test status
Simulation time 94349561 ps
CPU time 2.98 seconds
Started Jul 12 06:40:47 PM PDT 24
Finished Jul 12 06:40:52 PM PDT 24
Peak memory 208460 kb
Host smart-90c8a14f-39cd-4a15-a6b0-3852d70ef8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211008588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3211008588
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3247055928
Short name T333
Test name
Test status
Simulation time 4410623921 ps
CPU time 47.21 seconds
Started Jul 12 06:40:48 PM PDT 24
Finished Jul 12 06:41:37 PM PDT 24
Peak memory 222540 kb
Host smart-c786343a-e501-4e7a-8d01-644a7866789c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247055928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3247055928
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2946843984
Short name T445
Test name
Test status
Simulation time 367177684 ps
CPU time 3.59 seconds
Started Jul 12 06:40:48 PM PDT 24
Finished Jul 12 06:40:53 PM PDT 24
Peak memory 208100 kb
Host smart-1e8023e0-da18-4702-8ff5-49b172f46a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946843984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2946843984
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1619543411
Short name T165
Test name
Test status
Simulation time 2782175174 ps
CPU time 4.73 seconds
Started Jul 12 06:40:43 PM PDT 24
Finished Jul 12 06:40:50 PM PDT 24
Peak memory 210016 kb
Host smart-719fed15-567b-479b-aee6-0c6e14ce4fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619543411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1619543411
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.913190205
Short name T570
Test name
Test status
Simulation time 19145488 ps
CPU time 0.78 seconds
Started Jul 12 06:40:53 PM PDT 24
Finished Jul 12 06:40:57 PM PDT 24
Peak memory 206012 kb
Host smart-7a1a7c80-fa5c-4db1-9d4c-28a5c9967944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913190205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.913190205
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.933367857
Short name T721
Test name
Test status
Simulation time 266173372 ps
CPU time 4.66 seconds
Started Jul 12 06:40:51 PM PDT 24
Finished Jul 12 06:40:58 PM PDT 24
Peak memory 220900 kb
Host smart-741df3c2-fd85-4ed9-a191-a4fd71a54a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933367857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.933367857
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.260696434
Short name T754
Test name
Test status
Simulation time 186618049 ps
CPU time 2.4 seconds
Started Jul 12 06:40:51 PM PDT 24
Finished Jul 12 06:40:57 PM PDT 24
Peak memory 218400 kb
Host smart-4d93cef6-216d-4645-9b6a-bd6f7f5b086b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260696434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.260696434
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1138954401
Short name T80
Test name
Test status
Simulation time 277159018 ps
CPU time 6.8 seconds
Started Jul 12 06:40:46 PM PDT 24
Finished Jul 12 06:40:55 PM PDT 24
Peak memory 219868 kb
Host smart-cff5a06f-f2c3-43ab-bc75-68925c229098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138954401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1138954401
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1123161738
Short name T606
Test name
Test status
Simulation time 165443081 ps
CPU time 2.03 seconds
Started Jul 12 06:40:54 PM PDT 24
Finished Jul 12 06:40:59 PM PDT 24
Peak memory 214240 kb
Host smart-d3aaac72-33bd-4483-82e3-eefd746dfef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123161738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1123161738
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2813970619
Short name T616
Test name
Test status
Simulation time 112867543 ps
CPU time 3.66 seconds
Started Jul 12 06:40:52 PM PDT 24
Finished Jul 12 06:40:59 PM PDT 24
Peak memory 214332 kb
Host smart-b4a96e96-d0b5-4625-a070-1fd28d669faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813970619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2813970619
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3267190908
Short name T275
Test name
Test status
Simulation time 819559115 ps
CPU time 27.64 seconds
Started Jul 12 06:40:45 PM PDT 24
Finished Jul 12 06:41:15 PM PDT 24
Peak memory 210448 kb
Host smart-e15bab21-e4db-4ef4-8ede-676dcded2b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267190908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3267190908
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2147524736
Short name T905
Test name
Test status
Simulation time 154793975 ps
CPU time 2.74 seconds
Started Jul 12 06:40:48 PM PDT 24
Finished Jul 12 06:40:52 PM PDT 24
Peak memory 206896 kb
Host smart-ebee6b19-22f8-4220-a0e3-88577e45814d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147524736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2147524736
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3423627622
Short name T602
Test name
Test status
Simulation time 120565736 ps
CPU time 3.53 seconds
Started Jul 12 06:40:50 PM PDT 24
Finished Jul 12 06:40:56 PM PDT 24
Peak memory 208756 kb
Host smart-18d36dc5-b02f-419e-ae68-d7fe2e4f8578
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423627622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3423627622
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3372892083
Short name T768
Test name
Test status
Simulation time 840090371 ps
CPU time 3.86 seconds
Started Jul 12 06:40:50 PM PDT 24
Finished Jul 12 06:40:54 PM PDT 24
Peak memory 206820 kb
Host smart-f9623914-4af7-43c5-92cc-05cadd22a5bc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372892083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3372892083
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2286122819
Short name T299
Test name
Test status
Simulation time 242523296 ps
CPU time 3.37 seconds
Started Jul 12 06:40:46 PM PDT 24
Finished Jul 12 06:40:51 PM PDT 24
Peak memory 208904 kb
Host smart-f2fcb3e0-648e-4571-a626-c356f41c8dbe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286122819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2286122819
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.531649675
Short name T295
Test name
Test status
Simulation time 25667090 ps
CPU time 2.14 seconds
Started Jul 12 06:40:45 PM PDT 24
Finished Jul 12 06:40:49 PM PDT 24
Peak memory 209860 kb
Host smart-18558464-8f09-481c-a046-886ce9bbd7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531649675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.531649675
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2254546635
Short name T110
Test name
Test status
Simulation time 143188484 ps
CPU time 2.57 seconds
Started Jul 12 06:40:42 PM PDT 24
Finished Jul 12 06:40:47 PM PDT 24
Peak memory 206808 kb
Host smart-8a0911c7-a0d2-4470-a9a2-3388aa943a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254546635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2254546635
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2023982670
Short name T874
Test name
Test status
Simulation time 329900345 ps
CPU time 12.93 seconds
Started Jul 12 06:40:45 PM PDT 24
Finished Jul 12 06:41:00 PM PDT 24
Peak memory 215384 kb
Host smart-25a7a9ec-1c4a-499e-9308-54509fb01050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023982670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2023982670
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1796590923
Short name T363
Test name
Test status
Simulation time 1069425135 ps
CPU time 18.76 seconds
Started Jul 12 06:40:49 PM PDT 24
Finished Jul 12 06:41:15 PM PDT 24
Peak memory 222884 kb
Host smart-3bfbf9b0-2835-40e9-9440-f61e199cae38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796590923 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1796590923
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1964078722
Short name T597
Test name
Test status
Simulation time 1206869340 ps
CPU time 41.3 seconds
Started Jul 12 06:40:44 PM PDT 24
Finished Jul 12 06:41:27 PM PDT 24
Peak memory 219120 kb
Host smart-b8de94d6-faec-4d23-b355-67875a8faa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964078722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1964078722
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3555030751
Short name T920
Test name
Test status
Simulation time 94467244 ps
CPU time 0.81 seconds
Started Jul 12 06:39:55 PM PDT 24
Finished Jul 12 06:39:57 PM PDT 24
Peak memory 205912 kb
Host smart-3494d9ea-dfb4-401a-9b5c-314c928e7b88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555030751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3555030751
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2998865255
Short name T883
Test name
Test status
Simulation time 56267317 ps
CPU time 1.72 seconds
Started Jul 12 06:39:56 PM PDT 24
Finished Jul 12 06:39:59 PM PDT 24
Peak memory 208360 kb
Host smart-1111a255-ca45-477f-b7ab-53a9ab8251bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998865255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2998865255
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2214077104
Short name T482
Test name
Test status
Simulation time 298374232 ps
CPU time 3.14 seconds
Started Jul 12 06:39:56 PM PDT 24
Finished Jul 12 06:40:01 PM PDT 24
Peak memory 214324 kb
Host smart-095a1967-1d35-4fe1-b6a4-3be92de37be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214077104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2214077104
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1905335001
Short name T47
Test name
Test status
Simulation time 243651077 ps
CPU time 2.26 seconds
Started Jul 12 06:40:11 PM PDT 24
Finished Jul 12 06:40:16 PM PDT 24
Peak memory 214360 kb
Host smart-7ac84a8d-91ae-425f-adf2-e507f154a89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905335001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1905335001
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_random.2695427011
Short name T519
Test name
Test status
Simulation time 491128823 ps
CPU time 5.14 seconds
Started Jul 12 06:39:56 PM PDT 24
Finished Jul 12 06:40:03 PM PDT 24
Peak memory 214328 kb
Host smart-225cac45-5af9-4643-9110-b8f1933e44eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695427011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2695427011
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3330621878
Short name T12
Test name
Test status
Simulation time 1807178104 ps
CPU time 5.85 seconds
Started Jul 12 06:39:58 PM PDT 24
Finished Jul 12 06:40:05 PM PDT 24
Peak memory 230164 kb
Host smart-946b1a97-d9c0-4e23-aee0-f38cfb5f4139
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330621878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3330621878
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3718556352
Short name T440
Test name
Test status
Simulation time 169288639 ps
CPU time 2.5 seconds
Started Jul 12 06:39:58 PM PDT 24
Finished Jul 12 06:40:02 PM PDT 24
Peak memory 206756 kb
Host smart-07b1ecd1-cb2a-422b-9202-5f23f1bbcbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718556352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3718556352
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2595601549
Short name T851
Test name
Test status
Simulation time 506399860 ps
CPU time 5.68 seconds
Started Jul 12 06:46:21 PM PDT 24
Finished Jul 12 06:46:29 PM PDT 24
Peak memory 208620 kb
Host smart-f7add85c-0273-43f2-ba46-69293b8ac6b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595601549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2595601549
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.224667527
Short name T763
Test name
Test status
Simulation time 373120600 ps
CPU time 3.49 seconds
Started Jul 12 06:39:59 PM PDT 24
Finished Jul 12 06:40:04 PM PDT 24
Peak memory 206840 kb
Host smart-9e8c8069-24e0-473f-b6de-c34ff99a2721
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224667527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.224667527
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3396563559
Short name T651
Test name
Test status
Simulation time 5398872798 ps
CPU time 18.03 seconds
Started Jul 12 06:39:55 PM PDT 24
Finished Jul 12 06:40:14 PM PDT 24
Peak memory 208180 kb
Host smart-75b21146-4c57-48af-ad0b-b0427533f23d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396563559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3396563559
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.807592004
Short name T216
Test name
Test status
Simulation time 48058315 ps
CPU time 2.08 seconds
Started Jul 12 06:39:53 PM PDT 24
Finished Jul 12 06:39:56 PM PDT 24
Peak memory 208328 kb
Host smart-3a91693d-949f-4eef-8632-ad664311b347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807592004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.807592004
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.4235991429
Short name T899
Test name
Test status
Simulation time 1852583868 ps
CPU time 4.99 seconds
Started Jul 12 06:39:54 PM PDT 24
Finished Jul 12 06:40:00 PM PDT 24
Peak memory 208264 kb
Host smart-111ef5f6-0e3a-407f-a652-ed04b2c5f212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235991429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.4235991429
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2675188787
Short name T236
Test name
Test status
Simulation time 41537039678 ps
CPU time 148.34 seconds
Started Jul 12 06:39:59 PM PDT 24
Finished Jul 12 06:42:30 PM PDT 24
Peak memory 222524 kb
Host smart-e0ccae0f-0c8d-4d15-8a50-687134f12b17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675188787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2675188787
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.678383018
Short name T111
Test name
Test status
Simulation time 563590132 ps
CPU time 10.21 seconds
Started Jul 12 06:39:55 PM PDT 24
Finished Jul 12 06:40:06 PM PDT 24
Peak memory 222616 kb
Host smart-b758595b-f2e0-4f43-bf11-c24f0175a738
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678383018 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.678383018
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1374559817
Short name T274
Test name
Test status
Simulation time 596202357 ps
CPU time 6.48 seconds
Started Jul 12 06:39:54 PM PDT 24
Finished Jul 12 06:40:01 PM PDT 24
Peak memory 218412 kb
Host smart-8d73c07c-7e06-4c06-8590-6b997cb71f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374559817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1374559817
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2098923160
Short name T530
Test name
Test status
Simulation time 115200681 ps
CPU time 0.83 seconds
Started Jul 12 06:40:51 PM PDT 24
Finished Jul 12 06:40:55 PM PDT 24
Peak memory 205988 kb
Host smart-d25c7ad9-abe3-4818-a011-f02bb9e54402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098923160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2098923160
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3303694660
Short name T337
Test name
Test status
Simulation time 248211329 ps
CPU time 7.12 seconds
Started Jul 12 06:40:53 PM PDT 24
Finished Jul 12 06:41:04 PM PDT 24
Peak memory 215716 kb
Host smart-66fed8a0-9a39-4a47-8a0d-b0d0bd82505d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3303694660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3303694660
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1460665893
Short name T786
Test name
Test status
Simulation time 88741551 ps
CPU time 4.04 seconds
Started Jul 12 06:40:48 PM PDT 24
Finished Jul 12 06:40:54 PM PDT 24
Peak memory 210180 kb
Host smart-a0a7386e-9904-4ffc-aef2-d41862161dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460665893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1460665893
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.904856523
Short name T71
Test name
Test status
Simulation time 138556135 ps
CPU time 2.22 seconds
Started Jul 12 06:40:46 PM PDT 24
Finished Jul 12 06:40:51 PM PDT 24
Peak memory 207656 kb
Host smart-6c6f202d-9594-489c-9dfe-8b76914f1d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904856523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.904856523
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1364847695
Short name T88
Test name
Test status
Simulation time 613624213 ps
CPU time 17.77 seconds
Started Jul 12 06:40:47 PM PDT 24
Finished Jul 12 06:41:07 PM PDT 24
Peak memory 214404 kb
Host smart-efb30d23-950d-43a1-9b30-c2f7f44bd3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364847695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1364847695
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.1195234144
Short name T303
Test name
Test status
Simulation time 484040960 ps
CPU time 3.36 seconds
Started Jul 12 06:40:51 PM PDT 24
Finished Jul 12 06:40:58 PM PDT 24
Peak memory 214284 kb
Host smart-c95df45b-9bc3-46b4-9df9-5d677c8b6d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195234144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1195234144
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.764109274
Short name T58
Test name
Test status
Simulation time 218738036 ps
CPU time 4.31 seconds
Started Jul 12 06:40:46 PM PDT 24
Finished Jul 12 06:40:52 PM PDT 24
Peak memory 218776 kb
Host smart-5b598e31-6db6-4c80-9f5f-31eb3924aa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764109274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.764109274
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2575504045
Short name T623
Test name
Test status
Simulation time 3422799075 ps
CPU time 43.71 seconds
Started Jul 12 06:40:53 PM PDT 24
Finished Jul 12 06:41:41 PM PDT 24
Peak memory 209256 kb
Host smart-fdedbb91-9f7a-4171-b173-193e90ebab4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575504045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2575504045
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1335831905
Short name T717
Test name
Test status
Simulation time 635833194 ps
CPU time 13.2 seconds
Started Jul 12 06:40:47 PM PDT 24
Finished Jul 12 06:41:02 PM PDT 24
Peak memory 208660 kb
Host smart-cc497222-fab1-47f0-800c-3a80c7591e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335831905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1335831905
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1802569892
Short name T457
Test name
Test status
Simulation time 827354995 ps
CPU time 8.02 seconds
Started Jul 12 06:40:49 PM PDT 24
Finished Jul 12 06:40:58 PM PDT 24
Peak memory 208360 kb
Host smart-7a9931e8-304f-4337-af26-aab99d506997
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802569892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1802569892
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.648860846
Short name T541
Test name
Test status
Simulation time 60536230 ps
CPU time 3.02 seconds
Started Jul 12 06:40:51 PM PDT 24
Finished Jul 12 06:40:57 PM PDT 24
Peak memory 207980 kb
Host smart-6a6a16c2-b849-41bf-84a2-c806509a59f0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648860846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.648860846
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.139110787
Short name T804
Test name
Test status
Simulation time 294522990 ps
CPU time 3.25 seconds
Started Jul 12 06:40:53 PM PDT 24
Finished Jul 12 06:41:00 PM PDT 24
Peak memory 207060 kb
Host smart-607a0cdc-81c0-4a2e-8084-7da375d6c58b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139110787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.139110787
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3446272466
Short name T799
Test name
Test status
Simulation time 112635187 ps
CPU time 3.21 seconds
Started Jul 12 06:40:53 PM PDT 24
Finished Jul 12 06:40:59 PM PDT 24
Peak memory 209228 kb
Host smart-ab5020dc-f635-4bf3-a940-9a6c7ccf1238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446272466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3446272466
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.706236556
Short name T462
Test name
Test status
Simulation time 54414655 ps
CPU time 2.07 seconds
Started Jul 12 06:40:49 PM PDT 24
Finished Jul 12 06:40:52 PM PDT 24
Peak memory 207076 kb
Host smart-6a257ae0-bcd3-4361-9b27-ec104b16d514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706236556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.706236556
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2993822314
Short name T902
Test name
Test status
Simulation time 182181015 ps
CPU time 5.59 seconds
Started Jul 12 06:40:52 PM PDT 24
Finished Jul 12 06:41:00 PM PDT 24
Peak memory 218348 kb
Host smart-fe8c2631-ca02-4839-8cf7-71c29fd15f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993822314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2993822314
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3424467066
Short name T400
Test name
Test status
Simulation time 461552296 ps
CPU time 5.18 seconds
Started Jul 12 06:40:50 PM PDT 24
Finished Jul 12 06:40:58 PM PDT 24
Peak memory 210880 kb
Host smart-e8a49a19-2d22-4305-b42a-bf3c81589c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424467066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3424467066
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.792161649
Short name T200
Test name
Test status
Simulation time 10761824 ps
CPU time 0.78 seconds
Started Jul 12 06:40:53 PM PDT 24
Finished Jul 12 06:40:57 PM PDT 24
Peak memory 206008 kb
Host smart-f05234ed-4774-4924-b631-947217d1b316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792161649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.792161649
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3668281312
Short name T390
Test name
Test status
Simulation time 43488763 ps
CPU time 3.51 seconds
Started Jul 12 06:40:51 PM PDT 24
Finished Jul 12 06:40:58 PM PDT 24
Peak memory 222444 kb
Host smart-b2dde329-4493-4c05-a57f-b81fdc8c2678
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3668281312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3668281312
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1820512658
Short name T713
Test name
Test status
Simulation time 483966172 ps
CPU time 2.76 seconds
Started Jul 12 06:40:52 PM PDT 24
Finished Jul 12 06:40:58 PM PDT 24
Peak memory 209356 kb
Host smart-4f6f107a-3bdd-427b-862f-fcac69abd8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820512658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1820512658
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.396164160
Short name T604
Test name
Test status
Simulation time 478035658 ps
CPU time 5.06 seconds
Started Jul 12 06:40:52 PM PDT 24
Finished Jul 12 06:41:01 PM PDT 24
Peak memory 210024 kb
Host smart-75dc8a5d-366b-41cb-9d56-6815a6e407b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396164160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.396164160
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.479123321
Short name T577
Test name
Test status
Simulation time 219890664 ps
CPU time 2.97 seconds
Started Jul 12 06:40:50 PM PDT 24
Finished Jul 12 06:40:56 PM PDT 24
Peak memory 219796 kb
Host smart-82cca584-eb50-4327-bf89-a1eb35e9cc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479123321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.479123321
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3560583069
Short name T335
Test name
Test status
Simulation time 129058234 ps
CPU time 4.34 seconds
Started Jul 12 06:40:51 PM PDT 24
Finished Jul 12 06:40:57 PM PDT 24
Peak memory 208292 kb
Host smart-3b698b75-eaef-44d3-92d9-15b506d9b99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560583069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3560583069
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.963516732
Short name T563
Test name
Test status
Simulation time 75100556 ps
CPU time 3.42 seconds
Started Jul 12 06:40:51 PM PDT 24
Finished Jul 12 06:40:58 PM PDT 24
Peak memory 208660 kb
Host smart-a30bb37b-32cb-4cbf-89aa-55e43bc922af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963516732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.963516732
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1251916196
Short name T866
Test name
Test status
Simulation time 198068033 ps
CPU time 2.82 seconds
Started Jul 12 06:40:58 PM PDT 24
Finished Jul 12 06:41:02 PM PDT 24
Peak memory 206916 kb
Host smart-8f7030c8-53f9-4567-a867-bc4384c9497d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251916196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1251916196
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1791757906
Short name T442
Test name
Test status
Simulation time 69281411 ps
CPU time 1.74 seconds
Started Jul 12 06:40:53 PM PDT 24
Finished Jul 12 06:40:58 PM PDT 24
Peak memory 206860 kb
Host smart-23cf6ef5-4378-41a4-b9c8-b29562ca1a51
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791757906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1791757906
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.423424970
Short name T709
Test name
Test status
Simulation time 224138129 ps
CPU time 2.75 seconds
Started Jul 12 06:40:51 PM PDT 24
Finished Jul 12 06:40:57 PM PDT 24
Peak memory 206884 kb
Host smart-74d1b0f3-8e05-472f-9fca-fd5380b1f7fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423424970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.423424970
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.4269102196
Short name T330
Test name
Test status
Simulation time 91624851 ps
CPU time 4.17 seconds
Started Jul 12 06:40:53 PM PDT 24
Finished Jul 12 06:41:00 PM PDT 24
Peak memory 209136 kb
Host smart-205b347c-23b9-427d-aa2c-7456e3a5e409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269102196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.4269102196
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2051265899
Short name T476
Test name
Test status
Simulation time 85799704 ps
CPU time 2.85 seconds
Started Jul 12 06:40:48 PM PDT 24
Finished Jul 12 06:40:52 PM PDT 24
Peak memory 206592 kb
Host smart-352cd952-a939-44de-8bc0-b9947c173218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051265899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2051265899
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2705938513
Short name T202
Test name
Test status
Simulation time 5605530979 ps
CPU time 115.9 seconds
Started Jul 12 06:40:52 PM PDT 24
Finished Jul 12 06:42:51 PM PDT 24
Peak memory 222556 kb
Host smart-bb6afbf8-cf33-476c-8e49-d87ee4a5969e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705938513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2705938513
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.4250547324
Short name T587
Test name
Test status
Simulation time 400581608 ps
CPU time 9.31 seconds
Started Jul 12 06:40:58 PM PDT 24
Finished Jul 12 06:41:08 PM PDT 24
Peak memory 219008 kb
Host smart-1ecb2573-7d3c-4962-b53a-eed04c88ca4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250547324 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.4250547324
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1044993795
Short name T640
Test name
Test status
Simulation time 333675338 ps
CPU time 4.23 seconds
Started Jul 12 06:40:51 PM PDT 24
Finished Jul 12 06:40:59 PM PDT 24
Peak memory 209728 kb
Host smart-ee90a855-fd32-4f96-adb8-dc8ae209362a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044993795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1044993795
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2803374139
Short name T191
Test name
Test status
Simulation time 289088154 ps
CPU time 2.91 seconds
Started Jul 12 06:40:54 PM PDT 24
Finished Jul 12 06:41:00 PM PDT 24
Peak memory 210444 kb
Host smart-2d7f173b-4251-444a-be76-7a883a64a0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803374139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2803374139
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.4272100415
Short name T569
Test name
Test status
Simulation time 44866628 ps
CPU time 0.74 seconds
Started Jul 12 06:41:05 PM PDT 24
Finished Jul 12 06:41:07 PM PDT 24
Peak memory 205936 kb
Host smart-9b936d09-33c2-4e51-9c90-fe742a053cce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272100415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.4272100415
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.825469462
Short name T741
Test name
Test status
Simulation time 3925112388 ps
CPU time 14.83 seconds
Started Jul 12 06:40:59 PM PDT 24
Finished Jul 12 06:41:15 PM PDT 24
Peak memory 209320 kb
Host smart-772b14c9-a0db-4d78-9c63-70dca9cde3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825469462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.825469462
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.4071118818
Short name T78
Test name
Test status
Simulation time 267397319 ps
CPU time 4 seconds
Started Jul 12 06:40:58 PM PDT 24
Finished Jul 12 06:41:03 PM PDT 24
Peak memory 214376 kb
Host smart-a21c0f7d-bd50-4757-a25f-57299df98d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071118818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.4071118818
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2134286707
Short name T94
Test name
Test status
Simulation time 218987328 ps
CPU time 5.95 seconds
Started Jul 12 06:41:02 PM PDT 24
Finished Jul 12 06:41:09 PM PDT 24
Peak memory 221248 kb
Host smart-9f1038d6-9ef3-4207-979f-2947b8b9211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134286707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2134286707
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3305623654
Short name T237
Test name
Test status
Simulation time 217378997 ps
CPU time 3.64 seconds
Started Jul 12 06:40:55 PM PDT 24
Finished Jul 12 06:41:01 PM PDT 24
Peak memory 214288 kb
Host smart-d9f20d8b-3584-4198-bfb2-161154c8e34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305623654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3305623654
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.222594726
Short name T561
Test name
Test status
Simulation time 988042415 ps
CPU time 3.74 seconds
Started Jul 12 06:40:58 PM PDT 24
Finished Jul 12 06:41:03 PM PDT 24
Peak memory 209664 kb
Host smart-5dbffe98-149b-4fdb-a7cc-e235a702b137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222594726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.222594726
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.936622000
Short name T736
Test name
Test status
Simulation time 205971665 ps
CPU time 5.36 seconds
Started Jul 12 06:40:53 PM PDT 24
Finished Jul 12 06:41:02 PM PDT 24
Peak memory 208004 kb
Host smart-47be24ad-4910-40b9-afc9-e9548f0015f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936622000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.936622000
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2451143508
Short name T280
Test name
Test status
Simulation time 363956978 ps
CPU time 5.32 seconds
Started Jul 12 06:44:47 PM PDT 24
Finished Jul 12 06:44:55 PM PDT 24
Peak memory 207876 kb
Host smart-4a841734-3756-42f1-ad9f-a77e77432906
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451143508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2451143508
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.667109547
Short name T531
Test name
Test status
Simulation time 101947054 ps
CPU time 3.46 seconds
Started Jul 12 06:40:54 PM PDT 24
Finished Jul 12 06:41:00 PM PDT 24
Peak memory 208688 kb
Host smart-0ad82019-e344-41c7-99cb-d11b4a62991c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667109547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.667109547
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.219277940
Short name T688
Test name
Test status
Simulation time 673538513 ps
CPU time 17.8 seconds
Started Jul 12 06:40:54 PM PDT 24
Finished Jul 12 06:41:15 PM PDT 24
Peak memory 208404 kb
Host smart-f947a186-a2bf-47c6-8172-6865c2e9ebfe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219277940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.219277940
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.4213566014
Short name T470
Test name
Test status
Simulation time 502826644 ps
CPU time 2.77 seconds
Started Jul 12 06:41:00 PM PDT 24
Finished Jul 12 06:41:04 PM PDT 24
Peak memory 208804 kb
Host smart-b5e3082e-2d08-4514-9b4d-f93ab5bc37a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213566014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.4213566014
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.4097741146
Short name T789
Test name
Test status
Simulation time 191970033 ps
CPU time 2.16 seconds
Started Jul 12 06:40:52 PM PDT 24
Finished Jul 12 06:40:57 PM PDT 24
Peak memory 206824 kb
Host smart-e2af35eb-a601-45d4-90e4-3ca0b399e714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097741146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.4097741146
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.329316174
Short name T178
Test name
Test status
Simulation time 1400211096 ps
CPU time 13.4 seconds
Started Jul 12 06:40:56 PM PDT 24
Finished Jul 12 06:41:11 PM PDT 24
Peak memory 220492 kb
Host smart-0b6778d4-3db3-40b0-ba54-609887c5bb84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329316174 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.329316174
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.4067659531
Short name T469
Test name
Test status
Simulation time 8715238882 ps
CPU time 47.35 seconds
Started Jul 12 06:41:01 PM PDT 24
Finished Jul 12 06:41:49 PM PDT 24
Peak memory 220584 kb
Host smart-7355d1b0-44ee-4137-b647-9f6f6a26792f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067659531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.4067659531
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.156455197
Short name T60
Test name
Test status
Simulation time 264711488 ps
CPU time 2.76 seconds
Started Jul 12 06:41:01 PM PDT 24
Finished Jul 12 06:41:05 PM PDT 24
Peak memory 210388 kb
Host smart-ec4db26d-4db4-4ea9-81e5-2fd4a64f85ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156455197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.156455197
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.21578097
Short name T850
Test name
Test status
Simulation time 11376730 ps
CPU time 0.76 seconds
Started Jul 12 06:41:08 PM PDT 24
Finished Jul 12 06:41:11 PM PDT 24
Peak memory 205980 kb
Host smart-53bcabe8-28df-45ce-b0b0-108cc1b3ee5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21578097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.21578097
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.4086923782
Short name T104
Test name
Test status
Simulation time 597245214 ps
CPU time 28.64 seconds
Started Jul 12 06:41:01 PM PDT 24
Finished Jul 12 06:41:31 PM PDT 24
Peak memory 214324 kb
Host smart-d248d0c5-f445-485e-b53e-30d8a6f9aef6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4086923782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.4086923782
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2069122306
Short name T22
Test name
Test status
Simulation time 136649940 ps
CPU time 1.78 seconds
Started Jul 12 06:41:00 PM PDT 24
Finished Jul 12 06:41:03 PM PDT 24
Peak memory 214732 kb
Host smart-7a4f4879-5591-4689-b068-36b8eecb8527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069122306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2069122306
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1368868950
Short name T809
Test name
Test status
Simulation time 78590386 ps
CPU time 2.23 seconds
Started Jul 12 06:41:07 PM PDT 24
Finished Jul 12 06:41:11 PM PDT 24
Peak memory 209272 kb
Host smart-d3bd21f5-0b4e-45e9-9f69-81b60d387db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368868950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1368868950
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3414210313
Short name T582
Test name
Test status
Simulation time 89715770 ps
CPU time 2.45 seconds
Started Jul 12 06:41:00 PM PDT 24
Finished Jul 12 06:41:03 PM PDT 24
Peak memory 216060 kb
Host smart-8110f034-fc88-4ad9-94be-efde2c1c67c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414210313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3414210313
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3132777606
Short name T617
Test name
Test status
Simulation time 107386626 ps
CPU time 4.8 seconds
Started Jul 12 06:41:00 PM PDT 24
Finished Jul 12 06:41:07 PM PDT 24
Peak memory 207764 kb
Host smart-b54ff1f2-4308-4cb7-b84b-723b217e9dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132777606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3132777606
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1735163861
Short name T380
Test name
Test status
Simulation time 155742893 ps
CPU time 4.53 seconds
Started Jul 12 06:41:09 PM PDT 24
Finished Jul 12 06:41:18 PM PDT 24
Peak memory 207328 kb
Host smart-9292fa94-fe7b-4f94-b524-83b454a0d963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735163861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1735163861
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1114964638
Short name T601
Test name
Test status
Simulation time 61828498 ps
CPU time 2.4 seconds
Started Jul 12 06:41:03 PM PDT 24
Finished Jul 12 06:41:06 PM PDT 24
Peak memory 206948 kb
Host smart-17f87867-2df9-41a1-8cf1-c761cef68281
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114964638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1114964638
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.56378049
Short name T495
Test name
Test status
Simulation time 2965009824 ps
CPU time 16.76 seconds
Started Jul 12 06:41:01 PM PDT 24
Finished Jul 12 06:41:19 PM PDT 24
Peak memory 208480 kb
Host smart-875508a5-2b16-48fc-aeb1-3474a7c10f7c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56378049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.56378049
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2276169984
Short name T589
Test name
Test status
Simulation time 172733922 ps
CPU time 5.01 seconds
Started Jul 12 06:41:03 PM PDT 24
Finished Jul 12 06:41:09 PM PDT 24
Peak memory 207864 kb
Host smart-0b88e661-ec11-445d-bcec-ef939a301c6f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276169984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2276169984
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2953200459
Short name T548
Test name
Test status
Simulation time 112697005 ps
CPU time 2.98 seconds
Started Jul 12 06:41:02 PM PDT 24
Finished Jul 12 06:41:06 PM PDT 24
Peak memory 209792 kb
Host smart-bdb3cc91-a6c5-4400-b476-4b33861ea70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953200459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2953200459
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.248208848
Short name T433
Test name
Test status
Simulation time 317025507 ps
CPU time 4.83 seconds
Started Jul 12 06:41:06 PM PDT 24
Finished Jul 12 06:41:12 PM PDT 24
Peak memory 208508 kb
Host smart-fb0b276d-b0ed-4c4f-a792-f741ea96435f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248208848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.248208848
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.650744673
Short name T881
Test name
Test status
Simulation time 358254235 ps
CPU time 3.37 seconds
Started Jul 12 06:40:59 PM PDT 24
Finished Jul 12 06:41:04 PM PDT 24
Peak memory 209344 kb
Host smart-a3c5c2bc-b898-455c-b59e-794bae928b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650744673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.650744673
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.593009185
Short name T506
Test name
Test status
Simulation time 205401008 ps
CPU time 3.57 seconds
Started Jul 12 06:41:05 PM PDT 24
Finished Jul 12 06:41:10 PM PDT 24
Peak memory 210604 kb
Host smart-a9ae4e7b-d907-41f0-8bb1-a797f6138fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593009185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.593009185
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1162967841
Short name T571
Test name
Test status
Simulation time 11145593 ps
CPU time 0.74 seconds
Started Jul 12 06:41:05 PM PDT 24
Finished Jul 12 06:41:08 PM PDT 24
Peak memory 205988 kb
Host smart-70fc8cd5-1c86-4316-95c2-b47021f7b295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162967841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1162967841
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1498492134
Short name T906
Test name
Test status
Simulation time 4259945911 ps
CPU time 55.67 seconds
Started Jul 12 06:41:05 PM PDT 24
Finished Jul 12 06:42:03 PM PDT 24
Peak memory 215496 kb
Host smart-8cbd7cd3-20f7-44fa-8069-f8700badc58a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1498492134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1498492134
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1256061108
Short name T292
Test name
Test status
Simulation time 108712692 ps
CPU time 3.6 seconds
Started Jul 12 06:41:01 PM PDT 24
Finished Jul 12 06:41:06 PM PDT 24
Peak memory 219656 kb
Host smart-6a5aa622-b2f6-45b5-aaef-705363cd8d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256061108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1256061108
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2911781336
Short name T25
Test name
Test status
Simulation time 91563752 ps
CPU time 4.43 seconds
Started Jul 12 06:41:10 PM PDT 24
Finished Jul 12 06:41:18 PM PDT 24
Peak memory 219464 kb
Host smart-6a9d8288-6618-40cc-9bd3-9536abe54e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911781336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2911781336
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3431442801
Short name T630
Test name
Test status
Simulation time 184824474 ps
CPU time 3.6 seconds
Started Jul 12 06:41:04 PM PDT 24
Finished Jul 12 06:41:10 PM PDT 24
Peak memory 211480 kb
Host smart-0eeb4490-f900-4ef8-a8ee-00d98e443f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431442801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3431442801
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1932061995
Short name T605
Test name
Test status
Simulation time 97147262 ps
CPU time 4.96 seconds
Started Jul 12 06:41:04 PM PDT 24
Finished Jul 12 06:41:11 PM PDT 24
Peak memory 214408 kb
Host smart-f4966d85-2c6d-4d1f-b541-7714d5545a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932061995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1932061995
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2250125908
Short name T916
Test name
Test status
Simulation time 668790133 ps
CPU time 5.16 seconds
Started Jul 12 06:41:05 PM PDT 24
Finished Jul 12 06:41:12 PM PDT 24
Peak memory 219404 kb
Host smart-a0a91c4b-af1d-4f48-bcb4-43ee4ff7928b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250125908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2250125908
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.4077579850
Short name T278
Test name
Test status
Simulation time 3114774665 ps
CPU time 33.4 seconds
Started Jul 12 06:41:04 PM PDT 24
Finished Jul 12 06:41:39 PM PDT 24
Peak memory 209144 kb
Host smart-beabbf59-96cf-488b-bae9-e2e383f6ccf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077579850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.4077579850
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3147748341
Short name T256
Test name
Test status
Simulation time 7415047104 ps
CPU time 37.54 seconds
Started Jul 12 06:41:08 PM PDT 24
Finished Jul 12 06:41:50 PM PDT 24
Peak memory 208024 kb
Host smart-68ea62b5-20aa-4106-a045-5ba0aade4aac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147748341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3147748341
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.482572044
Short name T410
Test name
Test status
Simulation time 190348922 ps
CPU time 2.66 seconds
Started Jul 12 06:41:02 PM PDT 24
Finished Jul 12 06:41:06 PM PDT 24
Peak memory 206956 kb
Host smart-7091f52b-9312-4e05-ba63-d6c8f9ad5400
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482572044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.482572044
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2553594687
Short name T628
Test name
Test status
Simulation time 606846508 ps
CPU time 4.61 seconds
Started Jul 12 06:41:03 PM PDT 24
Finished Jul 12 06:41:08 PM PDT 24
Peak memory 207208 kb
Host smart-08c777f4-906f-47e6-8e29-34df7b06f861
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553594687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2553594687
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.909361353
Short name T887
Test name
Test status
Simulation time 94085353 ps
CPU time 2.41 seconds
Started Jul 12 06:41:04 PM PDT 24
Finished Jul 12 06:41:08 PM PDT 24
Peak memory 208008 kb
Host smart-ddad37be-8f1b-4674-8cbe-01da0e33ad52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909361353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.909361353
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.939646428
Short name T693
Test name
Test status
Simulation time 260600312 ps
CPU time 2.61 seconds
Started Jul 12 06:41:05 PM PDT 24
Finished Jul 12 06:41:09 PM PDT 24
Peak memory 206684 kb
Host smart-3148dedf-d44a-4034-8a42-1a160d3f9ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939646428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.939646428
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2830567005
Short name T347
Test name
Test status
Simulation time 771900114 ps
CPU time 32.49 seconds
Started Jul 12 06:41:04 PM PDT 24
Finished Jul 12 06:41:38 PM PDT 24
Peak memory 215744 kb
Host smart-40ebb42d-3cc9-4b19-adb8-0313ab84c8a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830567005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2830567005
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2910545510
Short name T127
Test name
Test status
Simulation time 2035885861 ps
CPU time 15.02 seconds
Started Jul 12 06:41:04 PM PDT 24
Finished Jul 12 06:41:21 PM PDT 24
Peak memory 222488 kb
Host smart-0cee2286-f1c1-4130-8d5d-f9d659bed3e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910545510 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2910545510
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1433904655
Short name T794
Test name
Test status
Simulation time 34916183299 ps
CPU time 63.13 seconds
Started Jul 12 06:41:01 PM PDT 24
Finished Jul 12 06:42:06 PM PDT 24
Peak memory 209572 kb
Host smart-83dd371c-13d1-48fb-ae46-5372dbf8ed07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433904655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1433904655
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3662716746
Short name T437
Test name
Test status
Simulation time 41915244 ps
CPU time 2.02 seconds
Started Jul 12 06:41:04 PM PDT 24
Finished Jul 12 06:41:08 PM PDT 24
Peak memory 210176 kb
Host smart-31bfe2e3-0775-40cb-aaad-29ce2c0712f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662716746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3662716746
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1794922254
Short name T919
Test name
Test status
Simulation time 44571907 ps
CPU time 0.86 seconds
Started Jul 12 06:41:08 PM PDT 24
Finished Jul 12 06:41:11 PM PDT 24
Peak memory 206004 kb
Host smart-4891f078-8b07-4c9b-9347-3767cb922093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794922254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1794922254
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.295423171
Short name T852
Test name
Test status
Simulation time 3273973839 ps
CPU time 33.01 seconds
Started Jul 12 06:41:10 PM PDT 24
Finished Jul 12 06:41:47 PM PDT 24
Peak memory 208912 kb
Host smart-975cff68-d0eb-474c-aab4-6e117c97fe42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295423171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.295423171
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.51615558
Short name T91
Test name
Test status
Simulation time 407684416 ps
CPU time 4.28 seconds
Started Jul 12 06:41:08 PM PDT 24
Finished Jul 12 06:41:15 PM PDT 24
Peak memory 214308 kb
Host smart-8746f35a-9bc3-44c1-9ca7-92dc61f440bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51615558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.51615558
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2646110223
Short name T611
Test name
Test status
Simulation time 165664288 ps
CPU time 6.2 seconds
Started Jul 12 06:41:09 PM PDT 24
Finished Jul 12 06:41:20 PM PDT 24
Peak memory 214232 kb
Host smart-ab00ce88-0eaa-4333-9898-f799e177cc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646110223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2646110223
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3630124925
Short name T247
Test name
Test status
Simulation time 98431617 ps
CPU time 3.64 seconds
Started Jul 12 06:41:08 PM PDT 24
Finished Jul 12 06:41:14 PM PDT 24
Peak memory 219904 kb
Host smart-6153bc03-bd66-4039-a3a6-dc818d300360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630124925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3630124925
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.4054925373
Short name T890
Test name
Test status
Simulation time 305500253 ps
CPU time 8.9 seconds
Started Jul 12 06:41:03 PM PDT 24
Finished Jul 12 06:41:13 PM PDT 24
Peak memory 210144 kb
Host smart-f9d200be-5865-4a6d-b705-1aae83ca0698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054925373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.4054925373
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2358222244
Short name T686
Test name
Test status
Simulation time 338057045 ps
CPU time 4.03 seconds
Started Jul 12 06:41:03 PM PDT 24
Finished Jul 12 06:41:08 PM PDT 24
Peak memory 208880 kb
Host smart-0223afdd-42a9-4e9b-9365-988fbc64ca27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358222244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2358222244
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3864898427
Short name T739
Test name
Test status
Simulation time 30336441 ps
CPU time 2.23 seconds
Started Jul 12 06:41:10 PM PDT 24
Finished Jul 12 06:41:16 PM PDT 24
Peak memory 209088 kb
Host smart-ff768f78-1370-49a0-b00e-51d112e175fd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864898427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3864898427
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3315541504
Short name T700
Test name
Test status
Simulation time 55369623 ps
CPU time 2.75 seconds
Started Jul 12 06:41:05 PM PDT 24
Finished Jul 12 06:41:10 PM PDT 24
Peak memory 206828 kb
Host smart-4afd8dca-2796-43e7-86bd-20bf94ac0c84
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315541504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3315541504
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1961583932
Short name T355
Test name
Test status
Simulation time 946840233 ps
CPU time 6.13 seconds
Started Jul 12 06:41:13 PM PDT 24
Finished Jul 12 06:41:23 PM PDT 24
Peak memory 208012 kb
Host smart-a41c3c80-efca-4386-9a2d-c9c908e75829
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961583932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1961583932
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.992858849
Short name T769
Test name
Test status
Simulation time 443535784 ps
CPU time 6.17 seconds
Started Jul 12 06:41:05 PM PDT 24
Finished Jul 12 06:41:13 PM PDT 24
Peak memory 209532 kb
Host smart-f9ffce33-62da-4227-869c-cceb44665c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992858849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.992858849
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.766536713
Short name T522
Test name
Test status
Simulation time 1324241468 ps
CPU time 17.21 seconds
Started Jul 12 06:41:09 PM PDT 24
Finished Jul 12 06:41:31 PM PDT 24
Peak memory 208600 kb
Host smart-79fa285f-fa2e-4206-9945-d8514fcccefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766536713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.766536713
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1321394085
Short name T581
Test name
Test status
Simulation time 346389651 ps
CPU time 6.06 seconds
Started Jul 12 06:41:05 PM PDT 24
Finished Jul 12 06:41:13 PM PDT 24
Peak memory 219424 kb
Host smart-2c58fd32-d26c-4094-9984-be6c6860b9ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321394085 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1321394085
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3463941724
Short name T643
Test name
Test status
Simulation time 133967119 ps
CPU time 2.73 seconds
Started Jul 12 06:41:12 PM PDT 24
Finished Jul 12 06:41:19 PM PDT 24
Peak memory 208020 kb
Host smart-65c8af33-20e9-4815-aed6-fa4d5f681973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463941724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3463941724
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3518133725
Short name T59
Test name
Test status
Simulation time 100195895 ps
CPU time 2.47 seconds
Started Jul 12 06:41:11 PM PDT 24
Finished Jul 12 06:41:18 PM PDT 24
Peak memory 210128 kb
Host smart-81883351-8e8e-484c-b8da-8d9c08f85fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518133725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3518133725
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.392202212
Short name T525
Test name
Test status
Simulation time 59504660 ps
CPU time 0.75 seconds
Started Jul 12 06:41:20 PM PDT 24
Finished Jul 12 06:41:24 PM PDT 24
Peak memory 205948 kb
Host smart-fcc01346-91f0-423f-95ae-6132306e9a96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392202212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.392202212
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3167292549
Short name T715
Test name
Test status
Simulation time 164505089 ps
CPU time 6.28 seconds
Started Jul 12 06:41:15 PM PDT 24
Finished Jul 12 06:41:24 PM PDT 24
Peak memory 214312 kb
Host smart-d278148f-b556-432b-aec7-51996c7d2a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167292549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3167292549
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1751487253
Short name T749
Test name
Test status
Simulation time 88872075 ps
CPU time 2.59 seconds
Started Jul 12 06:41:04 PM PDT 24
Finished Jul 12 06:41:09 PM PDT 24
Peak memory 207568 kb
Host smart-bcd9046c-c72b-41e9-b9d4-f1799154b2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751487253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1751487253
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.984243317
Short name T320
Test name
Test status
Simulation time 393254549 ps
CPU time 2.78 seconds
Started Jul 12 06:41:10 PM PDT 24
Finished Jul 12 06:41:17 PM PDT 24
Peak memory 214216 kb
Host smart-4dfa4429-319d-44f7-b633-ee358c467930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984243317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.984243317
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.335317427
Short name T650
Test name
Test status
Simulation time 248622370 ps
CPU time 5.25 seconds
Started Jul 12 06:41:07 PM PDT 24
Finished Jul 12 06:41:14 PM PDT 24
Peak memory 214324 kb
Host smart-d700fdad-22de-4f9c-a8dc-d04063fbae36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335317427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.335317427
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2096252822
Short name T265
Test name
Test status
Simulation time 388815960 ps
CPU time 4.46 seconds
Started Jul 12 06:41:10 PM PDT 24
Finished Jul 12 06:41:18 PM PDT 24
Peak memory 218168 kb
Host smart-70e56a71-d2fe-4ce2-ac33-75a447df80e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096252822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2096252822
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1103799154
Short name T680
Test name
Test status
Simulation time 361212246 ps
CPU time 6.09 seconds
Started Jul 12 06:41:04 PM PDT 24
Finished Jul 12 06:41:11 PM PDT 24
Peak memory 208908 kb
Host smart-69d6dd1d-4860-4354-80e9-13764d54ddeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103799154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1103799154
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2041217837
Short name T498
Test name
Test status
Simulation time 378577356 ps
CPU time 2.62 seconds
Started Jul 12 06:41:10 PM PDT 24
Finished Jul 12 06:41:17 PM PDT 24
Peak memory 207012 kb
Host smart-03f7f57c-38c0-4113-8070-e4f809a29615
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041217837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2041217837
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2842998479
Short name T487
Test name
Test status
Simulation time 81089634 ps
CPU time 1.93 seconds
Started Jul 12 06:41:04 PM PDT 24
Finished Jul 12 06:41:08 PM PDT 24
Peak memory 206980 kb
Host smart-7f86e47c-89c4-4855-85e0-b53cde454168
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842998479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2842998479
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3649310374
Short name T743
Test name
Test status
Simulation time 48535732 ps
CPU time 2.71 seconds
Started Jul 12 06:41:07 PM PDT 24
Finished Jul 12 06:41:11 PM PDT 24
Peak memory 206996 kb
Host smart-73a497c9-990b-439b-b94f-70299d1913ea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649310374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3649310374
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1945546082
Short name T898
Test name
Test status
Simulation time 254579683 ps
CPU time 2.39 seconds
Started Jul 12 06:41:10 PM PDT 24
Finished Jul 12 06:41:18 PM PDT 24
Peak memory 218052 kb
Host smart-ca165f49-4af5-4c42-a9cb-d25007538b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945546082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1945546082
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.515634863
Short name T778
Test name
Test status
Simulation time 138913651 ps
CPU time 2.1 seconds
Started Jul 12 06:41:02 PM PDT 24
Finished Jul 12 06:41:05 PM PDT 24
Peak memory 208580 kb
Host smart-e85bdf6b-4cb6-4f3b-9989-6f998c677ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515634863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.515634863
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.634654127
Short name T242
Test name
Test status
Simulation time 3509111580 ps
CPU time 33.62 seconds
Started Jul 12 06:41:10 PM PDT 24
Finished Jul 12 06:41:49 PM PDT 24
Peak memory 215752 kb
Host smart-28cb9a24-55a1-4caa-9f03-467297b899c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634654127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.634654127
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3412970647
Short name T511
Test name
Test status
Simulation time 6233017180 ps
CPU time 71.26 seconds
Started Jul 12 06:41:10 PM PDT 24
Finished Jul 12 06:42:25 PM PDT 24
Peak memory 218160 kb
Host smart-d01990da-2aed-49c0-b64d-834486a17a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412970647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3412970647
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1377925162
Short name T882
Test name
Test status
Simulation time 38489905 ps
CPU time 1.85 seconds
Started Jul 12 06:41:11 PM PDT 24
Finished Jul 12 06:41:18 PM PDT 24
Peak memory 210000 kb
Host smart-b3928162-3671-4b2a-9399-760977373b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377925162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1377925162
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2566866568
Short name T97
Test name
Test status
Simulation time 12121536 ps
CPU time 0.89 seconds
Started Jul 12 06:41:10 PM PDT 24
Finished Jul 12 06:41:16 PM PDT 24
Peak memory 206016 kb
Host smart-5c1bc315-4a8a-44ab-b2de-4fbffd67df3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566866568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2566866568
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3063376559
Short name T744
Test name
Test status
Simulation time 731467255 ps
CPU time 4.88 seconds
Started Jul 12 06:41:08 PM PDT 24
Finished Jul 12 06:41:15 PM PDT 24
Peak memory 215456 kb
Host smart-7dae496a-2d7a-4220-8c37-c9f2d93810dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3063376559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3063376559
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1850842609
Short name T710
Test name
Test status
Simulation time 222314575 ps
CPU time 2.16 seconds
Started Jul 12 06:41:08 PM PDT 24
Finished Jul 12 06:41:14 PM PDT 24
Peak memory 209860 kb
Host smart-ae0ded88-af63-4473-8d3d-df2e159b66a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850842609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1850842609
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.991393683
Short name T502
Test name
Test status
Simulation time 48509387 ps
CPU time 2.13 seconds
Started Jul 12 06:41:13 PM PDT 24
Finished Jul 12 06:41:19 PM PDT 24
Peak memory 207928 kb
Host smart-d2fa1afe-98e3-4c10-ab97-d0772dc0ea61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991393683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.991393683
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2198285023
Short name T817
Test name
Test status
Simulation time 489149451 ps
CPU time 4.63 seconds
Started Jul 12 06:41:11 PM PDT 24
Finished Jul 12 06:41:20 PM PDT 24
Peak memory 214312 kb
Host smart-28bb9f66-427e-4001-8847-1ef69eccb3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198285023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2198285023
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2154033040
Short name T266
Test name
Test status
Simulation time 98736200 ps
CPU time 2.78 seconds
Started Jul 12 06:41:17 PM PDT 24
Finished Jul 12 06:41:22 PM PDT 24
Peak memory 215940 kb
Host smart-b3783662-2eec-4cc3-8a7c-0c01dab167c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154033040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2154033040
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.4007514678
Short name T910
Test name
Test status
Simulation time 76430354 ps
CPU time 3.09 seconds
Started Jul 12 06:41:10 PM PDT 24
Finished Jul 12 06:41:17 PM PDT 24
Peak memory 207856 kb
Host smart-16bd8270-576e-4b76-8481-002f96af7ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007514678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.4007514678
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2043771730
Short name T460
Test name
Test status
Simulation time 179124561 ps
CPU time 2.7 seconds
Started Jul 12 06:41:09 PM PDT 24
Finished Jul 12 06:41:15 PM PDT 24
Peak memory 206796 kb
Host smart-de3b6083-83a4-4b3c-8f5b-0f47c5c72e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043771730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2043771730
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1679633841
Short name T880
Test name
Test status
Simulation time 507140091 ps
CPU time 3.24 seconds
Started Jul 12 06:41:15 PM PDT 24
Finished Jul 12 06:41:21 PM PDT 24
Peak memory 206864 kb
Host smart-5edeb91c-c12b-4594-ac49-29fd6ccb78ea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679633841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1679633841
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.544840491
Short name T814
Test name
Test status
Simulation time 279996891 ps
CPU time 3.69 seconds
Started Jul 12 06:41:08 PM PDT 24
Finished Jul 12 06:41:15 PM PDT 24
Peak memory 207000 kb
Host smart-de46a562-3957-4f9b-bc64-9d4b43c0f55c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544840491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.544840491
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.599855557
Short name T281
Test name
Test status
Simulation time 132487571 ps
CPU time 3.88 seconds
Started Jul 12 06:41:08 PM PDT 24
Finished Jul 12 06:41:14 PM PDT 24
Peak memory 207560 kb
Host smart-4c4c4400-bcb9-4c62-b1d5-a6b0dc6329e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599855557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.599855557
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2709699867
Short name T224
Test name
Test status
Simulation time 149399862 ps
CPU time 1.76 seconds
Started Jul 12 06:41:10 PM PDT 24
Finished Jul 12 06:41:16 PM PDT 24
Peak memory 205988 kb
Host smart-036ea699-4dce-45e5-b63b-16195706578d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709699867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2709699867
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2104582451
Short name T293
Test name
Test status
Simulation time 498222829 ps
CPU time 12.78 seconds
Started Jul 12 06:41:14 PM PDT 24
Finished Jul 12 06:41:30 PM PDT 24
Peak memory 216272 kb
Host smart-a09d40aa-2dff-444a-bac7-af665bab9349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104582451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2104582451
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3932860341
Short name T417
Test name
Test status
Simulation time 737899996 ps
CPU time 5.81 seconds
Started Jul 12 06:41:12 PM PDT 24
Finished Jul 12 06:41:22 PM PDT 24
Peak memory 218544 kb
Host smart-b28df8fa-330c-4a66-a9e2-7a1c5ed4df24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932860341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3932860341
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3446159928
Short name T399
Test name
Test status
Simulation time 105551657 ps
CPU time 3.06 seconds
Started Jul 12 06:41:09 PM PDT 24
Finished Jul 12 06:41:16 PM PDT 24
Peak memory 210096 kb
Host smart-7c1a0c35-a03b-4063-be92-4ce84ed89033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446159928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3446159928
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.859930954
Short name T503
Test name
Test status
Simulation time 8989886 ps
CPU time 0.79 seconds
Started Jul 12 06:41:16 PM PDT 24
Finished Jul 12 06:41:20 PM PDT 24
Peak memory 205992 kb
Host smart-62777502-a286-4cec-9f15-54532a69e583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859930954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.859930954
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.291229510
Short name T325
Test name
Test status
Simulation time 529350849 ps
CPU time 6.48 seconds
Started Jul 12 06:41:11 PM PDT 24
Finished Jul 12 06:41:22 PM PDT 24
Peak memory 214756 kb
Host smart-aecfa99b-3064-4b02-a457-4f839cfadb90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=291229510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.291229510
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3341069253
Short name T5
Test name
Test status
Simulation time 107459050 ps
CPU time 3.91 seconds
Started Jul 12 06:41:17 PM PDT 24
Finished Jul 12 06:41:24 PM PDT 24
Peak memory 222864 kb
Host smart-82e963e6-38c1-4b65-86a2-94b0e1d6dbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341069253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3341069253
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.488475490
Short name T642
Test name
Test status
Simulation time 315677186 ps
CPU time 4.79 seconds
Started Jul 12 06:41:10 PM PDT 24
Finished Jul 12 06:41:20 PM PDT 24
Peak memory 208580 kb
Host smart-4b6b71a3-3c3e-4cbe-85ce-835b5c7c3460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488475490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.488475490
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.4222728562
Short name T90
Test name
Test status
Simulation time 144089297 ps
CPU time 5.58 seconds
Started Jul 12 06:41:14 PM PDT 24
Finished Jul 12 06:41:23 PM PDT 24
Peak memory 220848 kb
Host smart-0cc03054-63b7-436f-86f5-fe09e9716175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222728562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.4222728562
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2239723452
Short name T414
Test name
Test status
Simulation time 729029177 ps
CPU time 3.78 seconds
Started Jul 12 06:41:12 PM PDT 24
Finished Jul 12 06:41:20 PM PDT 24
Peak memory 214332 kb
Host smart-3af6bde6-681e-41c8-a8ce-156d5a86da80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239723452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2239723452
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3864868187
Short name T76
Test name
Test status
Simulation time 37057173 ps
CPU time 2.71 seconds
Started Jul 12 06:41:10 PM PDT 24
Finished Jul 12 06:41:18 PM PDT 24
Peak memory 207336 kb
Host smart-59d48e83-e7e3-4327-b661-4e56efa5bccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864868187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3864868187
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2857397528
Short name T807
Test name
Test status
Simulation time 280804854 ps
CPU time 3.72 seconds
Started Jul 12 06:41:12 PM PDT 24
Finished Jul 12 06:41:20 PM PDT 24
Peak memory 206956 kb
Host smart-bf635001-f6c4-44a7-af5a-701fb2db251e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857397528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2857397528
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.4211756595
Short name T537
Test name
Test status
Simulation time 398740174 ps
CPU time 6.45 seconds
Started Jul 12 06:41:15 PM PDT 24
Finished Jul 12 06:41:24 PM PDT 24
Peak memory 208360 kb
Host smart-e64d1a6f-ff88-4112-88b3-c60501373368
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211756595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.4211756595
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3111118256
Short name T75
Test name
Test status
Simulation time 602458930 ps
CPU time 7.7 seconds
Started Jul 12 06:41:11 PM PDT 24
Finished Jul 12 06:41:24 PM PDT 24
Peak memory 207952 kb
Host smart-854e75f1-2f42-4171-a9e7-d7146a52eebb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111118256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3111118256
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1762338058
Short name T294
Test name
Test status
Simulation time 30925151 ps
CPU time 2.3 seconds
Started Jul 12 06:41:15 PM PDT 24
Finished Jul 12 06:41:20 PM PDT 24
Peak memory 209008 kb
Host smart-aaa82018-be74-4d15-bb93-224deab613c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762338058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1762338058
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3552922713
Short name T762
Test name
Test status
Simulation time 67765147 ps
CPU time 2.95 seconds
Started Jul 12 06:41:11 PM PDT 24
Finished Jul 12 06:41:19 PM PDT 24
Peak memory 208428 kb
Host smart-0fa94d10-3684-428c-9edb-d4cb071562ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552922713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3552922713
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3125267446
Short name T126
Test name
Test status
Simulation time 665113865 ps
CPU time 8.39 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:33 PM PDT 24
Peak memory 222568 kb
Host smart-06353d1a-f832-4d5d-83d6-8aac95a0c1c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125267446 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3125267446
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3897183961
Short name T875
Test name
Test status
Simulation time 158349985 ps
CPU time 4.89 seconds
Started Jul 12 06:41:28 PM PDT 24
Finished Jul 12 06:41:36 PM PDT 24
Peak memory 208920 kb
Host smart-eea55e8e-33a8-45d6-8d7d-539465968ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897183961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3897183961
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1597361506
Short name T398
Test name
Test status
Simulation time 266092062 ps
CPU time 1.83 seconds
Started Jul 12 06:41:22 PM PDT 24
Finished Jul 12 06:41:27 PM PDT 24
Peak memory 210980 kb
Host smart-f4a698ea-751e-4ffe-83ee-506edbe0839e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597361506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1597361506
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2776402356
Short name T98
Test name
Test status
Simulation time 14898293 ps
CPU time 0.71 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:26 PM PDT 24
Peak memory 205988 kb
Host smart-8dd8bda7-1861-463c-b0b2-b6014864d889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776402356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2776402356
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3754991332
Short name T861
Test name
Test status
Simulation time 216067813 ps
CPU time 11.05 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:36 PM PDT 24
Peak memory 215528 kb
Host smart-efd884cd-969c-4f8f-807a-815c3096b276
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3754991332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3754991332
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.540836500
Short name T730
Test name
Test status
Simulation time 120458522 ps
CPU time 3.37 seconds
Started Jul 12 06:41:26 PM PDT 24
Finished Jul 12 06:41:33 PM PDT 24
Peak memory 207932 kb
Host smart-f70995b2-52bb-4911-bec0-56ed43db1546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540836500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.540836500
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3971362351
Short name T339
Test name
Test status
Simulation time 141401150 ps
CPU time 2.68 seconds
Started Jul 12 06:41:20 PM PDT 24
Finished Jul 12 06:41:25 PM PDT 24
Peak memory 222484 kb
Host smart-0523fcff-99b6-4c32-89c1-86d5135abd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971362351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3971362351
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.158897951
Short name T480
Test name
Test status
Simulation time 437360422 ps
CPU time 3.84 seconds
Started Jul 12 06:41:14 PM PDT 24
Finished Jul 12 06:41:21 PM PDT 24
Peak memory 218376 kb
Host smart-a60de2a2-7ac9-45c7-94dd-22d4b6b3ee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158897951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.158897951
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2150537504
Short name T864
Test name
Test status
Simulation time 75048635 ps
CPU time 3.61 seconds
Started Jul 12 06:41:14 PM PDT 24
Finished Jul 12 06:41:22 PM PDT 24
Peak memory 207312 kb
Host smart-7182bbf1-efc0-4e95-9652-8ab839a5dca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150537504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2150537504
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2582629063
Short name T221
Test name
Test status
Simulation time 20795011 ps
CPU time 1.87 seconds
Started Jul 12 06:41:23 PM PDT 24
Finished Jul 12 06:41:29 PM PDT 24
Peak memory 206976 kb
Host smart-3fb54b2a-8ce7-43ef-aeed-85f34ebf3e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582629063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2582629063
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2896879752
Short name T384
Test name
Test status
Simulation time 82076216 ps
CPU time 3.67 seconds
Started Jul 12 06:41:16 PM PDT 24
Finished Jul 12 06:41:22 PM PDT 24
Peak memory 208948 kb
Host smart-88ea2783-eba5-4136-8024-f5072e55f70f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896879752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2896879752
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.36544995
Short name T389
Test name
Test status
Simulation time 42308102 ps
CPU time 2.32 seconds
Started Jul 12 06:41:17 PM PDT 24
Finished Jul 12 06:41:22 PM PDT 24
Peak memory 206968 kb
Host smart-a67aa215-23f7-4281-93cd-b9321cc84ee5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36544995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.36544995
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1781643731
Short name T568
Test name
Test status
Simulation time 63874408 ps
CPU time 2.88 seconds
Started Jul 12 06:41:23 PM PDT 24
Finished Jul 12 06:41:30 PM PDT 24
Peak memory 206664 kb
Host smart-887f2d4d-fa2f-424c-97b3-5a987dbde708
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781643731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1781643731
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3538780725
Short name T391
Test name
Test status
Simulation time 32612244 ps
CPU time 2.21 seconds
Started Jul 12 06:41:18 PM PDT 24
Finished Jul 12 06:41:23 PM PDT 24
Peak memory 207984 kb
Host smart-0cb6ba68-2801-459d-bda5-15d6f00f3e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538780725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3538780725
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1262166672
Short name T598
Test name
Test status
Simulation time 33111791 ps
CPU time 2.15 seconds
Started Jul 12 06:41:15 PM PDT 24
Finished Jul 12 06:41:20 PM PDT 24
Peak memory 206964 kb
Host smart-049941d6-4022-4559-b264-5fa35276aa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262166672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1262166672
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2761319930
Short name T797
Test name
Test status
Simulation time 873854389 ps
CPU time 11.99 seconds
Started Jul 12 06:41:15 PM PDT 24
Finished Jul 12 06:41:30 PM PDT 24
Peak memory 221072 kb
Host smart-2f1ce5d4-cb1a-42ae-a9e8-222a4858b2a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761319930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2761319930
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1795973919
Short name T125
Test name
Test status
Simulation time 1791544174 ps
CPU time 24.81 seconds
Started Jul 12 06:41:13 PM PDT 24
Finished Jul 12 06:41:42 PM PDT 24
Peak memory 222660 kb
Host smart-93586f5a-cb16-4479-a8c0-049cd277bb60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795973919 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1795973919
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.330293802
Short name T493
Test name
Test status
Simulation time 114430798 ps
CPU time 2.93 seconds
Started Jul 12 06:41:16 PM PDT 24
Finished Jul 12 06:41:22 PM PDT 24
Peak memory 207612 kb
Host smart-f9d3a99e-83bb-4770-aefc-b482593c68d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330293802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.330293802
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1335373792
Short name T590
Test name
Test status
Simulation time 59501339 ps
CPU time 2.9 seconds
Started Jul 12 06:41:26 PM PDT 24
Finished Jul 12 06:41:32 PM PDT 24
Peak memory 210300 kb
Host smart-4b1b4e62-8ca8-4cf1-85a6-fe8e07b4afec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335373792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1335373792
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2696357124
Short name T708
Test name
Test status
Simulation time 16677891 ps
CPU time 0.73 seconds
Started Jul 12 06:40:01 PM PDT 24
Finished Jul 12 06:40:04 PM PDT 24
Peak memory 205972 kb
Host smart-cc4b8c0b-c6b9-445b-8cb8-13b84b1483f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696357124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2696357124
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.4202043382
Short name T369
Test name
Test status
Simulation time 100265468 ps
CPU time 6.07 seconds
Started Jul 12 06:39:58 PM PDT 24
Finished Jul 12 06:40:05 PM PDT 24
Peak memory 215724 kb
Host smart-43d0af0a-6bbc-4e4b-a7ef-05192b90eb4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4202043382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.4202043382
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.4134704455
Short name T620
Test name
Test status
Simulation time 192274360 ps
CPU time 3.7 seconds
Started Jul 12 06:39:59 PM PDT 24
Finished Jul 12 06:40:05 PM PDT 24
Peak memory 210324 kb
Host smart-776c2a36-9062-4d2d-8728-95c6aa94d0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134704455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.4134704455
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.947492813
Short name T663
Test name
Test status
Simulation time 243029328 ps
CPU time 7.58 seconds
Started Jul 12 06:39:57 PM PDT 24
Finished Jul 12 06:40:06 PM PDT 24
Peak memory 208680 kb
Host smart-9af3046e-32e4-41c5-be0d-a2fa3721a49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947492813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.947492813
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3754967064
Short name T83
Test name
Test status
Simulation time 27860521 ps
CPU time 1.87 seconds
Started Jul 12 06:40:01 PM PDT 24
Finished Jul 12 06:40:05 PM PDT 24
Peak memory 214208 kb
Host smart-c89f575e-5225-4318-a88b-c7beac120c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754967064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3754967064
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.4224148382
Short name T667
Test name
Test status
Simulation time 242256415 ps
CPU time 5.88 seconds
Started Jul 12 06:39:58 PM PDT 24
Finished Jul 12 06:40:05 PM PDT 24
Peak memory 222488 kb
Host smart-3f4e525e-a7bc-4e7a-9afd-cd93085aae12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224148382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.4224148382
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1644857916
Short name T54
Test name
Test status
Simulation time 136716210 ps
CPU time 3.33 seconds
Started Jul 12 06:39:59 PM PDT 24
Finished Jul 12 06:40:04 PM PDT 24
Peak memory 214424 kb
Host smart-440953a8-62f2-4dd5-b412-6b10e74a1c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644857916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1644857916
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3052701256
Short name T824
Test name
Test status
Simulation time 535617372 ps
CPU time 3.15 seconds
Started Jul 12 06:39:57 PM PDT 24
Finished Jul 12 06:40:02 PM PDT 24
Peak memory 209476 kb
Host smart-b4f614f0-c996-47b2-b84e-d119715df472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052701256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3052701256
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2638343900
Short name T102
Test name
Test status
Simulation time 548660583 ps
CPU time 9.43 seconds
Started Jul 12 06:40:02 PM PDT 24
Finished Jul 12 06:40:14 PM PDT 24
Peak memory 230700 kb
Host smart-4c9e724f-c862-4e73-a609-767e7c671875
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638343900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2638343900
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.118085468
Short name T648
Test name
Test status
Simulation time 186192176 ps
CPU time 6.25 seconds
Started Jul 12 06:39:55 PM PDT 24
Finished Jul 12 06:40:02 PM PDT 24
Peak memory 208088 kb
Host smart-f5db7439-2fae-4ac5-bf12-4e6c4519c22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118085468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.118085468
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3437220962
Short name T636
Test name
Test status
Simulation time 141002516 ps
CPU time 2.8 seconds
Started Jul 12 06:39:59 PM PDT 24
Finished Jul 12 06:40:04 PM PDT 24
Peak memory 206748 kb
Host smart-e87dc195-66f1-47b6-aa90-b77351999596
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437220962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3437220962
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1426154953
Short name T277
Test name
Test status
Simulation time 207950992 ps
CPU time 4.15 seconds
Started Jul 12 06:39:53 PM PDT 24
Finished Jul 12 06:39:58 PM PDT 24
Peak memory 207912 kb
Host smart-9c859d8a-9482-46f0-9067-490a707ddad6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426154953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1426154953
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1028682717
Short name T586
Test name
Test status
Simulation time 264145752 ps
CPU time 5.49 seconds
Started Jul 12 06:40:13 PM PDT 24
Finished Jul 12 06:40:22 PM PDT 24
Peak memory 208740 kb
Host smart-0d8a5452-e70c-4aa6-a74a-2b3de92731bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028682717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1028682717
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1808203548
Short name T452
Test name
Test status
Simulation time 48307456 ps
CPU time 2.65 seconds
Started Jul 12 06:40:06 PM PDT 24
Finished Jul 12 06:40:10 PM PDT 24
Peak memory 209240 kb
Host smart-6c82823b-a356-4920-906c-363d9b4f8888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808203548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1808203548
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.733180539
Short name T103
Test name
Test status
Simulation time 228610406 ps
CPU time 4.14 seconds
Started Jul 12 06:40:12 PM PDT 24
Finished Jul 12 06:40:20 PM PDT 24
Peak memory 208152 kb
Host smart-efb42aed-2603-49fa-96eb-795bf54a1130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733180539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.733180539
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.984860712
Short name T203
Test name
Test status
Simulation time 4779220659 ps
CPU time 94.16 seconds
Started Jul 12 06:40:03 PM PDT 24
Finished Jul 12 06:41:39 PM PDT 24
Peak memory 216396 kb
Host smart-034f852c-f8a5-4320-9b3e-e2218a6ddeba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984860712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.984860712
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2965840988
Short name T184
Test name
Test status
Simulation time 61853519 ps
CPU time 2.49 seconds
Started Jul 12 06:39:55 PM PDT 24
Finished Jul 12 06:39:59 PM PDT 24
Peak memory 207916 kb
Host smart-f9739818-0533-4d2d-8e03-02e544c6a9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965840988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2965840988
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2145730927
Short name T733
Test name
Test status
Simulation time 55867279 ps
CPU time 2.55 seconds
Started Jul 12 06:39:58 PM PDT 24
Finished Jul 12 06:40:03 PM PDT 24
Peak memory 210048 kb
Host smart-967ecad3-3e1a-4d86-a27c-c302b2e4ebd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145730927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2145730927
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3229146511
Short name T635
Test name
Test status
Simulation time 14175539 ps
CPU time 0.98 seconds
Started Jul 12 06:41:23 PM PDT 24
Finished Jul 12 06:41:28 PM PDT 24
Peak memory 206116 kb
Host smart-4b4c55fa-2dda-49d9-a9bc-2e18c88ac45f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229146511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3229146511
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2786571510
Short name T842
Test name
Test status
Simulation time 95121113 ps
CPU time 3.09 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:28 PM PDT 24
Peak memory 214408 kb
Host smart-bb7ed824-9f95-4859-bb20-f759be039fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786571510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2786571510
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.4262966963
Short name T319
Test name
Test status
Simulation time 5157878106 ps
CPU time 38.9 seconds
Started Jul 12 06:41:22 PM PDT 24
Finished Jul 12 06:42:04 PM PDT 24
Peak memory 209572 kb
Host smart-7cd05e60-6fc6-4e25-8334-246092c3325b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262966963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.4262966963
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2877872465
Short name T243
Test name
Test status
Simulation time 116337200 ps
CPU time 4.45 seconds
Started Jul 12 06:41:23 PM PDT 24
Finished Jul 12 06:41:32 PM PDT 24
Peak memory 214336 kb
Host smart-d9f81912-5ea1-47e8-a803-f812e2460ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877872465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2877872465
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2984397334
Short name T773
Test name
Test status
Simulation time 14861056237 ps
CPU time 41.08 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:42:06 PM PDT 24
Peak memory 218400 kb
Host smart-d8fc0d3b-091f-4560-996b-1831551b293e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984397334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2984397334
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.33428580
Short name T478
Test name
Test status
Simulation time 144886543 ps
CPU time 5.31 seconds
Started Jul 12 06:41:26 PM PDT 24
Finished Jul 12 06:41:35 PM PDT 24
Peak memory 206956 kb
Host smart-c076fb99-cea9-4aa1-a3b6-766ff988b7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33428580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.33428580
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3361522968
Short name T684
Test name
Test status
Simulation time 1138681435 ps
CPU time 2.75 seconds
Started Jul 12 06:41:26 PM PDT 24
Finished Jul 12 06:41:32 PM PDT 24
Peak memory 206916 kb
Host smart-846c0ce7-3f90-4a68-93e6-c58a569f9da1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361522968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3361522968
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1670601397
Short name T641
Test name
Test status
Simulation time 54292368 ps
CPU time 2.61 seconds
Started Jul 12 06:41:23 PM PDT 24
Finished Jul 12 06:41:30 PM PDT 24
Peak memory 208048 kb
Host smart-eeb06f07-1810-40e8-bd4e-3e736cbbe919
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670601397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1670601397
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.286454386
Short name T901
Test name
Test status
Simulation time 149191871 ps
CPU time 5.78 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:31 PM PDT 24
Peak memory 206828 kb
Host smart-5d25dc39-a639-491a-9435-28c95e17e49d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286454386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.286454386
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3237305040
Short name T435
Test name
Test status
Simulation time 91907342 ps
CPU time 1.58 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:26 PM PDT 24
Peak memory 207120 kb
Host smart-87c26818-cbcd-4691-a6df-f0ab9b1785dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237305040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3237305040
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2498363812
Short name T551
Test name
Test status
Simulation time 55796447 ps
CPU time 2.53 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:27 PM PDT 24
Peak memory 207008 kb
Host smart-1a276fc9-bb78-4e3d-91f0-c1cf58f4f21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498363812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2498363812
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2817730432
Short name T204
Test name
Test status
Simulation time 109087931552 ps
CPU time 124.93 seconds
Started Jul 12 06:41:24 PM PDT 24
Finished Jul 12 06:43:33 PM PDT 24
Peak memory 216224 kb
Host smart-fd9df3fe-e02d-419a-876b-6d29f42ff93a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817730432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2817730432
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1480009438
Short name T893
Test name
Test status
Simulation time 150208196 ps
CPU time 5.78 seconds
Started Jul 12 06:41:16 PM PDT 24
Finished Jul 12 06:41:25 PM PDT 24
Peak memory 214300 kb
Host smart-430b0ee5-3301-4a29-9ae3-6e993067a3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480009438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1480009438
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3164355175
Short name T152
Test name
Test status
Simulation time 1216620734 ps
CPU time 2.27 seconds
Started Jul 12 06:41:15 PM PDT 24
Finished Jul 12 06:41:20 PM PDT 24
Peak memory 210080 kb
Host smart-a84cc438-5da7-46b1-8454-25a71d78333c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164355175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3164355175
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3644391874
Short name T517
Test name
Test status
Simulation time 10731177 ps
CPU time 0.76 seconds
Started Jul 12 06:41:22 PM PDT 24
Finished Jul 12 06:41:27 PM PDT 24
Peak memory 205964 kb
Host smart-ca95904c-e41b-4ef3-a58c-2d75a5af4ad1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644391874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3644391874
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1120969394
Short name T509
Test name
Test status
Simulation time 108857947 ps
CPU time 4.69 seconds
Started Jul 12 06:41:23 PM PDT 24
Finished Jul 12 06:41:32 PM PDT 24
Peak memory 210012 kb
Host smart-8053972d-8737-4d2b-b09a-293d51398cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120969394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1120969394
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2412069973
Short name T300
Test name
Test status
Simulation time 1326368721 ps
CPU time 13.22 seconds
Started Jul 12 06:41:18 PM PDT 24
Finished Jul 12 06:41:33 PM PDT 24
Peak memory 207600 kb
Host smart-69a4a2e4-a07c-467d-8b26-1aa06ce8d6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412069973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2412069973
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2274105872
Short name T896
Test name
Test status
Simulation time 30920211 ps
CPU time 2.26 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:27 PM PDT 24
Peak memory 214152 kb
Host smart-5440f457-f063-49ea-84a1-2e0200c0723a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274105872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2274105872
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3937366423
Short name T780
Test name
Test status
Simulation time 47083927 ps
CPU time 2.51 seconds
Started Jul 12 06:41:20 PM PDT 24
Finished Jul 12 06:41:25 PM PDT 24
Peak memory 214360 kb
Host smart-d0665568-92b3-45cf-bf0e-d68d5c85941b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937366423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3937366423
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3920835286
Short name T609
Test name
Test status
Simulation time 413530240 ps
CPU time 3.68 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:29 PM PDT 24
Peak memory 214328 kb
Host smart-7355a723-0440-4924-b9f3-9ad7d0416911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920835286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3920835286
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2855535939
Short name T411
Test name
Test status
Simulation time 120671066 ps
CPU time 5.36 seconds
Started Jul 12 06:41:25 PM PDT 24
Finished Jul 12 06:41:33 PM PDT 24
Peak memory 207476 kb
Host smart-88be68bd-f94f-4c39-9d22-17834230c475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855535939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2855535939
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.4194875345
Short name T575
Test name
Test status
Simulation time 406780876 ps
CPU time 5.41 seconds
Started Jul 12 06:41:24 PM PDT 24
Finished Jul 12 06:41:33 PM PDT 24
Peak memory 208600 kb
Host smart-743c8625-ea4a-48c6-ac55-53986e2c3d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194875345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.4194875345
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1600801636
Short name T226
Test name
Test status
Simulation time 20921922 ps
CPU time 1.77 seconds
Started Jul 12 06:41:20 PM PDT 24
Finished Jul 12 06:41:25 PM PDT 24
Peak memory 206956 kb
Host smart-2cf43e9e-e634-4906-bbc6-a55afa466b03
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600801636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1600801636
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1770074234
Short name T753
Test name
Test status
Simulation time 88720021 ps
CPU time 3.7 seconds
Started Jul 12 06:41:24 PM PDT 24
Finished Jul 12 06:41:31 PM PDT 24
Peak memory 206476 kb
Host smart-cb053dfb-15da-4827-b252-0b6f8b924245
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770074234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1770074234
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.858411968
Short name T705
Test name
Test status
Simulation time 32833737 ps
CPU time 2.19 seconds
Started Jul 12 06:41:26 PM PDT 24
Finished Jul 12 06:41:32 PM PDT 24
Peak memory 206812 kb
Host smart-59adb1d6-618f-4296-b025-58ac709fc309
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858411968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.858411968
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.630316883
Short name T276
Test name
Test status
Simulation time 242963389 ps
CPU time 5.13 seconds
Started Jul 12 06:41:25 PM PDT 24
Finished Jul 12 06:41:34 PM PDT 24
Peak memory 214296 kb
Host smart-25948935-d8a7-431d-9cb1-c66d31d73fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630316883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.630316883
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1103792638
Short name T439
Test name
Test status
Simulation time 81560685 ps
CPU time 1.72 seconds
Started Jul 12 06:41:18 PM PDT 24
Finished Jul 12 06:41:22 PM PDT 24
Peak memory 207088 kb
Host smart-31b2a934-fa3b-4581-acfd-ecc447e8e748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103792638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1103792638
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1295441237
Short name T206
Test name
Test status
Simulation time 8605712061 ps
CPU time 75.06 seconds
Started Jul 12 06:41:26 PM PDT 24
Finished Jul 12 06:42:45 PM PDT 24
Peak memory 222536 kb
Host smart-b65b8b86-4089-4839-8bc4-564bf97cb68e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295441237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1295441237
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3147009645
Short name T750
Test name
Test status
Simulation time 190807262 ps
CPU time 4.34 seconds
Started Jul 12 06:41:16 PM PDT 24
Finished Jul 12 06:41:23 PM PDT 24
Peak memory 208928 kb
Host smart-b952af78-c569-4e09-802f-2f32dfb4fb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147009645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3147009645
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.4292828912
Short name T894
Test name
Test status
Simulation time 255274602 ps
CPU time 2.75 seconds
Started Jul 12 06:41:22 PM PDT 24
Finished Jul 12 06:41:28 PM PDT 24
Peak memory 210112 kb
Host smart-9e85e234-6424-425f-991a-1436682d428c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292828912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.4292828912
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2641775580
Short name T815
Test name
Test status
Simulation time 15948555 ps
CPU time 0.77 seconds
Started Jul 12 06:41:25 PM PDT 24
Finished Jul 12 06:41:29 PM PDT 24
Peak memory 205976 kb
Host smart-3ce4a76a-052c-4a33-9825-2e53b24dcc84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641775580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2641775580
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.4286506443
Short name T135
Test name
Test status
Simulation time 49503799 ps
CPU time 3.39 seconds
Started Jul 12 06:41:25 PM PDT 24
Finished Jul 12 06:41:31 PM PDT 24
Peak memory 215648 kb
Host smart-66565e56-cf0d-4e9e-8715-806585faca10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4286506443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.4286506443
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1472660923
Short name T466
Test name
Test status
Simulation time 46574980 ps
CPU time 2.01 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:26 PM PDT 24
Peak memory 210472 kb
Host smart-7128f815-86f7-448c-b021-0fa9f22eaa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472660923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1472660923
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3100205062
Short name T85
Test name
Test status
Simulation time 42489714 ps
CPU time 2.82 seconds
Started Jul 12 06:41:25 PM PDT 24
Finished Jul 12 06:41:31 PM PDT 24
Peak memory 208768 kb
Host smart-5099c7f3-31f5-4da9-ade7-a752985dd883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100205062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3100205062
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1649450677
Short name T788
Test name
Test status
Simulation time 31993975 ps
CPU time 2.31 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:26 PM PDT 24
Peak memory 219492 kb
Host smart-f812b11a-6068-4a30-b052-a0171004d04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649450677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1649450677
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1867140746
Short name T379
Test name
Test status
Simulation time 142818085 ps
CPU time 4.41 seconds
Started Jul 12 06:41:22 PM PDT 24
Finished Jul 12 06:41:30 PM PDT 24
Peak memory 222464 kb
Host smart-b823cd06-c051-4989-8926-11e7b703a995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867140746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1867140746
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1651932156
Short name T352
Test name
Test status
Simulation time 4983593121 ps
CPU time 35.6 seconds
Started Jul 12 06:41:20 PM PDT 24
Finished Jul 12 06:42:04 PM PDT 24
Peak memory 208644 kb
Host smart-d656a82b-b5d4-4c3c-9ec3-c1fbb2cd5f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651932156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1651932156
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.650604772
Short name T716
Test name
Test status
Simulation time 333322428 ps
CPU time 6.36 seconds
Started Jul 12 06:41:26 PM PDT 24
Finished Jul 12 06:41:36 PM PDT 24
Peak memory 208620 kb
Host smart-3adf3389-85cf-4cff-ab91-bb19ef7663d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650604772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.650604772
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2578092658
Short name T370
Test name
Test status
Simulation time 213896999 ps
CPU time 2.64 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:27 PM PDT 24
Peak memory 207452 kb
Host smart-99f127e9-d038-490a-952e-6160c04f3c9c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578092658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2578092658
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1331260561
Short name T816
Test name
Test status
Simulation time 43163121 ps
CPU time 1.77 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:26 PM PDT 24
Peak memory 206868 kb
Host smart-07a3b082-db95-40fc-bce5-8b313f687255
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331260561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1331260561
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.830331108
Short name T691
Test name
Test status
Simulation time 220150992 ps
CPU time 6.06 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:31 PM PDT 24
Peak memory 208112 kb
Host smart-ebbdebe5-6e1b-4146-8365-31dd2b72ec46
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830331108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.830331108
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2131911451
Short name T674
Test name
Test status
Simulation time 208314591 ps
CPU time 2.9 seconds
Started Jul 12 06:41:22 PM PDT 24
Finished Jul 12 06:41:29 PM PDT 24
Peak memory 209056 kb
Host smart-a0d0310c-e19f-4da0-b954-ea350435b21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131911451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2131911451
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3140083873
Short name T188
Test name
Test status
Simulation time 32467982 ps
CPU time 2.15 seconds
Started Jul 12 06:41:22 PM PDT 24
Finished Jul 12 06:41:28 PM PDT 24
Peak memory 206788 kb
Host smart-8b0fa7da-c459-4e55-bc3a-29f3b97164d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140083873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3140083873
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.122178339
Short name T697
Test name
Test status
Simulation time 120835314 ps
CPU time 2.69 seconds
Started Jul 12 06:41:24 PM PDT 24
Finished Jul 12 06:41:31 PM PDT 24
Peak memory 206896 kb
Host smart-3ad2291a-26ae-4879-a753-19c965e94ed3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122178339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.122178339
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3793971409
Short name T324
Test name
Test status
Simulation time 231063536 ps
CPU time 6.74 seconds
Started Jul 12 06:41:27 PM PDT 24
Finished Jul 12 06:41:38 PM PDT 24
Peak memory 219376 kb
Host smart-badf8954-c706-4b2b-81a1-c7908cc3b680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793971409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3793971409
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2416159750
Short name T14
Test name
Test status
Simulation time 216879678 ps
CPU time 2.46 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:26 PM PDT 24
Peak memory 210224 kb
Host smart-41ae87f8-c41f-4cdc-992e-2a036ec7b4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416159750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2416159750
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3539236483
Short name T612
Test name
Test status
Simulation time 10422410 ps
CPU time 0.86 seconds
Started Jul 12 06:41:25 PM PDT 24
Finished Jul 12 06:41:30 PM PDT 24
Peak memory 205984 kb
Host smart-09693ebb-776c-4e7b-9701-97b5b217256c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539236483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3539236483
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.913370087
Short name T364
Test name
Test status
Simulation time 125256077 ps
CPU time 3.99 seconds
Started Jul 12 06:41:32 PM PDT 24
Finished Jul 12 06:41:39 PM PDT 24
Peak memory 215084 kb
Host smart-c46eef03-d097-4c64-b3b2-8362b4c81fc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=913370087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.913370087
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2314306522
Short name T229
Test name
Test status
Simulation time 3877103218 ps
CPU time 21.37 seconds
Started Jul 12 06:41:36 PM PDT 24
Finished Jul 12 06:42:00 PM PDT 24
Peak memory 222860 kb
Host smart-a871d91e-bdec-4086-9905-4588ed7af8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314306522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2314306522
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2805082398
Short name T453
Test name
Test status
Simulation time 1097056320 ps
CPU time 9.39 seconds
Started Jul 12 06:41:22 PM PDT 24
Finished Jul 12 06:41:35 PM PDT 24
Peak memory 208568 kb
Host smart-b416551d-740f-47c7-8f81-d4d110f474a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805082398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2805082398
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2148784891
Short name T24
Test name
Test status
Simulation time 716553720 ps
CPU time 4.88 seconds
Started Jul 12 06:41:27 PM PDT 24
Finished Jul 12 06:41:35 PM PDT 24
Peak memory 208852 kb
Host smart-5f6e9124-c015-4b6a-b5a9-7dae85b42dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148784891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2148784891
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3636252594
Short name T105
Test name
Test status
Simulation time 49380638 ps
CPU time 2.25 seconds
Started Jul 12 06:41:27 PM PDT 24
Finished Jul 12 06:41:32 PM PDT 24
Peak memory 220424 kb
Host smart-459e7a94-21b7-48a8-9b6a-cd396a4c650f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636252594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3636252594
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2132414700
Short name T244
Test name
Test status
Simulation time 59598641 ps
CPU time 2.04 seconds
Started Jul 12 06:41:19 PM PDT 24
Finished Jul 12 06:41:23 PM PDT 24
Peak memory 214492 kb
Host smart-c5c516c7-4ef8-47b9-afa1-5e6cd06acafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132414700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2132414700
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1864933687
Short name T811
Test name
Test status
Simulation time 269395295 ps
CPU time 8.82 seconds
Started Jul 12 06:41:21 PM PDT 24
Finished Jul 12 06:41:34 PM PDT 24
Peak memory 208632 kb
Host smart-b157eaf3-e446-4ed6-b402-8b13101b02af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864933687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1864933687
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1449319118
Short name T334
Test name
Test status
Simulation time 137255956 ps
CPU time 4.18 seconds
Started Jul 12 06:41:32 PM PDT 24
Finished Jul 12 06:41:39 PM PDT 24
Peak memory 208736 kb
Host smart-74b18a7b-acd2-4055-bcef-1f8b6612060e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449319118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1449319118
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3645355796
Short name T326
Test name
Test status
Simulation time 57728982 ps
CPU time 3.22 seconds
Started Jul 12 06:41:20 PM PDT 24
Finished Jul 12 06:41:26 PM PDT 24
Peak memory 208828 kb
Host smart-71649131-08db-48dc-9179-cc2a28ec8adc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645355796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3645355796
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2910653747
Short name T560
Test name
Test status
Simulation time 177751636 ps
CPU time 4.51 seconds
Started Jul 12 06:41:22 PM PDT 24
Finished Jul 12 06:41:30 PM PDT 24
Peak memory 208052 kb
Host smart-9ea4a091-d399-4268-b52a-cab0beaef07f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910653747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2910653747
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1926284613
Short name T190
Test name
Test status
Simulation time 308381358 ps
CPU time 2.33 seconds
Started Jul 12 06:41:20 PM PDT 24
Finished Jul 12 06:41:30 PM PDT 24
Peak memory 206972 kb
Host smart-40b9e3c5-fbaf-49fa-a89d-aede85c2c3fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926284613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1926284613
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3893697367
Short name T757
Test name
Test status
Simulation time 21363450 ps
CPU time 1.62 seconds
Started Jul 12 06:41:28 PM PDT 24
Finished Jul 12 06:41:32 PM PDT 24
Peak memory 207464 kb
Host smart-860bb155-7717-43a3-bc32-cf21d735690d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893697367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3893697367
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3575378738
Short name T496
Test name
Test status
Simulation time 214894468 ps
CPU time 3.27 seconds
Started Jul 12 06:41:23 PM PDT 24
Finished Jul 12 06:41:30 PM PDT 24
Peak memory 208700 kb
Host smart-2ef6a2e7-ca57-48e9-805f-74b4778b7a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575378738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3575378738
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.4208409375
Short name T912
Test name
Test status
Simulation time 3434391455 ps
CPU time 20.91 seconds
Started Jul 12 06:41:28 PM PDT 24
Finished Jul 12 06:41:52 PM PDT 24
Peak memory 215172 kb
Host smart-7e0cd6e9-8f81-4ac0-8516-d93dba49f994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208409375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.4208409375
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.3466798627
Short name T241
Test name
Test status
Simulation time 2243673330 ps
CPU time 20.61 seconds
Started Jul 12 06:41:28 PM PDT 24
Finished Jul 12 06:41:51 PM PDT 24
Peak memory 222592 kb
Host smart-2775842c-282e-4c16-8dd6-11a20ee8f143
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466798627 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.3466798627
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1047853300
Short name T331
Test name
Test status
Simulation time 499073918 ps
CPU time 7.86 seconds
Started Jul 12 06:41:23 PM PDT 24
Finished Jul 12 06:41:35 PM PDT 24
Peak memory 214344 kb
Host smart-b9d77d07-7079-4a50-a168-df80a7a37689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047853300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1047853300
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2712378018
Short name T813
Test name
Test status
Simulation time 110063023 ps
CPU time 1.86 seconds
Started Jul 12 06:41:28 PM PDT 24
Finished Jul 12 06:41:33 PM PDT 24
Peak memory 210684 kb
Host smart-ec8aa002-61aa-4ee2-92cd-25a17f06f552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712378018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2712378018
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1658559987
Short name T649
Test name
Test status
Simulation time 11969217 ps
CPU time 0.92 seconds
Started Jul 12 06:41:42 PM PDT 24
Finished Jul 12 06:41:44 PM PDT 24
Peak memory 205996 kb
Host smart-2fb9b26a-d229-4625-81a1-95c5e747b77b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658559987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1658559987
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2571092385
Short name T368
Test name
Test status
Simulation time 195493164 ps
CPU time 3.51 seconds
Started Jul 12 06:41:31 PM PDT 24
Finished Jul 12 06:41:38 PM PDT 24
Peak memory 222532 kb
Host smart-cd63cf78-0360-47a8-88be-3641cfbde205
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2571092385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2571092385
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3742399139
Short name T626
Test name
Test status
Simulation time 88186036 ps
CPU time 3.95 seconds
Started Jul 12 06:41:36 PM PDT 24
Finished Jul 12 06:41:42 PM PDT 24
Peak memory 209072 kb
Host smart-c60df7bb-0b6c-42a4-bdcf-03ebc33bde4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742399139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3742399139
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3215422703
Short name T588
Test name
Test status
Simulation time 89336167 ps
CPU time 2.16 seconds
Started Jul 12 06:41:28 PM PDT 24
Finished Jul 12 06:41:33 PM PDT 24
Peak memory 207280 kb
Host smart-25bd0069-df1b-40d5-88f4-9e3eaceddf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215422703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3215422703
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.681812600
Short name T214
Test name
Test status
Simulation time 97725399 ps
CPU time 3.23 seconds
Started Jul 12 06:41:27 PM PDT 24
Finished Jul 12 06:41:33 PM PDT 24
Peak memory 214328 kb
Host smart-a8799142-2dd8-4244-914b-cc3c20bbcc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681812600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.681812600
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1086577325
Short name T362
Test name
Test status
Simulation time 140786065 ps
CPU time 6.05 seconds
Started Jul 12 06:41:29 PM PDT 24
Finished Jul 12 06:41:38 PM PDT 24
Peak memory 214224 kb
Host smart-c4438438-362f-490b-83e0-746776d2a927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086577325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1086577325
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2774070517
Short name T847
Test name
Test status
Simulation time 50663712 ps
CPU time 2.84 seconds
Started Jul 12 06:41:27 PM PDT 24
Finished Jul 12 06:41:34 PM PDT 24
Peak memory 220716 kb
Host smart-1fca1c35-2e24-459c-9268-34fe126505eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774070517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2774070517
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2077908659
Short name T409
Test name
Test status
Simulation time 180260969 ps
CPU time 3 seconds
Started Jul 12 06:41:30 PM PDT 24
Finished Jul 12 06:41:36 PM PDT 24
Peak memory 207208 kb
Host smart-ed48f1d7-3b7f-4d06-bb0c-2341a7426750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077908659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2077908659
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.922279296
Short name T660
Test name
Test status
Simulation time 58158478 ps
CPU time 2.72 seconds
Started Jul 12 06:41:36 PM PDT 24
Finished Jul 12 06:41:42 PM PDT 24
Peak memory 208352 kb
Host smart-3df9802d-a7a0-46cc-baf3-5741b168b998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922279296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.922279296
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1644719355
Short name T354
Test name
Test status
Simulation time 228498408 ps
CPU time 3.07 seconds
Started Jul 12 06:41:30 PM PDT 24
Finished Jul 12 06:41:37 PM PDT 24
Peak memory 206924 kb
Host smart-b226cca6-dcff-4e80-b740-aece4fce8552
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644719355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1644719355
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2006818031
Short name T915
Test name
Test status
Simulation time 416529037 ps
CPU time 10.85 seconds
Started Jul 12 06:41:28 PM PDT 24
Finished Jul 12 06:41:43 PM PDT 24
Peak memory 208112 kb
Host smart-fec2204a-8138-473d-88e4-f4c78538c493
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006818031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2006818031
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3170554156
Short name T625
Test name
Test status
Simulation time 628259261 ps
CPU time 3.78 seconds
Started Jul 12 06:41:29 PM PDT 24
Finished Jul 12 06:41:36 PM PDT 24
Peak memory 210012 kb
Host smart-5b72e370-c116-4c91-b9b7-1102fa884f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170554156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3170554156
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1506494411
Short name T849
Test name
Test status
Simulation time 218526625 ps
CPU time 2.42 seconds
Started Jul 12 06:41:36 PM PDT 24
Finished Jul 12 06:41:41 PM PDT 24
Peak memory 206768 kb
Host smart-5e5bca88-af75-4678-ab31-9ba72812cd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506494411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1506494411
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1302770189
Short name T740
Test name
Test status
Simulation time 521033159 ps
CPU time 7.3 seconds
Started Jul 12 06:41:31 PM PDT 24
Finished Jul 12 06:41:42 PM PDT 24
Peak memory 222580 kb
Host smart-792b4dbc-e5e9-4975-821d-eb0b1b2fd727
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302770189 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1302770189
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3085188712
Short name T806
Test name
Test status
Simulation time 1212414195 ps
CPU time 8.98 seconds
Started Jul 12 06:41:26 PM PDT 24
Finished Jul 12 06:41:38 PM PDT 24
Peak memory 218460 kb
Host smart-3b47d615-687e-42c5-ab0c-e9853227f938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085188712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3085188712
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3884483975
Short name T132
Test name
Test status
Simulation time 107365706 ps
CPU time 1.39 seconds
Started Jul 12 06:41:29 PM PDT 24
Finished Jul 12 06:41:33 PM PDT 24
Peak memory 209672 kb
Host smart-6c7dc31c-6699-44d5-a9c7-efe1421eec97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884483975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3884483975
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.4286492017
Short name T724
Test name
Test status
Simulation time 40669946 ps
CPU time 0.9 seconds
Started Jul 12 06:41:40 PM PDT 24
Finished Jul 12 06:41:43 PM PDT 24
Peak memory 205988 kb
Host smart-99d02e9e-4506-47da-a435-adc9057a5d39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286492017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.4286492017
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1850088245
Short name T428
Test name
Test status
Simulation time 701199360 ps
CPU time 18.74 seconds
Started Jul 12 06:41:37 PM PDT 24
Finished Jul 12 06:41:58 PM PDT 24
Peak memory 214340 kb
Host smart-68e7ae6c-a553-4269-bbf4-3c71888bbbf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1850088245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1850088245
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.582976340
Short name T737
Test name
Test status
Simulation time 5477374604 ps
CPU time 18.74 seconds
Started Jul 12 06:41:31 PM PDT 24
Finished Jul 12 06:41:53 PM PDT 24
Peak memory 222088 kb
Host smart-8c593cfd-a2bb-4a7f-9e0d-872936e2125d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582976340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.582976340
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2634613256
Short name T564
Test name
Test status
Simulation time 37115365 ps
CPU time 1.87 seconds
Started Jul 12 06:41:49 PM PDT 24
Finished Jul 12 06:41:53 PM PDT 24
Peak memory 209208 kb
Host smart-ed3fee0c-0698-45ca-a7c5-5fb91755b4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634613256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2634613256
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3771471335
Short name T261
Test name
Test status
Simulation time 210759893 ps
CPU time 4.59 seconds
Started Jul 12 06:41:31 PM PDT 24
Finished Jul 12 06:41:39 PM PDT 24
Peak memory 214268 kb
Host smart-495e8c8b-3d28-4afe-be36-53132ec1145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771471335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3771471335
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.587514368
Short name T818
Test name
Test status
Simulation time 133728661 ps
CPU time 3.41 seconds
Started Jul 12 06:41:36 PM PDT 24
Finished Jul 12 06:41:42 PM PDT 24
Peak memory 222448 kb
Host smart-11dff06e-0a8f-4f42-a436-47ebe0d5a405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587514368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.587514368
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1027497064
Short name T429
Test name
Test status
Simulation time 63314976 ps
CPU time 2.65 seconds
Started Jul 12 06:41:32 PM PDT 24
Finished Jul 12 06:41:38 PM PDT 24
Peak memory 207608 kb
Host smart-952c9337-ddcb-400f-9983-407d4ac127aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027497064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1027497064
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.43675756
Short name T107
Test name
Test status
Simulation time 105129637 ps
CPU time 2.19 seconds
Started Jul 12 06:41:36 PM PDT 24
Finished Jul 12 06:41:40 PM PDT 24
Peak memory 208628 kb
Host smart-53e1ef36-b1e5-4a45-9598-3fcbb03d3289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43675756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.43675756
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.4195349641
Short name T725
Test name
Test status
Simulation time 355420623 ps
CPU time 2.74 seconds
Started Jul 12 06:41:50 PM PDT 24
Finished Jul 12 06:41:55 PM PDT 24
Peak memory 206964 kb
Host smart-4b62ea61-9a01-485a-ac17-957b1c75a456
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195349641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.4195349641
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3497326631
Short name T662
Test name
Test status
Simulation time 4468942720 ps
CPU time 49.46 seconds
Started Jul 12 06:41:33 PM PDT 24
Finished Jul 12 06:42:25 PM PDT 24
Peak memory 209092 kb
Host smart-d7d01c6a-244e-4dbd-a0fa-dd579c9751e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497326631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3497326631
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1289077365
Short name T803
Test name
Test status
Simulation time 533931052 ps
CPU time 5.99 seconds
Started Jul 12 06:41:36 PM PDT 24
Finished Jul 12 06:41:45 PM PDT 24
Peak memory 208036 kb
Host smart-dad74fa0-c3d6-4eda-9934-6ebfb53cfbe6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289077365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1289077365
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1173616011
Short name T350
Test name
Test status
Simulation time 133500873 ps
CPU time 3.53 seconds
Started Jul 12 06:41:36 PM PDT 24
Finished Jul 12 06:41:41 PM PDT 24
Peak memory 214328 kb
Host smart-729fd17e-de2b-45a9-953e-f41fa0905422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173616011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1173616011
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3073857695
Short name T491
Test name
Test status
Simulation time 81448375 ps
CPU time 2.25 seconds
Started Jul 12 06:41:25 PM PDT 24
Finished Jul 12 06:41:31 PM PDT 24
Peak memory 206712 kb
Host smart-89d2d9ff-be6d-415b-98d2-35d3ce0cfb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073857695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3073857695
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.542892482
Short name T613
Test name
Test status
Simulation time 23030564670 ps
CPU time 148.79 seconds
Started Jul 12 06:41:54 PM PDT 24
Finished Jul 12 06:44:25 PM PDT 24
Peak memory 222564 kb
Host smart-e3da017f-3871-4a52-b84e-183461b4331f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542892482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.542892482
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.1322319391
Short name T544
Test name
Test status
Simulation time 1734340185 ps
CPU time 7.95 seconds
Started Jul 12 06:41:58 PM PDT 24
Finished Jul 12 06:42:07 PM PDT 24
Peak memory 222616 kb
Host smart-d836f191-9717-41b6-8c18-62632d8d6f2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322319391 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.1322319391
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3712996607
Short name T471
Test name
Test status
Simulation time 209645376 ps
CPU time 8.22 seconds
Started Jul 12 06:41:47 PM PDT 24
Finished Jul 12 06:41:57 PM PDT 24
Peak memory 214400 kb
Host smart-ef560b80-be41-4c4c-aa72-d810119c1420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712996607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3712996607
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.192065991
Short name T151
Test name
Test status
Simulation time 56213791 ps
CPU time 1.73 seconds
Started Jul 12 06:41:47 PM PDT 24
Finished Jul 12 06:41:50 PM PDT 24
Peak memory 209664 kb
Host smart-eb3cd7c2-7575-402d-8904-d5af46d5c5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192065991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.192065991
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.4248149520
Short name T520
Test name
Test status
Simulation time 24716692 ps
CPU time 0.82 seconds
Started Jul 12 06:41:35 PM PDT 24
Finished Jul 12 06:41:38 PM PDT 24
Peak memory 205984 kb
Host smart-4454007c-c981-4d22-b0dd-ade992a87db1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248149520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.4248149520
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1022651923
Short name T267
Test name
Test status
Simulation time 96289260 ps
CPU time 2.69 seconds
Started Jul 12 06:41:36 PM PDT 24
Finished Jul 12 06:41:40 PM PDT 24
Peak memory 215104 kb
Host smart-89093899-1ce6-43c9-852b-4bb57b0eb24c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1022651923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1022651923
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.680170936
Short name T28
Test name
Test status
Simulation time 222270722 ps
CPU time 4.02 seconds
Started Jul 12 06:41:33 PM PDT 24
Finished Jul 12 06:41:40 PM PDT 24
Peak memory 209356 kb
Host smart-804e7bb1-9807-4148-bda5-faf2b55dcc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680170936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.680170936
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3701498124
Short name T558
Test name
Test status
Simulation time 51639152 ps
CPU time 1.8 seconds
Started Jul 12 06:41:33 PM PDT 24
Finished Jul 12 06:41:38 PM PDT 24
Peak memory 209848 kb
Host smart-f4c457e4-40f4-49b6-bc5a-f83b1f3609f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701498124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3701498124
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2565012117
Short name T397
Test name
Test status
Simulation time 358599945 ps
CPU time 4.86 seconds
Started Jul 12 06:41:33 PM PDT 24
Finished Jul 12 06:41:41 PM PDT 24
Peak memory 214324 kb
Host smart-3aa7bee3-3a3d-4ab9-ad55-0fd71052284d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565012117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2565012117
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2486426057
Short name T357
Test name
Test status
Simulation time 94557845 ps
CPU time 3.32 seconds
Started Jul 12 06:41:47 PM PDT 24
Finished Jul 12 06:41:52 PM PDT 24
Peak memory 222244 kb
Host smart-e017c910-5e9a-42e4-8fb2-8c0375054518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486426057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2486426057
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2832218606
Short name T6
Test name
Test status
Simulation time 42295817 ps
CPU time 1.91 seconds
Started Jul 12 06:41:50 PM PDT 24
Finished Jul 12 06:41:54 PM PDT 24
Peak memory 214808 kb
Host smart-82d7d7ea-2a05-4c5c-bda6-89f81e2700ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832218606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2832218606
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2298803648
Short name T488
Test name
Test status
Simulation time 228705734 ps
CPU time 5.71 seconds
Started Jul 12 06:41:32 PM PDT 24
Finished Jul 12 06:41:41 PM PDT 24
Peak memory 208968 kb
Host smart-bcf42257-7590-4f91-a031-4634671dd927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298803648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2298803648
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3510418190
Short name T826
Test name
Test status
Simulation time 3775935626 ps
CPU time 24.5 seconds
Started Jul 12 06:41:32 PM PDT 24
Finished Jul 12 06:41:59 PM PDT 24
Peak memory 208068 kb
Host smart-2b3695d9-448b-486a-8bbf-fdd5367c2a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510418190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3510418190
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.218612288
Short name T779
Test name
Test status
Simulation time 1229710410 ps
CPU time 4.39 seconds
Started Jul 12 06:41:51 PM PDT 24
Finished Jul 12 06:41:58 PM PDT 24
Peak memory 208764 kb
Host smart-88986632-42a8-4ee1-a91a-ee6ddc67230b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218612288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.218612288
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.773760350
Short name T450
Test name
Test status
Simulation time 184682382 ps
CPU time 2.6 seconds
Started Jul 12 06:41:41 PM PDT 24
Finished Jul 12 06:41:44 PM PDT 24
Peak memory 207192 kb
Host smart-29d776a8-c4e6-4b17-ad68-e218c601aa95
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773760350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.773760350
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3905720323
Short name T608
Test name
Test status
Simulation time 24466505 ps
CPU time 2.02 seconds
Started Jul 12 06:41:36 PM PDT 24
Finished Jul 12 06:41:40 PM PDT 24
Peak memory 208800 kb
Host smart-c91c84c6-e670-4a98-b87d-a1b18a0d07dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905720323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3905720323
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.436811193
Short name T627
Test name
Test status
Simulation time 1747064742 ps
CPU time 10.08 seconds
Started Jul 12 06:41:39 PM PDT 24
Finished Jul 12 06:41:51 PM PDT 24
Peak memory 218368 kb
Host smart-c8077bd4-ad74-4799-bf64-d544408caeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436811193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.436811193
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2560289031
Short name T129
Test name
Test status
Simulation time 235035959 ps
CPU time 2.81 seconds
Started Jul 12 06:41:38 PM PDT 24
Finished Jul 12 06:41:43 PM PDT 24
Peak memory 208456 kb
Host smart-e5f67661-f770-4ecc-9720-08accd5913ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560289031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2560289031
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3359263385
Short name T198
Test name
Test status
Simulation time 917676842 ps
CPU time 20.05 seconds
Started Jul 12 06:41:40 PM PDT 24
Finished Jul 12 06:42:01 PM PDT 24
Peak memory 222484 kb
Host smart-5bc771bf-54c6-4405-b49d-9474e9851c4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359263385 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3359263385
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2239697606
Short name T473
Test name
Test status
Simulation time 90346620 ps
CPU time 4.29 seconds
Started Jul 12 06:41:51 PM PDT 24
Finished Jul 12 06:41:58 PM PDT 24
Peak memory 209552 kb
Host smart-3a070e81-af3b-45af-9fdf-a43ae1987e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239697606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2239697606
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1332558477
Short name T533
Test name
Test status
Simulation time 64241492 ps
CPU time 1.33 seconds
Started Jul 12 06:41:38 PM PDT 24
Finished Jul 12 06:41:41 PM PDT 24
Peak memory 209564 kb
Host smart-d603d70a-d773-4258-93b1-f0d8b9986eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332558477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1332558477
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.253924874
Short name T448
Test name
Test status
Simulation time 41521478 ps
CPU time 0.71 seconds
Started Jul 12 06:41:49 PM PDT 24
Finished Jul 12 06:41:52 PM PDT 24
Peak memory 205940 kb
Host smart-d98f3b14-2439-4bb2-9fe1-d26cab311b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253924874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.253924874
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.4149954884
Short name T327
Test name
Test status
Simulation time 54332571 ps
CPU time 3.92 seconds
Started Jul 12 06:41:52 PM PDT 24
Finished Jul 12 06:41:58 PM PDT 24
Peak memory 214308 kb
Host smart-71c2020c-9f81-4e52-bd58-1d5f11df3727
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4149954884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.4149954884
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.861118481
Short name T21
Test name
Test status
Simulation time 138477093 ps
CPU time 5.52 seconds
Started Jul 12 06:41:39 PM PDT 24
Finished Jul 12 06:41:46 PM PDT 24
Peak memory 221732 kb
Host smart-786bbed3-c0b4-4edd-8df6-340c0b0a3438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861118481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.861118481
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2362180965
Short name T822
Test name
Test status
Simulation time 87015656 ps
CPU time 3.26 seconds
Started Jul 12 06:41:40 PM PDT 24
Finished Jul 12 06:41:44 PM PDT 24
Peak memory 218468 kb
Host smart-5679aff5-9a0a-4ac6-80af-3ae9cf92b637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362180965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2362180965
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.4094094980
Short name T830
Test name
Test status
Simulation time 1062647753 ps
CPU time 21.63 seconds
Started Jul 12 06:41:43 PM PDT 24
Finished Jul 12 06:42:06 PM PDT 24
Peak memory 222468 kb
Host smart-92c32fbc-8424-47ee-bbd0-1d26c698fb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094094980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.4094094980
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.979769347
Short name T534
Test name
Test status
Simulation time 115176249 ps
CPU time 2.32 seconds
Started Jul 12 06:41:48 PM PDT 24
Finished Jul 12 06:41:51 PM PDT 24
Peak memory 221024 kb
Host smart-c9030e12-aff3-4879-a43e-60eb75bf8afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979769347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.979769347
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.777597078
Short name T252
Test name
Test status
Simulation time 989836562 ps
CPU time 4.03 seconds
Started Jul 12 06:41:39 PM PDT 24
Finished Jul 12 06:41:45 PM PDT 24
Peak memory 214316 kb
Host smart-d0a1d12b-4914-465b-a0c6-67b9c6734d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777597078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.777597078
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2444643770
Short name T268
Test name
Test status
Simulation time 3295040496 ps
CPU time 14.21 seconds
Started Jul 12 06:41:37 PM PDT 24
Finished Jul 12 06:41:54 PM PDT 24
Peak memory 209800 kb
Host smart-2ee6aae3-7b33-4993-8f91-14e5c7025f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444643770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2444643770
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2045642719
Short name T223
Test name
Test status
Simulation time 121414690 ps
CPU time 4.7 seconds
Started Jul 12 06:41:36 PM PDT 24
Finished Jul 12 06:41:44 PM PDT 24
Peak memory 208020 kb
Host smart-f7e90ab6-888b-407f-8ded-c5f83f5af4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045642719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2045642719
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.4078253125
Short name T777
Test name
Test status
Simulation time 139089571 ps
CPU time 2.62 seconds
Started Jul 12 06:41:45 PM PDT 24
Finished Jul 12 06:41:49 PM PDT 24
Peak memory 206996 kb
Host smart-f0f12b9d-28a7-4181-a84e-1b744240f798
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078253125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.4078253125
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2627847188
Short name T761
Test name
Test status
Simulation time 31511378 ps
CPU time 2.45 seconds
Started Jul 12 06:41:40 PM PDT 24
Finished Jul 12 06:41:44 PM PDT 24
Peak memory 207520 kb
Host smart-e87c4e28-0388-43ae-934f-0907efbb8efc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627847188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2627847188
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3253113705
Short name T367
Test name
Test status
Simulation time 59626699 ps
CPU time 2.92 seconds
Started Jul 12 06:41:37 PM PDT 24
Finished Jul 12 06:41:43 PM PDT 24
Peak memory 208596 kb
Host smart-39c4cfb3-a14d-4ace-adb4-6348b9bde9a8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253113705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3253113705
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1602731670
Short name T408
Test name
Test status
Simulation time 175335285 ps
CPU time 3.71 seconds
Started Jul 12 06:41:39 PM PDT 24
Finished Jul 12 06:41:44 PM PDT 24
Peak memory 214328 kb
Host smart-b114c301-4747-4166-a5ab-a74caa23d084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602731670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1602731670
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.598179043
Short name T523
Test name
Test status
Simulation time 2425997600 ps
CPU time 20.99 seconds
Started Jul 12 06:41:59 PM PDT 24
Finished Jul 12 06:42:22 PM PDT 24
Peak memory 208348 kb
Host smart-2a9ae4f5-97b8-4e11-a0a6-55ba31d77245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598179043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.598179043
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.285896267
Short name T225
Test name
Test status
Simulation time 2660757314 ps
CPU time 27.41 seconds
Started Jul 12 06:41:57 PM PDT 24
Finished Jul 12 06:42:26 PM PDT 24
Peak memory 222508 kb
Host smart-5b3e5f09-7ed4-4bda-8417-c8aa7e31ec04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285896267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.285896267
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.760631637
Short name T738
Test name
Test status
Simulation time 196887152 ps
CPU time 11 seconds
Started Jul 12 06:41:51 PM PDT 24
Finished Jul 12 06:42:05 PM PDT 24
Peak memory 221012 kb
Host smart-5809d345-7ea5-41d0-8b98-3cde22e2aef0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760631637 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.760631637
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3850980333
Short name T316
Test name
Test status
Simulation time 262017901 ps
CPU time 9.2 seconds
Started Jul 12 06:41:42 PM PDT 24
Finished Jul 12 06:41:52 PM PDT 24
Peak memory 218272 kb
Host smart-e5760cbb-b0ee-4109-bb22-af42178b7c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850980333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3850980333
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2250107445
Short name T895
Test name
Test status
Simulation time 242063371 ps
CPU time 2.54 seconds
Started Jul 12 06:41:42 PM PDT 24
Finished Jul 12 06:41:46 PM PDT 24
Peak memory 210680 kb
Host smart-496cbd47-3053-4fbe-a651-0d72d32deb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250107445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2250107445
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3953252367
Short name T646
Test name
Test status
Simulation time 29799886 ps
CPU time 0.78 seconds
Started Jul 12 06:41:50 PM PDT 24
Finished Jul 12 06:41:54 PM PDT 24
Peak memory 206000 kb
Host smart-11f44014-f68f-4f61-813c-0fdf88570caf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953252367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3953252367
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1820117172
Short name T657
Test name
Test status
Simulation time 87515990 ps
CPU time 3.41 seconds
Started Jul 12 06:41:43 PM PDT 24
Finished Jul 12 06:41:48 PM PDT 24
Peak memory 218416 kb
Host smart-321f6b87-ce5a-402c-a0fc-5bd006e1208c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820117172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1820117172
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3291655945
Short name T800
Test name
Test status
Simulation time 734549868 ps
CPU time 7.82 seconds
Started Jul 12 06:41:45 PM PDT 24
Finished Jul 12 06:41:53 PM PDT 24
Peak memory 215692 kb
Host smart-a69936bd-a2af-4df4-92e6-256dc3fa8ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291655945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3291655945
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2983559374
Short name T359
Test name
Test status
Simulation time 303559531 ps
CPU time 2.98 seconds
Started Jul 12 06:41:47 PM PDT 24
Finished Jul 12 06:41:51 PM PDT 24
Peak memory 222396 kb
Host smart-bec60de2-ec2e-4e03-836d-1b9cc6ee98ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983559374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2983559374
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3709786399
Short name T872
Test name
Test status
Simulation time 39211168 ps
CPU time 2.38 seconds
Started Jul 12 06:41:51 PM PDT 24
Finished Jul 12 06:41:56 PM PDT 24
Peak memory 209884 kb
Host smart-29012417-8ab7-47fc-9a94-3c87f7dc66df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709786399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3709786399
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1640954909
Short name T775
Test name
Test status
Simulation time 5486273906 ps
CPU time 34.69 seconds
Started Jul 12 06:41:53 PM PDT 24
Finished Jul 12 06:42:30 PM PDT 24
Peak memory 209304 kb
Host smart-a9bbf397-4fcf-43a1-80a1-d8f2f045fe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640954909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1640954909
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2706785247
Short name T758
Test name
Test status
Simulation time 30087268 ps
CPU time 2.38 seconds
Started Jul 12 06:41:45 PM PDT 24
Finished Jul 12 06:41:49 PM PDT 24
Peak memory 208760 kb
Host smart-f56ad8f9-e566-40f5-a318-73d1d72a2d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706785247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2706785247
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1761310334
Short name T722
Test name
Test status
Simulation time 52934939 ps
CPU time 2.89 seconds
Started Jul 12 06:41:42 PM PDT 24
Finished Jul 12 06:41:46 PM PDT 24
Peak memory 207064 kb
Host smart-6412a80b-007b-42fd-8131-966e19159964
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761310334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1761310334
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.4279712595
Short name T639
Test name
Test status
Simulation time 117571859 ps
CPU time 3.92 seconds
Started Jul 12 06:41:42 PM PDT 24
Finished Jul 12 06:41:47 PM PDT 24
Peak memory 208756 kb
Host smart-b23cfed7-956f-4e7b-a9de-3d65f70b18f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279712595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.4279712595
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1635980045
Short name T77
Test name
Test status
Simulation time 105024801 ps
CPU time 4.42 seconds
Started Jul 12 06:41:50 PM PDT 24
Finished Jul 12 06:41:57 PM PDT 24
Peak memory 206928 kb
Host smart-9675b28d-b9f6-443c-bf94-852a942fe50b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635980045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1635980045
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1417466754
Short name T592
Test name
Test status
Simulation time 102346291 ps
CPU time 3.11 seconds
Started Jul 12 06:41:52 PM PDT 24
Finished Jul 12 06:41:58 PM PDT 24
Peak memory 207748 kb
Host smart-25aa2802-d32e-49fa-a3c1-4c0f07840042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417466754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1417466754
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.6901455
Short name T436
Test name
Test status
Simulation time 142611061 ps
CPU time 2.52 seconds
Started Jul 12 06:41:37 PM PDT 24
Finished Jul 12 06:41:42 PM PDT 24
Peak memory 208532 kb
Host smart-440c07b0-d15c-49af-b6af-d190776bf7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6901455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.6901455
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1824845113
Short name T372
Test name
Test status
Simulation time 394795264 ps
CPU time 8.25 seconds
Started Jul 12 06:41:52 PM PDT 24
Finished Jul 12 06:42:02 PM PDT 24
Peak memory 222672 kb
Host smart-cdd275a2-f6a2-4595-a7d6-308715bfcad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824845113 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1824845113
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2185892657
Short name T513
Test name
Test status
Simulation time 189883067 ps
CPU time 3.37 seconds
Started Jul 12 06:41:43 PM PDT 24
Finished Jul 12 06:41:48 PM PDT 24
Peak memory 207984 kb
Host smart-bc717a5e-a546-416a-9e27-b77c4344840e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185892657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2185892657
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.653192681
Short name T801
Test name
Test status
Simulation time 298749539 ps
CPU time 3.25 seconds
Started Jul 12 06:41:46 PM PDT 24
Finished Jul 12 06:41:51 PM PDT 24
Peak memory 210940 kb
Host smart-ab254f7b-f626-43c5-ab7b-291a3bf9812f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653192681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.653192681
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1153075102
Short name T752
Test name
Test status
Simulation time 44357179 ps
CPU time 0.85 seconds
Started Jul 12 06:41:52 PM PDT 24
Finished Jul 12 06:41:55 PM PDT 24
Peak memory 206004 kb
Host smart-039209c7-7953-4965-9764-526106b9d318
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153075102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1153075102
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3160211109
Short name T812
Test name
Test status
Simulation time 155354130 ps
CPU time 3.48 seconds
Started Jul 12 06:41:39 PM PDT 24
Finished Jul 12 06:41:44 PM PDT 24
Peak memory 215328 kb
Host smart-018dd7e9-f980-48be-9297-5cae26a3f671
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3160211109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3160211109
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1172901903
Short name T31
Test name
Test status
Simulation time 187912381 ps
CPU time 3.44 seconds
Started Jul 12 06:41:50 PM PDT 24
Finished Jul 12 06:42:00 PM PDT 24
Peak memory 206384 kb
Host smart-7c09c89b-e8ba-4285-a4ec-eb03ecb94c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172901903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1172901903
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.4232709113
Short name T392
Test name
Test status
Simulation time 100642436 ps
CPU time 3.65 seconds
Started Jul 12 06:41:51 PM PDT 24
Finished Jul 12 06:41:57 PM PDT 24
Peak memory 209908 kb
Host smart-82164a34-7b6c-487c-af86-29b17cbbcbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232709113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.4232709113
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3740266473
Short name T262
Test name
Test status
Simulation time 49905035 ps
CPU time 3.61 seconds
Started Jul 12 06:41:49 PM PDT 24
Finished Jul 12 06:41:54 PM PDT 24
Peak memory 222380 kb
Host smart-fbaaeff4-0cd7-432a-b922-6ea03fc2b56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740266473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3740266473
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2335428868
Short name T413
Test name
Test status
Simulation time 47203675 ps
CPU time 2.58 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:21 PM PDT 24
Peak memory 222484 kb
Host smart-f1bf8cf3-aa70-4268-baea-267050f9acb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335428868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2335428868
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1871283058
Short name T449
Test name
Test status
Simulation time 1316863772 ps
CPU time 7.91 seconds
Started Jul 12 06:42:03 PM PDT 24
Finished Jul 12 06:42:13 PM PDT 24
Peak memory 208492 kb
Host smart-16f21428-422e-4460-966f-e20b4d7b93e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871283058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1871283058
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3794009466
Short name T526
Test name
Test status
Simulation time 82280471 ps
CPU time 3.53 seconds
Started Jul 12 06:41:48 PM PDT 24
Finished Jul 12 06:41:52 PM PDT 24
Peak memory 208752 kb
Host smart-589e12c5-2e7d-423a-b5ca-0eef955ae89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794009466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3794009466
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.734688262
Short name T868
Test name
Test status
Simulation time 395102019 ps
CPU time 3.1 seconds
Started Jul 12 06:41:37 PM PDT 24
Finished Jul 12 06:41:43 PM PDT 24
Peak memory 208992 kb
Host smart-d826dbb7-e6e8-4aff-8778-6cb14a91d98d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734688262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.734688262
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2539046708
Short name T227
Test name
Test status
Simulation time 38962401 ps
CPU time 2.46 seconds
Started Jul 12 06:41:45 PM PDT 24
Finished Jul 12 06:41:49 PM PDT 24
Peak memory 207076 kb
Host smart-d37e8ad3-711f-4cda-bd20-4089447b33f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539046708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2539046708
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2335079819
Short name T821
Test name
Test status
Simulation time 367557847 ps
CPU time 10.8 seconds
Started Jul 12 06:41:42 PM PDT 24
Finished Jul 12 06:41:55 PM PDT 24
Peak memory 208112 kb
Host smart-ae13b54c-a740-4bd8-8bf6-6ea140045497
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335079819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2335079819
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.3505439496
Short name T289
Test name
Test status
Simulation time 64264573 ps
CPU time 2.44 seconds
Started Jul 12 06:41:47 PM PDT 24
Finished Jul 12 06:41:50 PM PDT 24
Peak memory 214360 kb
Host smart-b495d248-2c47-47db-8c8f-c2c3ee3c184e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505439496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3505439496
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.612700999
Short name T632
Test name
Test status
Simulation time 367099105 ps
CPU time 3.95 seconds
Started Jul 12 06:41:50 PM PDT 24
Finished Jul 12 06:41:57 PM PDT 24
Peak memory 206920 kb
Host smart-fa17008d-58c0-40c2-90b8-a268720e4ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612700999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.612700999
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3650176742
Short name T790
Test name
Test status
Simulation time 981089762 ps
CPU time 39.95 seconds
Started Jul 12 06:41:44 PM PDT 24
Finished Jul 12 06:42:25 PM PDT 24
Peak memory 222496 kb
Host smart-57fdec13-3e75-43ed-a2e0-454367d31abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650176742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3650176742
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3531447566
Short name T176
Test name
Test status
Simulation time 3355069561 ps
CPU time 27.8 seconds
Started Jul 12 06:41:48 PM PDT 24
Finished Jul 12 06:42:17 PM PDT 24
Peak memory 222588 kb
Host smart-c6b3572a-3fab-4ab7-8cc1-323cf4e658bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531447566 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3531447566
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1263476097
Short name T580
Test name
Test status
Simulation time 945068390 ps
CPU time 11.33 seconds
Started Jul 12 06:42:08 PM PDT 24
Finished Jul 12 06:42:21 PM PDT 24
Peak memory 214272 kb
Host smart-4b3954a4-aeea-4e24-aab0-893b2c756b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263476097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1263476097
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2951648521
Short name T729
Test name
Test status
Simulation time 867854360 ps
CPU time 4.33 seconds
Started Jul 12 06:41:55 PM PDT 24
Finished Jul 12 06:42:01 PM PDT 24
Peak memory 210300 kb
Host smart-488c4b77-4523-4b1f-b56a-e1da85121e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951648521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2951648521
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.321541272
Short name T787
Test name
Test status
Simulation time 24459714 ps
CPU time 0.74 seconds
Started Jul 12 06:40:02 PM PDT 24
Finished Jul 12 06:40:05 PM PDT 24
Peak memory 205936 kb
Host smart-8b7e6ffb-7c41-4787-924d-01a03b14781d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321541272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.321541272
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2984021062
Short name T211
Test name
Test status
Simulation time 263595536 ps
CPU time 12.82 seconds
Started Jul 12 06:40:00 PM PDT 24
Finished Jul 12 06:40:15 PM PDT 24
Peak memory 215416 kb
Host smart-82df055a-0cb8-4934-ab60-3c9752921631
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2984021062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2984021062
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.317397022
Short name T492
Test name
Test status
Simulation time 798892177 ps
CPU time 2.85 seconds
Started Jul 12 06:40:01 PM PDT 24
Finished Jul 12 06:40:06 PM PDT 24
Peak memory 207532 kb
Host smart-3d27596f-5415-42cf-ada9-06229148a616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317397022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.317397022
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2631461551
Short name T382
Test name
Test status
Simulation time 1069369111 ps
CPU time 7.56 seconds
Started Jul 12 06:40:03 PM PDT 24
Finished Jul 12 06:40:13 PM PDT 24
Peak memory 222456 kb
Host smart-7e3544fc-b764-435b-a403-8c24ae37dd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631461551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2631461551
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1681527663
Short name T878
Test name
Test status
Simulation time 398084867 ps
CPU time 4.78 seconds
Started Jul 12 06:40:04 PM PDT 24
Finished Jul 12 06:40:11 PM PDT 24
Peak memory 214300 kb
Host smart-a5dc3ce7-d3a4-4563-921e-2948bdc0ec1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681527663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1681527663
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.4000970968
Short name T420
Test name
Test status
Simulation time 83171337 ps
CPU time 4.33 seconds
Started Jul 12 06:39:58 PM PDT 24
Finished Jul 12 06:40:03 PM PDT 24
Peak memory 218748 kb
Host smart-44177de3-0eb6-4744-b070-bc6bc632e3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000970968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.4000970968
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3510610371
Short name T615
Test name
Test status
Simulation time 1284915366 ps
CPU time 28.61 seconds
Started Jul 12 06:40:01 PM PDT 24
Finished Jul 12 06:40:32 PM PDT 24
Peak memory 214276 kb
Host smart-9f8c0ba9-1fa4-48a0-941e-51e63168c4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510610371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3510610371
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.440286590
Short name T42
Test name
Test status
Simulation time 431035973 ps
CPU time 9.88 seconds
Started Jul 12 06:40:01 PM PDT 24
Finished Jul 12 06:40:13 PM PDT 24
Peak memory 237420 kb
Host smart-5e9f0622-4df7-400b-98f7-e3a837ebfe4a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440286590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.440286590
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2502718067
Short name T388
Test name
Test status
Simulation time 441004199 ps
CPU time 2.64 seconds
Started Jul 12 06:39:58 PM PDT 24
Finished Jul 12 06:40:03 PM PDT 24
Peak memory 207048 kb
Host smart-82e4f6ee-b800-4b6d-9fa8-d3d1436f5557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502718067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2502718067
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2094357208
Short name T591
Test name
Test status
Simulation time 201696172 ps
CPU time 2.64 seconds
Started Jul 12 06:39:59 PM PDT 24
Finished Jul 12 06:40:03 PM PDT 24
Peak memory 206980 kb
Host smart-e45ba082-182b-4ce9-8ca5-e3ef39716081
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094357208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2094357208
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.4049988659
Short name T659
Test name
Test status
Simulation time 222831858 ps
CPU time 7.75 seconds
Started Jul 12 06:40:01 PM PDT 24
Finished Jul 12 06:40:11 PM PDT 24
Peak memory 208788 kb
Host smart-28a21c51-accb-4fc7-a4be-328cffd98673
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049988659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4049988659
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2623242076
Short name T193
Test name
Test status
Simulation time 595483148 ps
CPU time 7.69 seconds
Started Jul 12 06:39:59 PM PDT 24
Finished Jul 12 06:40:09 PM PDT 24
Peak memory 208524 kb
Host smart-2b73fcd9-6320-4a88-b9ce-b4aa03b893c3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623242076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2623242076
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1788059508
Short name T685
Test name
Test status
Simulation time 324897813 ps
CPU time 3.61 seconds
Started Jul 12 06:40:00 PM PDT 24
Finished Jul 12 06:40:06 PM PDT 24
Peak memory 206664 kb
Host smart-26899649-ca66-405c-b7ff-9f376b590deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788059508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1788059508
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.537685453
Short name T692
Test name
Test status
Simulation time 2434683498 ps
CPU time 18.74 seconds
Started Jul 12 06:40:00 PM PDT 24
Finished Jul 12 06:40:21 PM PDT 24
Peak memory 216372 kb
Host smart-1e44414d-327a-4d90-9f07-1c2d8218ae8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537685453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.537685453
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3295603416
Short name T583
Test name
Test status
Simulation time 103271900 ps
CPU time 5.18 seconds
Started Jul 12 06:40:01 PM PDT 24
Finished Jul 12 06:40:08 PM PDT 24
Peak memory 218464 kb
Host smart-7091aa6b-4001-428a-b49d-2f85da6c0815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295603416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3295603416
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3968193077
Short name T401
Test name
Test status
Simulation time 205596639 ps
CPU time 2.82 seconds
Started Jul 12 06:39:59 PM PDT 24
Finished Jul 12 06:40:04 PM PDT 24
Peak memory 210288 kb
Host smart-956432d1-8783-4537-8789-29ceaa843f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968193077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3968193077
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1039106362
Short name T918
Test name
Test status
Simulation time 16887413 ps
CPU time 0.81 seconds
Started Jul 12 06:41:45 PM PDT 24
Finished Jul 12 06:41:47 PM PDT 24
Peak memory 205956 kb
Host smart-274b8fb6-3482-47ce-b784-021886c8e394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039106362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1039106362
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2524650502
Short name T406
Test name
Test status
Simulation time 128417039 ps
CPU time 5.63 seconds
Started Jul 12 06:41:49 PM PDT 24
Finished Jul 12 06:41:57 PM PDT 24
Peak memory 214684 kb
Host smart-c7f06c17-2700-413e-8cd2-b60f431f551c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2524650502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2524650502
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3970361798
Short name T891
Test name
Test status
Simulation time 166746566 ps
CPU time 2.91 seconds
Started Jul 12 06:41:45 PM PDT 24
Finished Jul 12 06:41:49 PM PDT 24
Peak memory 222844 kb
Host smart-6e44bf66-5f02-4163-9c53-fc748b3c5f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970361798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3970361798
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3045617290
Short name T279
Test name
Test status
Simulation time 435677144 ps
CPU time 6.65 seconds
Started Jul 12 06:41:52 PM PDT 24
Finished Jul 12 06:42:02 PM PDT 24
Peak memory 222420 kb
Host smart-ba4f96e9-60a9-44eb-8467-c66588ecd11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045617290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3045617290
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2514899834
Short name T393
Test name
Test status
Simulation time 117376418 ps
CPU time 2.42 seconds
Started Jul 12 06:41:48 PM PDT 24
Finished Jul 12 06:41:52 PM PDT 24
Peak memory 214288 kb
Host smart-b5d1f69a-d23a-4675-b728-e3b2c7560352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514899834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2514899834
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2377728162
Short name T302
Test name
Test status
Simulation time 137176966 ps
CPU time 2.62 seconds
Started Jul 12 06:41:45 PM PDT 24
Finished Jul 12 06:41:49 PM PDT 24
Peak memory 206072 kb
Host smart-a0cb6683-2bfb-41c0-873f-2522a725df94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377728162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2377728162
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.38577297
Short name T235
Test name
Test status
Simulation time 258426436 ps
CPU time 3.67 seconds
Started Jul 12 06:41:50 PM PDT 24
Finished Jul 12 06:41:56 PM PDT 24
Peak memory 222472 kb
Host smart-c14efed7-690d-46e6-8074-9016b5e5f4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38577297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.38577297
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.661358925
Short name T848
Test name
Test status
Simulation time 782178850 ps
CPU time 6.94 seconds
Started Jul 12 06:41:46 PM PDT 24
Finished Jul 12 06:41:54 PM PDT 24
Peak memory 214308 kb
Host smart-63be9416-7df0-43de-9635-f12624708239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661358925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.661358925
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1436304636
Short name T514
Test name
Test status
Simulation time 143463317 ps
CPU time 2.55 seconds
Started Jul 12 06:41:57 PM PDT 24
Finished Jul 12 06:42:01 PM PDT 24
Peak memory 206724 kb
Host smart-205d0582-d2c0-44e0-b6ff-bd6a284613a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436304636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1436304636
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1395765446
Short name T432
Test name
Test status
Simulation time 47239221 ps
CPU time 2.75 seconds
Started Jul 12 06:41:43 PM PDT 24
Finished Jul 12 06:41:48 PM PDT 24
Peak memory 206848 kb
Host smart-9532e279-e0c5-4207-909d-fa0fac33f02e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395765446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1395765446
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1720732859
Short name T877
Test name
Test status
Simulation time 102976128 ps
CPU time 4.49 seconds
Started Jul 12 06:41:42 PM PDT 24
Finished Jul 12 06:41:48 PM PDT 24
Peak memory 208668 kb
Host smart-ebcfe29e-f850-4e3a-bad1-0af80c8868f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720732859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1720732859
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2304493105
Short name T914
Test name
Test status
Simulation time 213978013 ps
CPU time 2.96 seconds
Started Jul 12 06:41:46 PM PDT 24
Finished Jul 12 06:41:50 PM PDT 24
Peak memory 206976 kb
Host smart-dddc533d-2e74-4e26-af57-13fb5de49f04
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304493105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2304493105
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.317067016
Short name T766
Test name
Test status
Simulation time 142781656 ps
CPU time 4.87 seconds
Started Jul 12 06:41:49 PM PDT 24
Finished Jul 12 06:41:56 PM PDT 24
Peak memory 214320 kb
Host smart-ae085644-c9c1-494f-9a15-49948f28c63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317067016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.317067016
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.867551697
Short name T798
Test name
Test status
Simulation time 133128309 ps
CPU time 3.39 seconds
Started Jul 12 06:41:54 PM PDT 24
Finished Jul 12 06:42:00 PM PDT 24
Peak memory 206864 kb
Host smart-f974b9f0-0df5-47d4-98b2-1f6f621d2000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867551697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.867551697
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.4053840623
Short name T123
Test name
Test status
Simulation time 312956812 ps
CPU time 18.43 seconds
Started Jul 12 06:41:48 PM PDT 24
Finished Jul 12 06:42:07 PM PDT 24
Peak memory 219624 kb
Host smart-863520e5-0069-43bc-a9c1-23adac31efbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053840623 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.4053840623
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3385965375
Short name T552
Test name
Test status
Simulation time 1254516336 ps
CPU time 36.78 seconds
Started Jul 12 06:41:49 PM PDT 24
Finished Jul 12 06:42:28 PM PDT 24
Peak memory 209268 kb
Host smart-12631b9e-0565-4d1c-a3a7-51e58cf62fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385965375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3385965375
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1625702851
Short name T655
Test name
Test status
Simulation time 65951805 ps
CPU time 1.99 seconds
Started Jul 12 06:41:47 PM PDT 24
Finished Jul 12 06:41:51 PM PDT 24
Peak memory 210180 kb
Host smart-cb6eeede-a437-4259-9485-fcb1fa277891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625702851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1625702851
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2158272582
Short name T726
Test name
Test status
Simulation time 17146310 ps
CPU time 0.78 seconds
Started Jul 12 06:41:52 PM PDT 24
Finished Jul 12 06:41:55 PM PDT 24
Peak memory 205976 kb
Host smart-ae6085ac-9b6b-44a3-a137-7b64ac70aafe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158272582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2158272582
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2809467808
Short name T427
Test name
Test status
Simulation time 65783369 ps
CPU time 3.02 seconds
Started Jul 12 06:41:49 PM PDT 24
Finished Jul 12 06:41:53 PM PDT 24
Peak memory 214368 kb
Host smart-e6784bf6-e498-4fb6-abb6-d311335285dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809467808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2809467808
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3891007239
Short name T751
Test name
Test status
Simulation time 153687386 ps
CPU time 1.59 seconds
Started Jul 12 06:41:50 PM PDT 24
Finished Jul 12 06:41:54 PM PDT 24
Peak memory 222852 kb
Host smart-29daa7be-b8d3-473b-894b-f277bdf68b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891007239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3891007239
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3514801469
Short name T619
Test name
Test status
Simulation time 142552793 ps
CPU time 1.7 seconds
Started Jul 12 06:42:06 PM PDT 24
Finished Jul 12 06:42:09 PM PDT 24
Peak memory 214348 kb
Host smart-90bf8412-8882-460f-a774-3575ef128c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514801469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3514801469
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2077812146
Short name T361
Test name
Test status
Simulation time 30093845 ps
CPU time 1.95 seconds
Started Jul 12 06:41:51 PM PDT 24
Finished Jul 12 06:41:55 PM PDT 24
Peak memory 214288 kb
Host smart-ba1c73da-0855-4422-ab45-ac95e244996c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077812146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2077812146
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3127041045
Short name T249
Test name
Test status
Simulation time 1939462872 ps
CPU time 26.81 seconds
Started Jul 12 06:41:49 PM PDT 24
Finished Jul 12 06:42:18 PM PDT 24
Peak memory 220300 kb
Host smart-a8bd70a4-acc8-4c63-9199-52c985137e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127041045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3127041045
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1676652112
Short name T746
Test name
Test status
Simulation time 1186521826 ps
CPU time 14.18 seconds
Started Jul 12 06:41:49 PM PDT 24
Finished Jul 12 06:42:06 PM PDT 24
Peak memory 208884 kb
Host smart-d1ddb363-f3b4-44aa-9bed-0e55792dda5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676652112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1676652112
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1591948534
Short name T353
Test name
Test status
Simulation time 144257267 ps
CPU time 2.39 seconds
Started Jul 12 06:41:52 PM PDT 24
Finished Jul 12 06:41:57 PM PDT 24
Peak memory 206728 kb
Host smart-1f6e0c93-ceb1-4636-9a69-6cdcba4de637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591948534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1591948534
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1652988076
Short name T109
Test name
Test status
Simulation time 77341701 ps
CPU time 3.19 seconds
Started Jul 12 06:41:49 PM PDT 24
Finished Jul 12 06:41:55 PM PDT 24
Peak memory 208564 kb
Host smart-ec1158a6-e746-4953-b997-0a2cd3d59f1a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652988076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1652988076
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3609541628
Short name T701
Test name
Test status
Simulation time 53668825 ps
CPU time 2.79 seconds
Started Jul 12 06:41:50 PM PDT 24
Finished Jul 12 06:41:55 PM PDT 24
Peak memory 208228 kb
Host smart-18dbd6cb-0019-492d-9793-9beaea98d6f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609541628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3609541628
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2064322355
Short name T510
Test name
Test status
Simulation time 1075388643 ps
CPU time 20.11 seconds
Started Jul 12 06:41:57 PM PDT 24
Finished Jul 12 06:42:19 PM PDT 24
Peak memory 208276 kb
Host smart-6f32810a-f105-42e5-a233-ed3403318bcb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064322355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2064322355
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.430869406
Short name T461
Test name
Test status
Simulation time 76566137 ps
CPU time 2.14 seconds
Started Jul 12 06:41:55 PM PDT 24
Finished Jul 12 06:41:59 PM PDT 24
Peak memory 209308 kb
Host smart-179d8b48-c904-45db-baef-b0c56c70ebdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430869406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.430869406
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.477415007
Short name T516
Test name
Test status
Simulation time 1010965655 ps
CPU time 5.3 seconds
Started Jul 12 06:41:49 PM PDT 24
Finished Jul 12 06:41:57 PM PDT 24
Peak memory 208392 kb
Host smart-f0f79315-038a-464a-9a2d-81fa9e3e3868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477415007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.477415007
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2588109450
Short name T258
Test name
Test status
Simulation time 229378278 ps
CPU time 9.9 seconds
Started Jul 12 06:41:59 PM PDT 24
Finished Jul 12 06:42:11 PM PDT 24
Peak memory 215272 kb
Host smart-752035a0-590d-4fdb-aac1-eda957b0e41a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588109450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2588109450
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.567339421
Short name T49
Test name
Test status
Simulation time 2249683810 ps
CPU time 20.46 seconds
Started Jul 12 06:42:07 PM PDT 24
Finished Jul 12 06:42:29 PM PDT 24
Peak memory 222668 kb
Host smart-a31f4bd1-c0b2-4c7d-99b5-79d95df2e0a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567339421 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.567339421
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.4152190847
Short name T677
Test name
Test status
Simulation time 241736790 ps
CPU time 5.4 seconds
Started Jul 12 06:41:46 PM PDT 24
Finished Jul 12 06:41:53 PM PDT 24
Peak memory 214292 kb
Host smart-a4f07380-23f0-4444-9fc0-7ffcc7cb0254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152190847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.4152190847
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2745296531
Short name T168
Test name
Test status
Simulation time 164974693 ps
CPU time 2.61 seconds
Started Jul 12 06:41:56 PM PDT 24
Finished Jul 12 06:42:00 PM PDT 24
Peak memory 210948 kb
Host smart-ca901307-4998-40f5-ba07-1af0bb3e77d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745296531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2745296531
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1576670814
Short name T727
Test name
Test status
Simulation time 26145308 ps
CPU time 0.85 seconds
Started Jul 12 06:41:58 PM PDT 24
Finished Jul 12 06:42:01 PM PDT 24
Peak memory 205984 kb
Host smart-ab4f9109-f37a-49df-820f-21a8f86fbcbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576670814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1576670814
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2945632443
Short name T431
Test name
Test status
Simulation time 39805020 ps
CPU time 3.16 seconds
Started Jul 12 06:41:57 PM PDT 24
Finished Jul 12 06:42:01 PM PDT 24
Peak memory 214340 kb
Host smart-652efbcf-71cd-426f-90e8-5a90f6f62688
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2945632443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2945632443
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2381807682
Short name T20
Test name
Test status
Simulation time 49741027 ps
CPU time 2.74 seconds
Started Jul 12 06:41:59 PM PDT 24
Finished Jul 12 06:42:04 PM PDT 24
Peak memory 214696 kb
Host smart-8057f49f-2543-4766-a616-db1a2f1c7c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381807682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2381807682
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3510252844
Short name T477
Test name
Test status
Simulation time 594406413 ps
CPU time 3.06 seconds
Started Jul 12 06:41:48 PM PDT 24
Finished Jul 12 06:41:53 PM PDT 24
Peak memory 207592 kb
Host smart-6b5065c3-5ef2-4486-8cfd-38a78b05f05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510252844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3510252844
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.4156949235
Short name T321
Test name
Test status
Simulation time 56987780 ps
CPU time 2.12 seconds
Started Jul 12 06:42:03 PM PDT 24
Finished Jul 12 06:42:08 PM PDT 24
Peak memory 214432 kb
Host smart-55885522-368a-44e0-b4cd-7d951f03aa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156949235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.4156949235
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2046044488
Short name T831
Test name
Test status
Simulation time 449100679 ps
CPU time 3.69 seconds
Started Jul 12 06:41:54 PM PDT 24
Finished Jul 12 06:42:00 PM PDT 24
Peak memory 209640 kb
Host smart-33f2f5e4-685b-4244-82d2-450d720dc82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046044488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2046044488
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2476127897
Short name T576
Test name
Test status
Simulation time 1235029300 ps
CPU time 6.93 seconds
Started Jul 12 06:41:51 PM PDT 24
Finished Jul 12 06:42:00 PM PDT 24
Peak memory 209256 kb
Host smart-2d620926-0f0f-4031-892e-4bbe8643f422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476127897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2476127897
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.4027135896
Short name T784
Test name
Test status
Simulation time 179473288 ps
CPU time 2.5 seconds
Started Jul 12 06:42:06 PM PDT 24
Finished Jul 12 06:42:10 PM PDT 24
Peak memory 208240 kb
Host smart-dbb1d79b-96a0-49c5-998f-76de733dd656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027135896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.4027135896
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3440450859
Short name T765
Test name
Test status
Simulation time 94180649 ps
CPU time 1.92 seconds
Started Jul 12 06:41:51 PM PDT 24
Finished Jul 12 06:41:56 PM PDT 24
Peak memory 207500 kb
Host smart-dd46e917-a463-460a-b3c7-d205df44d711
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440450859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3440450859
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.210938306
Short name T723
Test name
Test status
Simulation time 281772644 ps
CPU time 1.91 seconds
Started Jul 12 06:41:49 PM PDT 24
Finished Jul 12 06:41:53 PM PDT 24
Peak memory 206952 kb
Host smart-7d3c7048-721c-45c0-ab18-a12072b498cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210938306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.210938306
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.352437805
Short name T499
Test name
Test status
Simulation time 1854510341 ps
CPU time 25.16 seconds
Started Jul 12 06:41:58 PM PDT 24
Finished Jul 12 06:42:25 PM PDT 24
Peak memory 208488 kb
Host smart-b262055e-9a9b-4f48-886e-f66126c1e9ba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352437805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.352437805
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.745694590
Short name T308
Test name
Test status
Simulation time 115578733 ps
CPU time 3.09 seconds
Started Jul 12 06:41:59 PM PDT 24
Finished Jul 12 06:42:04 PM PDT 24
Peak memory 210260 kb
Host smart-170488ba-b55e-4d4c-9572-6b42153839e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745694590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.745694590
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1962024961
Short name T771
Test name
Test status
Simulation time 1276448787 ps
CPU time 6.89 seconds
Started Jul 12 06:42:03 PM PDT 24
Finished Jul 12 06:42:12 PM PDT 24
Peak memory 206828 kb
Host smart-e0335eda-265f-4dd6-bbf1-2e603ca34e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962024961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1962024961
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1385694625
Short name T666
Test name
Test status
Simulation time 233299052 ps
CPU time 6.24 seconds
Started Jul 12 06:41:53 PM PDT 24
Finished Jul 12 06:42:02 PM PDT 24
Peak memory 211072 kb
Host smart-8a3dc7f6-ba60-41e2-ac05-4d00bb900750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385694625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1385694625
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1932629310
Short name T36
Test name
Test status
Simulation time 40426487 ps
CPU time 1.97 seconds
Started Jul 12 06:41:58 PM PDT 24
Finished Jul 12 06:42:02 PM PDT 24
Peak memory 209652 kb
Host smart-78d595e8-82a8-466b-9e4f-754b8de4b858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932629310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1932629310
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.4182565558
Short name T489
Test name
Test status
Simulation time 67671774 ps
CPU time 0.72 seconds
Started Jul 12 06:42:01 PM PDT 24
Finished Jul 12 06:42:04 PM PDT 24
Peak memory 206008 kb
Host smart-87885ec5-8599-4de9-9a8e-ee85e16619c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182565558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.4182565558
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1673024416
Short name T136
Test name
Test status
Simulation time 50999382 ps
CPU time 3.3 seconds
Started Jul 12 06:42:07 PM PDT 24
Finished Jul 12 06:42:12 PM PDT 24
Peak memory 214400 kb
Host smart-02295ad4-d4b0-48bf-9997-9323a1346535
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673024416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1673024416
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3767468822
Short name T356
Test name
Test status
Simulation time 36109133 ps
CPU time 2.42 seconds
Started Jul 12 06:41:56 PM PDT 24
Finished Jul 12 06:42:00 PM PDT 24
Peak memory 218616 kb
Host smart-d2ac31aa-6df5-43f2-a49f-1ae0177855f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767468822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3767468822
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1890708465
Short name T889
Test name
Test status
Simulation time 412095919 ps
CPU time 4.81 seconds
Started Jul 12 06:42:00 PM PDT 24
Finished Jul 12 06:42:07 PM PDT 24
Peak memory 214324 kb
Host smart-ec705a2d-6dc2-48eb-9dc9-0f52a3d24627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890708465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1890708465
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3093766426
Short name T573
Test name
Test status
Simulation time 40291136 ps
CPU time 2.81 seconds
Started Jul 12 06:41:54 PM PDT 24
Finished Jul 12 06:41:59 PM PDT 24
Peak memory 214144 kb
Host smart-db9b31e3-949d-4006-84ee-d29f0f2f65a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093766426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3093766426
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.895062421
Short name T512
Test name
Test status
Simulation time 94572502 ps
CPU time 2.13 seconds
Started Jul 12 06:41:59 PM PDT 24
Finished Jul 12 06:42:03 PM PDT 24
Peak memory 216888 kb
Host smart-8aa4ac7a-8bcb-4a0c-b8b4-0adb061b6993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895062421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.895062421
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3128509281
Short name T776
Test name
Test status
Simulation time 212662505 ps
CPU time 3.12 seconds
Started Jul 12 06:41:59 PM PDT 24
Finished Jul 12 06:42:04 PM PDT 24
Peak memory 207440 kb
Host smart-c465b974-ce93-42dd-95df-d61f2207ffa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128509281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3128509281
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.4073434305
Short name T217
Test name
Test status
Simulation time 64851662 ps
CPU time 2.75 seconds
Started Jul 12 06:41:58 PM PDT 24
Finished Jul 12 06:42:03 PM PDT 24
Peak memory 206992 kb
Host smart-9d61e6d6-9693-401a-9841-7bbd92d9bf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073434305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.4073434305
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3183312813
Short name T556
Test name
Test status
Simulation time 1804412249 ps
CPU time 23.58 seconds
Started Jul 12 06:42:02 PM PDT 24
Finished Jul 12 06:42:28 PM PDT 24
Peak memory 208684 kb
Host smart-ea63c350-7b1f-4388-9cee-19220db95777
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183312813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3183312813
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1096618295
Short name T665
Test name
Test status
Simulation time 1248300191 ps
CPU time 25.37 seconds
Started Jul 12 06:42:12 PM PDT 24
Finished Jul 12 06:42:41 PM PDT 24
Peak memory 208228 kb
Host smart-393914e8-e92e-4339-8de0-fc983562b3af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096618295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1096618295
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1153041869
Short name T186
Test name
Test status
Simulation time 173566877 ps
CPU time 5.29 seconds
Started Jul 12 06:42:09 PM PDT 24
Finished Jul 12 06:42:16 PM PDT 24
Peak memory 208888 kb
Host smart-ebc9b5f8-8f98-4136-998a-a3a5bb0f5e82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153041869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1153041869
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1400231593
Short name T645
Test name
Test status
Simulation time 59576048 ps
CPU time 3.08 seconds
Started Jul 12 06:42:04 PM PDT 24
Finished Jul 12 06:42:10 PM PDT 24
Peak memory 214392 kb
Host smart-67cb8c0f-ac7d-4448-8083-ec7dc968115d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400231593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1400231593
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1912353746
Short name T412
Test name
Test status
Simulation time 319694358 ps
CPU time 3.07 seconds
Started Jul 12 06:41:59 PM PDT 24
Finished Jul 12 06:42:04 PM PDT 24
Peak memory 208516 kb
Host smart-e1b8b8e6-792a-436a-8728-6a69946c6469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912353746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1912353746
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3525874508
Short name T72
Test name
Test status
Simulation time 953858712 ps
CPU time 14.77 seconds
Started Jul 12 06:41:59 PM PDT 24
Finished Jul 12 06:42:16 PM PDT 24
Peak memory 216408 kb
Host smart-d99b0637-3c3c-4605-9452-ee1503294e58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525874508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3525874508
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1488020485
Short name T543
Test name
Test status
Simulation time 251433702 ps
CPU time 3.02 seconds
Started Jul 12 06:41:59 PM PDT 24
Finished Jul 12 06:42:04 PM PDT 24
Peak memory 207912 kb
Host smart-597b975a-ccd6-4f92-b49f-a943b35efff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488020485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1488020485
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3030396005
Short name T419
Test name
Test status
Simulation time 48994840 ps
CPU time 2.3 seconds
Started Jul 12 06:42:00 PM PDT 24
Finished Jul 12 06:42:05 PM PDT 24
Peak memory 209912 kb
Host smart-c437ef49-3a07-401a-a542-674ab8cccf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030396005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3030396005
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1678960677
Short name T459
Test name
Test status
Simulation time 11137261 ps
CPU time 0.85 seconds
Started Jul 12 06:42:11 PM PDT 24
Finished Jul 12 06:42:14 PM PDT 24
Peak memory 205984 kb
Host smart-2cdaeeba-8bac-4f10-9898-219ec4a32356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678960677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1678960677
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.684908684
Short name T183
Test name
Test status
Simulation time 227702574 ps
CPU time 4.18 seconds
Started Jul 12 06:42:13 PM PDT 24
Finished Jul 12 06:42:21 PM PDT 24
Peak memory 214908 kb
Host smart-e722e751-f03f-4c1e-b8ad-eab92e3c62c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=684908684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.684908684
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.336787693
Short name T13
Test name
Test status
Simulation time 70758980 ps
CPU time 3.1 seconds
Started Jul 12 06:41:59 PM PDT 24
Finished Jul 12 06:42:05 PM PDT 24
Peak memory 209912 kb
Host smart-66ffc028-94a8-4e3d-82f2-6c04aaa5f75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336787693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.336787693
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1811356854
Short name T451
Test name
Test status
Simulation time 45571152 ps
CPU time 2.22 seconds
Started Jul 12 06:42:06 PM PDT 24
Finished Jul 12 06:42:10 PM PDT 24
Peak memory 209436 kb
Host smart-ce4ee2bc-0c0a-447f-b98b-7d7a24194eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811356854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1811356854
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3352722494
Short name T900
Test name
Test status
Simulation time 2404846526 ps
CPU time 10.54 seconds
Started Jul 12 06:42:01 PM PDT 24
Finished Jul 12 06:42:14 PM PDT 24
Peak memory 214392 kb
Host smart-c40cedd0-0c82-4578-9759-2f2aee065598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352722494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3352722494
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1739016401
Short name T695
Test name
Test status
Simulation time 507546486 ps
CPU time 10.08 seconds
Started Jul 12 06:42:00 PM PDT 24
Finished Jul 12 06:42:13 PM PDT 24
Peak memory 214288 kb
Host smart-5c0ff2e9-d7ca-4c88-932a-de3e992c3a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739016401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1739016401
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2761329963
Short name T50
Test name
Test status
Simulation time 88547046 ps
CPU time 3.78 seconds
Started Jul 12 06:42:11 PM PDT 24
Finished Jul 12 06:42:19 PM PDT 24
Peak memory 214340 kb
Host smart-a6edba97-4081-47ff-928e-42e936423d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761329963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2761329963
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2877121574
Short name T315
Test name
Test status
Simulation time 482340617 ps
CPU time 6.74 seconds
Started Jul 12 06:42:02 PM PDT 24
Finished Jul 12 06:42:11 PM PDT 24
Peak memory 214408 kb
Host smart-9a79a4ac-7168-476a-ae07-532e7341149e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877121574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2877121574
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.4252182151
Short name T867
Test name
Test status
Simulation time 129789729 ps
CPU time 2.56 seconds
Started Jul 12 06:42:00 PM PDT 24
Finished Jul 12 06:42:06 PM PDT 24
Peak memory 208660 kb
Host smart-6ab361e8-9d5d-46e9-8af8-a8a45a1aae6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252182151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.4252182151
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.333471954
Short name T508
Test name
Test status
Simulation time 45985587 ps
CPU time 2.45 seconds
Started Jul 12 06:41:57 PM PDT 24
Finished Jul 12 06:42:01 PM PDT 24
Peak memory 206840 kb
Host smart-56afc061-1e3e-44dc-8de0-57dac62a28b9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333471954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.333471954
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.484616900
Short name T904
Test name
Test status
Simulation time 83288964 ps
CPU time 3.95 seconds
Started Jul 12 06:42:05 PM PDT 24
Finished Jul 12 06:42:11 PM PDT 24
Peak memory 208784 kb
Host smart-6c4f310c-1da2-4bf9-bbd8-cd779971ddd1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484616900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.484616900
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2469711833
Short name T614
Test name
Test status
Simulation time 103265072 ps
CPU time 4.53 seconds
Started Jul 12 06:42:11 PM PDT 24
Finished Jul 12 06:42:19 PM PDT 24
Peak memory 208784 kb
Host smart-7db34333-2b59-40f6-8249-14a5a2c90117
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469711833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2469711833
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1719024881
Short name T884
Test name
Test status
Simulation time 95010975 ps
CPU time 3.26 seconds
Started Jul 12 06:42:08 PM PDT 24
Finished Jul 12 06:42:13 PM PDT 24
Peak memory 208056 kb
Host smart-5bb2086d-4a81-4df9-b0ac-e715df771556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719024881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1719024881
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2842452377
Short name T897
Test name
Test status
Simulation time 2462471192 ps
CPU time 7.96 seconds
Started Jul 12 06:41:56 PM PDT 24
Finished Jul 12 06:42:06 PM PDT 24
Peak memory 208144 kb
Host smart-9476470d-1769-4efc-80ae-526edcfa5d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842452377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2842452377
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1386384046
Short name T385
Test name
Test status
Simulation time 705233359 ps
CPU time 5.52 seconds
Started Jul 12 06:41:54 PM PDT 24
Finished Jul 12 06:42:01 PM PDT 24
Peak memory 208372 kb
Host smart-190ca73b-c56f-4401-b60b-187f045ab0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386384046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1386384046
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1068584831
Short name T652
Test name
Test status
Simulation time 341059610 ps
CPU time 3.52 seconds
Started Jul 12 06:42:12 PM PDT 24
Finished Jul 12 06:42:19 PM PDT 24
Peak memory 209808 kb
Host smart-21b44b35-670b-427b-9139-7c5995352ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068584831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1068584831
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1337657940
Short name T96
Test name
Test status
Simulation time 39975278 ps
CPU time 0.84 seconds
Started Jul 12 06:42:01 PM PDT 24
Finished Jul 12 06:42:05 PM PDT 24
Peak memory 206008 kb
Host smart-eded4e54-a237-4ad6-8f81-1b98e6836267
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337657940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1337657940
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1644658760
Short name T714
Test name
Test status
Simulation time 152321052 ps
CPU time 3.37 seconds
Started Jul 12 06:42:01 PM PDT 24
Finished Jul 12 06:42:07 PM PDT 24
Peak memory 214336 kb
Host smart-8b428ada-c359-4111-8e4d-1529902fde79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1644658760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1644658760
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2689735120
Short name T682
Test name
Test status
Simulation time 139827176 ps
CPU time 5.32 seconds
Started Jul 12 06:42:10 PM PDT 24
Finished Jul 12 06:42:18 PM PDT 24
Peak memory 211068 kb
Host smart-590a6cd8-6738-4ca2-9c04-ffba8854a6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689735120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2689735120
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2265265932
Short name T497
Test name
Test status
Simulation time 170901194 ps
CPU time 2.18 seconds
Started Jul 12 06:42:13 PM PDT 24
Finished Jul 12 06:42:19 PM PDT 24
Peak memory 207732 kb
Host smart-e524e0c2-420a-4e92-a836-b835e7f77708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265265932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2265265932
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1857669917
Short name T84
Test name
Test status
Simulation time 109553167 ps
CPU time 5.27 seconds
Started Jul 12 06:42:11 PM PDT 24
Finished Jul 12 06:42:20 PM PDT 24
Peak memory 214392 kb
Host smart-7a44fab1-e77d-419f-8eb5-b9f262b9faf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857669917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1857669917
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3267989196
Short name T792
Test name
Test status
Simulation time 343728221 ps
CPU time 4.34 seconds
Started Jul 12 06:41:58 PM PDT 24
Finished Jul 12 06:42:04 PM PDT 24
Peak memory 214228 kb
Host smart-c5f371a5-86d1-40d6-b1e8-9feb7ba753c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267989196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3267989196
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3992039230
Short name T656
Test name
Test status
Simulation time 186538615 ps
CPU time 3.12 seconds
Started Jul 12 06:42:02 PM PDT 24
Finished Jul 12 06:42:08 PM PDT 24
Peak memory 214380 kb
Host smart-85568ae4-8fc8-4fd6-8479-89708acf8234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992039230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3992039230
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3858891585
Short name T832
Test name
Test status
Simulation time 471799876 ps
CPU time 7.46 seconds
Started Jul 12 06:42:16 PM PDT 24
Finished Jul 12 06:42:27 PM PDT 24
Peak memory 207956 kb
Host smart-f5c5ab3b-9fc2-4c61-8c5f-69d2442e7766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858891585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3858891585
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1728584900
Short name T349
Test name
Test status
Simulation time 165856026 ps
CPU time 3.22 seconds
Started Jul 12 06:42:10 PM PDT 24
Finished Jul 12 06:42:16 PM PDT 24
Peak memory 206708 kb
Host smart-7e84d1f6-985e-49ae-a9f8-d734ca05acc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728584900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1728584900
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3740627512
Short name T856
Test name
Test status
Simulation time 99235005 ps
CPU time 2.74 seconds
Started Jul 12 06:42:12 PM PDT 24
Finished Jul 12 06:42:18 PM PDT 24
Peak memory 207032 kb
Host smart-f31d9725-8593-4328-9c29-08644b13611e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740627512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3740627512
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1896977823
Short name T747
Test name
Test status
Simulation time 64282404 ps
CPU time 3.24 seconds
Started Jul 12 06:41:57 PM PDT 24
Finished Jul 12 06:42:02 PM PDT 24
Peak memory 206844 kb
Host smart-28e1a2d6-481a-474f-9adc-56b901d98ad4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896977823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1896977823
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1321584000
Short name T671
Test name
Test status
Simulation time 3510943689 ps
CPU time 6.61 seconds
Started Jul 12 06:42:05 PM PDT 24
Finished Jul 12 06:42:14 PM PDT 24
Peak memory 209044 kb
Host smart-87886652-2839-4741-848f-170d57d075a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321584000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1321584000
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2856925856
Short name T332
Test name
Test status
Simulation time 52129784 ps
CPU time 2.15 seconds
Started Jul 12 06:42:05 PM PDT 24
Finished Jul 12 06:42:09 PM PDT 24
Peak memory 215752 kb
Host smart-4ea1cbf9-8dd9-4ee1-af34-4a34d1f1dc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856925856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2856925856
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.391425403
Short name T748
Test name
Test status
Simulation time 1229626670 ps
CPU time 3.61 seconds
Started Jul 12 06:42:05 PM PDT 24
Finished Jul 12 06:42:11 PM PDT 24
Peak memory 206724 kb
Host smart-ac7ee28d-8318-4079-bb5b-872035a93e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391425403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.391425403
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3105713481
Short name T540
Test name
Test status
Simulation time 414204547 ps
CPU time 3.61 seconds
Started Jul 12 06:42:09 PM PDT 24
Finished Jul 12 06:42:14 PM PDT 24
Peak memory 214328 kb
Host smart-e2b87b81-6f64-4fd6-b12f-5cc0a5c5e309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105713481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3105713481
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1077263416
Short name T219
Test name
Test status
Simulation time 108596169 ps
CPU time 1.75 seconds
Started Jul 12 06:42:09 PM PDT 24
Finished Jul 12 06:42:12 PM PDT 24
Peak memory 210032 kb
Host smart-f6bc0394-c19a-46d5-918d-dc1ce3729aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077263416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1077263416
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1964088762
Short name T903
Test name
Test status
Simulation time 19858255 ps
CPU time 0.78 seconds
Started Jul 12 06:42:16 PM PDT 24
Finished Jul 12 06:42:21 PM PDT 24
Peak memory 205884 kb
Host smart-1c2abbf2-d916-46fc-ada2-665b2540a199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964088762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1964088762
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2363588054
Short name T317
Test name
Test status
Simulation time 45368696 ps
CPU time 3.28 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:22 PM PDT 24
Peak memory 214340 kb
Host smart-2604f0b8-a063-4726-8e6a-2ec6638504e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2363588054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2363588054
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3349855538
Short name T681
Test name
Test status
Simulation time 50355816 ps
CPU time 2.55 seconds
Started Jul 12 06:42:06 PM PDT 24
Finished Jul 12 06:42:11 PM PDT 24
Peak memory 214308 kb
Host smart-1c4b88ff-e1d9-405b-b83e-494a53259bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349855538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3349855538
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2326078264
Short name T562
Test name
Test status
Simulation time 1161916249 ps
CPU time 9.86 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:29 PM PDT 24
Peak memory 209196 kb
Host smart-27c3d4cd-d4eb-4d19-8efb-4074bf910387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326078264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2326078264
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.521355247
Short name T340
Test name
Test status
Simulation time 124968806 ps
CPU time 2.31 seconds
Started Jul 12 06:42:05 PM PDT 24
Finished Jul 12 06:42:09 PM PDT 24
Peak memory 214348 kb
Host smart-550af8bd-98ed-4eda-a8ea-f681269db093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521355247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.521355247
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3087924505
Short name T35
Test name
Test status
Simulation time 399182025 ps
CPU time 3.45 seconds
Started Jul 12 06:42:01 PM PDT 24
Finished Jul 12 06:42:07 PM PDT 24
Peak memory 214276 kb
Host smart-f34d2b82-e911-49e4-baca-2953a7b6d627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087924505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3087924505
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.799820609
Short name T863
Test name
Test status
Simulation time 113989239 ps
CPU time 4.77 seconds
Started Jul 12 06:42:09 PM PDT 24
Finished Jul 12 06:42:16 PM PDT 24
Peak memory 222448 kb
Host smart-604217ae-d1e6-45c0-9293-32bebf0309d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799820609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.799820609
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.447489389
Short name T654
Test name
Test status
Simulation time 89063553 ps
CPU time 4.34 seconds
Started Jul 12 06:42:07 PM PDT 24
Finished Jul 12 06:42:13 PM PDT 24
Peak memory 218512 kb
Host smart-2364e103-f14d-4758-b5ff-1e3c99374eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447489389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.447489389
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3138490269
Short name T599
Test name
Test status
Simulation time 264526999 ps
CPU time 6.58 seconds
Started Jul 12 06:42:01 PM PDT 24
Finished Jul 12 06:42:10 PM PDT 24
Peak memory 208196 kb
Host smart-cf8bbedc-8145-4859-87cb-2cabd5be5ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138490269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3138490269
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.83844707
Short name T441
Test name
Test status
Simulation time 794920678 ps
CPU time 19.35 seconds
Started Jul 12 06:42:01 PM PDT 24
Finished Jul 12 06:42:23 PM PDT 24
Peak memory 208048 kb
Host smart-7cfa985b-6031-41b9-ad54-d85b4101b663
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83844707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.83844707
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2450992303
Short name T711
Test name
Test status
Simulation time 69505926 ps
CPU time 3.56 seconds
Started Jul 12 06:42:01 PM PDT 24
Finished Jul 12 06:42:07 PM PDT 24
Peak memory 208612 kb
Host smart-28691116-82b2-4454-8ebd-11ee676877c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450992303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2450992303
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.712682087
Short name T860
Test name
Test status
Simulation time 197537506 ps
CPU time 7.34 seconds
Started Jul 12 06:42:12 PM PDT 24
Finished Jul 12 06:42:23 PM PDT 24
Peak memory 208084 kb
Host smart-2e2db580-33f0-422f-8755-58857e75793a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712682087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.712682087
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2224371772
Short name T306
Test name
Test status
Simulation time 732434129 ps
CPU time 21.49 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:41 PM PDT 24
Peak memory 209844 kb
Host smart-82e93119-1e7b-4039-8ddb-8ed35a9623c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224371772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2224371772
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1360710658
Short name T578
Test name
Test status
Simulation time 418118993 ps
CPU time 8.72 seconds
Started Jul 12 06:42:05 PM PDT 24
Finished Jul 12 06:42:16 PM PDT 24
Peak memory 208396 kb
Host smart-e38eca4f-8491-4d29-9502-bc01b29c7d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360710658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1360710658
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3911506146
Short name T917
Test name
Test status
Simulation time 1499243108 ps
CPU time 49.64 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:43:09 PM PDT 24
Peak memory 222504 kb
Host smart-1ad3a21c-e1db-4e18-be5e-92710fcd8751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911506146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3911506146
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2313967497
Short name T584
Test name
Test status
Simulation time 1055956153 ps
CPU time 3.67 seconds
Started Jul 12 06:42:11 PM PDT 24
Finished Jul 12 06:42:17 PM PDT 24
Peak memory 208148 kb
Host smart-e1ab5ba6-1d24-4fd0-9885-2a61fa370651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313967497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2313967497
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2817723379
Short name T547
Test name
Test status
Simulation time 327439298 ps
CPU time 5.95 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:24 PM PDT 24
Peak memory 210852 kb
Host smart-c494a830-bc7d-4232-aa60-172ca1e0cd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817723379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2817723379
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2343342111
Short name T566
Test name
Test status
Simulation time 15191763 ps
CPU time 0.92 seconds
Started Jul 12 06:42:11 PM PDT 24
Finished Jul 12 06:42:15 PM PDT 24
Peak memory 206064 kb
Host smart-83251bc9-dd32-4cad-bbc7-325597d861bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343342111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2343342111
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1541099292
Short name T782
Test name
Test status
Simulation time 1067525280 ps
CPU time 4.77 seconds
Started Jul 12 06:42:15 PM PDT 24
Finished Jul 12 06:42:24 PM PDT 24
Peak memory 221440 kb
Host smart-d5985e57-11d8-4006-af64-7adeec26a69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541099292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1541099292
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.975240646
Short name T70
Test name
Test status
Simulation time 75752310 ps
CPU time 3.08 seconds
Started Jul 12 06:42:17 PM PDT 24
Finished Jul 12 06:42:24 PM PDT 24
Peak memory 210096 kb
Host smart-8162f086-42ff-4d74-bae4-5d99af4ccce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975240646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.975240646
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1128563021
Short name T603
Test name
Test status
Simulation time 152323180 ps
CPU time 2.56 seconds
Started Jul 12 06:42:05 PM PDT 24
Finished Jul 12 06:42:10 PM PDT 24
Peak memory 215380 kb
Host smart-722cb58c-176c-4b2a-a60a-bf099358bf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128563021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1128563021
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3825049405
Short name T288
Test name
Test status
Simulation time 486070280 ps
CPU time 3.99 seconds
Started Jul 12 06:42:09 PM PDT 24
Finished Jul 12 06:42:15 PM PDT 24
Peak memory 214308 kb
Host smart-ac9839de-f5e1-47fa-995b-786600db60c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825049405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3825049405
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3747630273
Short name T61
Test name
Test status
Simulation time 35372968 ps
CPU time 2.82 seconds
Started Jul 12 06:42:16 PM PDT 24
Finished Jul 12 06:42:23 PM PDT 24
Peak memory 220184 kb
Host smart-a469abcb-1655-4eba-9bea-49dee6456bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747630273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3747630273
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2539997945
Short name T839
Test name
Test status
Simulation time 213786655 ps
CPU time 3.11 seconds
Started Jul 12 06:42:05 PM PDT 24
Finished Jul 12 06:42:10 PM PDT 24
Peak memory 207252 kb
Host smart-ae44046f-fb30-4372-8e15-8b6110b9fc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539997945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2539997945
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1242775920
Short name T835
Test name
Test status
Simulation time 368031378 ps
CPU time 5.48 seconds
Started Jul 12 06:42:04 PM PDT 24
Finished Jul 12 06:42:12 PM PDT 24
Peak memory 208668 kb
Host smart-b530de2c-4839-49dd-abfa-9e0197e13bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242775920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1242775920
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3003924923
Short name T820
Test name
Test status
Simulation time 41378397 ps
CPU time 2.45 seconds
Started Jul 12 06:42:13 PM PDT 24
Finished Jul 12 06:42:19 PM PDT 24
Peak memory 206980 kb
Host smart-1a57813d-ad67-4a50-957e-6b72ddf7bd47
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003924923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3003924923
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3850818841
Short name T760
Test name
Test status
Simulation time 1046701023 ps
CPU time 2.95 seconds
Started Jul 12 06:42:06 PM PDT 24
Finished Jul 12 06:42:11 PM PDT 24
Peak memory 206992 kb
Host smart-901f6c84-8c0d-4cc3-90b5-d3dead0a2246
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850818841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3850818841
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2057959547
Short name T131
Test name
Test status
Simulation time 856100518 ps
CPU time 27.75 seconds
Started Jul 12 06:42:12 PM PDT 24
Finished Jul 12 06:42:44 PM PDT 24
Peak memory 208252 kb
Host smart-bd3cbead-441e-447a-8991-650623f1464f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057959547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2057959547
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3552001474
Short name T2
Test name
Test status
Simulation time 652064011 ps
CPU time 16.94 seconds
Started Jul 12 06:42:03 PM PDT 24
Finished Jul 12 06:42:23 PM PDT 24
Peak memory 208728 kb
Host smart-f2ca9171-5e38-47ac-abc0-d8a46c9fb9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552001474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3552001474
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1370936214
Short name T481
Test name
Test status
Simulation time 127575114 ps
CPU time 2.86 seconds
Started Jul 12 06:42:12 PM PDT 24
Finished Jul 12 06:42:18 PM PDT 24
Peak memory 206860 kb
Host smart-9668f2be-b381-4869-b893-ad9daf15d6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370936214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1370936214
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1209599018
Short name T908
Test name
Test status
Simulation time 494535461 ps
CPU time 7.79 seconds
Started Jul 12 06:42:04 PM PDT 24
Finished Jul 12 06:42:14 PM PDT 24
Peak memory 214288 kb
Host smart-f2319bd3-f819-4be1-8b00-683d5ba52cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209599018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1209599018
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2380205704
Short name T555
Test name
Test status
Simulation time 140149318 ps
CPU time 2.28 seconds
Started Jul 12 06:42:11 PM PDT 24
Finished Jul 12 06:42:17 PM PDT 24
Peak memory 210500 kb
Host smart-3d8c5acc-8064-42cc-b249-3dbbc7efc95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380205704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2380205704
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1919287935
Short name T698
Test name
Test status
Simulation time 11885298 ps
CPU time 0.88 seconds
Started Jul 12 06:42:19 PM PDT 24
Finished Jul 12 06:42:23 PM PDT 24
Peak memory 205996 kb
Host smart-80fedbca-d80b-477a-b90d-78afd5cf203f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919287935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1919287935
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3205977836
Short name T51
Test name
Test status
Simulation time 111956925 ps
CPU time 1.85 seconds
Started Jul 12 06:42:05 PM PDT 24
Finished Jul 12 06:42:09 PM PDT 24
Peak memory 214328 kb
Host smart-03b6649e-6d08-4a4d-8c19-331e363dbd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205977836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3205977836
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.333773583
Short name T196
Test name
Test status
Simulation time 143874692 ps
CPU time 3.46 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:22 PM PDT 24
Peak memory 214328 kb
Host smart-68946b86-41b4-4f74-b899-08bbd6a5fd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333773583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.333773583
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2649820042
Short name T56
Test name
Test status
Simulation time 144221156 ps
CPU time 6.11 seconds
Started Jul 12 06:42:15 PM PDT 24
Finished Jul 12 06:42:26 PM PDT 24
Peak memory 221568 kb
Host smart-f56ae9ab-d4c7-4f9c-b5ec-c9fefc23743c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649820042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2649820042
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.104288424
Short name T859
Test name
Test status
Simulation time 373159153 ps
CPU time 4.15 seconds
Started Jul 12 06:42:05 PM PDT 24
Finished Jul 12 06:42:11 PM PDT 24
Peak memory 208824 kb
Host smart-994ed337-602a-44d6-88ac-7528d6f004d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104288424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.104288424
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3767704802
Short name T699
Test name
Test status
Simulation time 110129689 ps
CPU time 4.51 seconds
Started Jul 12 06:42:13 PM PDT 24
Finished Jul 12 06:42:22 PM PDT 24
Peak memory 218440 kb
Host smart-4e321cd4-d9e4-44a7-b502-dff4f408acd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767704802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3767704802
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1960225975
Short name T770
Test name
Test status
Simulation time 281934732 ps
CPU time 2.96 seconds
Started Jul 12 06:42:04 PM PDT 24
Finished Jul 12 06:42:09 PM PDT 24
Peak memory 206708 kb
Host smart-81f6108d-186c-4b2c-9b70-6a70e526bfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960225975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1960225975
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.704493253
Short name T383
Test name
Test status
Simulation time 42211955 ps
CPU time 2.14 seconds
Started Jul 12 06:42:10 PM PDT 24
Finished Jul 12 06:42:15 PM PDT 24
Peak memory 208804 kb
Host smart-44da6671-0926-4ae0-9fc3-f5f7e0c8ee60
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704493253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.704493253
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3838894601
Short name T128
Test name
Test status
Simulation time 1211014473 ps
CPU time 4.2 seconds
Started Jul 12 06:42:13 PM PDT 24
Finished Jul 12 06:42:22 PM PDT 24
Peak memory 207372 kb
Host smart-a17e815b-ef35-4952-8557-9bf47fa27941
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838894601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3838894601
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.264917828
Short name T678
Test name
Test status
Simulation time 83281818 ps
CPU time 3.03 seconds
Started Jul 12 06:42:12 PM PDT 24
Finished Jul 12 06:42:19 PM PDT 24
Peak memory 207068 kb
Host smart-cb408a4f-4fe1-421b-a161-9553fcd81b10
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264917828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.264917828
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2209246508
Short name T672
Test name
Test status
Simulation time 50261105 ps
CPU time 2.12 seconds
Started Jul 12 06:42:24 PM PDT 24
Finished Jul 12 06:42:31 PM PDT 24
Peak memory 215808 kb
Host smart-3cb18604-f528-48ea-832a-dc738d2c7a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209246508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2209246508
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1458246902
Short name T438
Test name
Test status
Simulation time 319738657 ps
CPU time 3.56 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:22 PM PDT 24
Peak memory 208888 kb
Host smart-687b8735-6f93-4da3-b5a8-8ecd1b7937bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458246902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1458246902
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.569236178
Short name T829
Test name
Test status
Simulation time 277626144 ps
CPU time 4.65 seconds
Started Jul 12 06:42:08 PM PDT 24
Finished Jul 12 06:42:14 PM PDT 24
Peak memory 209324 kb
Host smart-3addff85-7ea5-4fcf-a404-2702539c707e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569236178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.569236178
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.671541478
Short name T907
Test name
Test status
Simulation time 490409988 ps
CPU time 4.33 seconds
Started Jul 12 06:42:10 PM PDT 24
Finished Jul 12 06:42:17 PM PDT 24
Peak memory 210560 kb
Host smart-1048e45a-b3bd-40ed-86ce-95625cfb3864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671541478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.671541478
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3399470421
Short name T841
Test name
Test status
Simulation time 39320756 ps
CPU time 1.09 seconds
Started Jul 12 06:42:18 PM PDT 24
Finished Jul 12 06:42:23 PM PDT 24
Peak memory 206140 kb
Host smart-806fca55-14b6-4174-b2d9-60d6d4141690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399470421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3399470421
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2738591960
Short name T827
Test name
Test status
Simulation time 134571913 ps
CPU time 7.87 seconds
Started Jul 12 06:42:18 PM PDT 24
Finished Jul 12 06:42:30 PM PDT 24
Peak memory 214756 kb
Host smart-af11a4b6-f0f4-4e20-a998-0875a38f4a47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2738591960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2738591960
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3949232260
Short name T538
Test name
Test status
Simulation time 70744028 ps
CPU time 1.63 seconds
Started Jul 12 06:42:10 PM PDT 24
Finished Jul 12 06:42:15 PM PDT 24
Peak memory 207908 kb
Host smart-2432b7df-6688-406e-b31c-a43e615400f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949232260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3949232260
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3715618023
Short name T286
Test name
Test status
Simulation time 361473441 ps
CPU time 2.84 seconds
Started Jul 12 06:42:17 PM PDT 24
Finished Jul 12 06:42:23 PM PDT 24
Peak memory 214336 kb
Host smart-4a762388-b36d-4c73-9792-7ec48d628ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715618023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3715618023
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2633332547
Short name T394
Test name
Test status
Simulation time 154148586 ps
CPU time 3.74 seconds
Started Jul 12 06:42:10 PM PDT 24
Finished Jul 12 06:42:17 PM PDT 24
Peak memory 214288 kb
Host smart-cae4b9ca-ec87-475b-9079-ca4b5b643880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633332547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2633332547
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.4065655440
Short name T553
Test name
Test status
Simulation time 283009770 ps
CPU time 4.11 seconds
Started Jul 12 06:42:13 PM PDT 24
Finished Jul 12 06:42:21 PM PDT 24
Peak memory 209616 kb
Host smart-3b55d107-7fb5-426e-9b90-2a5783adac7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065655440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.4065655440
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1410958046
Short name T845
Test name
Test status
Simulation time 712421577 ps
CPU time 6.52 seconds
Started Jul 12 06:42:11 PM PDT 24
Finished Jul 12 06:42:21 PM PDT 24
Peak memory 207380 kb
Host smart-ee951a18-ebde-429c-a1bd-112bf4c99e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410958046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1410958046
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.944824255
Short name T472
Test name
Test status
Simulation time 766450982 ps
CPU time 6.22 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:24 PM PDT 24
Peak memory 206892 kb
Host smart-0d162d31-e464-425a-aea1-e5340cfcc30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944824255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.944824255
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.191021830
Short name T637
Test name
Test status
Simulation time 330995718 ps
CPU time 3.2 seconds
Started Jul 12 06:42:13 PM PDT 24
Finished Jul 12 06:42:21 PM PDT 24
Peak memory 207024 kb
Host smart-585a5668-3b0c-4840-8a91-c8ac6474442a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191021830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.191021830
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1168160931
Short name T549
Test name
Test status
Simulation time 131748828 ps
CPU time 3.86 seconds
Started Jul 12 06:42:13 PM PDT 24
Finished Jul 12 06:42:21 PM PDT 24
Peak memory 208068 kb
Host smart-8cb2e1b2-1050-45d4-928f-eff659d8ff68
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168160931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1168160931
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1470526291
Short name T885
Test name
Test status
Simulation time 38514181 ps
CPU time 2.62 seconds
Started Jul 12 06:42:16 PM PDT 24
Finished Jul 12 06:42:23 PM PDT 24
Peak memory 208816 kb
Host smart-84589774-6a04-4d96-8e25-83fd8113e675
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470526291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1470526291
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.346879487
Short name T271
Test name
Test status
Simulation time 145849166 ps
CPU time 3.67 seconds
Started Jul 12 06:42:12 PM PDT 24
Finished Jul 12 06:42:19 PM PDT 24
Peak memory 214412 kb
Host smart-590b13ea-7460-4461-a590-722b7d8aa315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346879487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.346879487
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1674594180
Short name T629
Test name
Test status
Simulation time 219267384 ps
CPU time 4.96 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:23 PM PDT 24
Peak memory 206852 kb
Host smart-76f16645-7684-4422-9761-857d19dda882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674594180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1674594180
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3752939076
Short name T669
Test name
Test status
Simulation time 357190033 ps
CPU time 5.21 seconds
Started Jul 12 06:42:19 PM PDT 24
Finished Jul 12 06:42:27 PM PDT 24
Peak memory 217224 kb
Host smart-3e7beb93-39c5-40e0-b366-b1d9f9079623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752939076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3752939076
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2851994281
Short name T683
Test name
Test status
Simulation time 15909744632 ps
CPU time 20.07 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:39 PM PDT 24
Peak memory 214376 kb
Host smart-a691aeed-ff25-4a44-861d-5f899bf5d070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851994281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2851994281
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1988719282
Short name T828
Test name
Test status
Simulation time 539111380 ps
CPU time 8.68 seconds
Started Jul 12 06:42:14 PM PDT 24
Finished Jul 12 06:42:27 PM PDT 24
Peak memory 210424 kb
Host smart-72b8a956-0be6-4c7e-9660-b6ce6c792567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988719282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1988719282
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1719295411
Short name T443
Test name
Test status
Simulation time 38408839 ps
CPU time 0.79 seconds
Started Jul 12 06:40:16 PM PDT 24
Finished Jul 12 06:40:21 PM PDT 24
Peak memory 205936 kb
Host smart-4bb29ac6-9e63-4fda-b7c4-0570f268d12a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719295411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1719295411
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3516567441
Short name T182
Test name
Test status
Simulation time 137749383 ps
CPU time 6.73 seconds
Started Jul 12 06:40:01 PM PDT 24
Finished Jul 12 06:40:10 PM PDT 24
Peak memory 214320 kb
Host smart-a2c7d45c-cd66-40f7-b9b4-aee4164b4d90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3516567441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3516567441
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3139695988
Short name T579
Test name
Test status
Simulation time 1786353507 ps
CPU time 12.56 seconds
Started Jul 12 06:40:12 PM PDT 24
Finished Jul 12 06:40:26 PM PDT 24
Peak memory 218408 kb
Host smart-35dc1396-2035-4896-bf0c-c36eb3b2c764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139695988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3139695988
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1598731314
Short name T819
Test name
Test status
Simulation time 40411682 ps
CPU time 1.8 seconds
Started Jul 12 06:40:02 PM PDT 24
Finished Jul 12 06:40:06 PM PDT 24
Peak memory 214352 kb
Host smart-cbde084e-5035-4e41-bac4-c0f75174bf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598731314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1598731314
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1578561331
Short name T93
Test name
Test status
Simulation time 415953028 ps
CPU time 6.39 seconds
Started Jul 12 06:39:59 PM PDT 24
Finished Jul 12 06:40:07 PM PDT 24
Peak memory 208412 kb
Host smart-d384f873-29d1-49a1-b9d1-ccdb823d456f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578561331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1578561331
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1640967840
Short name T365
Test name
Test status
Simulation time 440586333 ps
CPU time 3.91 seconds
Started Jul 12 06:40:19 PM PDT 24
Finished Jul 12 06:40:29 PM PDT 24
Peak memory 214220 kb
Host smart-15e0f4e0-95b1-4572-be2e-be4aa994d10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640967840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1640967840
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2103556764
Short name T250
Test name
Test status
Simulation time 176392147 ps
CPU time 3.36 seconds
Started Jul 12 06:40:00 PM PDT 24
Finished Jul 12 06:40:05 PM PDT 24
Peak memory 214304 kb
Host smart-432fc816-0242-4e79-9e87-6605648f74cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103556764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2103556764
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3511364212
Short name T374
Test name
Test status
Simulation time 1233879764 ps
CPU time 6.18 seconds
Started Jul 12 06:39:59 PM PDT 24
Finished Jul 12 06:40:08 PM PDT 24
Peak memory 209560 kb
Host smart-f45d912a-1931-4e43-8c3a-1699c5721818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511364212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3511364212
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1965329283
Short name T189
Test name
Test status
Simulation time 594059573 ps
CPU time 19.78 seconds
Started Jul 12 06:40:02 PM PDT 24
Finished Jul 12 06:40:24 PM PDT 24
Peak memory 208568 kb
Host smart-80d70028-8693-47bd-aa0a-1594c7b9f7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965329283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1965329283
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2414344938
Short name T500
Test name
Test status
Simulation time 6545968811 ps
CPU time 43.8 seconds
Started Jul 12 06:40:01 PM PDT 24
Finished Jul 12 06:40:47 PM PDT 24
Peak memory 208304 kb
Host smart-6b0b7787-37c5-458b-9268-9140de6f618d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414344938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2414344938
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1283358174
Short name T876
Test name
Test status
Simulation time 215864297 ps
CPU time 2.91 seconds
Started Jul 12 06:39:58 PM PDT 24
Finished Jul 12 06:40:03 PM PDT 24
Peak memory 206960 kb
Host smart-b801f415-4fa1-4d6f-89a9-996bb89b8d5d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283358174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1283358174
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1662705705
Short name T888
Test name
Test status
Simulation time 144236446 ps
CPU time 2.07 seconds
Started Jul 12 06:40:12 PM PDT 24
Finished Jul 12 06:40:16 PM PDT 24
Peak memory 208656 kb
Host smart-b8be33b2-eb0a-4387-809f-3b921808cd2a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662705705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1662705705
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1726834453
Short name T264
Test name
Test status
Simulation time 183518048 ps
CPU time 3.53 seconds
Started Jul 12 06:40:10 PM PDT 24
Finished Jul 12 06:40:15 PM PDT 24
Peak memory 214348 kb
Host smart-387756c4-ddf9-4cdf-b0f5-aadbe8ecf878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726834453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1726834453
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.934448900
Short name T853
Test name
Test status
Simulation time 192739195 ps
CPU time 2.46 seconds
Started Jul 12 06:39:59 PM PDT 24
Finished Jul 12 06:40:04 PM PDT 24
Peak memory 206708 kb
Host smart-91d6606a-86c4-4211-a2f7-221cbe3ec4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934448900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.934448900
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2970953789
Short name T245
Test name
Test status
Simulation time 1080594568 ps
CPU time 33.17 seconds
Started Jul 12 06:40:09 PM PDT 24
Finished Jul 12 06:40:43 PM PDT 24
Peak memory 220548 kb
Host smart-8c3f92b8-a121-454e-9eb1-53c87f561500
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970953789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2970953789
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2687266474
Short name T373
Test name
Test status
Simulation time 145253025 ps
CPU time 3.86 seconds
Started Jul 12 06:39:59 PM PDT 24
Finished Jul 12 06:40:05 PM PDT 24
Peak memory 207264 kb
Host smart-96a84b5a-48c8-4a88-a93d-db84e627ba5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687266474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2687266474
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2266155381
Short name T133
Test name
Test status
Simulation time 647927285 ps
CPU time 2.94 seconds
Started Jul 12 06:40:13 PM PDT 24
Finished Jul 12 06:40:21 PM PDT 24
Peak memory 210112 kb
Host smart-6fbec4d1-509d-46a7-a9cc-8995866af01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266155381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2266155381
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.823744565
Short name T843
Test name
Test status
Simulation time 41389739 ps
CPU time 0.88 seconds
Started Jul 12 06:40:17 PM PDT 24
Finished Jul 12 06:40:23 PM PDT 24
Peak memory 206060 kb
Host smart-e512cb6f-a56c-4a19-9b95-2fa87c5e7186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823744565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.823744565
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.996640560
Short name T424
Test name
Test status
Simulation time 393344480 ps
CPU time 3.94 seconds
Started Jul 12 06:40:19 PM PDT 24
Finished Jul 12 06:40:29 PM PDT 24
Peak memory 214216 kb
Host smart-cdb8aa75-db8b-4a8c-b972-7322f25f6263
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996640560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.996640560
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3677982635
Short name T62
Test name
Test status
Simulation time 290965241 ps
CPU time 11.57 seconds
Started Jul 12 06:40:12 PM PDT 24
Finished Jul 12 06:40:27 PM PDT 24
Peak memory 214784 kb
Host smart-ed1c8c8f-01e3-4bd9-88da-a7ed013fad71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677982635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3677982635
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3544583580
Short name T301
Test name
Test status
Simulation time 256072554 ps
CPU time 2.63 seconds
Started Jul 12 06:40:12 PM PDT 24
Finished Jul 12 06:40:18 PM PDT 24
Peak memory 214288 kb
Host smart-33945d84-6785-42b4-8b59-b0d04ed2e486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544583580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3544583580
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.617459865
Short name T92
Test name
Test status
Simulation time 531617777 ps
CPU time 4.11 seconds
Started Jul 12 06:40:13 PM PDT 24
Finished Jul 12 06:40:20 PM PDT 24
Peak memory 221656 kb
Host smart-9c23e008-55ec-419d-b9c9-d2b8346f06de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617459865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.617459865
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2349475720
Short name T467
Test name
Test status
Simulation time 137792154 ps
CPU time 5.09 seconds
Started Jul 12 06:40:11 PM PDT 24
Finished Jul 12 06:40:19 PM PDT 24
Peak memory 218008 kb
Host smart-a9cfc2e5-f4f7-42b5-af14-e240c37c27fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349475720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2349475720
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1035201069
Short name T719
Test name
Test status
Simulation time 538843209 ps
CPU time 11.48 seconds
Started Jul 12 06:40:12 PM PDT 24
Finished Jul 12 06:40:26 PM PDT 24
Peak memory 214356 kb
Host smart-f3e19d1e-38c2-4366-af56-b344aae141ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035201069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1035201069
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1837320581
Short name T381
Test name
Test status
Simulation time 119672117 ps
CPU time 4.06 seconds
Started Jul 12 06:40:12 PM PDT 24
Finished Jul 12 06:40:18 PM PDT 24
Peak memory 208584 kb
Host smart-a1bb80bc-251a-4626-b048-cb637c655113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837320581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1837320581
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.684813039
Short name T416
Test name
Test status
Simulation time 178718873 ps
CPU time 2.56 seconds
Started Jul 12 06:40:13 PM PDT 24
Finished Jul 12 06:40:20 PM PDT 24
Peak memory 206844 kb
Host smart-0d8f07bc-bb70-428a-a956-222a1b95d623
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684813039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.684813039
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2541248451
Short name T484
Test name
Test status
Simulation time 404330733 ps
CPU time 3.83 seconds
Started Jul 12 06:40:17 PM PDT 24
Finished Jul 12 06:40:26 PM PDT 24
Peak memory 207012 kb
Host smart-4b1afe6a-5c46-4448-97e3-c5a609878ae1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541248451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2541248451
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2657742933
Short name T366
Test name
Test status
Simulation time 195398008 ps
CPU time 5.58 seconds
Started Jul 12 06:40:16 PM PDT 24
Finished Jul 12 06:40:26 PM PDT 24
Peak memory 208712 kb
Host smart-014a9991-4aa6-4bb4-a2e7-838f9a5cfff0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657742933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2657742933
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3704955275
Short name T454
Test name
Test status
Simulation time 356247651 ps
CPU time 1.99 seconds
Started Jul 12 06:40:12 PM PDT 24
Finished Jul 12 06:40:17 PM PDT 24
Peak memory 209196 kb
Host smart-e27c1e96-7cac-4de4-89e8-4a1cac01979b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704955275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3704955275
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3269291
Short name T805
Test name
Test status
Simulation time 2405844342 ps
CPU time 7.74 seconds
Started Jul 12 06:40:16 PM PDT 24
Finished Jul 12 06:40:28 PM PDT 24
Peak memory 207880 kb
Host smart-4b252afb-b534-4c8f-a30d-d5730f514c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3269291
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3747000797
Short name T100
Test name
Test status
Simulation time 241463185 ps
CPU time 10.96 seconds
Started Jul 12 06:40:16 PM PDT 24
Finished Jul 12 06:40:31 PM PDT 24
Peak memory 214432 kb
Host smart-bf083b89-e678-49b2-aff3-d15b49825969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747000797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3747000797
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1376554660
Short name T464
Test name
Test status
Simulation time 178061980 ps
CPU time 4.17 seconds
Started Jul 12 06:40:19 PM PDT 24
Finished Jul 12 06:40:29 PM PDT 24
Peak memory 208888 kb
Host smart-791c73f3-0d34-4c27-a9e5-58a74dd31966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376554660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1376554660
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.216534547
Short name T455
Test name
Test status
Simulation time 22834816 ps
CPU time 1.45 seconds
Started Jul 12 06:40:16 PM PDT 24
Finished Jul 12 06:40:22 PM PDT 24
Peak memory 209848 kb
Host smart-f4ea3b90-3f60-49e6-aac3-6b47232cb897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216534547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.216534547
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2920405900
Short name T810
Test name
Test status
Simulation time 11955156 ps
CPU time 0.86 seconds
Started Jul 12 06:40:18 PM PDT 24
Finished Jul 12 06:40:23 PM PDT 24
Peak memory 205824 kb
Host smart-eba1b15f-4c67-4bf8-994d-5611040752f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920405900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2920405900
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2141142601
Short name T255
Test name
Test status
Simulation time 565272695 ps
CPU time 8.23 seconds
Started Jul 12 06:40:18 PM PDT 24
Finished Jul 12 06:40:31 PM PDT 24
Peak memory 214332 kb
Host smart-125dd976-68b2-48a7-ac7c-3d1d7dc03bad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2141142601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2141142601
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2395778745
Short name T30
Test name
Test status
Simulation time 108643157 ps
CPU time 3.56 seconds
Started Jul 12 06:40:09 PM PDT 24
Finished Jul 12 06:40:14 PM PDT 24
Peak memory 207164 kb
Host smart-775d6250-55bb-4608-8cef-587c5f08ac49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395778745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2395778745
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2164327671
Short name T17
Test name
Test status
Simulation time 103048338 ps
CPU time 4.53 seconds
Started Jul 12 06:40:12 PM PDT 24
Finished Jul 12 06:40:19 PM PDT 24
Peak memory 210540 kb
Host smart-8f5e9a2c-4659-411a-9e5c-f48ac07f281e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164327671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2164327671
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2382862500
Short name T703
Test name
Test status
Simulation time 57403247 ps
CPU time 3.28 seconds
Started Jul 12 06:40:12 PM PDT 24
Finished Jul 12 06:40:17 PM PDT 24
Peak memory 214304 kb
Host smart-22df2101-86ef-4d8c-8444-2bbf9a8443b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382862500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2382862500
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.462793274
Short name T728
Test name
Test status
Simulation time 349115066 ps
CPU time 4.71 seconds
Started Jul 12 06:40:11 PM PDT 24
Finished Jul 12 06:40:17 PM PDT 24
Peak memory 222384 kb
Host smart-e58bc765-dd2c-424e-847d-46c476e735d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462793274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.462793274
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.4181741119
Short name T48
Test name
Test status
Simulation time 273657345 ps
CPU time 3.37 seconds
Started Jul 12 06:40:13 PM PDT 24
Finished Jul 12 06:40:20 PM PDT 24
Peak memory 214344 kb
Host smart-ef5ec152-e611-4436-b0aa-0b5179921ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181741119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.4181741119
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.466915424
Short name T546
Test name
Test status
Simulation time 869391243 ps
CPU time 24.13 seconds
Started Jul 12 06:40:19 PM PDT 24
Finished Jul 12 06:40:49 PM PDT 24
Peak memory 218220 kb
Host smart-0442af16-dc47-471d-ac6c-1be9da37b895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466915424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.466915424
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1640419724
Short name T222
Test name
Test status
Simulation time 1045327168 ps
CPU time 10.85 seconds
Started Jul 12 06:40:14 PM PDT 24
Finished Jul 12 06:40:29 PM PDT 24
Peak memory 207812 kb
Host smart-f3959acf-e44a-4ca3-9f57-33cfda6de202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640419724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1640419724
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2394351372
Short name T634
Test name
Test status
Simulation time 31285538 ps
CPU time 1.86 seconds
Started Jul 12 06:40:09 PM PDT 24
Finished Jul 12 06:40:11 PM PDT 24
Peak memory 208868 kb
Host smart-3cf4c78e-7868-4baf-8ba4-f21c1a4be7f7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394351372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2394351372
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3438888811
Short name T479
Test name
Test status
Simulation time 902947169 ps
CPU time 29.37 seconds
Started Jul 12 06:40:17 PM PDT 24
Finished Jul 12 06:40:51 PM PDT 24
Peak memory 208544 kb
Host smart-fe748605-90fb-4739-af3a-ed3a404f41eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438888811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3438888811
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3742730971
Short name T735
Test name
Test status
Simulation time 269974897 ps
CPU time 3.26 seconds
Started Jul 12 06:40:10 PM PDT 24
Finished Jul 12 06:40:14 PM PDT 24
Peak memory 208788 kb
Host smart-4dc44d39-4642-45b5-94b5-06dbe40afcb3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742730971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3742730971
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3854850346
Short name T501
Test name
Test status
Simulation time 90844897 ps
CPU time 1.9 seconds
Started Jul 12 06:40:20 PM PDT 24
Finished Jul 12 06:40:27 PM PDT 24
Peak memory 218364 kb
Host smart-f5cdaace-9a5f-4368-b5ea-86e14b69ead7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854850346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3854850346
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3094663653
Short name T621
Test name
Test status
Simulation time 4400570294 ps
CPU time 22.45 seconds
Started Jul 12 06:40:13 PM PDT 24
Finished Jul 12 06:40:39 PM PDT 24
Peak memory 208492 kb
Host smart-4ba1f97e-e728-448f-a765-daf7801fa5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094663653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3094663653
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.79327450
Short name T823
Test name
Test status
Simulation time 398387444 ps
CPU time 8.05 seconds
Started Jul 12 06:40:11 PM PDT 24
Finished Jul 12 06:40:21 PM PDT 24
Peak memory 221240 kb
Host smart-9056c2f6-69f6-444f-9b67-c1f66a05f53a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79327450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.79327450
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.4253003117
Short name T844
Test name
Test status
Simulation time 802955959 ps
CPU time 11.67 seconds
Started Jul 12 06:40:20 PM PDT 24
Finished Jul 12 06:40:37 PM PDT 24
Peak memory 222564 kb
Host smart-ee01ca82-f414-4419-a6d8-edb4912b24d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253003117 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.4253003117
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3051877329
Short name T27
Test name
Test status
Simulation time 204320806 ps
CPU time 3.69 seconds
Started Jul 12 06:40:16 PM PDT 24
Finished Jul 12 06:40:24 PM PDT 24
Peak memory 208376 kb
Host smart-43fee8af-18fb-4430-a8d3-76dd7aa59773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051877329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3051877329
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2429590491
Short name T402
Test name
Test status
Simulation time 1395868978 ps
CPU time 6.99 seconds
Started Jul 12 06:40:12 PM PDT 24
Finished Jul 12 06:40:22 PM PDT 24
Peak memory 209940 kb
Host smart-0a9c2713-1c44-4cdf-9b09-2eda7af0a3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429590491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2429590491
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.251918767
Short name T734
Test name
Test status
Simulation time 12246288 ps
CPU time 0.74 seconds
Started Jul 12 06:40:18 PM PDT 24
Finished Jul 12 06:40:24 PM PDT 24
Peak memory 205988 kb
Host smart-2d2bd21b-e433-4e2f-99d7-dcabb0e3766a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251918767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.251918767
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1411649398
Short name T405
Test name
Test status
Simulation time 656377968 ps
CPU time 5.62 seconds
Started Jul 12 06:40:14 PM PDT 24
Finished Jul 12 06:40:24 PM PDT 24
Peak memory 214336 kb
Host smart-f7cca1e0-f144-44d0-9246-19453ec0f34c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411649398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1411649398
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.827434622
Short name T474
Test name
Test status
Simulation time 95214854 ps
CPU time 2.52 seconds
Started Jul 12 06:40:15 PM PDT 24
Finished Jul 12 06:40:22 PM PDT 24
Peak memory 209012 kb
Host smart-29ec3181-d793-4f17-a459-e48db3cc6042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827434622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.827434622
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.4287713665
Short name T924
Test name
Test status
Simulation time 131030501 ps
CPU time 2.21 seconds
Started Jul 12 06:40:16 PM PDT 24
Finished Jul 12 06:40:23 PM PDT 24
Peak memory 214372 kb
Host smart-c454fefa-b2ed-4355-8793-c9a7c7e1337c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287713665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.4287713665
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.687603944
Short name T34
Test name
Test status
Simulation time 128362829 ps
CPU time 2.06 seconds
Started Jul 12 06:40:15 PM PDT 24
Finished Jul 12 06:40:21 PM PDT 24
Peak memory 214276 kb
Host smart-6c19f91f-054a-466a-8525-5e8de4f8db9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687603944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.687603944
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_random.16424074
Short name T387
Test name
Test status
Simulation time 74008923 ps
CPU time 3.57 seconds
Started Jul 12 06:40:11 PM PDT 24
Finished Jul 12 06:40:17 PM PDT 24
Peak memory 207820 kb
Host smart-e37409dc-fe16-43b4-a5a4-602736c83a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16424074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.16424074
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.698420850
Short name T756
Test name
Test status
Simulation time 156049226 ps
CPU time 2.54 seconds
Started Jul 12 06:40:15 PM PDT 24
Finished Jul 12 06:40:21 PM PDT 24
Peak memory 208600 kb
Host smart-f19bb72d-917f-45ef-99a9-1d7e6b93dd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698420850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.698420850
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.4162641949
Short name T15
Test name
Test status
Simulation time 131168999 ps
CPU time 4.04 seconds
Started Jul 12 06:40:15 PM PDT 24
Finished Jul 12 06:40:23 PM PDT 24
Peak memory 208144 kb
Host smart-1938210f-ec61-47a9-994b-9c366972305e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162641949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.4162641949
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1369933221
Short name T922
Test name
Test status
Simulation time 208928407 ps
CPU time 2.34 seconds
Started Jul 12 06:40:15 PM PDT 24
Finished Jul 12 06:40:22 PM PDT 24
Peak memory 206792 kb
Host smart-57cc0ba4-97de-4381-9cc0-2e19be7edbc9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369933221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1369933221
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1680141736
Short name T783
Test name
Test status
Simulation time 184426202 ps
CPU time 7.31 seconds
Started Jul 12 06:40:16 PM PDT 24
Finished Jul 12 06:40:28 PM PDT 24
Peak memory 208588 kb
Host smart-1c8611b8-ecd3-4bd3-8b4a-6d4ace797169
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680141736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1680141736
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2104693661
Short name T593
Test name
Test status
Simulation time 33670670 ps
CPU time 2.34 seconds
Started Jul 12 06:40:15 PM PDT 24
Finished Jul 12 06:40:22 PM PDT 24
Peak memory 208084 kb
Host smart-dcd34843-f4bb-4af7-a40b-7b3579e8c9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104693661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2104693661
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3527469318
Short name T187
Test name
Test status
Simulation time 1454334250 ps
CPU time 27.04 seconds
Started Jul 12 06:40:12 PM PDT 24
Finished Jul 12 06:40:42 PM PDT 24
Peak memory 208872 kb
Host smart-7f273505-5263-4ac6-acd5-55fc0178aa77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527469318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3527469318
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2103306868
Short name T336
Test name
Test status
Simulation time 3046521821 ps
CPU time 18.85 seconds
Started Jul 12 06:40:15 PM PDT 24
Finished Jul 12 06:40:38 PM PDT 24
Peak memory 215192 kb
Host smart-4f976877-aedc-448c-ac47-d1581b31ee31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103306868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2103306868
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.4281059203
Short name T694
Test name
Test status
Simulation time 589948443 ps
CPU time 4.68 seconds
Started Jul 12 06:40:14 PM PDT 24
Finished Jul 12 06:40:22 PM PDT 24
Peak memory 209868 kb
Host smart-29a0ddfd-f383-47b1-9daf-45f9abdd5e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281059203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.4281059203
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1820530772
Short name T95
Test name
Test status
Simulation time 117720485 ps
CPU time 2.99 seconds
Started Jul 12 06:40:14 PM PDT 24
Finished Jul 12 06:40:21 PM PDT 24
Peak memory 210288 kb
Host smart-2d63afcf-bcf8-4ebb-a1b7-1917376e722b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820530772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1820530772
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2739883508
Short name T921
Test name
Test status
Simulation time 15559364 ps
CPU time 0.94 seconds
Started Jul 12 06:40:17 PM PDT 24
Finished Jul 12 06:40:22 PM PDT 24
Peak memory 206112 kb
Host smart-d30101b7-0656-4aac-b700-32be37a5e694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739883508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2739883508
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1669927293
Short name T386
Test name
Test status
Simulation time 61165563 ps
CPU time 4.23 seconds
Started Jul 12 06:40:15 PM PDT 24
Finished Jul 12 06:40:23 PM PDT 24
Peak memory 214348 kb
Host smart-d9c9cad4-ed87-4951-9114-cf9fa269a190
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1669927293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1669927293
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1697468441
Short name T690
Test name
Test status
Simulation time 69736604 ps
CPU time 2.09 seconds
Started Jul 12 06:40:15 PM PDT 24
Finished Jul 12 06:40:22 PM PDT 24
Peak memory 222812 kb
Host smart-5443211e-5c0c-4760-924c-52451f0e0d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697468441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1697468441
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1011284127
Short name T557
Test name
Test status
Simulation time 522661448 ps
CPU time 3.13 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:36 PM PDT 24
Peak memory 208660 kb
Host smart-71e1f356-9840-443e-bc68-c66d34172de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011284127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1011284127
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3137624225
Short name T785
Test name
Test status
Simulation time 50351971 ps
CPU time 3.39 seconds
Started Jul 12 06:40:13 PM PDT 24
Finished Jul 12 06:40:20 PM PDT 24
Peak memory 214384 kb
Host smart-0ac14b70-84d3-4a35-a0b3-e7786921056f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137624225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3137624225
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.4080015933
Short name T892
Test name
Test status
Simulation time 346435184 ps
CPU time 3.98 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:35 PM PDT 24
Peak memory 214264 kb
Host smart-6d6f4edf-6a00-43e3-98ac-e3bcb646cce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080015933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.4080015933
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3493533810
Short name T232
Test name
Test status
Simulation time 369604553 ps
CPU time 2.91 seconds
Started Jul 12 06:40:14 PM PDT 24
Finished Jul 12 06:40:22 PM PDT 24
Peak memory 214968 kb
Host smart-64bdc4ba-87cc-4cf9-9087-c8cc9b69b86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493533810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3493533810
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3128753348
Short name T871
Test name
Test status
Simulation time 109636409 ps
CPU time 4.52 seconds
Started Jul 12 06:40:14 PM PDT 24
Finished Jul 12 06:40:23 PM PDT 24
Peak memory 214312 kb
Host smart-63db294a-c64f-47b8-86f9-bf9c47df5f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128753348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3128753348
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2237168277
Short name T273
Test name
Test status
Simulation time 279291393 ps
CPU time 3.9 seconds
Started Jul 12 06:40:15 PM PDT 24
Finished Jul 12 06:40:23 PM PDT 24
Peak memory 208676 kb
Host smart-5d53a582-3089-49fc-8375-9654a7edd6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237168277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2237168277
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1747751952
Short name T312
Test name
Test status
Simulation time 1221058014 ps
CPU time 32.47 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:41:04 PM PDT 24
Peak memory 208752 kb
Host smart-1e9f0617-eba8-45a1-9263-212a1041bad7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747751952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1747751952
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3327306713
Short name T774
Test name
Test status
Simulation time 94524127 ps
CPU time 4.11 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:37 PM PDT 24
Peak memory 208424 kb
Host smart-4b32535c-b4b5-4f1c-bf6d-60cfe71a53fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327306713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3327306713
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3448290769
Short name T664
Test name
Test status
Simulation time 210685550 ps
CPU time 6.4 seconds
Started Jul 12 06:40:29 PM PDT 24
Finished Jul 12 06:40:39 PM PDT 24
Peak memory 208068 kb
Host smart-49240bd5-e7d5-4ab5-bca7-07ccb45e922e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448290769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3448290769
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1967442284
Short name T870
Test name
Test status
Simulation time 682090606 ps
CPU time 7.56 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:40 PM PDT 24
Peak memory 214248 kb
Host smart-5e03a4f7-a9eb-48f1-9fc0-588d57ea3541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967442284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1967442284
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.822456334
Short name T607
Test name
Test status
Simulation time 274755874 ps
CPU time 5.22 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:38 PM PDT 24
Peak memory 207892 kb
Host smart-9ff3bb67-79f0-4e52-abef-181add2e54db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822456334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.822456334
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1891186636
Short name T913
Test name
Test status
Simulation time 4561883876 ps
CPU time 26.08 seconds
Started Jul 12 06:40:20 PM PDT 24
Finished Jul 12 06:40:52 PM PDT 24
Peak memory 220684 kb
Host smart-c9c97907-c1b7-4248-b42d-52aca482e248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891186636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1891186636
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2382211643
Short name T64
Test name
Test status
Simulation time 2626848648 ps
CPU time 26.04 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:59 PM PDT 24
Peak memory 221348 kb
Host smart-1bab1bbf-57be-42a6-afc1-b08d34b8c500
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382211643 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2382211643
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3590143803
Short name T515
Test name
Test status
Simulation time 1813707154 ps
CPU time 5.39 seconds
Started Jul 12 06:40:28 PM PDT 24
Finished Jul 12 06:40:38 PM PDT 24
Peak memory 210148 kb
Host smart-128fe3fe-dab0-46a6-9f55-0214ba277d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590143803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3590143803
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3560374543
Short name T422
Test name
Test status
Simulation time 129689660 ps
CPU time 2.02 seconds
Started Jul 12 06:40:15 PM PDT 24
Finished Jul 12 06:40:22 PM PDT 24
Peak memory 209756 kb
Host smart-4f13fee8-2804-4fb1-9c09-44f73fc54f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560374543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3560374543
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%