Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4605

1

T1

3

T2

5

T3

13

auto[1]

567

1

T1

1

T15

1

T20

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4605

1

T1

3

T2

5

T3

13

auto[1]

567

1

T1

1

T15

1

T20

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4626

1

T1

3

T2

5

T3

11

auto[1]

546

1

T1

1

T3

2

T20

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4626

1

T1

3

T2

5

T3

11

auto[1]

546

1

T1

1

T3

2

T20

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	411	1			T1	1		T15	1		T19	1
auto[OpGenId]	1059	1			T1	3		T2	1		T4	2
auto[OpGenSwOut]	1113	1			T2	3		T5	4		T4	2
auto[OpGenHwOut]	2524	1			T2	1		T3	13		T5	1
auto[OpDisable]	65	1			T4	1		T51	2		T64	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	411	1			T1	1		T15	1		T19	1
auto[OpGenId]	1059	1			T1	3		T2	1		T4	2
auto[OpGenSwOut]	1113	1			T2	3		T5	4		T4	2
auto[OpGenHwOut]	2524	1			T2	1		T3	13		T5	1
auto[OpDisable]	65	1			T4	1		T51	2		T64	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4650

1

T1

3

T2

5

T3

13

auto[1]

522

1

T1

1

T4

3

T16

2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4650

1

T1

3

T2

5

T3

13

auto[1]

522

1

T1

1

T4

3

T16

2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4873

1

T1

4

T2

5

T3

13

auto[1]

299

1

T119

5

T120

20

T148

6

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1786	1			T1	3		T2	2		T3	3
auto[1]	700	1			T5	1		T4	2		T16	1
auto[2]	672	1			T2	1		T3	3		T4	1
auto[3]	692	1			T3	4		T5	1		T4	1
auto[4]	311	1			T17	1		T86	2		T44	1
auto[5]	333	1			T2	2		T3	1		T16	2
auto[6]	359	1			T3	2		T5	1		T131	1
auto[7]	319	1			T1	1		T16	1		T87	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1322	1			T1	1		T2	2		T3	3
clear_one[1]	700	1			T5	1		T4	2		T16	1
clear_one[2]	672	1			T2	1		T3	3		T4	1
clear_one[3]	692	1			T3	4		T5	1		T4	1
clear_none	1786	1			T1	3		T2	2		T3	3

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	959	1			T1	2		T2	2		T3	5
auto[StInit]	618	1			T1	1		T3	1		T15	1
auto[StCreatorRootKey]	542	1			T3	1		T4	1		T15	1
auto[StOwnerIntKey]	478	1			T3	1		T16	1		T86	1
auto[StOwnerKey]	439	1			T3	1		T86	1		T87	1
auto[StDisabled]	1807	1			T1	1		T3	4		T4	2
auto[StInvalid]	329	1			T2	3		T5	3		T17	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	959	1			T1	2		T2	2		T3	5
auto[StInit]	618	1			T1	1		T3	1		T15	1
auto[StCreatorRootKey]	542	1			T3	1		T4	1		T15	1
auto[StOwnerIntKey]	478	1			T3	1		T16	1		T86	1
auto[StOwnerKey]	439	1			T3	1		T86	1		T87	1
auto[StDisabled]	1807	1			T1	1		T3	4		T4	2
auto[StInvalid]	329	1			T2	3		T5	3		T17	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[0] - auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[2] - auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	5
[auto[2] - auto[6]]	[auto[StReset]]	[auto[OpDisable]]	--	--	5
[auto[2] - auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	20
[auto[2] - auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	5
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[7]]	[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T120	1		T245	1		T246	1
auto[0]	auto[StReset]	auto[OpGenId]	161	1			T1	1		T4	1		T17	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	149	1			T2	1		T5	1		T16	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	257	1			T3	2		T5	1		T17	1
auto[0]	auto[StInit]	auto[OpAdvance]	42	1			T1	1		T15	1		T87	1
auto[0]	auto[StInit]	auto[OpGenId]	82	1			T16	1		T19	1		T134	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	78	1			T131	1		T52	1		T199	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	189	1			T3	1		T86	1		T44	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	19	1			T215	1		T132	1		T247	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	62	1			T15	1		T120	1		T84	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	48	1			T65	1		T136	1		T68	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	63	1			T218	1		T212	1		T248	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	17	1			T199	1		T6	1		T222	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	19	1			T249	1		T126	1		T250	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	33	1			T130	1		T204	1		T135	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	49	1			T56	1		T212	1		T248	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	12	1			T119	1		T107	1		T251	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	19	1			T55	1		T206	1		T43	2
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T131	1		T252	1		T253	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	47	1			T199	1		T112	1		T254	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	19	1			T199	1		T206	1		T207	1
auto[0]	auto[StDisabled]	auto[OpGenId]	62	1			T1	1		T16	1		T44	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	75	1			T20	1		T28	1		T56	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	165	1			T55	1		T27	1		T199	1
auto[0]	auto[StDisabled]	auto[OpDisable]	11	1			T51	1		T255	1		T256	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	13	1			T81	1		T257	1		T191	1
auto[0]	auto[StInvalid]	auto[OpGenId]	21	1			T2	1		T258	1		T79	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	27	1			T47	1		T79	1		T259	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	30	1			T17	1		T46	1		T260	2
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T261	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	16	1			T94	1		T258	2		T262	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	22	1			T82	1		T67	1		T263	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	57	1			T44	1		T212	1		T217	2
auto[1]	auto[StInit]	auto[OpAdvance]	6	1			T72	1		T154	1		T261	1
auto[1]	auto[StInit]	auto[OpGenId]	10	1			T27	1		T216	1		T264	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	8	1			T27	1		T137	1		T43	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	26	1			T18	1		T199	1		T265	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T266	1		T73	1		T74	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T42	1		T267	1		T268	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T4	1		T200	1		T269	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	28	1			T270	1		T271	1		T138	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T148	1		T43	1		T138	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T272	1		T273	1		T73	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T16	1		T138	1		T274	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	29	1			T213	1		T83	1		T112	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	15	1			T120	5		T43	1		T275	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	13	1			T204	1		T218	1		T276	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	22	1			T70	1		T189	1		T277	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T148	1		T196	1		T198	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	24	1			T148	1		T199	1		T216	1
auto[1]	auto[StDisabled]	auto[OpGenId]	54	1			T55	1		T56	1		T199	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	58	1			T136	1		T120	3		T148	2
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	136	1			T86	1		T208	1		T209	1
auto[1]	auto[StDisabled]	auto[OpDisable]	13	1			T4	1		T82	1		T42	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	8	1			T258	1		T79	1		T92	1
auto[1]	auto[StInvalid]	auto[OpGenId]	14	1			T278	1		T81	1		T92	2
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T5	1		T258	1		T79	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T258	1		T260	1		T279	1
auto[2]	auto[StReset]	auto[OpGenId]	23	1			T44	1		T269	1		T280	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	17	1			T56	1		T22	1		T42	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	29	1			T281	1		T282	1		T283	1
auto[2]	auto[StInit]	auto[OpAdvance]	10	1			T19	1		T119	1		T94	1
auto[2]	auto[StInit]	auto[OpGenId]	7	1			T43	1		T26	2		T284	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	6	1			T285	1		T128	1		T286	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	18	1			T44	1		T270	1		T287	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T137	1		T40	1		T288	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T86	1		T119	1		T69	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T289	1		T290	1		T291	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	49	1			T3	1		T131	1		T135	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T119	1		T292	2		T222	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T214	1		T137	1		T268	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T210	1		T221	1		T293	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	35	1			T80	1		T109	1		T294	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T295	1		T243	1		T296	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	10	1			T136	1		T199	1		T132	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T135	1		T42	1		T250	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	32	1			T44	1		T209	1		T213	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	24	1			T44	1		T119	1		T135	1
auto[2]	auto[StDisabled]	auto[OpGenId]	49	1			T16	1		T51	1		T119	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	53	1			T4	1		T87	1		T130	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	171	1			T3	2		T86	1		T44	1
auto[2]	auto[StDisabled]	auto[OpDisable]	11	1			T134	1		T52	1		T82	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	3	1			T297	2		T298	1		-	-
auto[2]	auto[StInvalid]	auto[OpGenId]	14	1			T17	1		T258	1		T85	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	18	1			T2	1		T47	2		T258	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T278	1		T192	1		T93	1
auto[3]	auto[StReset]	auto[OpGenId]	13	1			T4	1		T22	1		T42	2
auto[3]	auto[StReset]	auto[OpGenSwOut]	14	1			T17	1		T27	1		T207	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	40	1			T3	2		T27	2		T208	1
auto[3]	auto[StInit]	auto[OpAdvance]	2	1			T242	1		T299	1		-	-
auto[3]	auto[StInit]	auto[OpGenId]	10	1			T64	1		T69	1		T269	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	13	1			T42	1		T251	1		T300	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	20	1			T83	1		T42	1		T112	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T262	1		T301	1		T302	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T70	1		T303	1		T304	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T27	1		T285	1		T220	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T44	1		T27	1		T83	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T43	1		T8	1		T193	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T86	1		T22	1		T8	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T120	1		T189	1		T100	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T208	1		T196	1		T110	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T293	1		T305	1		T237	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	15	1			T82	1		T43	1		T306	2
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T87	1		T60	1		T307	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T201	1		T120	2		T248	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	23	1			T204	1		T218	1		T6	1
auto[3]	auto[StDisabled]	auto[OpGenId]	55	1			T131	1		T199	1		T42	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	45	1			T199	1		T276	1		T43	2
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	165	1			T3	2		T55	1		T208	1
auto[3]	auto[StDisabled]	auto[OpDisable]	12	1			T64	1		T65	1		T280	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	10	1			T85	1		T92	1		T91	1
auto[3]	auto[StInvalid]	auto[OpGenId]	16	1			T308	1		T259	1		T191	2
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T5	1		T93	1		T297	2
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	21	1			T17	1		T278	1		T81	1
auto[4]	auto[StReset]	auto[OpGenId]	7	1			T126	1		T305	1		T309	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	6	1			T69	1		T78	1		T310	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	22	1			T311	1		T190	1		T312	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T281	1		T286	1		T313	1
auto[4]	auto[StInit]	auto[OpGenId]	3	1			T314	1		T315	1		T234	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	2	1			T193	1		T170	1		-	-
auto[4]	auto[StInit]	auto[OpGenHwOut]	14	1			T217	1		T42	1		T60	2
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T316	1		T317	1		T318	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T319	1		T219	1		T320	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T126	1		T321	1		T242	2
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T209	1		T112	1		T322	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T238	1		T323	1		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T107	1		T187	1		T324	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T44	1		T251	1		T277	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T211	1		T252	1		T48	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T72	1		T325	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	6	1			T43	1		T326	1		T288	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T86	1		T60	1		T222	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	14	1			T211	1		T327	1		T282	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	8	1			T328	1		T316	1		T73	1
auto[4]	auto[StDisabled]	auto[OpGenId]	17	1			T250	1		T329	1		T330	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T86	1		T269	1		T193	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	74	1			T208	1		T248	1		T211	1
auto[4]	auto[StDisabled]	auto[OpDisable]	8	1			T51	1		T78	1		T42	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T46	1		T331	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T308	1		T332	1		T333	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T17	1		T92	1		T334	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T81	1		T260	1		T279	1
auto[5]	auto[StReset]	auto[OpGenId]	7	1			T201	1		T335	1		T288	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	10	1			T16	1		T55	1		T269	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	21	1			T2	1		T55	1		T211	1
auto[5]	auto[StInit]	auto[OpAdvance]	3	1			T336	1		T233	1		T337	1
auto[5]	auto[StInit]	auto[OpGenId]	8	1			T283	1		T60	1		T72	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	6	1			T8	1		T338	1		T50	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	10	1			T212	1		T96	1		T339	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T336	1		T98	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T16	1		T67	1		T48	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T37	1		T193	1		T128	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T208	1		T327	1		T340	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T27	1		T341	1		T342	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T82	1		T295	1		T343	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T131	1		-	-		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T3	1		T344	1		T345	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T242	1		-	-		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	7	1			T222	1		T72	1		T346	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T286	1		T347	1		T348	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T212	1		T349	1		T190	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	10	1			T199	1		T276	1		T350	1
auto[5]	auto[StDisabled]	auto[OpGenId]	25	1			T120	2		T43	1		T262	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	37	1			T135	1		T136	1		T120	2
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	75	1			T212	1		T248	1		T196	1
auto[5]	auto[StDisabled]	auto[OpDisable]	3	1			T290	1		T351	1		T241	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	5	1			T352	1		T353	2		T354	1
auto[5]	auto[StInvalid]	auto[OpGenId]	5	1			T334	1		T355	1		T356	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T2	1		T85	1		T357	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T308	1		T358	1		T359	1
auto[6]	auto[StReset]	auto[OpGenId]	6	1			T283	1		T288	1		T74	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	10	1			T64	1		T56	1		T194	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	26	1			T3	1		T56	1		T42	1
auto[6]	auto[StInit]	auto[OpAdvance]	4	1			T148	1		T8	1		T360	1
auto[6]	auto[StInit]	auto[OpGenId]	5	1			T361	1		T73	1		T96	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	3	1			T135	1		T33	1		T362	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	9	1			T63	1		T327	1		T221	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T341	2		T266	1		T286	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	1	1			T193	1		-	-		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T148	1		T363	1		T329	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	24	1			T70	1		T364	1		T344	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T266	2		T365	1		T246	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T199	1		T194	1		T288	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T341	1		T266	1		T283	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T217	1		T366	1		T266	2
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T267	1		T266	1		T367	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	3	1			T60	1		T368	1		T50	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T199	1		T369	1		T370	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T3	1		T199	1		T216	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	9	1			T268	4		T194	1		T371	2
auto[6]	auto[StDisabled]	auto[OpGenId]	39	1			T134	1		T199	1		T42	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T43	1		T250	1		T60	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	84	1			T131	1		T212	1		T211	1
auto[6]	auto[StDisabled]	auto[OpDisable]	1	1			T372	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T278	1		T297	1		T373	1
auto[6]	auto[StInvalid]	auto[OpGenId]	8	1			T85	1		T257	1		T374	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T5	1		T46	1		T332	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T94	1		T278	1		T333	1
auto[7]	auto[StReset]	auto[OpGenId]	11	1			T1	1		T16	1		T78	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	7	1			T229	1		T375	1		T376	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	24	1			T208	1		T217	1		T377	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T273	1		T378	1		T379	1
auto[7]	auto[StInit]	auto[OpGenId]	2	1			T288	1		T320	1		-	-
auto[7]	auto[StInit]	auto[OpGenSwOut]	5	1			T309	2		T219	1		T315	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	11	1			T207	1		T380	1		T381	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T328	1		T186	1		T317	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T326	1		T222	1		T273	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T254	1		T274	1		T48	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T217	1		T349	1		T43	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T43	1		T382	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T193	1		T221	1		T375	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T43	1		T60	1		T222	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T209	1		T111	1		T70	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	2	1			T8	1		T383	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T384	1		T288	1		T74	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T208	1		T83	1		T111	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	17	1			T87	1		T213	1		T137	2
auto[7]	auto[StDisabled]	auto[OpGenId]	25	1			T44	1		T218	1		T67	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T213	1		T210	1		T109	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	68	1			T208	1		T209	1		T212	1
auto[7]	auto[StDisabled]	auto[OpDisable]	6	1			T385	1		T76	1		T386	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	1	1			T387	1		-	-		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	4	1			T85	1		T298	1		T89	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T333	1		T358	1		T388	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T278	1		T298	1		T389	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1322

1

T1

1

T2

2

T3

3

clear_one[1]

auto[0]

auto[0]

auto[0]

429

1

T5

1

T16

1

T18

1

clear_one[1]

auto[0]

auto[0]

auto[1]

121

1

T4

2

T86

1

T218

1

clear_one[1]

auto[0]

auto[1]

auto[0]

125

1

T120

8

T217

1

T83

2

clear_one[1]

auto[0]

auto[1]

auto[1]

25

1

T55

1

T120

4

T206

2

clear_one[2]

auto[0]

auto[0]

auto[0]

381

1

T2

1

T3

3

T17

1

clear_one[2]

auto[0]

auto[0]

auto[1]

121

1

T4

1

T16

1

T86

1

clear_one[2]

auto[1]

auto[0]

auto[0]

127

1

T44

1

T119

1

T131

1

clear_one[2]

auto[1]

auto[0]

auto[1]

43

1

T44

1

T119

4

T215

1

clear_one[3]

auto[0]

auto[0]

auto[0]

409

1

T3

2

T5

1

T4

1

clear_one[3]

auto[0]

auto[1]

auto[0]

119

1

T3

2

T27

1

T131

1

clear_one[3]

auto[1]

auto[0]

auto[0]

125

1

T44

1

T208

2

T201

1

clear_one[3]

auto[1]

auto[1]

auto[0]

39

1

T55

1

T42

2

T276

1

clear_none

auto[0]

auto[0]

auto[0]

1266

1

T1

2

T2

2

T3

3

clear_none

auto[0]

auto[0]

auto[1]

111

1

T16

1

T27

2

T130

1

clear_none

auto[0]

auto[1]

auto[0]

145

1

T131

1

T211

2

T83

1

clear_none

auto[0]

auto[1]

auto[1]

31

1

T131

1

T206

1

T390

1

clear_none

auto[1]

auto[0]

auto[0]

128

1

T15

1

T248

3

T80

3

clear_none

auto[1]

auto[0]

auto[1]

43

1

T28

1

T218

1

T199

2

clear_none

auto[1]

auto[1]

auto[0]

35

1

T20

1

T44

1

T43

2

clear_none

auto[1]

auto[1]

auto[1]

27

1

T1

1

T55

2

T56

2

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1243	1			T1	1		T2	2		T3	3
clear_all	auto[1]	79	1			T120	3		T148	1		T137	3
clear_one[1]	auto[0]	642	1			T5	1		T4	2		T16	1
clear_one[1]	auto[1]	58	1			T120	11		T148	4		T275	2
clear_one[2]	auto[0]	647	1			T2	1		T3	3		T4	1
clear_one[2]	auto[1]	25	1			T119	5		T148	1		T137	2
clear_one[3]	auto[0]	653	1			T3	4		T5	1		T4	1
clear_one[3]	auto[1]	39	1			T120	2		T292	2		T384	1
clear_none	auto[0]	1688	1			T1	3		T2	2		T3	3
clear_none	auto[1]	98	1			T120	4		T275	1		T138	1