Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10630

1

T1

12

T2

13

T3

14

auto[Attestation]

7153

1

T1

13

T3

5

T5

9

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2544	1			T1	4		T2	3		T5	3
auto[Aes]	3205	1			T1	7		T2	2		T5	1
auto[Kmac]	3301	1			T1	4		T2	4		T3	19
auto[Otbn]	3209	1			T1	4		T2	1		T5	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7136	1			T1	8		T2	1		T3	8
auto[OpGenId]	5524	1			T1	6		T2	3		T5	7
auto[OpGenSwOut]	5524	1			T1	7		T2	3		T5	5
auto[OpGenHwOut]	6735	1			T1	12		T2	7		T3	19
auto[OpDisable]	129	1			T4	1		T20	1		T44	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9961

1

T1

15

T2

1

T3

8

auto[OpDoneFail]

15087

1

T1

18

T2

13

T3

19

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6203	1			T1	7		T2	14		T3	12
auto[StInit]	3445	1			T1	1		T3	2		T5	2
auto[StCreatorRootKey]	2962	1			T1	5		T3	2		T4	4
auto[StOwnerIntKey]	2679	1			T1	6		T3	2		T15	4
auto[StOwnerKey]	2252	1			T1	2		T3	2		T15	5
auto[StDisabled]	7507	1			T1	12		T3	7		T4	1

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	324	1			T2	1		T5	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	82	1			T55	1		T44	1		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	92	1			T1	1		T15	1		T119	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	72	1			T16	1		T20	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	62	1			T86	1		T63	1		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	195	1			T1	1		T4	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	309	1			T2	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	97	1			T35	1		T27	1		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	67	1			T129	1		T200	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	77	1			T55	1		T201	1		T84	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	51	1			T1	1		T87	1		T27	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	221	1			T16	1		T44	1		T28	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	324	1			T2	1		T4	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	85	1			T44	1		T51	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	81	1			T55	1		T64	1		T135	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	71	1			T27	1		T28	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	46	1			T44	1		T135	1		T202	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	198	1			T55	2		T44	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	331	1			T5	1		T4	4		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	101	1			T27	1		T131	1		T43	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	81	1			T87	1		T44	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T44	1		T120	1		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	49	1			T15	1		T27	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	202	1			T1	1		T44	2		T27	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	72	1			T5	2		T17	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	90	1			T19	1		T20	1		T27	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	75	1			T135	1		T200	1		T203	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	71	1			T1	1		T131	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	46	1			T199	1		T42	1		T109	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	200	1			T87	1		T44	1		T27	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	80	1			T5	1		T17	1		T27	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	98	1			T27	1		T51	1		T119	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	77	1			T1	1		T4	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	65	1			T15	1		T44	2		T130	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	65	1			T63	1		T205	1		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	186	1			T86	1		T27	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	59	1			T44	1		T71	1		T207	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	69	1			T19	1		T27	2		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	82	1			T44	2		T27	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T55	1		T44	2		T135	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	74	1			T27	1		T130	1		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	189	1			T1	1		T16	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	66	1			T44	1		T27	1		T42	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	91	1			T17	1		T27	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T44	1		T136	1		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	74	1			T16	1		T55	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	61	1			T15	1		T55	2		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	187	1			T16	1		T20	1		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	214	1			T2	2		T16	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	82	1			T29	1		T57	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	70	1			T18	1		T204	1		T134	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	60	1			T16	1		T28	1		T131	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	46	1			T15	1		T20	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	174	1			T44	1		T27	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	433	1			T2	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	119	1			T19	1		T44	1		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	110	1			T15	1		T16	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	82	1			T1	1		T20	1		T209	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	86	1			T15	1		T208	1		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	267	1			T16	1		T20	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	537	1			T1	2		T2	3		T3	11
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	102	1			T3	1		T44	1		T204	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T3	1		T16	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	90	1			T15	1		T44	1		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	87	1			T211	1		T82	2		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	286	1			T3	1		T55	2		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	457	1			T1	1		T2	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	111	1			T18	1		T86	1		T44	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T1	1		T64	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	106	1			T55	1		T130	1		T212	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	88	1			T27	2		T201	2		T199	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	233	1			T16	2		T86	1		T55	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	59	1			T17	1		T27	1		T8	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	104	1			T19	1		T44	2		T51	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	70	1			T44	1		T64	1		T135	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	50	1			T213	1		T214	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	47	1			T204	1		T215	2		T216	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	187	1			T1	1		T27	1		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	67	1			T17	1		T44	1		T27	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	93	1			T44	1		T45	1		T119	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	99	1			T15	1		T18	1		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	106	1			T1	1		T55	1		T28	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	84	1			T15	1		T44	1		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	266	1			T1	3		T44	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	65	1			T5	1		T17	2		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	120	1			T19	2		T44	1		T65	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	101	1			T1	1		T44	1		T217	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	106	1			T3	1		T63	1		T56	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	77	1			T3	1		T55	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	275	1			T3	3		T130	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	56	1			T5	1		T27	2		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	113	1			T4	1		T19	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	87	1			T4	1		T28	1		T218	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	88	1			T1	1		T44	1		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	73	1			T44	1		T27	1		T120	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	286	1			T16	1		T86	1		T87	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	210	1			T1	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	617	1			T1	1		T2	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	180	1			T1	1		T87	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	642	1			T2	1		T16	2		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	184	1			T55	1		T44	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	621	1			T2	1		T4	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	189	1			T15	1		T87	1		T44	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	645	1			T1	1		T5	1		T4	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	179	1			T1	1		T131	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	375	1			T5	2		T17	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	194	1			T1	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	377	1			T5	1		T17	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	213	1			T55	1		T44	4		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	334	1			T1	1		T16	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	205	1			T15	1		T16	1		T55	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	359	1			T16	1		T17	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	166	1			T15	1		T16	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	480	1			T2	2		T16	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	260	1			T1	1		T15	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	837	1			T2	1		T16	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	264	1			T3	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	941	1			T1	2		T2	3		T3	13
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	289	1			T1	1		T55	1		T27	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	819	1			T1	1		T2	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	154	1			T44	1		T64	1		T135	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	363	1			T1	1		T17	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	275	1			T1	1		T15	2		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	440	1			T1	3		T17	1		T44	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	261	1			T1	1		T3	2		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	483	1			T3	3		T5	1		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	234	1			T1	1		T4	1		T44	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	469	1			T5	1		T4	1		T16	1