Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31144

1

T1

36

T2

46

T3

33

auto[1]

295

1

T119

3

T120

16

T148

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31155	1			T1	36		T2	46		T3	33
auto[134217728:268435455]	5	1			T341	1		T268	1		T245	1
auto[268435456:402653183]	13	1			T120	1		T414	1		T371	1
auto[402653184:536870911]	9	1			T119	1		T341	1		T266	1
auto[536870912:671088639]	8	1			T137	1		T268	1		T397	1
auto[671088640:805306367]	12	1			T350	1		T268	1		T415	1
auto[805306368:939524095]	12	1			T138	1		T266	1		T382	1
auto[939524096:1073741823]	6	1			T120	1		T350	1		T414	1
auto[1073741824:1207959551]	8	1			T137	1		T268	1		T309	1
auto[1207959552:1342177279]	9	1			T120	1		T341	1		T306	3
auto[1342177280:1476395007]	14	1			T119	1		T268	1		T416	2
auto[1476395008:1610612735]	7	1			T120	1		T341	2		T382	1
auto[1610612736:1744830463]	13	1			T138	1		T140	1		T266	1
auto[1744830464:1879048191]	14	1			T292	1		T341	1		T384	1
auto[1879048192:2013265919]	10	1			T292	1		T306	1		T397	1
auto[2013265920:2147483647]	7	1			T306	1		T371	1		T309	1
auto[2147483648:2281701375]	6	1			T120	1		T306	1		T416	1
auto[2281701376:2415919103]	11	1			T120	1		T292	1		T341	1
auto[2415919104:2550136831]	4	1			T140	1		T350	2		T306	1
auto[2550136832:2684354559]	8	1			T120	1		T341	1		T415	1
auto[2684354560:2818572287]	9	1			T138	1		T382	1		T306	1
auto[2818572288:2952790015]	2	1			T350	1		T309	1		-	-
auto[2952790016:3087007743]	7	1			T119	1		T341	1		T415	1
auto[3087007744:3221225471]	13	1			T341	1		T350	1		T384	1
auto[3221225472:3355443199]	10	1			T120	1		T341	2		T397	1
auto[3355443200:3489660927]	12	1			T120	3		T148	1		T137	1
auto[3489660928:3623878655]	8	1			T120	1		T138	1		T140	1
auto[3623878656:3758096383]	9	1			T292	1		T273	1		T245	2
auto[3758096384:3892314111]	7	1			T120	1		T275	1		T400	1
auto[3892314112:4026531839]	11	1			T140	1		T415	1		T306	1
auto[4026531840:4160749567]	13	1			T275	1		T266	1		T384	1
auto[4160749568:4294967295]	7	1			T120	1		T341	2		T350	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31144	1			T1	36		T2	46		T3	33
auto[0:134217727]	auto[1]	11	1			T120	2		T292	1		T266	1
auto[134217728:268435455]	auto[1]	5	1			T341	1		T268	1		T245	1
auto[268435456:402653183]	auto[1]	13	1			T120	1		T414	1		T371	1
auto[402653184:536870911]	auto[1]	9	1			T119	1		T341	1		T266	1
auto[536870912:671088639]	auto[1]	8	1			T137	1		T268	1		T397	1
auto[671088640:805306367]	auto[1]	12	1			T350	1		T268	1		T415	1
auto[805306368:939524095]	auto[1]	12	1			T138	1		T266	1		T382	1
auto[939524096:1073741823]	auto[1]	6	1			T120	1		T350	1		T414	1
auto[1073741824:1207959551]	auto[1]	8	1			T137	1		T268	1		T309	1
auto[1207959552:1342177279]	auto[1]	9	1			T120	1		T341	1		T306	3
auto[1342177280:1476395007]	auto[1]	14	1			T119	1		T268	1		T416	2
auto[1476395008:1610612735]	auto[1]	7	1			T120	1		T341	2		T382	1
auto[1610612736:1744830463]	auto[1]	13	1			T138	1		T140	1		T266	1
auto[1744830464:1879048191]	auto[1]	14	1			T292	1		T341	1		T384	1
auto[1879048192:2013265919]	auto[1]	10	1			T292	1		T306	1		T397	1
auto[2013265920:2147483647]	auto[1]	7	1			T306	1		T371	1		T309	1
auto[2147483648:2281701375]	auto[1]	6	1			T120	1		T306	1		T416	1
auto[2281701376:2415919103]	auto[1]	11	1			T120	1		T292	1		T341	1
auto[2415919104:2550136831]	auto[1]	4	1			T140	1		T350	2		T306	1
auto[2550136832:2684354559]	auto[1]	8	1			T120	1		T341	1		T415	1
auto[2684354560:2818572287]	auto[1]	9	1			T138	1		T382	1		T306	1
auto[2818572288:2952790015]	auto[1]	2	1			T350	1		T309	1		-	-
auto[2952790016:3087007743]	auto[1]	7	1			T119	1		T341	1		T415	1
auto[3087007744:3221225471]	auto[1]	13	1			T341	1		T350	1		T384	1
auto[3221225472:3355443199]	auto[1]	10	1			T120	1		T341	2		T397	1
auto[3355443200:3489660927]	auto[1]	12	1			T120	3		T148	1		T137	1
auto[3489660928:3623878655]	auto[1]	8	1			T120	1		T138	1		T140	1
auto[3623878656:3758096383]	auto[1]	9	1			T292	1		T273	1		T245	2
auto[3758096384:3892314111]	auto[1]	7	1			T120	1		T275	1		T400	1
auto[3892314112:4026531839]	auto[1]	11	1			T140	1		T415	1		T306	1
auto[4026531840:4160749567]	auto[1]	13	1			T275	1		T266	1		T384	1
auto[4160749568:4294967295]	auto[1]	7	1			T120	1		T341	2		T350	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1482

1

T1

3

T2

2

T5

5

auto[1]

1751

1

T1

6

T2

4

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T51	1		T204	1		T42	1
auto[134217728:268435455]	99	1			T2	1		T44	1		T94	1
auto[268435456:402653183]	101	1			T1	1		T20	1		T44	1
auto[402653184:536870911]	95	1			T1	1		T2	1		T18	1
auto[536870912:671088639]	103	1			T27	2		T131	1		T215	2
auto[671088640:805306367]	96	1			T1	1		T4	1		T15	1
auto[805306368:939524095]	110	1			T17	1		T27	1		T28	1
auto[939524096:1073741823]	101	1			T27	1		T130	1		T64	1
auto[1073741824:1207959551]	94	1			T1	1		T5	1		T16	1
auto[1207959552:1342177279]	103	1			T1	1		T4	1		T27	1
auto[1342177280:1476395007]	92	1			T27	1		T94	2		T56	1
auto[1476395008:1610612735]	105	1			T2	1		T17	1		T44	1
auto[1610612736:1744830463]	116	1			T18	1		T20	1		T55	1
auto[1744830464:1879048191]	91	1			T2	1		T5	1		T16	1
auto[1879048192:2013265919]	111	1			T1	1		T5	1		T19	1
auto[2013265920:2147483647]	92	1			T1	1		T20	1		T131	1
auto[2147483648:2281701375]	90	1			T2	1		T5	1		T17	1
auto[2281701376:2415919103]	101	1			T15	1		T44	2		T27	1
auto[2415919104:2550136831]	101	1			T55	3		T44	1		T119	1
auto[2550136832:2684354559]	100	1			T5	1		T4	1		T17	1
auto[2684354560:2818572287]	94	1			T17	1		T19	1		T27	2
auto[2818572288:2952790015]	97	1			T1	1		T44	3		T63	1
auto[2952790016:3087007743]	105	1			T5	1		T18	1		T131	1
auto[3087007744:3221225471]	115	1			T15	1		T19	1		T87	1
auto[3221225472:3355443199]	102	1			T2	1		T44	2		T64	1
auto[3355443200:3489660927]	92	1			T201	1		T135	1		T199	1
auto[3489660928:3623878655]	115	1			T16	1		T17	1		T27	2
auto[3623878656:3758096383]	104	1			T1	1		T5	1		T55	2
auto[3758096384:3892314111]	81	1			T55	1		T27	1		T218	1
auto[3892314112:4026531839]	115	1			T27	1		T119	1		T63	1
auto[4026531840:4160749567]	126	1			T5	1		T16	1		T19	1
auto[4160749568:4294967295]	81	1			T17	1		T87	1		T55	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T51	1		T107	1		T108	1
auto[0:134217727]	auto[1]	63	1			T204	1		T42	1		T70	1
auto[134217728:268435455]	auto[0]	43	1			T2	1		T120	1		T82	1
auto[134217728:268435455]	auto[1]	56	1			T44	1		T94	1		T53	1
auto[268435456:402653183]	auto[0]	36	1			T20	1		T201	1		T200	1
auto[268435456:402653183]	auto[1]	65	1			T1	1		T44	1		T65	1
auto[402653184:536870911]	auto[0]	46	1			T82	1		T42	2		T92	1
auto[402653184:536870911]	auto[1]	49	1			T1	1		T2	1		T18	1
auto[536870912:671088639]	auto[0]	59	1			T27	2		T131	1		T215	1
auto[536870912:671088639]	auto[1]	44	1			T215	1		T206	1		T85	1
auto[671088640:805306367]	auto[0]	42	1			T4	1		T63	1		T85	1
auto[671088640:805306367]	auto[1]	54	1			T1	1		T15	1		T20	1
auto[805306368:939524095]	auto[0]	43	1			T27	1		T130	1		T63	1
auto[805306368:939524095]	auto[1]	67	1			T17	1		T28	1		T199	2
auto[939524096:1073741823]	auto[0]	53	1			T27	1		T130	1		T52	1
auto[939524096:1073741823]	auto[1]	48	1			T64	1		T218	2		T56	1
auto[1073741824:1207959551]	auto[0]	45	1			T5	1		T16	1		T27	1
auto[1073741824:1207959551]	auto[1]	49	1			T1	1		T87	1		T53	1
auto[1207959552:1342177279]	auto[0]	43	1			T27	1		T94	1		T200	1
auto[1207959552:1342177279]	auto[1]	60	1			T1	1		T4	1		T63	1
auto[1342177280:1476395007]	auto[0]	50	1			T27	1		T42	1		T43	1
auto[1342177280:1476395007]	auto[1]	42	1			T94	2		T56	1		T66	1
auto[1476395008:1610612735]	auto[0]	45	1			T17	1		T44	1		T27	1
auto[1476395008:1610612735]	auto[1]	60	1			T2	1		T204	1		T258	1
auto[1610612736:1744830463]	auto[0]	51	1			T18	1		T20	1		T131	1
auto[1610612736:1744830463]	auto[1]	65	1			T55	1		T53	1		T43	1
auto[1744830464:1879048191]	auto[0]	40	1			T5	1		T16	1		T18	1
auto[1744830464:1879048191]	auto[1]	51	1			T2	1		T119	1		T148	1
auto[1879048192:2013265919]	auto[0]	46	1			T5	1		T19	1		T44	1
auto[1879048192:2013265919]	auto[1]	65	1			T1	1		T28	1		T131	2
auto[2013265920:2147483647]	auto[0]	40	1			T1	1		T20	1		T201	1
auto[2013265920:2147483647]	auto[1]	52	1			T131	1		T64	1		T134	1
auto[2147483648:2281701375]	auto[0]	41	1			T2	1		T17	1		T18	1
auto[2147483648:2281701375]	auto[1]	49	1			T5	1		T199	1		T70	1
auto[2281701376:2415919103]	auto[0]	56	1			T44	2		T27	1		T130	1
auto[2281701376:2415919103]	auto[1]	45	1			T15	1		T130	1		T135	1
auto[2415919104:2550136831]	auto[0]	44	1			T119	1		T42	3		T417	1
auto[2415919104:2550136831]	auto[1]	57	1			T55	3		T44	1		T148	1
auto[2550136832:2684354559]	auto[0]	45	1			T17	1		T44	1		T27	2
auto[2550136832:2684354559]	auto[1]	55	1			T5	1		T4	1		T30	1
auto[2684354560:2818572287]	auto[0]	43	1			T17	1		T19	1		T27	1
auto[2684354560:2818572287]	auto[1]	51	1			T27	1		T120	1		T47	1
auto[2818572288:2952790015]	auto[0]	45	1			T1	1		T44	1		T42	1
auto[2818572288:2952790015]	auto[1]	52	1			T44	2		T63	1		T84	1
auto[2952790016:3087007743]	auto[0]	57	1			T5	1		T18	1		T135	1
auto[2952790016:3087007743]	auto[1]	48	1			T131	1		T46	1		T94	1
auto[3087007744:3221225471]	auto[0]	58	1			T215	1		T278	2		T82	1
auto[3087007744:3221225471]	auto[1]	57	1			T15	1		T19	1		T87	1
auto[3221225472:3355443199]	auto[0]	45	1			T46	1		T218	1		T192	1
auto[3221225472:3355443199]	auto[1]	57	1			T2	1		T44	2		T64	1
auto[3355443200:3489660927]	auto[0]	41	1			T201	1		T22	1		T308	1
auto[3355443200:3489660927]	auto[1]	51	1			T135	1		T199	1		T258	1
auto[3489660928:3623878655]	auto[0]	54	1			T17	1		T27	1		T130	1
auto[3489660928:3623878655]	auto[1]	61	1			T16	1		T27	1		T218	1
auto[3623878656:3758096383]	auto[0]	40	1			T1	1		T5	1		T55	1
auto[3623878656:3758096383]	auto[1]	64	1			T55	1		T51	1		T201	1
auto[3758096384:3892314111]	auto[0]	40	1			T55	1		T27	1		T218	1
auto[3758096384:3892314111]	auto[1]	41	1			T206	1		T210	1		T68	1
auto[3892314112:4026531839]	auto[0]	53	1			T47	1		T56	1		T84	1
auto[3892314112:4026531839]	auto[1]	62	1			T27	1		T119	1		T63	1
auto[4026531840:4160749567]	auto[0]	58	1			T19	1		T94	1		T199	1
auto[4026531840:4160749567]	auto[1]	68	1			T5	1		T16	1		T27	2
auto[4160749568:4294967295]	auto[0]	38	1			T17	1		T44	1		T27	1
auto[4160749568:4294967295]	auto[1]	43	1			T87	1		T55	1		T53	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1516

1

T1

2

T2

2

T5

5

auto[1]

1717

1

T1

7

T2

4

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T87	1		T27	2		T201	1
auto[134217728:268435455]	94	1			T15	1		T16	1		T46	1
auto[268435456:402653183]	110	1			T4	1		T16	1		T18	1
auto[402653184:536870911]	98	1			T17	1		T44	1		T213	1
auto[536870912:671088639]	88	1			T1	2		T20	1		T87	1
auto[671088640:805306367]	87	1			T4	1		T44	1		T27	2
auto[805306368:939524095]	107	1			T2	1		T18	1		T27	2
auto[939524096:1073741823]	94	1			T17	1		T44	4		T27	1
auto[1073741824:1207959551]	117	1			T5	1		T19	1		T20	1
auto[1207959552:1342177279]	108	1			T1	1		T5	1		T44	1
auto[1342177280:1476395007]	105	1			T1	1		T18	1		T20	1
auto[1476395008:1610612735]	90	1			T2	1		T5	1		T17	1
auto[1610612736:1744830463]	99	1			T2	1		T55	1		T44	1
auto[1744830464:1879048191]	113	1			T5	1		T18	1		T19	1
auto[1879048192:2013265919]	105	1			T1	2		T5	1		T27	2
auto[2013265920:2147483647]	114	1			T15	1		T16	1		T27	1
auto[2147483648:2281701375]	97	1			T17	1		T44	1		T27	1
auto[2281701376:2415919103]	100	1			T15	1		T44	2		T27	1
auto[2415919104:2550136831]	103	1			T5	1		T55	1		T119	1
auto[2550136832:2684354559]	99	1			T2	1		T18	1		T44	1
auto[2684354560:2818572287]	102	1			T1	1		T2	1		T55	2
auto[2818572288:2952790015]	80	1			T5	1		T17	1		T55	1
auto[2952790016:3087007743]	88	1			T1	1		T27	2		T94	1
auto[3087007744:3221225471]	109	1			T27	2		T200	1		T148	1
auto[3221225472:3355443199]	83	1			T44	1		T27	2		T119	1
auto[3355443200:3489660927]	102	1			T1	1		T17	1		T55	1
auto[3489660928:3623878655]	103	1			T28	1		T63	1		T120	1
auto[3623878656:3758096383]	109	1			T27	1		T63	1		T53	1
auto[3758096384:3892314111]	99	1			T201	1		T53	1		T200	1
auto[3892314112:4026531839]	111	1			T16	1		T17	1		T55	1
auto[4026531840:4160749567]	104	1			T4	1		T55	1		T27	1
auto[4160749568:4294967295]	111	1			T2	1		T5	1		T19	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T27	2		T201	1		T269	1
auto[0:134217727]	auto[1]	61	1			T87	1		T53	1		T120	1
auto[134217728:268435455]	auto[0]	39	1			T16	1		T135	1		T43	1
auto[134217728:268435455]	auto[1]	55	1			T15	1		T46	1		T70	1
auto[268435456:402653183]	auto[0]	57	1			T4	1		T18	1		T27	1
auto[268435456:402653183]	auto[1]	53	1			T16	1		T47	1		T42	1
auto[402653184:536870911]	auto[0]	54	1			T17	1		T44	1		T258	1
auto[402653184:536870911]	auto[1]	44	1			T213	1		T259	1		T62	1
auto[536870912:671088639]	auto[0]	46	1			T1	1		T20	1		T44	1
auto[536870912:671088639]	auto[1]	42	1			T1	1		T87	1		T119	1
auto[671088640:805306367]	auto[0]	42	1			T44	1		T27	2		T94	1
auto[671088640:805306367]	auto[1]	45	1			T4	1		T204	1		T47	1
auto[805306368:939524095]	auto[0]	51	1			T18	1		T27	1		T47	1
auto[805306368:939524095]	auto[1]	56	1			T2	1		T27	1		T148	1
auto[939524096:1073741823]	auto[0]	39	1			T17	1		T44	3		T130	1
auto[939524096:1073741823]	auto[1]	55	1			T44	1		T27	1		T199	1
auto[1073741824:1207959551]	auto[0]	53	1			T5	1		T20	1		T130	1
auto[1073741824:1207959551]	auto[1]	64	1			T19	1		T204	1		T210	1
auto[1207959552:1342177279]	auto[0]	54	1			T1	1		T135	1		T69	1
auto[1207959552:1342177279]	auto[1]	54	1			T5	1		T44	1		T64	1
auto[1342177280:1476395007]	auto[0]	51	1			T63	1		T278	1		T68	1
auto[1342177280:1476395007]	auto[1]	54	1			T1	1		T18	1		T20	1
auto[1476395008:1610612735]	auto[0]	38	1			T2	1		T5	1		T20	1
auto[1476395008:1610612735]	auto[1]	52	1			T17	1		T27	1		T131	1
auto[1610612736:1744830463]	auto[0]	48	1			T55	1		T44	1		T27	1
auto[1610612736:1744830463]	auto[1]	51	1			T2	1		T206	1		T68	1
auto[1744830464:1879048191]	auto[0]	56	1			T19	1		T44	1		T135	1
auto[1744830464:1879048191]	auto[1]	57	1			T5	1		T18	1		T44	1
auto[1879048192:2013265919]	auto[0]	54	1			T27	1		T56	2		T22	1
auto[1879048192:2013265919]	auto[1]	51	1			T1	2		T5	1		T27	1
auto[2013265920:2147483647]	auto[0]	53	1			T16	1		T27	1		T201	1
auto[2013265920:2147483647]	auto[1]	61	1			T15	1		T28	1		T199	1
auto[2147483648:2281701375]	auto[0]	43	1			T17	1		T44	1		T94	2
auto[2147483648:2281701375]	auto[1]	54	1			T27	1		T135	1		T120	1
auto[2281701376:2415919103]	auto[0]	44	1			T15	1		T27	1		T278	1
auto[2281701376:2415919103]	auto[1]	56	1			T44	2		T64	1		T135	2
auto[2415919104:2550136831]	auto[0]	53	1			T5	1		T204	1		T46	1
auto[2415919104:2550136831]	auto[1]	50	1			T55	1		T119	1		T131	2
auto[2550136832:2684354559]	auto[0]	36	1			T18	1		T42	1		T43	1
auto[2550136832:2684354559]	auto[1]	63	1			T2	1		T44	1		T201	1
auto[2684354560:2818572287]	auto[0]	42	1			T55	1		T44	1		T81	1
auto[2684354560:2818572287]	auto[1]	60	1			T1	1		T2	1		T55	1
auto[2818572288:2952790015]	auto[0]	41	1			T5	1		T17	1		T55	1
auto[2818572288:2952790015]	auto[1]	39	1			T44	1		T199	1		T79	1
auto[2952790016:3087007743]	auto[0]	33	1			T27	2		T215	1		T22	1
auto[2952790016:3087007743]	auto[1]	55	1			T1	1		T94	1		T30	1
auto[3087007744:3221225471]	auto[0]	51	1			T27	2		T200	1		T42	3
auto[3087007744:3221225471]	auto[1]	58	1			T148	1		T42	1		T43	1
auto[3221225472:3355443199]	auto[0]	32	1			T27	2		T119	1		T56	1
auto[3221225472:3355443199]	auto[1]	51	1			T44	1		T131	1		T63	1
auto[3355443200:3489660927]	auto[0]	47	1			T17	1		T27	1		T130	1
auto[3355443200:3489660927]	auto[1]	55	1			T1	1		T55	1		T27	2
auto[3489660928:3623878655]	auto[0]	55	1			T63	1		T82	1		T42	2
auto[3489660928:3623878655]	auto[1]	48	1			T28	1		T120	1		T216	1
auto[3623878656:3758096383]	auto[0]	56	1			T27	1		T63	1		T85	1
auto[3623878656:3758096383]	auto[1]	53	1			T53	1		T42	1		T6	1
auto[3758096384:3892314111]	auto[0]	41	1			T200	1		T218	1		T42	1
auto[3758096384:3892314111]	auto[1]	58	1			T201	1		T53	1		T218	1
auto[3892314112:4026531839]	auto[0]	48	1			T17	1		T55	1		T215	1
auto[3892314112:4026531839]	auto[1]	63	1			T16	1		T119	1		T200	1
auto[4026531840:4160749567]	auto[0]	55	1			T27	1		T52	1		T218	1
auto[4026531840:4160749567]	auto[1]	49	1			T4	1		T55	1		T64	1
auto[4160749568:4294967295]	auto[0]	61	1			T2	1		T5	1		T19	2
auto[4160749568:4294967295]	auto[1]	50	1			T87	1		T204	1		T94	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1497

1

T1

5

T2

2

T5

5

auto[1]

1736

1

T1

4

T2

4

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T55	1		T27	1		T204	1
auto[134217728:268435455]	87	1			T1	1		T27	1		T56	2
auto[268435456:402653183]	84	1			T1	1		T18	1		T51	1
auto[402653184:536870911]	99	1			T2	1		T16	1		T19	1
auto[536870912:671088639]	107	1			T17	1		T55	1		T27	2
auto[671088640:805306367]	100	1			T20	1		T44	2		T27	2
auto[805306368:939524095]	103	1			T18	1		T55	1		T44	1
auto[939524096:1073741823]	90	1			T5	1		T55	1		T120	1
auto[1073741824:1207959551]	102	1			T5	1		T87	1		T204	1
auto[1207959552:1342177279]	92	1			T4	1		T27	1		T119	1
auto[1342177280:1476395007]	111	1			T44	1		T27	1		T131	1
auto[1476395008:1610612735]	85	1			T1	1		T5	2		T17	1
auto[1610612736:1744830463]	111	1			T1	1		T27	2		T204	1
auto[1744830464:1879048191]	93	1			T16	1		T27	1		T201	1
auto[1879048192:2013265919]	99	1			T2	1		T44	1		T27	1
auto[2013265920:2147483647]	98	1			T16	1		T44	1		T27	2
auto[2147483648:2281701375]	95	1			T5	1		T55	1		T44	1
auto[2281701376:2415919103]	80	1			T5	1		T44	1		T27	2
auto[2415919104:2550136831]	104	1			T4	1		T18	1		T20	1
auto[2550136832:2684354559]	103	1			T17	1		T19	1		T55	1
auto[2684354560:2818572287]	112	1			T17	1		T55	1		T204	1
auto[2818572288:2952790015]	102	1			T1	1		T87	1		T44	1
auto[2952790016:3087007743]	107	1			T5	1		T15	1		T17	1
auto[3087007744:3221225471]	99	1			T15	1		T28	1		T94	1
auto[3221225472:3355443199]	129	1			T15	1		T55	1		T27	1
auto[3355443200:3489660927]	117	1			T1	1		T2	1		T5	1
auto[3489660928:3623878655]	92	1			T1	1		T119	1		T201	1
auto[3623878656:3758096383]	114	1			T20	1		T44	1		T119	1
auto[3758096384:3892314111]	95	1			T1	1		T2	1		T4	1
auto[3892314112:4026531839]	103	1			T2	1		T17	1		T19	1
auto[4026531840:4160749567]	109	1			T1	1		T2	1		T19	1
auto[4160749568:4294967295]	109	1			T20	1		T44	2		T27	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	36	1			T55	1		T27	1		T260	1
auto[0:134217727]	auto[1]	66	1			T204	1		T218	1		T56	1
auto[134217728:268435455]	auto[0]	40	1			T1	1		T27	1		T278	1
auto[134217728:268435455]	auto[1]	47	1			T56	2		T42	1		T108	1
auto[268435456:402653183]	auto[0]	39	1			T18	1		T51	1		T82	2
auto[268435456:402653183]	auto[1]	45	1			T1	1		T46	1		T43	2
auto[402653184:536870911]	auto[0]	43	1			T16	1		T19	1		T258	1
auto[402653184:536870911]	auto[1]	56	1			T2	1		T134	1		T56	1
auto[536870912:671088639]	auto[0]	56	1			T17	1		T27	2		T200	1
auto[536870912:671088639]	auto[1]	51	1			T55	1		T119	1		T47	1
auto[671088640:805306367]	auto[0]	45	1			T44	1		T27	1		T42	1
auto[671088640:805306367]	auto[1]	55	1			T20	1		T44	1		T27	1
auto[805306368:939524095]	auto[0]	53	1			T18	1		T51	1		T130	1
auto[805306368:939524095]	auto[1]	50	1			T55	1		T44	1		T27	1
auto[939524096:1073741823]	auto[0]	41	1			T5	1		T55	1		T215	1
auto[939524096:1073741823]	auto[1]	49	1			T120	1		T30	1		T199	1
auto[1073741824:1207959551]	auto[0]	46	1			T5	1		T63	1		T94	1
auto[1073741824:1207959551]	auto[1]	56	1			T87	1		T204	1		T66	1
auto[1207959552:1342177279]	auto[0]	46	1			T4	1		T27	1		T119	1
auto[1207959552:1342177279]	auto[1]	46	1			T40	1		T189	1		T8	1
auto[1342177280:1476395007]	auto[0]	51	1			T44	1		T94	1		T278	1
auto[1342177280:1476395007]	auto[1]	60	1			T27	1		T131	1		T94	1
auto[1476395008:1610612735]	auto[0]	38	1			T5	1		T17	1		T130	1
auto[1476395008:1610612735]	auto[1]	47	1			T1	1		T5	1		T53	1
auto[1610612736:1744830463]	auto[0]	56	1			T27	1		T22	1		T214	1
auto[1610612736:1744830463]	auto[1]	55	1			T1	1		T27	1		T204	1
auto[1744830464:1879048191]	auto[0]	47	1			T16	1		T201	1		T47	2
auto[1744830464:1879048191]	auto[1]	46	1			T27	1		T215	1		T148	1
auto[1879048192:2013265919]	auto[0]	51	1			T2	1		T27	1		T210	1
auto[1879048192:2013265919]	auto[1]	48	1			T44	1		T199	1		T108	1
auto[2013265920:2147483647]	auto[0]	47	1			T16	1		T44	1		T27	2
auto[2013265920:2147483647]	auto[1]	51	1			T82	1		T43	1		T62	1
auto[2147483648:2281701375]	auto[0]	41	1			T55	1		T27	1		T42	1
auto[2147483648:2281701375]	auto[1]	54	1			T5	1		T44	1		T135	1
auto[2281701376:2415919103]	auto[0]	37	1			T5	1		T44	1		T27	1
auto[2281701376:2415919103]	auto[1]	43	1			T27	1		T68	1		T42	2
auto[2415919104:2550136831]	auto[0]	51	1			T18	1		T44	3		T27	1
auto[2415919104:2550136831]	auto[1]	53	1			T4	1		T20	1		T204	2
auto[2550136832:2684354559]	auto[0]	38	1			T17	1		T131	1		T137	1
auto[2550136832:2684354559]	auto[1]	65	1			T19	1		T55	1		T44	1
auto[2684354560:2818572287]	auto[0]	52	1			T55	1		T204	1		T108	1
auto[2684354560:2818572287]	auto[1]	60	1			T17	1		T216	1		T78	1
auto[2818572288:2952790015]	auto[0]	38	1			T1	1		T27	1		T131	1
auto[2818572288:2952790015]	auto[1]	64	1			T87	1		T44	1		T64	1
auto[2952790016:3087007743]	auto[0]	49	1			T17	1		T18	1		T27	1
auto[2952790016:3087007743]	auto[1]	58	1			T5	1		T15	1		T131	1
auto[3087007744:3221225471]	auto[0]	42	1			T70	1		T308	1		T262	1
auto[3087007744:3221225471]	auto[1]	57	1			T15	1		T28	1		T94	1
auto[3221225472:3355443199]	auto[0]	57	1			T27	1		T201	1		T94	1
auto[3221225472:3355443199]	auto[1]	72	1			T15	1		T55	1		T28	1
auto[3355443200:3489660927]	auto[0]	58	1			T1	1		T2	1		T5	1
auto[3355443200:3489660927]	auto[1]	59	1			T44	1		T200	1		T56	2
auto[3489660928:3623878655]	auto[0]	39	1			T1	1		T119	1		T201	1
auto[3489660928:3623878655]	auto[1]	53	1			T148	1		T199	1		T22	1
auto[3623878656:3758096383]	auto[0]	58	1			T44	1		T63	1		T46	1
auto[3623878656:3758096383]	auto[1]	56	1			T20	1		T119	1		T65	1
auto[3758096384:3892314111]	auto[0]	48	1			T1	1		T17	1		T44	1
auto[3758096384:3892314111]	auto[1]	47	1			T2	1		T4	1		T210	1
auto[3892314112:4026531839]	auto[0]	45	1			T17	1		T130	1		T262	1
auto[3892314112:4026531839]	auto[1]	58	1			T2	1		T19	1		T131	1
auto[4026531840:4160749567]	auto[0]	56	1			T19	1		T27	1		T278	1
auto[4026531840:4160749567]	auto[1]	53	1			T1	1		T2	1		T87	1
auto[4160749568:4294967295]	auto[0]	53	1			T20	1		T44	1		T27	1
auto[4160749568:4294967295]	auto[1]	56	1			T44	1		T131	1		T64	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1485

1

T1

4

T2

1

T5

5

auto[1]

1748

1

T1

5

T2

5

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	116	1			T1	1		T87	1		T27	2
auto[134217728:268435455]	100	1			T18	1		T55	1		T29	1
auto[268435456:402653183]	81	1			T119	1		T131	1		T63	1
auto[402653184:536870911]	107	1			T1	1		T2	1		T44	1
auto[536870912:671088639]	106	1			T2	1		T44	1		T27	1
auto[671088640:805306367]	99	1			T55	1		T27	1		T201	1
auto[805306368:939524095]	84	1			T15	1		T18	1		T55	1
auto[939524096:1073741823]	113	1			T2	1		T15	1		T20	1
auto[1073741824:1207959551]	106	1			T15	1		T17	2		T131	1
auto[1207959552:1342177279]	94	1			T1	1		T5	1		T20	1
auto[1342177280:1476395007]	107	1			T44	2		T27	1		T28	1
auto[1476395008:1610612735]	93	1			T19	1		T55	1		T63	1
auto[1610612736:1744830463]	121	1			T1	1		T5	1		T17	1
auto[1744830464:1879048191]	99	1			T1	1		T2	1		T5	1
auto[1879048192:2013265919]	103	1			T55	1		T65	1		T53	2
auto[2013265920:2147483647]	114	1			T18	1		T44	2		T200	1
auto[2147483648:2281701375]	103	1			T1	1		T16	1		T130	1
auto[2281701376:2415919103]	93	1			T1	2		T2	1		T87	1
auto[2415919104:2550136831]	110	1			T5	1		T4	1		T44	1
auto[2550136832:2684354559]	100	1			T27	2		T52	1		T42	2
auto[2684354560:2818572287]	97	1			T4	1		T17	1		T44	1
auto[2818572288:2952790015]	79	1			T55	1		T27	1		T94	1
auto[2952790016:3087007743]	107	1			T1	1		T44	2		T27	2
auto[3087007744:3221225471]	105	1			T4	1		T44	1		T27	1
auto[3221225472:3355443199]	111	1			T2	1		T16	1		T18	1
auto[3355443200:3489660927]	98	1			T17	1		T19	1		T27	1
auto[3489660928:3623878655]	113	1			T5	1		T17	1		T20	1
auto[3623878656:3758096383]	80	1			T16	1		T20	1		T55	1
auto[3758096384:3892314111]	88	1			T5	2		T16	1		T17	1
auto[3892314112:4026531839]	107	1			T27	3		T94	1		T200	1
auto[4026531840:4160749567]	101	1			T87	1		T51	1		T119	1
auto[4160749568:4294967295]	98	1			T5	1		T44	1		T27	1