Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2820

1

T1

9

T2

6

T5

8

auto[1]

304

1

T119

2

T120

7

T148

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T27	1		T120	1		T47	1
auto[134217728:268435455]	81	1			T1	1		T44	2		T130	1
auto[268435456:402653183]	101	1			T5	2		T27	1		T51	1
auto[402653184:536870911]	85	1			T4	1		T16	1		T55	1
auto[536870912:671088639]	111	1			T1	1		T5	2		T17	1
auto[671088640:805306367]	96	1			T19	1		T44	1		T27	1
auto[805306368:939524095]	101	1			T1	1		T16	2		T18	1
auto[939524096:1073741823]	101	1			T4	1		T17	2		T44	1
auto[1073741824:1207959551]	107	1			T5	1		T18	1		T44	1
auto[1207959552:1342177279]	94	1			T44	1		T27	1		T119	1
auto[1342177280:1476395007]	114	1			T17	1		T20	1		T27	2
auto[1476395008:1610612735]	95	1			T2	1		T20	1		T44	1
auto[1610612736:1744830463]	98	1			T17	1		T87	1		T44	1
auto[1744830464:1879048191]	98	1			T5	1		T15	1		T55	1
auto[1879048192:2013265919]	95	1			T2	1		T55	1		T44	1
auto[2013265920:2147483647]	93	1			T1	1		T119	1		T201	1
auto[2147483648:2281701375]	91	1			T55	1		T44	1		T199	1
auto[2281701376:2415919103]	97	1			T1	1		T5	1		T120	1
auto[2415919104:2550136831]	82	1			T19	1		T200	1		T56	1
auto[2550136832:2684354559]	98	1			T1	1		T44	1		T27	1
auto[2684354560:2818572287]	108	1			T1	1		T15	1		T17	1
auto[2818572288:2952790015]	118	1			T27	1		T130	1		T119	1
auto[2952790016:3087007743]	82	1			T2	1		T19	1		T63	1
auto[3087007744:3221225471]	92	1			T55	1		T27	1		T130	1
auto[3221225472:3355443199]	99	1			T4	1		T19	1		T87	1
auto[3355443200:3489660927]	105	1			T1	2		T2	1		T16	1
auto[3489660928:3623878655]	92	1			T55	1		T119	1		T148	2
auto[3623878656:3758096383]	108	1			T17	1		T44	1		T27	1
auto[3758096384:3892314111]	87	1			T2	1		T5	1		T44	1
auto[3892314112:4026531839]	101	1			T2	1		T204	1		T120	1
auto[4026531840:4160749567]	103	1			T87	1		T44	1		T119	1
auto[4160749568:4294967295]	92	1			T44	2		T27	1		T28	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	89	1			T27	1		T47	1		T278	1
auto[0:134217727]	auto[1]	10	1			T120	1		T268	1		T306	1
auto[134217728:268435455]	auto[0]	75	1			T1	1		T44	2		T130	1
auto[134217728:268435455]	auto[1]	6	1			T120	1		T140	1		T382	1
auto[268435456:402653183]	auto[0]	87	1			T5	2		T27	1		T51	1
auto[268435456:402653183]	auto[1]	14	1			T120	1		T137	1		T341	2
auto[402653184:536870911]	auto[0]	81	1			T4	1		T16	1		T55	1
auto[402653184:536870911]	auto[1]	4	1			T148	1		T382	1		T302	1
auto[536870912:671088639]	auto[0]	97	1			T1	1		T5	2		T17	1
auto[536870912:671088639]	auto[1]	14	1			T120	1		T137	1		T140	1
auto[671088640:805306367]	auto[0]	80	1			T19	1		T44	1		T27	1
auto[671088640:805306367]	auto[1]	16	1			T138	1		T341	1		T268	1
auto[805306368:939524095]	auto[0]	93	1			T1	1		T16	2		T18	1
auto[805306368:939524095]	auto[1]	8	1			T350	2		T268	1		T371	1
auto[939524096:1073741823]	auto[0]	93	1			T4	1		T17	2		T44	1
auto[939524096:1073741823]	auto[1]	8	1			T266	1		T384	1		T336	1
auto[1073741824:1207959551]	auto[0]	101	1			T5	1		T18	1		T44	1
auto[1073741824:1207959551]	auto[1]	6	1			T371	1		T422	2		T423	1
auto[1207959552:1342177279]	auto[0]	86	1			T44	1		T27	1		T119	1
auto[1207959552:1342177279]	auto[1]	8	1			T341	1		T266	1		T415	1
auto[1342177280:1476395007]	auto[0]	102	1			T17	1		T20	1		T27	2
auto[1342177280:1476395007]	auto[1]	12	1			T138	1		T341	2		T140	1
auto[1476395008:1610612735]	auto[0]	87	1			T2	1		T20	1		T44	1
auto[1476395008:1610612735]	auto[1]	8	1			T341	2		T350	2		T306	1
auto[1610612736:1744830463]	auto[0]	87	1			T17	1		T87	1		T44	1
auto[1610612736:1744830463]	auto[1]	11	1			T148	1		T341	1		T140	1
auto[1744830464:1879048191]	auto[0]	88	1			T5	1		T15	1		T55	1
auto[1744830464:1879048191]	auto[1]	10	1			T120	1		T415	1		T306	2
auto[1879048192:2013265919]	auto[0]	89	1			T2	1		T55	1		T44	1
auto[1879048192:2013265919]	auto[1]	6	1			T120	1		T419	1		T343	1
auto[2013265920:2147483647]	auto[0]	89	1			T1	1		T119	1		T201	1
auto[2013265920:2147483647]	auto[1]	4	1			T268	1		T416	1		T309	1
auto[2147483648:2281701375]	auto[0]	84	1			T55	1		T44	1		T199	1
auto[2147483648:2281701375]	auto[1]	7	1			T341	2		T384	1		T309	2
auto[2281701376:2415919103]	auto[0]	88	1			T1	1		T5	1		T120	1
auto[2281701376:2415919103]	auto[1]	9	1			T350	1		T399	1		T309	1
auto[2415919104:2550136831]	auto[0]	73	1			T19	1		T200	1		T56	1
auto[2415919104:2550136831]	auto[1]	9	1			T140	1		T268	1		T415	1
auto[2550136832:2684354559]	auto[0]	81	1			T1	1		T44	1		T27	1
auto[2550136832:2684354559]	auto[1]	17	1			T138	1		T266	1		T350	2
auto[2684354560:2818572287]	auto[0]	99	1			T1	1		T15	1		T17	1
auto[2684354560:2818572287]	auto[1]	9	1			T268	1		T382	1		T273	1
auto[2818572288:2952790015]	auto[0]	104	1			T27	1		T130	1		T135	1
auto[2818572288:2952790015]	auto[1]	14	1			T119	1		T138	1		T382	1
auto[2952790016:3087007743]	auto[0]	73	1			T2	1		T19	1		T63	1
auto[2952790016:3087007743]	auto[1]	9	1			T137	1		T140	1		T382	1
auto[3087007744:3221225471]	auto[0]	87	1			T55	1		T27	1		T130	1
auto[3087007744:3221225471]	auto[1]	5	1			T266	1		T306	1		T416	1
auto[3221225472:3355443199]	auto[0]	90	1			T4	1		T19	1		T87	1
auto[3221225472:3355443199]	auto[1]	9	1			T306	1		T397	2		T414	1
auto[3355443200:3489660927]	auto[0]	96	1			T1	2		T2	1		T16	1
auto[3355443200:3489660927]	auto[1]	9	1			T120	1		T341	2		T350	1
auto[3489660928:3623878655]	auto[0]	84	1			T55	1		T148	2		T218	1
auto[3489660928:3623878655]	auto[1]	8	1			T119	1		T273	1		T306	1
auto[3623878656:3758096383]	auto[0]	99	1			T17	1		T44	1		T27	1
auto[3623878656:3758096383]	auto[1]	9	1			T137	1		T266	1		T350	1
auto[3758096384:3892314111]	auto[0]	75	1			T2	1		T5	1		T44	1
auto[3758096384:3892314111]	auto[1]	12	1			T341	2		T268	1		T415	2
auto[3892314112:4026531839]	auto[0]	90	1			T2	1		T204	1		T120	1
auto[3892314112:4026531839]	auto[1]	11	1			T148	1		T292	1		T268	1
auto[4026531840:4160749567]	auto[0]	91	1			T87	1		T44	1		T119	1
auto[4026531840:4160749567]	auto[1]	12	1			T292	1		T341	1		T266	1
auto[4160749568:4294967295]	auto[0]	82	1			T44	2		T27	1		T28	1
auto[4160749568:4294967295]	auto[1]	10	1			T137	1		T416	1		T371	1