Unified Coverage Report :: Group Instance : sealing_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1517

1

T1

5

T2

2

T5

5

auto[1]

1716

1

T1

4

T2

4

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	88	1			T18	1		T19	1		T44	1
auto[134217728:268435455]	113	1			T15	1		T44	1		T201	1
auto[268435456:402653183]	107	1			T5	1		T16	1		T55	2
auto[402653184:536870911]	83	1			T1	1		T18	1		T44	2
auto[536870912:671088639]	102	1			T66	1		T81	1		T82	1
auto[671088640:805306367]	109	1			T44	1		T130	1		T64	1
auto[805306368:939524095]	117	1			T2	1		T18	1		T27	2
auto[939524096:1073741823]	99	1			T44	1		T130	1		T131	1
auto[1073741824:1207959551]	97	1			T55	1		T44	1		T27	1
auto[1207959552:1342177279]	95	1			T17	1		T44	2		T27	2
auto[1342177280:1476395007]	85	1			T27	1		T28	1		T130	1
auto[1476395008:1610612735]	86	1			T1	2		T5	1		T20	1
auto[1610612736:1744830463]	119	1			T1	1		T2	1		T17	1
auto[1744830464:1879048191]	102	1			T5	1		T17	1		T44	1
auto[1879048192:2013265919]	104	1			T2	1		T19	1		T131	1
auto[2013265920:2147483647]	101	1			T46	1		T94	1		T216	1
auto[2147483648:2281701375]	123	1			T15	1		T17	1		T19	1
auto[2281701376:2415919103]	95	1			T5	1		T55	1		T27	1
auto[2415919104:2550136831]	100	1			T28	1		T201	1		T148	1
auto[2550136832:2684354559]	89	1			T44	1		T27	2		T204	2
auto[2684354560:2818572287]	107	1			T44	1		T201	1		T204	1
auto[2818572288:2952790015]	91	1			T1	2		T5	1		T16	1
auto[2952790016:3087007743]	94	1			T1	1		T2	1		T16	1
auto[3087007744:3221225471]	82	1			T55	1		T27	1		T29	1
auto[3221225472:3355443199]	112	1			T5	1		T19	1		T20	1
auto[3355443200:3489660927]	87	1			T1	1		T2	1		T5	1
auto[3489660928:3623878655]	100	1			T201	1		T46	1		T120	1
auto[3623878656:3758096383]	106	1			T4	2		T44	1		T94	1
auto[3758096384:3892314111]	114	1			T17	1		T27	3		T119	1
auto[3892314112:4026531839]	107	1			T4	1		T18	1		T44	1
auto[4026531840:4160749567]	112	1			T17	1		T87	1		T55	1
auto[4160749568:4294967295]	107	1			T1	1		T2	1		T5	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	39	1			T18	1		T82	1		T42	1
auto[0:134217727]	auto[1]	49	1			T19	1		T44	1		T27	1
auto[134217728:268435455]	auto[0]	57	1			T15	1		T201	1		T278	2
auto[134217728:268435455]	auto[1]	56	1			T44	1		T135	1		T120	1
auto[268435456:402653183]	auto[0]	51	1			T55	1		T27	2		T42	3
auto[268435456:402653183]	auto[1]	56	1			T5	1		T16	1		T55	1
auto[402653184:536870911]	auto[0]	38	1			T18	1		T44	2		T47	1
auto[402653184:536870911]	auto[1]	45	1			T1	1		T120	1		T148	1
auto[536870912:671088639]	auto[0]	57	1			T82	1		T42	1		T108	1
auto[536870912:671088639]	auto[1]	45	1			T66	1		T81	1		T108	1
auto[671088640:805306367]	auto[0]	44	1			T44	1		T130	1		T42	2
auto[671088640:805306367]	auto[1]	65	1			T64	1		T199	1		T210	1
auto[805306368:939524095]	auto[0]	54	1			T2	1		T18	1		T27	1
auto[805306368:939524095]	auto[1]	63	1			T27	1		T204	1		T120	1
auto[939524096:1073741823]	auto[0]	47	1			T44	1		T130	1		T63	1
auto[939524096:1073741823]	auto[1]	52	1			T131	1		T42	1		T137	1
auto[1073741824:1207959551]	auto[0]	40	1			T44	1		T84	1		T85	1
auto[1073741824:1207959551]	auto[1]	57	1			T55	1		T27	1		T135	1
auto[1207959552:1342177279]	auto[0]	44	1			T17	1		T27	1		T51	1
auto[1207959552:1342177279]	auto[1]	51	1			T44	2		T27	1		T94	1
auto[1342177280:1476395007]	auto[0]	40	1			T27	1		T130	1		T56	1
auto[1342177280:1476395007]	auto[1]	45	1			T28	1		T204	1		T148	1
auto[1476395008:1610612735]	auto[0]	42	1			T1	2		T5	1		T20	1
auto[1476395008:1610612735]	auto[1]	44	1			T30	1		T79	1		T42	1
auto[1610612736:1744830463]	auto[0]	56	1			T1	1		T17	1		T27	1
auto[1610612736:1744830463]	auto[1]	63	1			T2	1		T199	1		T42	1
auto[1744830464:1879048191]	auto[0]	46	1			T17	1		T44	1		T27	3
auto[1744830464:1879048191]	auto[1]	56	1			T5	1		T27	1		T204	1
auto[1879048192:2013265919]	auto[0]	47	1			T19	1		T201	1		T63	1
auto[1879048192:2013265919]	auto[1]	57	1			T2	1		T131	1		T148	1
auto[2013265920:2147483647]	auto[0]	44	1			T82	1		T308	1		T259	1
auto[2013265920:2147483647]	auto[1]	57	1			T46	1		T94	1		T216	1
auto[2147483648:2281701375]	auto[0]	67	1			T17	1		T19	1		T94	1
auto[2147483648:2281701375]	auto[1]	56	1			T15	1		T87	1		T44	1
auto[2281701376:2415919103]	auto[0]	39	1			T5	1		T27	1		T210	1
auto[2281701376:2415919103]	auto[1]	56	1			T55	1		T119	1		T131	1
auto[2415919104:2550136831]	auto[0]	52	1			T201	1		T251	1		T62	1
auto[2415919104:2550136831]	auto[1]	48	1			T28	1		T148	1		T42	1
auto[2550136832:2684354559]	auto[0]	41	1			T44	1		T27	1		T47	1
auto[2550136832:2684354559]	auto[1]	48	1			T27	1		T204	2		T135	1
auto[2684354560:2818572287]	auto[0]	46	1			T201	1		T218	1		T85	1
auto[2684354560:2818572287]	auto[1]	61	1			T44	1		T204	1		T63	1
auto[2818572288:2952790015]	auto[0]	44	1			T5	1		T16	1		T18	1
auto[2818572288:2952790015]	auto[1]	47	1			T1	2		T44	1		T56	1
auto[2952790016:3087007743]	auto[0]	43	1			T1	1		T16	1		T20	1
auto[2952790016:3087007743]	auto[1]	51	1			T2	1		T87	1		T119	1
auto[3087007744:3221225471]	auto[0]	44	1			T55	1		T27	1		T22	1
auto[3087007744:3221225471]	auto[1]	38	1			T29	1		T218	1		T69	1
auto[3221225472:3355443199]	auto[0]	50	1			T5	1		T19	1		T20	1
auto[3221225472:3355443199]	auto[1]	62	1			T131	1		T53	1		T68	1
auto[3355443200:3489660927]	auto[0]	35	1			T5	1		T15	1		T16	1
auto[3355443200:3489660927]	auto[1]	52	1			T1	1		T2	1		T17	1
auto[3489660928:3623878655]	auto[0]	39	1			T215	1		T56	1		T206	1
auto[3489660928:3623878655]	auto[1]	61	1			T201	1		T46	1		T120	1
auto[3623878656:3758096383]	auto[0]	56	1			T4	1		T44	1		T94	1
auto[3623878656:3758096383]	auto[1]	50	1			T4	1		T56	1		T137	1
auto[3758096384:3892314111]	auto[0]	57	1			T17	1		T27	2		T131	1
auto[3758096384:3892314111]	auto[1]	57	1			T27	1		T119	1		T53	1
auto[3892314112:4026531839]	auto[0]	53	1			T18	1		T27	1		T51	1
auto[3892314112:4026531839]	auto[1]	54	1			T4	1		T44	1		T27	2
auto[4026531840:4160749567]	auto[0]	51	1			T17	1		T204	1		T135	1
auto[4026531840:4160749567]	auto[1]	61	1			T87	1		T55	1		T119	1
auto[4160749568:4294967295]	auto[0]	54	1			T1	1		T2	1		T27	1
auto[4160749568:4294967295]	auto[1]	53	1			T5	1		T55	1		T44	1