Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4464

1

T1

18

T2

12

T5

14

auto[1]

2002

1

T5

2

T15

4

T16

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	204	1			T2	2		T5	2		T17	2
auto[134217728:268435455]	226	1			T4	2		T15	2		T27	2
auto[268435456:402653183]	194	1			T2	4		T15	4		T55	2
auto[402653184:536870911]	204	1			T27	2		T204	2		T29	2
auto[536870912:671088639]	208	1			T1	4		T16	2		T19	2
auto[671088640:805306367]	202	1			T44	2		T130	2		T94	2
auto[805306368:939524095]	210	1			T1	2		T5	2		T27	4
auto[939524096:1073741823]	228	1			T44	4		T27	4		T119	2
auto[1073741824:1207959551]	196	1			T16	2		T20	4		T201	2
auto[1207959552:1342177279]	200	1			T16	2		T55	4		T27	2
auto[1342177280:1476395007]	212	1			T44	2		T56	2		T199	2
auto[1476395008:1610612735]	236	1			T1	2		T55	2		T44	6
auto[1610612736:1744830463]	232	1			T1	2		T19	2		T27	4
auto[1744830464:1879048191]	164	1			T17	2		T18	2		T55	4
auto[1879048192:2013265919]	204	1			T1	2		T4	2		T119	2
auto[2013265920:2147483647]	186	1			T17	2		T87	4		T204	2
auto[2147483648:2281701375]	234	1			T17	2		T18	2		T19	2
auto[2281701376:2415919103]	166	1			T5	2		T27	2		T130	2
auto[2415919104:2550136831]	182	1			T5	2		T28	2		T51	2
auto[2550136832:2684354559]	220	1			T2	2		T44	2		T131	2
auto[2684354560:2818572287]	160	1			T18	2		T44	2		T204	4
auto[2818572288:2952790015]	170	1			T4	2		T17	4		T87	2
auto[2952790016:3087007743]	206	1			T5	4		T119	2		T63	2
auto[3087007744:3221225471]	206	1			T17	2		T55	2		T94	2
auto[3221225472:3355443199]	228	1			T2	2		T16	2		T44	2
auto[3355443200:3489660927]	178	1			T19	2		T94	2		T56	2
auto[3489660928:3623878655]	218	1			T44	6		T27	2		T131	2
auto[3623878656:3758096383]	186	1			T1	2		T5	2		T44	2
auto[3758096384:3892314111]	200	1			T20	2		T55	2		T44	2
auto[3892314112:4026531839]	194	1			T1	2		T2	2		T44	2
auto[4026531840:4160749567]	212	1			T1	2		T18	4		T44	2
auto[4160749568:4294967295]	200	1			T5	2		T20	2		T55	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	126	1			T2	2		T5	2		T17	2
auto[0:134217727]	auto[1]	78	1			T137	2		T281	2		T126	2
auto[134217728:268435455]	auto[0]	146	1			T4	2		T15	2		T28	2
auto[134217728:268435455]	auto[1]	80	1			T27	2		T218	2		T260	2
auto[268435456:402653183]	auto[0]	130	1			T2	4		T28	2		T204	2
auto[268435456:402653183]	auto[1]	64	1			T15	4		T55	2		T27	2
auto[402653184:536870911]	auto[0]	142	1			T27	2		T204	2		T199	2
auto[402653184:536870911]	auto[1]	62	1			T29	2		T120	2		T30	2
auto[536870912:671088639]	auto[0]	142	1			T1	4		T19	2		T27	4
auto[536870912:671088639]	auto[1]	66	1			T16	2		T47	2		T22	2
auto[671088640:805306367]	auto[0]	116	1			T44	2		T94	2		T135	2
auto[671088640:805306367]	auto[1]	86	1			T130	2		T53	2		T199	2
auto[805306368:939524095]	auto[0]	142	1			T1	2		T5	2		T27	2
auto[805306368:939524095]	auto[1]	68	1			T27	2		T79	2		T70	2
auto[939524096:1073741823]	auto[0]	176	1			T44	4		T27	2		T119	2
auto[939524096:1073741823]	auto[1]	52	1			T27	2		T65	2		T30	2
auto[1073741824:1207959551]	auto[0]	146	1			T20	2		T201	2		T63	2
auto[1073741824:1207959551]	auto[1]	50	1			T16	2		T20	2		T390	2
auto[1207959552:1342177279]	auto[0]	132	1			T55	2		T27	2		T206	2
auto[1207959552:1342177279]	auto[1]	68	1			T16	2		T55	2		T210	2
auto[1342177280:1476395007]	auto[0]	142	1			T44	2		T56	2		T278	2
auto[1342177280:1476395007]	auto[1]	70	1			T199	2		T78	2		T269	2
auto[1476395008:1610612735]	auto[0]	160	1			T1	2		T55	2		T44	6
auto[1476395008:1610612735]	auto[1]	76	1			T64	2		T42	2		T70	2
auto[1610612736:1744830463]	auto[0]	150	1			T1	2		T27	2		T130	2
auto[1610612736:1744830463]	auto[1]	82	1			T19	2		T27	2		T52	2
auto[1744830464:1879048191]	auto[0]	114	1			T17	2		T18	2		T55	4
auto[1744830464:1879048191]	auto[1]	50	1			T148	2		T68	2		T251	2
auto[1879048192:2013265919]	auto[0]	144	1			T1	2		T4	2		T119	2
auto[1879048192:2013265919]	auto[1]	60	1			T53	2		T56	2		T42	2
auto[2013265920:2147483647]	auto[0]	126	1			T17	2		T87	4		T204	2
auto[2013265920:2147483647]	auto[1]	60	1			T81	2		T42	2		T70	2
auto[2147483648:2281701375]	auto[0]	156	1			T17	2		T18	2		T27	6
auto[2147483648:2281701375]	auto[1]	78	1			T19	2		T51	2		T53	2
auto[2281701376:2415919103]	auto[0]	128	1			T5	2		T27	2		T130	2
auto[2281701376:2415919103]	auto[1]	38	1			T258	2		T70	2		T126	2
auto[2415919104:2550136831]	auto[0]	118	1			T5	2		T28	2		T51	2
auto[2415919104:2550136831]	auto[1]	64	1			T56	4		T276	2		T43	8
auto[2550136832:2684354559]	auto[0]	154	1			T2	2		T131	2		T46	2
auto[2550136832:2684354559]	auto[1]	66	1			T44	2		T22	2		T278	2
auto[2684354560:2818572287]	auto[0]	100	1			T18	2		T44	2		T204	2
auto[2684354560:2818572287]	auto[1]	60	1			T204	2		T199	2		T85	2
auto[2818572288:2952790015]	auto[0]	126	1			T4	2		T17	2		T87	2
auto[2818572288:2952790015]	auto[1]	44	1			T17	2		T64	2		T126	2
auto[2952790016:3087007743]	auto[0]	140	1			T5	2		T119	2		T63	2
auto[2952790016:3087007743]	auto[1]	66	1			T5	2		T53	2		T120	2
auto[3087007744:3221225471]	auto[0]	150	1			T17	2		T55	2		T94	2
auto[3087007744:3221225471]	auto[1]	56	1			T218	2		T278	2		T258	2
auto[3221225472:3355443199]	auto[0]	170	1			T2	2		T44	2		T27	4
auto[3221225472:3355443199]	auto[1]	58	1			T16	2		T56	2		T405	2
auto[3355443200:3489660927]	auto[0]	128	1			T19	2		T94	2		T276	2
auto[3355443200:3489660927]	auto[1]	50	1			T56	2		T213	2		T81	2
auto[3489660928:3623878655]	auto[0]	154	1			T44	4		T27	2		T131	2
auto[3489660928:3623878655]	auto[1]	64	1			T44	2		T63	2		T46	2
auto[3623878656:3758096383]	auto[0]	136	1			T1	2		T5	2		T44	2
auto[3623878656:3758096383]	auto[1]	50	1			T201	2		T42	2		T32	2
auto[3758096384:3892314111]	auto[0]	148	1			T130	2		T94	2		T258	2
auto[3758096384:3892314111]	auto[1]	52	1			T20	2		T55	2		T44	2
auto[3892314112:4026531839]	auto[0]	136	1			T1	2		T2	2		T218	2
auto[3892314112:4026531839]	auto[1]	58	1			T44	2		T27	2		T64	2
auto[4026531840:4160749567]	auto[0]	162	1			T1	2		T18	4		T44	2
auto[4026531840:4160749567]	auto[1]	50	1			T210	2		T263	2		T257	2
auto[4160749568:4294967295]	auto[0]	124	1			T5	2		T20	2		T55	2
auto[4160749568:4294967295]	auto[1]	76	1			T56	2		T213	2		T22	2