Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.71 99.04 97.95 98.38 100.00 99.02 98.41 91.19


Total test records in report: 1077
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T1008 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3166200626 Jul 13 06:53:13 PM PDT 24 Jul 13 06:53:14 PM PDT 24 140900000 ps
T1009 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2205169860 Jul 13 06:53:13 PM PDT 24 Jul 13 06:53:14 PM PDT 24 37863220 ps
T1010 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3426881751 Jul 13 06:52:49 PM PDT 24 Jul 13 06:52:51 PM PDT 24 286033774 ps
T1011 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3499403687 Jul 13 06:53:11 PM PDT 24 Jul 13 06:53:18 PM PDT 24 585025126 ps
T1012 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1106459644 Jul 13 06:53:16 PM PDT 24 Jul 13 06:53:18 PM PDT 24 19672047 ps
T1013 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1931323953 Jul 13 06:51:57 PM PDT 24 Jul 13 06:51:59 PM PDT 24 35848801 ps
T1014 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2597261076 Jul 13 06:51:41 PM PDT 24 Jul 13 06:51:46 PM PDT 24 70351618 ps
T1015 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2341145795 Jul 13 06:53:15 PM PDT 24 Jul 13 06:53:16 PM PDT 24 12866706 ps
T1016 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1332259457 Jul 13 06:52:45 PM PDT 24 Jul 13 06:52:47 PM PDT 24 18349609 ps
T1017 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3345402984 Jul 13 06:53:16 PM PDT 24 Jul 13 06:53:18 PM PDT 24 82978516 ps
T1018 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.12098514 Jul 13 06:53:16 PM PDT 24 Jul 13 06:53:18 PM PDT 24 46402047 ps
T1019 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4137058247 Jul 13 06:52:59 PM PDT 24 Jul 13 06:53:03 PM PDT 24 92713473 ps
T1020 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1321369012 Jul 13 06:53:12 PM PDT 24 Jul 13 06:53:13 PM PDT 24 70321980 ps
T1021 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3219952789 Jul 13 06:52:46 PM PDT 24 Jul 13 06:52:47 PM PDT 24 53735449 ps
T1022 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1504017292 Jul 13 06:53:07 PM PDT 24 Jul 13 06:53:08 PM PDT 24 14235857 ps
T1023 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.456765332 Jul 13 06:52:23 PM PDT 24 Jul 13 06:52:32 PM PDT 24 716472883 ps
T1024 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1194880594 Jul 13 06:52:49 PM PDT 24 Jul 13 06:52:51 PM PDT 24 32013508 ps
T1025 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.331109921 Jul 13 06:52:17 PM PDT 24 Jul 13 06:52:25 PM PDT 24 372153926 ps
T1026 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2271210447 Jul 13 06:53:09 PM PDT 24 Jul 13 06:53:10 PM PDT 24 34353637 ps
T1027 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2831190249 Jul 13 06:53:11 PM PDT 24 Jul 13 06:53:13 PM PDT 24 28156043 ps
T1028 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2680892559 Jul 13 06:53:17 PM PDT 24 Jul 13 06:53:19 PM PDT 24 11079871 ps
T1029 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.382259425 Jul 13 06:52:46 PM PDT 24 Jul 13 06:52:48 PM PDT 24 75768784 ps
T1030 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3577335331 Jul 13 06:52:27 PM PDT 24 Jul 13 06:52:29 PM PDT 24 186888527 ps
T1031 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1468553941 Jul 13 06:51:38 PM PDT 24 Jul 13 06:51:41 PM PDT 24 195332688 ps
T1032 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1051818094 Jul 13 06:51:48 PM PDT 24 Jul 13 06:51:50 PM PDT 24 17006953 ps
T175 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.900709630 Jul 13 06:52:13 PM PDT 24 Jul 13 06:52:20 PM PDT 24 951164937 ps
T1033 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1744892363 Jul 13 06:53:16 PM PDT 24 Jul 13 06:53:18 PM PDT 24 8876366 ps
T1034 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1268679367 Jul 13 06:52:36 PM PDT 24 Jul 13 06:52:39 PM PDT 24 33581061 ps
T1035 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2566428121 Jul 13 06:51:39 PM PDT 24 Jul 13 06:51:40 PM PDT 24 73799843 ps
T1036 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2457326323 Jul 13 06:52:14 PM PDT 24 Jul 13 06:52:17 PM PDT 24 188373604 ps
T1037 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.781222319 Jul 13 06:53:14 PM PDT 24 Jul 13 06:53:15 PM PDT 24 42418818 ps
T1038 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1926846654 Jul 13 06:52:45 PM PDT 24 Jul 13 06:52:47 PM PDT 24 66095530 ps
T173 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2028214727 Jul 13 06:52:42 PM PDT 24 Jul 13 06:52:48 PM PDT 24 329656294 ps
T182 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2080498672 Jul 13 06:52:34 PM PDT 24 Jul 13 06:52:41 PM PDT 24 785568258 ps
T1039 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1327699240 Jul 13 06:51:41 PM PDT 24 Jul 13 06:51:50 PM PDT 24 394036503 ps
T1040 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2607977231 Jul 13 06:53:15 PM PDT 24 Jul 13 06:53:17 PM PDT 24 16923769 ps
T1041 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2726737763 Jul 13 06:52:42 PM PDT 24 Jul 13 06:52:46 PM PDT 24 71825499 ps
T1042 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3102939961 Jul 13 06:53:15 PM PDT 24 Jul 13 06:53:17 PM PDT 24 8996515 ps
T1043 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.471701438 Jul 13 06:52:00 PM PDT 24 Jul 13 06:52:01 PM PDT 24 25156823 ps
T160 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1908998050 Jul 13 06:52:56 PM PDT 24 Jul 13 06:53:02 PM PDT 24 230425637 ps
T1044 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3313692846 Jul 13 06:51:39 PM PDT 24 Jul 13 06:51:41 PM PDT 24 14720979 ps
T176 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1879837669 Jul 13 06:52:06 PM PDT 24 Jul 13 06:52:10 PM PDT 24 51656559 ps
T1045 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1915771345 Jul 13 06:52:59 PM PDT 24 Jul 13 06:53:01 PM PDT 24 144831669 ps
T1046 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.4233756962 Jul 13 06:52:27 PM PDT 24 Jul 13 06:52:30 PM PDT 24 59213614 ps
T1047 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.408950280 Jul 13 06:52:34 PM PDT 24 Jul 13 06:52:38 PM PDT 24 746798163 ps
T1048 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3408550047 Jul 13 06:51:59 PM PDT 24 Jul 13 06:52:04 PM PDT 24 739528186 ps
T1049 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1504272811 Jul 13 06:52:57 PM PDT 24 Jul 13 06:52:59 PM PDT 24 43336385 ps
T1050 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.139842951 Jul 13 06:52:57 PM PDT 24 Jul 13 06:53:01 PM PDT 24 451914811 ps
T1051 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.301687465 Jul 13 06:53:16 PM PDT 24 Jul 13 06:53:18 PM PDT 24 9069824 ps
T1052 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.4116031899 Jul 13 06:51:57 PM PDT 24 Jul 13 06:52:00 PM PDT 24 78630069 ps
T1053 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3114585569 Jul 13 06:53:14 PM PDT 24 Jul 13 06:53:15 PM PDT 24 17770984 ps
T1054 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.15899450 Jul 13 06:52:23 PM PDT 24 Jul 13 06:52:25 PM PDT 24 44867684 ps
T1055 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1979693291 Jul 13 06:51:51 PM PDT 24 Jul 13 06:51:59 PM PDT 24 235737352 ps
T1056 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3945825548 Jul 13 06:53:14 PM PDT 24 Jul 13 06:53:15 PM PDT 24 34591644 ps
T1057 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2151244396 Jul 13 06:52:58 PM PDT 24 Jul 13 06:52:59 PM PDT 24 143381545 ps
T174 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.679750643 Jul 13 06:52:15 PM PDT 24 Jul 13 06:52:22 PM PDT 24 213268681 ps
T1058 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1770392789 Jul 13 06:52:59 PM PDT 24 Jul 13 06:53:06 PM PDT 24 189432146 ps
T1059 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2710970130 Jul 13 06:52:34 PM PDT 24 Jul 13 06:52:40 PM PDT 24 626090940 ps
T1060 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3872021131 Jul 13 06:52:59 PM PDT 24 Jul 13 06:53:00 PM PDT 24 7884987 ps
T1061 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2910439506 Jul 13 06:51:39 PM PDT 24 Jul 13 06:51:41 PM PDT 24 26725615 ps
T1062 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3277483365 Jul 13 06:52:33 PM PDT 24 Jul 13 06:52:34 PM PDT 24 10894915 ps
T1063 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.59961579 Jul 13 06:51:49 PM PDT 24 Jul 13 06:51:59 PM PDT 24 229197737 ps
T1064 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3597327298 Jul 13 06:52:23 PM PDT 24 Jul 13 06:52:24 PM PDT 24 35962035 ps
T1065 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3409207044 Jul 13 06:52:16 PM PDT 24 Jul 13 06:52:25 PM PDT 24 215194276 ps
T1066 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1682324103 Jul 13 06:52:33 PM PDT 24 Jul 13 06:52:36 PM PDT 24 288765814 ps
T1067 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3907743503 Jul 13 06:53:08 PM PDT 24 Jul 13 06:53:11 PM PDT 24 494252335 ps
T1068 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.203175817 Jul 13 06:51:38 PM PDT 24 Jul 13 06:51:39 PM PDT 24 39523125 ps
T1069 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1590270154 Jul 13 06:52:48 PM PDT 24 Jul 13 06:52:50 PM PDT 24 49629283 ps
T1070 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.379964480 Jul 13 06:53:15 PM PDT 24 Jul 13 06:53:21 PM PDT 24 615726741 ps
T1071 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1233023529 Jul 13 06:51:57 PM PDT 24 Jul 13 06:52:11 PM PDT 24 380588040 ps
T1072 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.632600334 Jul 13 06:52:42 PM PDT 24 Jul 13 06:52:44 PM PDT 24 107992888 ps
T1073 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1780979404 Jul 13 06:52:14 PM PDT 24 Jul 13 06:52:15 PM PDT 24 12934144 ps
T1074 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1368509999 Jul 13 06:52:14 PM PDT 24 Jul 13 06:52:15 PM PDT 24 23334775 ps
T1075 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3176823051 Jul 13 06:52:07 PM PDT 24 Jul 13 06:52:08 PM PDT 24 64838284 ps
T161 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2530335676 Jul 13 06:52:44 PM PDT 24 Jul 13 06:52:51 PM PDT 24 971572656 ps
T1076 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2463002050 Jul 13 06:52:44 PM PDT 24 Jul 13 06:52:47 PM PDT 24 199023681 ps
T1077 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3031826104 Jul 13 06:52:24 PM PDT 24 Jul 13 06:52:26 PM PDT 24 172488197 ps

Test location /workspace/coverage/default/20.keymgr_lc_disable.3239961180
Short name T16
Test name
Test status
Simulation time 52587587 ps
CPU time 3.51 seconds
Started Jul 13 06:56:54 PM PDT 24
Finished Jul 13 06:56:59 PM PDT 24
Peak memory 222564 kb
Host smart-bb1e733f-3190-40ed-974f-36bb112f5154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239961180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3239961180
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.780293998
Short name T42
Test name
Test status
Simulation time 1163604537 ps
CPU time 35 seconds
Started Jul 13 06:56:04 PM PDT 24
Finished Jul 13 06:56:39 PM PDT 24
Peak memory 221096 kb
Host smart-478bfa6e-9df0-4421-8f07-1869a5722c31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780293998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.780293998
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1951149946
Short name T27
Test name
Test status
Simulation time 2922771123 ps
CPU time 20.7 seconds
Started Jul 13 06:57:34 PM PDT 24
Finished Jul 13 06:57:56 PM PDT 24
Peak memory 215280 kb
Host smart-96d96f22-a84a-4744-8ba6-e8f08511219d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951149946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1951149946
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.984330470
Short name T55
Test name
Test status
Simulation time 196357291 ps
CPU time 13.25 seconds
Started Jul 13 06:56:03 PM PDT 24
Finished Jul 13 06:56:17 PM PDT 24
Peak memory 222068 kb
Host smart-46183f87-a137-4901-8fcc-47b1e34e3531
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984330470 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.984330470
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3243924812
Short name T12
Test name
Test status
Simulation time 1161264279 ps
CPU time 10.54 seconds
Started Jul 13 06:55:54 PM PDT 24
Finished Jul 13 06:56:05 PM PDT 24
Peak memory 229740 kb
Host smart-aab6d6c6-87a0-4c20-b2df-ffaec63ae6e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243924812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3243924812
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.596095318
Short name T8
Test name
Test status
Simulation time 16842717249 ps
CPU time 118.71 seconds
Started Jul 13 06:57:18 PM PDT 24
Finished Jul 13 06:59:17 PM PDT 24
Peak memory 216332 kb
Host smart-6637d187-353b-48c9-b759-f013018ea371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596095318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.596095318
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3564302092
Short name T156
Test name
Test status
Simulation time 1070384646 ps
CPU time 9.61 seconds
Started Jul 13 06:52:33 PM PDT 24
Finished Jul 13 06:52:43 PM PDT 24
Peak memory 205520 kb
Host smart-1ccfd6cf-4213-424b-b839-5b09dacd71d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564302092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3564302092
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1159727342
Short name T43
Test name
Test status
Simulation time 5483646551 ps
CPU time 66.42 seconds
Started Jul 13 06:57:51 PM PDT 24
Finished Jul 13 06:58:59 PM PDT 24
Peak memory 222364 kb
Host smart-129c093c-4107-4208-baca-7217bfddcfb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159727342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1159727342
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3784031471
Short name T120
Test name
Test status
Simulation time 110821696 ps
CPU time 6.38 seconds
Started Jul 13 06:56:54 PM PDT 24
Finished Jul 13 06:57:01 PM PDT 24
Peak memory 214348 kb
Host smart-a51e3e92-1128-4a2d-b1b6-87df28620844
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3784031471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3784031471
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1009706908
Short name T2
Test name
Test status
Simulation time 97089533 ps
CPU time 3.12 seconds
Started Jul 13 06:55:33 PM PDT 24
Finished Jul 13 06:55:36 PM PDT 24
Peak memory 222532 kb
Host smart-9e3b627b-5420-4de3-be63-72ab3faae560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009706908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1009706908
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.878636753
Short name T10
Test name
Test status
Simulation time 340180794 ps
CPU time 3.1 seconds
Started Jul 13 06:57:40 PM PDT 24
Finished Jul 13 06:57:44 PM PDT 24
Peak memory 220688 kb
Host smart-cd6407c4-17fa-4d57-9fb8-473c49ce09fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878636753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.878636753
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1800736185
Short name T44
Test name
Test status
Simulation time 587051765 ps
CPU time 12.65 seconds
Started Jul 13 06:56:36 PM PDT 24
Finished Jul 13 06:56:50 PM PDT 24
Peak memory 220676 kb
Host smart-65eb0bcc-f25d-4938-bbee-68c64487deba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800736185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1800736185
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2480780036
Short name T268
Test name
Test status
Simulation time 3013630859 ps
CPU time 82.35 seconds
Started Jul 13 06:55:45 PM PDT 24
Finished Jul 13 06:57:08 PM PDT 24
Peak memory 215000 kb
Host smart-182c7f37-a6fa-474c-9813-2443607f4dbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2480780036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2480780036
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3554162279
Short name T121
Test name
Test status
Simulation time 324856723 ps
CPU time 3.2 seconds
Started Jul 13 06:52:24 PM PDT 24
Finished Jul 13 06:52:27 PM PDT 24
Peak memory 213956 kb
Host smart-8dad03cc-a10c-42de-80e9-eba09bdb0cfd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554162279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3554162279
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1120606756
Short name T17
Test name
Test status
Simulation time 891810979 ps
CPU time 5.16 seconds
Started Jul 13 06:56:37 PM PDT 24
Finished Jul 13 06:56:44 PM PDT 24
Peak memory 214276 kb
Host smart-cecf1e43-14d1-4099-a994-aa2d6c88e56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120606756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1120606756
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3788274339
Short name T19
Test name
Test status
Simulation time 29608289 ps
CPU time 2.17 seconds
Started Jul 13 06:55:45 PM PDT 24
Finished Jul 13 06:55:48 PM PDT 24
Peak memory 208952 kb
Host smart-277edf11-711e-419c-b7de-7d4b1fbace32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788274339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3788274339
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3356205126
Short name T341
Test name
Test status
Simulation time 1612325808 ps
CPU time 42.26 seconds
Started Jul 13 06:58:17 PM PDT 24
Finished Jul 13 06:59:04 PM PDT 24
Peak memory 214808 kb
Host smart-b67843de-cb16-48cd-8eac-69af5f978eb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3356205126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3356205126
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3485239376
Short name T138
Test name
Test status
Simulation time 87902780 ps
CPU time 5.26 seconds
Started Jul 13 06:58:22 PM PDT 24
Finished Jul 13 06:58:31 PM PDT 24
Peak memory 215352 kb
Host smart-39d8ff87-4e80-4a21-9699-42174c638e5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3485239376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3485239376
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1574280024
Short name T199
Test name
Test status
Simulation time 741603454 ps
CPU time 10.62 seconds
Started Jul 13 06:56:19 PM PDT 24
Finished Jul 13 06:56:31 PM PDT 24
Peak memory 215944 kb
Host smart-8056570c-1c9f-4352-a56d-59dca6790c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574280024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1574280024
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2569621626
Short name T48
Test name
Test status
Simulation time 1943825895 ps
CPU time 20.91 seconds
Started Jul 13 06:57:54 PM PDT 24
Finished Jul 13 06:58:16 PM PDT 24
Peak memory 220840 kb
Host smart-811415fb-da17-4f15-a4b7-91d2f30f6ba3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569621626 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2569621626
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.24864327
Short name T309
Test name
Test status
Simulation time 2215609429 ps
CPU time 59.83 seconds
Started Jul 13 06:57:21 PM PDT 24
Finished Jul 13 06:58:23 PM PDT 24
Peak memory 217324 kb
Host smart-e0239ff9-cbd7-470e-8ff7-85c4be1e18aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24864327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.24864327
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.126380598
Short name T36
Test name
Test status
Simulation time 62414644 ps
CPU time 3.31 seconds
Started Jul 13 06:56:30 PM PDT 24
Finished Jul 13 06:56:34 PM PDT 24
Peak memory 210044 kb
Host smart-2e170053-fe39-4e8d-9e6c-b623699a3084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126380598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.126380598
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1354139168
Short name T60
Test name
Test status
Simulation time 5549012707 ps
CPU time 107.85 seconds
Started Jul 13 06:58:28 PM PDT 24
Finished Jul 13 07:00:18 PM PDT 24
Peak memory 216760 kb
Host smart-a5ac32eb-41b7-42ee-b71f-407a6ee91275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354139168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1354139168
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.825578380
Short name T21
Test name
Test status
Simulation time 232503815 ps
CPU time 1.78 seconds
Started Jul 13 06:58:09 PM PDT 24
Finished Jul 13 06:58:13 PM PDT 24
Peak memory 214708 kb
Host smart-ffc031f3-8191-427a-924b-5afe04fe6257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825578380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.825578380
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3410162983
Short name T414
Test name
Test status
Simulation time 1206394838 ps
CPU time 18.38 seconds
Started Jul 13 06:56:38 PM PDT 24
Finished Jul 13 06:56:58 PM PDT 24
Peak memory 215184 kb
Host smart-dc4582ac-c26c-41f7-ac9d-a661fef014d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3410162983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3410162983
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2318989044
Short name T151
Test name
Test status
Simulation time 711624045 ps
CPU time 3.43 seconds
Started Jul 13 06:57:17 PM PDT 24
Finished Jul 13 06:57:21 PM PDT 24
Peak memory 217420 kb
Host smart-aae709f4-d4fe-4ef2-92c7-a658c07f1fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318989044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2318989044
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.117998283
Short name T115
Test name
Test status
Simulation time 355152384 ps
CPU time 6.54 seconds
Started Jul 13 06:52:24 PM PDT 24
Finished Jul 13 06:52:31 PM PDT 24
Peak memory 213944 kb
Host smart-63ec2f6f-4a43-48e7-9fd6-cb0016367cfd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117998283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.117998283
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/45.keymgr_random.2321040304
Short name T131
Test name
Test status
Simulation time 1915423345 ps
CPU time 18.29 seconds
Started Jul 13 06:58:18 PM PDT 24
Finished Jul 13 06:58:42 PM PDT 24
Peak memory 208836 kb
Host smart-17389220-5457-4a49-b819-a5a1c4a42e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321040304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2321040304
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1097700545
Short name T84
Test name
Test status
Simulation time 38322064 ps
CPU time 2.72 seconds
Started Jul 13 06:56:11 PM PDT 24
Finished Jul 13 06:56:15 PM PDT 24
Peak memory 209460 kb
Host smart-490b5a2c-bba6-4d34-ae16-b8d9a139f282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097700545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1097700545
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2722257089
Short name T225
Test name
Test status
Simulation time 64338248 ps
CPU time 1.84 seconds
Started Jul 13 06:58:21 PM PDT 24
Finished Jul 13 06:58:27 PM PDT 24
Peak memory 208884 kb
Host smart-29530b45-1637-480a-a883-45e350fb4d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722257089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2722257089
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2793112649
Short name T140
Test name
Test status
Simulation time 1343569041 ps
CPU time 17.58 seconds
Started Jul 13 06:58:15 PM PDT 24
Finished Jul 13 06:58:39 PM PDT 24
Peak memory 214340 kb
Host smart-c414e666-dc96-4e73-81c3-2e288fe69dd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2793112649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2793112649
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3810675352
Short name T273
Test name
Test status
Simulation time 61034646 ps
CPU time 4 seconds
Started Jul 13 06:58:09 PM PDT 24
Finished Jul 13 06:58:17 PM PDT 24
Peak memory 215140 kb
Host smart-91ca4568-859c-4294-ab48-761e2033ef4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3810675352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3810675352
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2170531084
Short name T54
Test name
Test status
Simulation time 622651265 ps
CPU time 2.27 seconds
Started Jul 13 06:57:53 PM PDT 24
Finished Jul 13 06:57:57 PM PDT 24
Peak memory 210148 kb
Host smart-2254836c-05da-4ee5-be7c-74bf3dce11f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170531084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2170531084
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2227971047
Short name T266
Test name
Test status
Simulation time 374276923 ps
CPU time 4.79 seconds
Started Jul 13 06:55:47 PM PDT 24
Finished Jul 13 06:55:53 PM PDT 24
Peak memory 222456 kb
Host smart-af118006-a34a-474a-94d7-9c0bd651b5c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2227971047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2227971047
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3548464813
Short name T221
Test name
Test status
Simulation time 288751852 ps
CPU time 15.16 seconds
Started Jul 13 06:58:15 PM PDT 24
Finished Jul 13 06:58:36 PM PDT 24
Peak memory 215604 kb
Host smart-cf06bcb5-b295-457a-84f9-fa823409eeec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548464813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3548464813
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.4176483890
Short name T33
Test name
Test status
Simulation time 278320418 ps
CPU time 9.29 seconds
Started Jul 13 06:57:19 PM PDT 24
Finished Jul 13 06:57:30 PM PDT 24
Peak memory 223116 kb
Host smart-841bd2a9-c336-4ee3-83a0-e0ba08728f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176483890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.4176483890
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3982564101
Short name T288
Test name
Test status
Simulation time 89512240240 ps
CPU time 583.86 seconds
Started Jul 13 06:56:49 PM PDT 24
Finished Jul 13 07:06:33 PM PDT 24
Peak memory 222604 kb
Host smart-ecbb0a0c-ece7-4c72-94d1-303eedb15f2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982564101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3982564101
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_random.398040365
Short name T215
Test name
Test status
Simulation time 89446060 ps
CPU time 4.41 seconds
Started Jul 13 06:58:10 PM PDT 24
Finished Jul 13 06:58:18 PM PDT 24
Peak memory 207908 kb
Host smart-1bf135f7-6e98-4bfd-8e14-b72c519ab941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398040365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.398040365
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.417960119
Short name T298
Test name
Test status
Simulation time 245084731 ps
CPU time 3.65 seconds
Started Jul 13 06:58:12 PM PDT 24
Finished Jul 13 06:58:20 PM PDT 24
Peak memory 217396 kb
Host smart-1b3b3ab6-dd2a-4339-b622-07e7ce54eaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417960119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.417960119
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.298469124
Short name T444
Test name
Test status
Simulation time 30455202 ps
CPU time 0.83 seconds
Started Jul 13 06:56:22 PM PDT 24
Finished Jul 13 06:56:24 PM PDT 24
Peak memory 205956 kb
Host smart-6aca5e12-fbb8-40c3-859a-911de2692804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298469124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.298469124
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2906525260
Short name T242
Test name
Test status
Simulation time 1546406044 ps
CPU time 38.72 seconds
Started Jul 13 06:57:09 PM PDT 24
Finished Jul 13 06:57:49 PM PDT 24
Peak memory 222524 kb
Host smart-75f42ae0-95ba-4eda-9452-deeeddf88709
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906525260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2906525260
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.78262134
Short name T422
Test name
Test status
Simulation time 290183150 ps
CPU time 16.53 seconds
Started Jul 13 06:55:39 PM PDT 24
Finished Jul 13 06:55:57 PM PDT 24
Peak memory 215568 kb
Host smart-4c3510a3-9763-40bc-a494-9def9ee7ba06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78262134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.78262134
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2052977738
Short name T278
Test name
Test status
Simulation time 131130013 ps
CPU time 4.01 seconds
Started Jul 13 06:55:43 PM PDT 24
Finished Jul 13 06:55:47 PM PDT 24
Peak memory 214340 kb
Host smart-689ed674-9984-4ad1-9c72-e9c9591bd773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052977738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2052977738
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2725712144
Short name T208
Test name
Test status
Simulation time 362013874 ps
CPU time 3.69 seconds
Started Jul 13 06:56:46 PM PDT 24
Finished Jul 13 06:56:50 PM PDT 24
Peak memory 208760 kb
Host smart-94bac047-caf7-4fe7-a479-7e025a9e8f2d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725712144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2725712144
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.263825646
Short name T900
Test name
Test status
Simulation time 706891820 ps
CPU time 27.9 seconds
Started Jul 13 06:57:50 PM PDT 24
Finished Jul 13 06:58:18 PM PDT 24
Peak memory 215036 kb
Host smart-5e7bc52e-15ad-44fb-9b57-387006e5d212
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263825646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.263825646
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1918150128
Short name T350
Test name
Test status
Simulation time 942190271 ps
CPU time 49.55 seconds
Started Jul 13 06:58:09 PM PDT 24
Finished Jul 13 06:59:02 PM PDT 24
Peak memory 214816 kb
Host smart-75f02da4-6235-450d-89fd-500fd4a3f1f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1918150128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1918150128
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1679173484
Short name T308
Test name
Test status
Simulation time 854337363 ps
CPU time 4.21 seconds
Started Jul 13 06:58:08 PM PDT 24
Finished Jul 13 06:58:15 PM PDT 24
Peak memory 214344 kb
Host smart-c662699d-5020-4c95-8ff5-af6d0df7e52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679173484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1679173484
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3377337427
Short name T98
Test name
Test status
Simulation time 437501218 ps
CPU time 5.01 seconds
Started Jul 13 06:55:54 PM PDT 24
Finished Jul 13 06:56:00 PM PDT 24
Peak memory 214368 kb
Host smart-523dfc6e-159b-4c1d-a477-02ab18aaf51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377337427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3377337427
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2280951745
Short name T149
Test name
Test status
Simulation time 31121356 ps
CPU time 2.07 seconds
Started Jul 13 06:56:09 PM PDT 24
Finished Jul 13 06:56:12 PM PDT 24
Peak memory 215968 kb
Host smart-655b5b89-fc2e-426e-bd4a-0857b0bfe547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280951745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2280951745
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1602986066
Short name T233
Test name
Test status
Simulation time 1875925857 ps
CPU time 57.35 seconds
Started Jul 13 06:57:18 PM PDT 24
Finished Jul 13 06:58:18 PM PDT 24
Peak memory 216332 kb
Host smart-447d5181-b079-402c-86fd-2b5b48794c06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602986066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1602986066
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2079225684
Short name T159
Test name
Test status
Simulation time 109988851 ps
CPU time 3.33 seconds
Started Jul 13 06:52:30 PM PDT 24
Finished Jul 13 06:52:33 PM PDT 24
Peak memory 213756 kb
Host smart-dff23659-6b9c-4b08-9a48-c5d9282d9e46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079225684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2079225684
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.407435165
Short name T153
Test name
Test status
Simulation time 170618721 ps
CPU time 3.28 seconds
Started Jul 13 06:57:16 PM PDT 24
Finished Jul 13 06:57:20 PM PDT 24
Peak memory 217964 kb
Host smart-d1eb5c92-3c89-4a2e-a21e-c748c9649466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407435165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.407435165
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.787862416
Short name T172
Test name
Test status
Simulation time 160947196 ps
CPU time 3.79 seconds
Started Jul 13 06:51:48 PM PDT 24
Finished Jul 13 06:51:52 PM PDT 24
Peak memory 205700 kb
Host smart-e4cadb05-997b-47c2-b963-edd698b932e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787862416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
787862416
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.679750643
Short name T174
Test name
Test status
Simulation time 213268681 ps
CPU time 6.26 seconds
Started Jul 13 06:52:15 PM PDT 24
Finished Jul 13 06:52:22 PM PDT 24
Peak memory 213976 kb
Host smart-f248ee59-28d6-48c0-8c37-4ce3a2f0b86e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679750643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
679750643
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.787539964
Short name T72
Test name
Test status
Simulation time 3077789559 ps
CPU time 31.85 seconds
Started Jul 13 06:55:40 PM PDT 24
Finished Jul 13 06:56:13 PM PDT 24
Peak memory 216048 kb
Host smart-50d0f995-8e63-4cfe-bbc6-a4e7a7c77a09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787539964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.787539964
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2224256789
Short name T46
Test name
Test status
Simulation time 129329734 ps
CPU time 2.02 seconds
Started Jul 13 06:57:42 PM PDT 24
Finished Jul 13 06:57:46 PM PDT 24
Peak memory 214344 kb
Host smart-2807ac6c-a75e-4539-8fa8-aa5be76e9cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224256789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2224256789
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3543907007
Short name T286
Test name
Test status
Simulation time 2849002684 ps
CPU time 14.43 seconds
Started Jul 13 06:58:09 PM PDT 24
Finished Jul 13 06:58:28 PM PDT 24
Peak memory 222656 kb
Host smart-8d8191c8-c2f5-476c-8b83-2d6dc2043b77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543907007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3543907007
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.76205629
Short name T854
Test name
Test status
Simulation time 44936888662 ps
CPU time 96.83 seconds
Started Jul 13 06:58:15 PM PDT 24
Finished Jul 13 06:59:58 PM PDT 24
Peak memory 222556 kb
Host smart-b95711f1-0168-495e-bb9c-8662798e75e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76205629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.76205629
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.769629738
Short name T178
Test name
Test status
Simulation time 100863687 ps
CPU time 1.69 seconds
Started Jul 13 06:56:30 PM PDT 24
Finished Jul 13 06:56:32 PM PDT 24
Peak memory 209736 kb
Host smart-6af1c84b-0453-4edc-ae41-f5599c396817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769629738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.769629738
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1879837669
Short name T176
Test name
Test status
Simulation time 51656559 ps
CPU time 2.94 seconds
Started Jul 13 06:52:06 PM PDT 24
Finished Jul 13 06:52:10 PM PDT 24
Peak memory 205512 kb
Host smart-1c284c51-e8d4-4f71-b493-a01b50058a39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879837669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1879837669
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.900709630
Short name T175
Test name
Test status
Simulation time 951164937 ps
CPU time 6.15 seconds
Started Jul 13 06:52:13 PM PDT 24
Finished Jul 13 06:52:20 PM PDT 24
Peak memory 215132 kb
Host smart-9931ec45-47cc-47cf-b4b8-d8508ce79bc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900709630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
900709630
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1287893194
Short name T472
Test name
Test status
Simulation time 444519517 ps
CPU time 3.69 seconds
Started Jul 13 06:56:42 PM PDT 24
Finished Jul 13 06:56:47 PM PDT 24
Peak memory 222364 kb
Host smart-b7fe7669-5bc1-4a50-8af3-95a1959483eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287893194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1287893194
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1547529004
Short name T260
Test name
Test status
Simulation time 48929183 ps
CPU time 1.89 seconds
Started Jul 13 06:56:37 PM PDT 24
Finished Jul 13 06:56:40 PM PDT 24
Peak memory 214272 kb
Host smart-f8788185-791c-43ff-be0d-f855f01c9a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547529004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1547529004
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1000753359
Short name T816
Test name
Test status
Simulation time 240703868 ps
CPU time 3.22 seconds
Started Jul 13 06:57:07 PM PDT 24
Finished Jul 13 06:57:10 PM PDT 24
Peak memory 214364 kb
Host smart-f7684202-cbc7-4ed8-bb3a-99c3825f5b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000753359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1000753359
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3650353403
Short name T82
Test name
Test status
Simulation time 1263215318 ps
CPU time 13.58 seconds
Started Jul 13 06:57:08 PM PDT 24
Finished Jul 13 06:57:24 PM PDT 24
Peak memory 222872 kb
Host smart-8feeffe6-5cd1-4adf-83b6-2f7202e96159
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650353403 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3650353403
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2894923163
Short name T415
Test name
Test status
Simulation time 1069700529 ps
CPU time 53.02 seconds
Started Jul 13 06:58:28 PM PDT 24
Finished Jul 13 06:59:23 PM PDT 24
Peak memory 214876 kb
Host smart-613d83d7-2e5b-4017-8f7f-d50437b0f58e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2894923163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2894923163
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1003149217
Short name T179
Test name
Test status
Simulation time 86043067 ps
CPU time 3.01 seconds
Started Jul 13 06:58:07 PM PDT 24
Finished Jul 13 06:58:11 PM PDT 24
Peak memory 210068 kb
Host smart-9818eee3-34d4-4bd5-ba9a-e311959f580d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003149217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1003149217
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2766607697
Short name T150
Test name
Test status
Simulation time 346861777 ps
CPU time 4.19 seconds
Started Jul 13 06:58:20 PM PDT 24
Finished Jul 13 06:58:28 PM PDT 24
Peak memory 217448 kb
Host smart-464bc09c-5b10-414b-b851-8e2af66e9944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766607697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2766607697
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1167329054
Short name T320
Test name
Test status
Simulation time 11739193461 ps
CPU time 328.6 seconds
Started Jul 13 06:55:42 PM PDT 24
Finished Jul 13 07:01:11 PM PDT 24
Peak memory 221596 kb
Host smart-841a84bb-b1f9-44c6-9740-febcde37b205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167329054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1167329054
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.37294017
Short name T416
Test name
Test status
Simulation time 2644227531 ps
CPU time 12.92 seconds
Started Jul 13 06:56:46 PM PDT 24
Finished Jul 13 06:57:00 PM PDT 24
Peak memory 214400 kb
Host smart-0d00f73b-9296-4f5d-8ba7-a3306fbfad95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37294017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.37294017
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1468010496
Short name T249
Test name
Test status
Simulation time 317991647 ps
CPU time 7.99 seconds
Started Jul 13 06:56:48 PM PDT 24
Finished Jul 13 06:56:57 PM PDT 24
Peak memory 208392 kb
Host smart-b5bf0da9-19c5-4299-b3d4-f8876eaaa931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468010496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1468010496
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.193676661
Short name T239
Test name
Test status
Simulation time 81510353098 ps
CPU time 214.49 seconds
Started Jul 13 06:56:56 PM PDT 24
Finished Jul 13 07:00:32 PM PDT 24
Peak memory 217140 kb
Host smart-34b0f7aa-44e9-418c-997b-7efd7f4f8463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193676661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.193676661
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.451333448
Short name T193
Test name
Test status
Simulation time 2840401546 ps
CPU time 27.94 seconds
Started Jul 13 06:57:24 PM PDT 24
Finished Jul 13 06:57:54 PM PDT 24
Peak memory 218828 kb
Host smart-8e28c988-b04c-4f1e-8a0d-84abfbbf9af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451333448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.451333448
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.19270699
Short name T243
Test name
Test status
Simulation time 1793273153 ps
CPU time 34.19 seconds
Started Jul 13 06:57:24 PM PDT 24
Finished Jul 13 06:58:00 PM PDT 24
Peak memory 215616 kb
Host smart-225bbfae-c883-4648-9114-4fbf1df59ce5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19270699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.19270699
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1201056215
Short name T234
Test name
Test status
Simulation time 1340430103 ps
CPU time 48.98 seconds
Started Jul 13 06:57:24 PM PDT 24
Finished Jul 13 06:58:15 PM PDT 24
Peak memory 217076 kb
Host smart-f9599a09-4d22-4d8c-b005-eee00943a3ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201056215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1201056215
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2697162280
Short name T492
Test name
Test status
Simulation time 55067511 ps
CPU time 2.93 seconds
Started Jul 13 06:58:13 PM PDT 24
Finished Jul 13 06:58:21 PM PDT 24
Peak memory 208412 kb
Host smart-27e657db-e86d-4d29-ac5a-045a1dd4d966
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697162280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2697162280
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3800943338
Short name T241
Test name
Test status
Simulation time 1626377972 ps
CPU time 23.28 seconds
Started Jul 13 06:58:21 PM PDT 24
Finished Jul 13 06:58:48 PM PDT 24
Peak memory 215376 kb
Host smart-8ccf74e8-d4b6-4a40-af44-1766aa3848d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800943338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3800943338
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2364684495
Short name T158
Test name
Test status
Simulation time 92108924 ps
CPU time 2.34 seconds
Started Jul 13 06:52:57 PM PDT 24
Finished Jul 13 06:53:00 PM PDT 24
Peak memory 213740 kb
Host smart-9780a38a-954c-4294-ac08-92012c7affd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364684495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2364684495
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1168879704
Short name T169
Test name
Test status
Simulation time 95269343 ps
CPU time 2.47 seconds
Started Jul 13 06:51:57 PM PDT 24
Finished Jul 13 06:52:00 PM PDT 24
Peak memory 213700 kb
Host smart-85bf4a57-5023-4ffa-927d-58ace8083977
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168879704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1168879704
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.241089463
Short name T177
Test name
Test status
Simulation time 1123159658 ps
CPU time 9.65 seconds
Started Jul 13 06:52:31 PM PDT 24
Finished Jul 13 06:52:41 PM PDT 24
Peak memory 213640 kb
Host smart-7205d844-210f-4aa4-85ab-4d62c93236d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241089463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
241089463
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1216081481
Short name T23
Test name
Test status
Simulation time 389674487 ps
CPU time 2.99 seconds
Started Jul 13 06:56:22 PM PDT 24
Finished Jul 13 06:56:26 PM PDT 24
Peak memory 222944 kb
Host smart-e5cef7ad-c6d8-4292-8023-f285620b7912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216081481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1216081481
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.164844606
Short name T155
Test name
Test status
Simulation time 321219093 ps
CPU time 3.47 seconds
Started Jul 13 06:57:26 PM PDT 24
Finished Jul 13 06:57:31 PM PDT 24
Peak memory 218432 kb
Host smart-4e823cf4-5318-4454-bba9-5ee4e3170d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164844606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.164844606
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3950015736
Short name T59
Test name
Test status
Simulation time 112488158 ps
CPU time 2.53 seconds
Started Jul 13 06:58:12 PM PDT 24
Finished Jul 13 06:58:19 PM PDT 24
Peak memory 210152 kb
Host smart-3a01a5d6-c0df-450b-98f5-c5a98e82341a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950015736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3950015736
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.177123148
Short name T26
Test name
Test status
Simulation time 2008794065 ps
CPU time 26.34 seconds
Started Jul 13 06:55:31 PM PDT 24
Finished Jul 13 06:55:59 PM PDT 24
Peak memory 214392 kb
Host smart-e31448d1-6e05-4b9b-9365-9d1ec84c6e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177123148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.177123148
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3372106555
Short name T6
Test name
Test status
Simulation time 805183772 ps
CPU time 9.49 seconds
Started Jul 13 06:55:40 PM PDT 24
Finished Jul 13 06:55:50 PM PDT 24
Peak memory 222648 kb
Host smart-6a5f4abc-5f76-4de3-aaea-dcb0089b2ea0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372106555 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3372106555
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.4266098988
Short name T357
Test name
Test status
Simulation time 478773599 ps
CPU time 4.25 seconds
Started Jul 13 06:56:20 PM PDT 24
Finished Jul 13 06:56:25 PM PDT 24
Peak memory 214300 kb
Host smart-929f03f9-472d-476e-99c9-6035cca5c2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266098988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.4266098988
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1798155267
Short name T237
Test name
Test status
Simulation time 292932550 ps
CPU time 8.57 seconds
Started Jul 13 06:56:17 PM PDT 24
Finished Jul 13 06:56:26 PM PDT 24
Peak memory 221896 kb
Host smart-344977ef-dbd3-4ffa-a06a-6af7d3096548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798155267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1798155267
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3659468197
Short name T427
Test name
Test status
Simulation time 367105418 ps
CPU time 3.57 seconds
Started Jul 13 06:56:22 PM PDT 24
Finished Jul 13 06:56:27 PM PDT 24
Peak memory 214344 kb
Host smart-83ca2b4c-a248-4cc0-b3db-b15d54d493d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3659468197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3659468197
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2768018858
Short name T354
Test name
Test status
Simulation time 418749572 ps
CPU time 3.45 seconds
Started Jul 13 06:56:30 PM PDT 24
Finished Jul 13 06:56:34 PM PDT 24
Peak memory 214548 kb
Host smart-c44ec078-d747-42af-8461-6459dc12d224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768018858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2768018858
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3629895352
Short name T726
Test name
Test status
Simulation time 155010352 ps
CPU time 2.31 seconds
Started Jul 13 06:56:38 PM PDT 24
Finished Jul 13 06:56:42 PM PDT 24
Peak memory 215788 kb
Host smart-cc871f54-4cfd-4349-83cf-270a6f267a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629895352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3629895352
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2729478706
Short name T389
Test name
Test status
Simulation time 159208254 ps
CPU time 3.07 seconds
Started Jul 13 06:56:38 PM PDT 24
Finished Jul 13 06:56:43 PM PDT 24
Peak memory 222504 kb
Host smart-6f6fcdb8-79fb-42e1-a5fb-80390e5b26a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729478706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2729478706
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1940834181
Short name T318
Test name
Test status
Simulation time 507165262 ps
CPU time 9.78 seconds
Started Jul 13 06:56:49 PM PDT 24
Finished Jul 13 06:56:59 PM PDT 24
Peak memory 218240 kb
Host smart-2b45b624-756f-4303-b0c3-f706b061cbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940834181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1940834181
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2491134851
Short name T97
Test name
Test status
Simulation time 119242913 ps
CPU time 3.98 seconds
Started Jul 13 06:56:55 PM PDT 24
Finished Jul 13 06:57:00 PM PDT 24
Peak memory 220676 kb
Host smart-ed3899a1-a8b1-4c91-99fa-864f01f2d5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491134851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2491134851
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1434590431
Short name T363
Test name
Test status
Simulation time 162528150 ps
CPU time 2.62 seconds
Started Jul 13 06:56:54 PM PDT 24
Finished Jul 13 06:56:58 PM PDT 24
Peak memory 207376 kb
Host smart-451b512a-e29e-4416-9520-75c087f9459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434590431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1434590431
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.709091706
Short name T372
Test name
Test status
Simulation time 77148410 ps
CPU time 2.05 seconds
Started Jul 13 06:57:07 PM PDT 24
Finished Jul 13 06:57:09 PM PDT 24
Peak memory 214260 kb
Host smart-7a2775c3-4f5b-4273-9e00-1288bd757cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709091706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.709091706
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1063081733
Short name T232
Test name
Test status
Simulation time 508809748 ps
CPU time 3.87 seconds
Started Jul 13 06:57:18 PM PDT 24
Finished Jul 13 06:57:23 PM PDT 24
Peak memory 210272 kb
Host smart-5c778b07-a1e6-4aeb-b940-b83007701bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063081733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1063081733
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1049552232
Short name T323
Test name
Test status
Simulation time 54030829 ps
CPU time 3.64 seconds
Started Jul 13 06:57:18 PM PDT 24
Finished Jul 13 06:57:24 PM PDT 24
Peak memory 214328 kb
Host smart-26802c93-c05a-4bc2-9b11-46901f4a56f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049552232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1049552232
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.178903471
Short name T261
Test name
Test status
Simulation time 217728539 ps
CPU time 5.04 seconds
Started Jul 13 06:57:28 PM PDT 24
Finished Jul 13 06:57:35 PM PDT 24
Peak memory 215468 kb
Host smart-d3cc3290-2762-44e6-b9bd-7bab99f8b142
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=178903471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.178903471
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.4192341214
Short name T219
Test name
Test status
Simulation time 336466364 ps
CPU time 4.27 seconds
Started Jul 13 06:57:33 PM PDT 24
Finished Jul 13 06:57:38 PM PDT 24
Peak memory 214328 kb
Host smart-b3a5a756-34c1-4dcb-a229-88a8a1b666ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192341214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.4192341214
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.532565096
Short name T387
Test name
Test status
Simulation time 70300589 ps
CPU time 3.2 seconds
Started Jul 13 06:58:18 PM PDT 24
Finished Jul 13 06:58:26 PM PDT 24
Peak memory 214276 kb
Host smart-b46a61ce-a98d-44a6-8b19-2a4ee552a580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532565096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.532565096
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1023296824
Short name T223
Test name
Test status
Simulation time 115712063 ps
CPU time 4.38 seconds
Started Jul 13 06:58:19 PM PDT 24
Finished Jul 13 06:58:28 PM PDT 24
Peak memory 210068 kb
Host smart-af2d121f-0dfb-49df-a40a-15884e5f8de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023296824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1023296824
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1217753297
Short name T154
Test name
Test status
Simulation time 113544185 ps
CPU time 3.94 seconds
Started Jul 13 06:56:58 PM PDT 24
Finished Jul 13 06:57:03 PM PDT 24
Peak memory 222756 kb
Host smart-32bd5d39-bbb4-4c0f-a8ed-718cd6399d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217753297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1217753297
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1271005817
Short name T152
Test name
Test status
Simulation time 78014160 ps
CPU time 2.62 seconds
Started Jul 13 06:55:52 PM PDT 24
Finished Jul 13 06:55:55 PM PDT 24
Peak memory 222652 kb
Host smart-89c7dc01-923e-4f96-8489-b869a85c9285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271005817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1271005817
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2597261076
Short name T1014
Test name
Test status
Simulation time 70351618 ps
CPU time 4.3 seconds
Started Jul 13 06:51:41 PM PDT 24
Finished Jul 13 06:51:46 PM PDT 24
Peak memory 205528 kb
Host smart-896f97c9-eb82-428c-82e1-520088ec92f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597261076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
597261076
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2754389725
Short name T936
Test name
Test status
Simulation time 310872641 ps
CPU time 12.51 seconds
Started Jul 13 06:51:39 PM PDT 24
Finished Jul 13 06:51:52 PM PDT 24
Peak memory 205596 kb
Host smart-b77e961d-4ba6-40e8-9f7d-42784e79fced
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754389725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
754389725
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2566428121
Short name T1035
Test name
Test status
Simulation time 73799843 ps
CPU time 1 seconds
Started Jul 13 06:51:39 PM PDT 24
Finished Jul 13 06:51:40 PM PDT 24
Peak memory 205436 kb
Host smart-65c45480-8a0b-4e62-89cc-67a0db24db08
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566428121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
566428121
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2910439506
Short name T1061
Test name
Test status
Simulation time 26725615 ps
CPU time 1.15 seconds
Started Jul 13 06:51:39 PM PDT 24
Finished Jul 13 06:51:41 PM PDT 24
Peak memory 205588 kb
Host smart-31c3053d-b7e0-431a-a4e2-224a34aefcd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910439506 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2910439506
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3313692846
Short name T1044
Test name
Test status
Simulation time 14720979 ps
CPU time 1.25 seconds
Started Jul 13 06:51:39 PM PDT 24
Finished Jul 13 06:51:41 PM PDT 24
Peak memory 205536 kb
Host smart-5325f34f-4c21-445d-8bc6-d075595fe881
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313692846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3313692846
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.203175817
Short name T1068
Test name
Test status
Simulation time 39523125 ps
CPU time 0.74 seconds
Started Jul 13 06:51:38 PM PDT 24
Finished Jul 13 06:51:39 PM PDT 24
Peak memory 205248 kb
Host smart-ba74a9ac-bab0-445e-a01c-9640e8a22ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203175817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.203175817
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1467405614
Short name T975
Test name
Test status
Simulation time 35172813 ps
CPU time 1.97 seconds
Started Jul 13 06:51:39 PM PDT 24
Finished Jul 13 06:51:42 PM PDT 24
Peak memory 205408 kb
Host smart-d48f196b-4d14-43c5-b9f7-1dae7b50b9da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467405614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1467405614
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2185343371
Short name T955
Test name
Test status
Simulation time 292781366 ps
CPU time 4.45 seconds
Started Jul 13 06:51:37 PM PDT 24
Finished Jul 13 06:51:42 PM PDT 24
Peak memory 218708 kb
Host smart-1113e660-32de-46b4-a455-d948b0866990
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185343371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2185343371
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1327699240
Short name T1039
Test name
Test status
Simulation time 394036503 ps
CPU time 8.69 seconds
Started Jul 13 06:51:41 PM PDT 24
Finished Jul 13 06:51:50 PM PDT 24
Peak memory 214256 kb
Host smart-7b1132be-5b15-4437-bda2-b509a8276cca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327699240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1327699240
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1468553941
Short name T1031
Test name
Test status
Simulation time 195332688 ps
CPU time 2.05 seconds
Started Jul 13 06:51:38 PM PDT 24
Finished Jul 13 06:51:41 PM PDT 24
Peak memory 213720 kb
Host smart-e928a677-8464-43c2-8f46-11132f109fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468553941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1468553941
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2785855353
Short name T157
Test name
Test status
Simulation time 860818579 ps
CPU time 5.98 seconds
Started Jul 13 06:51:40 PM PDT 24
Finished Jul 13 06:51:46 PM PDT 24
Peak memory 215012 kb
Host smart-cae25f1d-0ea8-4fa2-ab9e-8736c8ec66d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785855353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2785855353
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2095173653
Short name T965
Test name
Test status
Simulation time 1787994681 ps
CPU time 10.52 seconds
Started Jul 13 06:51:51 PM PDT 24
Finished Jul 13 06:52:02 PM PDT 24
Peak memory 205616 kb
Host smart-78130507-ed03-4647-8ba6-bbf927d977d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095173653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
095173653
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2128416459
Short name T921
Test name
Test status
Simulation time 3441748320 ps
CPU time 25.4 seconds
Started Jul 13 06:51:46 PM PDT 24
Finished Jul 13 06:52:12 PM PDT 24
Peak memory 205516 kb
Host smart-2ee77867-ae4c-4a8f-a4ed-3d3af576d422
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128416459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
128416459
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1898399421
Short name T988
Test name
Test status
Simulation time 15875732 ps
CPU time 1.1 seconds
Started Jul 13 06:51:51 PM PDT 24
Finished Jul 13 06:51:53 PM PDT 24
Peak memory 205520 kb
Host smart-10ba9754-4bb4-4a6f-a08d-0c1f21ff322a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898399421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
898399421
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.4084116614
Short name T959
Test name
Test status
Simulation time 68144486 ps
CPU time 1.6 seconds
Started Jul 13 06:51:49 PM PDT 24
Finished Jul 13 06:51:51 PM PDT 24
Peak memory 216324 kb
Host smart-c60b870e-d8a2-470c-b504-dc8bdd89a3ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084116614 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.4084116614
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.622440270
Short name T1000
Test name
Test status
Simulation time 55824278 ps
CPU time 1.02 seconds
Started Jul 13 06:51:46 PM PDT 24
Finished Jul 13 06:51:47 PM PDT 24
Peak memory 205452 kb
Host smart-e934f472-379b-4d3c-b0eb-f0a218350f83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622440270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.622440270
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1051818094
Short name T1032
Test name
Test status
Simulation time 17006953 ps
CPU time 0.78 seconds
Started Jul 13 06:51:48 PM PDT 24
Finished Jul 13 06:51:50 PM PDT 24
Peak memory 205220 kb
Host smart-4e546151-405d-41dc-9141-7751064aef76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051818094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1051818094
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1524992460
Short name T142
Test name
Test status
Simulation time 62941657 ps
CPU time 2.28 seconds
Started Jul 13 06:51:49 PM PDT 24
Finished Jul 13 06:51:51 PM PDT 24
Peak memory 205484 kb
Host smart-a1cf878b-c8b5-4a23-91dc-473321121d27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524992460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1524992460
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1735174621
Short name T956
Test name
Test status
Simulation time 181994820 ps
CPU time 2.43 seconds
Started Jul 13 06:51:51 PM PDT 24
Finished Jul 13 06:51:53 PM PDT 24
Peak memory 213956 kb
Host smart-7791827d-2bdf-4685-a85e-44f204f15c75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735174621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1735174621
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.59961579
Short name T1063
Test name
Test status
Simulation time 229197737 ps
CPU time 9.6 seconds
Started Jul 13 06:51:49 PM PDT 24
Finished Jul 13 06:51:59 PM PDT 24
Peak memory 213936 kb
Host smart-8957541e-edd0-4bb6-bbdf-eb2bde1dfd30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59961579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.ke
ymgr_shadow_reg_errors_with_csr_rw.59961579
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4016151639
Short name T928
Test name
Test status
Simulation time 314894187 ps
CPU time 3.73 seconds
Started Jul 13 06:51:45 PM PDT 24
Finished Jul 13 06:51:49 PM PDT 24
Peak memory 213728 kb
Host smart-0e1699b8-a846-4e6b-8800-a63affc3ac3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016151639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4016151639
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.626666487
Short name T933
Test name
Test status
Simulation time 17363314 ps
CPU time 1.07 seconds
Started Jul 13 06:52:44 PM PDT 24
Finished Jul 13 06:52:46 PM PDT 24
Peak memory 205508 kb
Host smart-e0b6d330-b7d2-4658-8cea-2aa1f4c858dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626666487 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.626666487
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1926846654
Short name T1038
Test name
Test status
Simulation time 66095530 ps
CPU time 1.21 seconds
Started Jul 13 06:52:45 PM PDT 24
Finished Jul 13 06:52:47 PM PDT 24
Peak memory 205536 kb
Host smart-80e51c0b-921a-46bb-babf-24fe9347f8e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926846654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1926846654
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3277483365
Short name T1062
Test name
Test status
Simulation time 10894915 ps
CPU time 0.69 seconds
Started Jul 13 06:52:33 PM PDT 24
Finished Jul 13 06:52:34 PM PDT 24
Peak memory 205248 kb
Host smart-c2a01e3b-944f-4dbf-9f70-0aade57ac37f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277483365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3277483365
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.632600334
Short name T1072
Test name
Test status
Simulation time 107992888 ps
CPU time 1.58 seconds
Started Jul 13 06:52:42 PM PDT 24
Finished Jul 13 06:52:44 PM PDT 24
Peak memory 205456 kb
Host smart-5867a769-8f5b-4c39-9d48-7d0efa2fde3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632600334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.632600334
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.408950280
Short name T1047
Test name
Test status
Simulation time 746798163 ps
CPU time 3.45 seconds
Started Jul 13 06:52:34 PM PDT 24
Finished Jul 13 06:52:38 PM PDT 24
Peak memory 214028 kb
Host smart-ae982af7-4a81-4d7e-8267-9785c7c42844
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408950280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.408950280
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2710970130
Short name T1059
Test name
Test status
Simulation time 626090940 ps
CPU time 6.14 seconds
Started Jul 13 06:52:34 PM PDT 24
Finished Jul 13 06:52:40 PM PDT 24
Peak memory 220052 kb
Host smart-52e2f3a4-d5ca-415b-987b-1c37569e3449
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710970130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2710970130
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2870728600
Short name T953
Test name
Test status
Simulation time 92761328 ps
CPU time 3.3 seconds
Started Jul 13 06:52:33 PM PDT 24
Finished Jul 13 06:52:37 PM PDT 24
Peak memory 213796 kb
Host smart-f56c9005-cdce-43fb-a9e5-3bfd8df6ab01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870728600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2870728600
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3608995181
Short name T941
Test name
Test status
Simulation time 517585415 ps
CPU time 1.48 seconds
Started Jul 13 06:52:46 PM PDT 24
Finished Jul 13 06:52:48 PM PDT 24
Peak memory 205652 kb
Host smart-14bbaa6d-64af-4fad-a00b-4965f7bf053d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608995181 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3608995181
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1590270154
Short name T1069
Test name
Test status
Simulation time 49629283 ps
CPU time 1.02 seconds
Started Jul 13 06:52:48 PM PDT 24
Finished Jul 13 06:52:50 PM PDT 24
Peak memory 205536 kb
Host smart-b874cb03-7025-4a37-8f20-a285c169d8a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590270154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1590270154
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2347228279
Short name T957
Test name
Test status
Simulation time 16399539 ps
CPU time 0.92 seconds
Started Jul 13 06:52:44 PM PDT 24
Finished Jul 13 06:52:46 PM PDT 24
Peak memory 205348 kb
Host smart-891d13d1-96d0-40da-9468-80d727853dca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347228279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2347228279
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2893185561
Short name T970
Test name
Test status
Simulation time 121708569 ps
CPU time 4.14 seconds
Started Jul 13 06:52:48 PM PDT 24
Finished Jul 13 06:52:53 PM PDT 24
Peak memory 205568 kb
Host smart-b77c568f-444f-4f7e-b761-1497af559fc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893185561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2893185561
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1879246902
Short name T997
Test name
Test status
Simulation time 70754230 ps
CPU time 2.6 seconds
Started Jul 13 06:52:43 PM PDT 24
Finished Jul 13 06:52:46 PM PDT 24
Peak memory 213944 kb
Host smart-cf935341-4b3d-48b4-92d3-239f0a1b7a89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879246902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1879246902
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.346284716
Short name T952
Test name
Test status
Simulation time 1363730951 ps
CPU time 8.55 seconds
Started Jul 13 06:52:44 PM PDT 24
Finished Jul 13 06:52:53 PM PDT 24
Peak memory 213988 kb
Host smart-26904c8a-e18d-4968-a934-605ebc9193f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346284716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.346284716
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.67693844
Short name T938
Test name
Test status
Simulation time 603388477 ps
CPU time 2.69 seconds
Started Jul 13 06:52:42 PM PDT 24
Finished Jul 13 06:52:45 PM PDT 24
Peak memory 215804 kb
Host smart-9a6065e2-df73-41f4-bfc0-cedcc155bf26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67693844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.67693844
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2530335676
Short name T161
Test name
Test status
Simulation time 971572656 ps
CPU time 6.05 seconds
Started Jul 13 06:52:44 PM PDT 24
Finished Jul 13 06:52:51 PM PDT 24
Peak memory 205668 kb
Host smart-9b2a9803-740d-45bf-8492-0c4379586543
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530335676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2530335676
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1194880594
Short name T1024
Test name
Test status
Simulation time 32013508 ps
CPU time 1.59 seconds
Started Jul 13 06:52:49 PM PDT 24
Finished Jul 13 06:52:51 PM PDT 24
Peak memory 213784 kb
Host smart-4cc07ec3-8eee-41d0-a360-8e5e8251e5b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194880594 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1194880594
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1332259457
Short name T1016
Test name
Test status
Simulation time 18349609 ps
CPU time 0.87 seconds
Started Jul 13 06:52:45 PM PDT 24
Finished Jul 13 06:52:47 PM PDT 24
Peak memory 205392 kb
Host smart-612e12e1-64c5-4cb5-a3a9-90dc559d5aab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332259457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1332259457
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3219952789
Short name T1021
Test name
Test status
Simulation time 53735449 ps
CPU time 0.87 seconds
Started Jul 13 06:52:46 PM PDT 24
Finished Jul 13 06:52:47 PM PDT 24
Peak memory 205592 kb
Host smart-243e12c7-fd87-48b2-a6a2-fa242107be91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219952789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3219952789
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3479679868
Short name T143
Test name
Test status
Simulation time 49791286 ps
CPU time 1.52 seconds
Started Jul 13 06:52:45 PM PDT 24
Finished Jul 13 06:52:47 PM PDT 24
Peak memory 205444 kb
Host smart-5e04ac68-e542-4941-bf90-e44f890ca611
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479679868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3479679868
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2706550597
Short name T968
Test name
Test status
Simulation time 500247056 ps
CPU time 2.36 seconds
Started Jul 13 06:52:47 PM PDT 24
Finished Jul 13 06:52:50 PM PDT 24
Peak memory 213984 kb
Host smart-91ac7c91-0f8f-4bf3-88bd-92180f0e2569
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706550597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2706550597
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1297275567
Short name T998
Test name
Test status
Simulation time 91274520 ps
CPU time 3.7 seconds
Started Jul 13 06:52:45 PM PDT 24
Finished Jul 13 06:52:49 PM PDT 24
Peak memory 213972 kb
Host smart-b7190bd9-1ef4-4c87-ab4e-926f53340dfb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297275567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1297275567
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1658520640
Short name T994
Test name
Test status
Simulation time 129377575 ps
CPU time 3.57 seconds
Started Jul 13 06:52:44 PM PDT 24
Finished Jul 13 06:52:49 PM PDT 24
Peak memory 216008 kb
Host smart-0d64ca8a-f210-40b6-8b47-c9943451acdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658520640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1658520640
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2028214727
Short name T173
Test name
Test status
Simulation time 329656294 ps
CPU time 5.23 seconds
Started Jul 13 06:52:42 PM PDT 24
Finished Jul 13 06:52:48 PM PDT 24
Peak memory 213712 kb
Host smart-95b73da6-b6ad-42b3-9a17-088314963094
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028214727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2028214727
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3426881751
Short name T1010
Test name
Test status
Simulation time 286033774 ps
CPU time 1.22 seconds
Started Jul 13 06:52:49 PM PDT 24
Finished Jul 13 06:52:51 PM PDT 24
Peak memory 213752 kb
Host smart-dece443d-c7c0-4905-96d3-a1e5d2a7a804
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426881751 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3426881751
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.382259425
Short name T1029
Test name
Test status
Simulation time 75768784 ps
CPU time 1.24 seconds
Started Jul 13 06:52:46 PM PDT 24
Finished Jul 13 06:52:48 PM PDT 24
Peak memory 205540 kb
Host smart-39bc0984-d78e-4fb0-80f0-d81bc277f0a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382259425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.382259425
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1939497492
Short name T971
Test name
Test status
Simulation time 16190648 ps
CPU time 0.84 seconds
Started Jul 13 06:52:47 PM PDT 24
Finished Jul 13 06:52:48 PM PDT 24
Peak memory 205340 kb
Host smart-d4633c0c-d027-49d1-8050-969d337c1b21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939497492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1939497492
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4266042712
Short name T962
Test name
Test status
Simulation time 96778152 ps
CPU time 1.81 seconds
Started Jul 13 06:52:47 PM PDT 24
Finished Jul 13 06:52:49 PM PDT 24
Peak memory 205464 kb
Host smart-cc1aa8d4-9b24-414b-b3bd-0b48801d9da1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266042712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.4266042712
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2463002050
Short name T1076
Test name
Test status
Simulation time 199023681 ps
CPU time 1.67 seconds
Started Jul 13 06:52:44 PM PDT 24
Finished Jul 13 06:52:47 PM PDT 24
Peak memory 214060 kb
Host smart-c0b6f2b6-1ce7-4d74-82a6-cbdab80f5009
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463002050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2463002050
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.673154987
Short name T992
Test name
Test status
Simulation time 2402881685 ps
CPU time 9.04 seconds
Started Jul 13 06:52:46 PM PDT 24
Finished Jul 13 06:52:56 PM PDT 24
Peak memory 222300 kb
Host smart-3c529745-ec8d-418b-b033-736bf9c1de8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673154987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.673154987
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.876232333
Short name T931
Test name
Test status
Simulation time 33597118 ps
CPU time 2.35 seconds
Started Jul 13 06:52:44 PM PDT 24
Finished Jul 13 06:52:47 PM PDT 24
Peak memory 213608 kb
Host smart-5d7f158f-42a7-4b3a-a942-80f6ee2665c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876232333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.876232333
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.707224711
Short name T166
Test name
Test status
Simulation time 1072572259 ps
CPU time 10.67 seconds
Started Jul 13 06:52:48 PM PDT 24
Finished Jul 13 06:52:59 PM PDT 24
Peak memory 213656 kb
Host smart-94c7e888-eb54-4e50-b835-f1aada9795c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707224711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.707224711
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2911522398
Short name T1003
Test name
Test status
Simulation time 57850057 ps
CPU time 1.73 seconds
Started Jul 13 06:52:57 PM PDT 24
Finished Jul 13 06:53:00 PM PDT 24
Peak memory 213776 kb
Host smart-eb807878-60c2-4b69-8cef-0b8be251e1be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911522398 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2911522398
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1504272811
Short name T1049
Test name
Test status
Simulation time 43336385 ps
CPU time 1.08 seconds
Started Jul 13 06:52:57 PM PDT 24
Finished Jul 13 06:52:59 PM PDT 24
Peak memory 205380 kb
Host smart-8092d1e6-3911-4785-8bcf-952ea5aa4cce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504272811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1504272811
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2151244396
Short name T1057
Test name
Test status
Simulation time 143381545 ps
CPU time 0.91 seconds
Started Jul 13 06:52:58 PM PDT 24
Finished Jul 13 06:52:59 PM PDT 24
Peak memory 205332 kb
Host smart-a2ac43bb-4203-4239-a054-20ae7a79d50b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151244396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2151244396
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.480357655
Short name T951
Test name
Test status
Simulation time 57332072 ps
CPU time 1.62 seconds
Started Jul 13 06:52:55 PM PDT 24
Finished Jul 13 06:52:57 PM PDT 24
Peak memory 205584 kb
Host smart-a18abd45-6b51-4294-9120-2652776a59f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480357655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.480357655
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3819196930
Short name T122
Test name
Test status
Simulation time 492747483 ps
CPU time 3.87 seconds
Started Jul 13 06:52:44 PM PDT 24
Finished Jul 13 06:52:48 PM PDT 24
Peak memory 213960 kb
Host smart-2a6cec11-6475-4fde-805a-8687173f204f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819196930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3819196930
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2726737763
Short name T1041
Test name
Test status
Simulation time 71825499 ps
CPU time 4.4 seconds
Started Jul 13 06:52:42 PM PDT 24
Finished Jul 13 06:52:46 PM PDT 24
Peak memory 222188 kb
Host smart-12d8e647-9518-4f4c-bed6-57b03f580522
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726737763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2726737763
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3255374025
Short name T911
Test name
Test status
Simulation time 69004758 ps
CPU time 2.96 seconds
Started Jul 13 06:52:48 PM PDT 24
Finished Jul 13 06:52:51 PM PDT 24
Peak memory 213732 kb
Host smart-73727c74-3785-4d1e-af55-675588421723
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255374025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3255374025
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3193182832
Short name T180
Test name
Test status
Simulation time 278029275 ps
CPU time 5.43 seconds
Started Jul 13 06:52:55 PM PDT 24
Finished Jul 13 06:53:01 PM PDT 24
Peak memory 213628 kb
Host smart-30676143-a24e-4327-a90b-9c455ad92262
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193182832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3193182832
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2912450329
Short name T964
Test name
Test status
Simulation time 104399959 ps
CPU time 1.13 seconds
Started Jul 13 06:52:56 PM PDT 24
Finished Jul 13 06:52:57 PM PDT 24
Peak memory 205600 kb
Host smart-7aac07b9-6620-44e7-aa2c-fb48837734c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912450329 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2912450329
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3387527619
Short name T984
Test name
Test status
Simulation time 57952847 ps
CPU time 1.01 seconds
Started Jul 13 06:52:57 PM PDT 24
Finished Jul 13 06:52:59 PM PDT 24
Peak memory 205364 kb
Host smart-43af9bd5-3817-49aa-af05-18a0f2c7779d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387527619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3387527619
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3523199628
Short name T923
Test name
Test status
Simulation time 36866793 ps
CPU time 0.71 seconds
Started Jul 13 06:52:56 PM PDT 24
Finished Jul 13 06:52:57 PM PDT 24
Peak memory 205284 kb
Host smart-0fd3fc84-48b0-4284-8c57-88a5ca0c8d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523199628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3523199628
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.697823805
Short name T946
Test name
Test status
Simulation time 96742080 ps
CPU time 1.78 seconds
Started Jul 13 06:52:57 PM PDT 24
Finished Jul 13 06:52:59 PM PDT 24
Peak memory 205488 kb
Host smart-582c21a9-2584-4544-98a9-4fbb636956e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697823805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.697823805
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.139842951
Short name T1050
Test name
Test status
Simulation time 451914811 ps
CPU time 2.61 seconds
Started Jul 13 06:52:57 PM PDT 24
Finished Jul 13 06:53:01 PM PDT 24
Peak memory 214076 kb
Host smart-4e62d703-1530-4389-aebf-e08d2ba29d91
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139842951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.139842951
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1770392789
Short name T1058
Test name
Test status
Simulation time 189432146 ps
CPU time 6.64 seconds
Started Jul 13 06:52:59 PM PDT 24
Finished Jul 13 06:53:06 PM PDT 24
Peak memory 220268 kb
Host smart-7f86a84e-1f43-45ad-9e79-ad4c90759df2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770392789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1770392789
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.618220320
Short name T932
Test name
Test status
Simulation time 115289589 ps
CPU time 2.43 seconds
Started Jul 13 06:52:57 PM PDT 24
Finished Jul 13 06:53:00 PM PDT 24
Peak memory 213792 kb
Host smart-5c4d8309-55bf-4295-91e1-512d1f7205bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618220320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.618220320
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3281937925
Short name T181
Test name
Test status
Simulation time 423526863 ps
CPU time 7.25 seconds
Started Jul 13 06:52:58 PM PDT 24
Finished Jul 13 06:53:06 PM PDT 24
Peak memory 213664 kb
Host smart-e15a8a9b-5333-4924-bbb5-c0216fc620f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281937925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3281937925
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1915771345
Short name T1045
Test name
Test status
Simulation time 144831669 ps
CPU time 1.38 seconds
Started Jul 13 06:52:59 PM PDT 24
Finished Jul 13 06:53:01 PM PDT 24
Peak memory 205624 kb
Host smart-b75523c7-c8dd-4efe-b5d2-adfb376c4005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915771345 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1915771345
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2976437266
Short name T954
Test name
Test status
Simulation time 49233983 ps
CPU time 1.13 seconds
Started Jul 13 06:52:56 PM PDT 24
Finished Jul 13 06:52:57 PM PDT 24
Peak memory 205500 kb
Host smart-67b73d72-d7f8-49a1-bbcb-dbea45498c3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976437266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2976437266
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3872021131
Short name T1060
Test name
Test status
Simulation time 7884987 ps
CPU time 0.69 seconds
Started Jul 13 06:52:59 PM PDT 24
Finished Jul 13 06:53:00 PM PDT 24
Peak memory 205352 kb
Host smart-bbca42dd-beec-464b-825e-cf06c8c9f2c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872021131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3872021131
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1221444473
Short name T949
Test name
Test status
Simulation time 304425580 ps
CPU time 2.78 seconds
Started Jul 13 06:52:58 PM PDT 24
Finished Jul 13 06:53:01 PM PDT 24
Peak memory 205548 kb
Host smart-d7a57dba-d56e-4ada-be31-e7f5a2424fc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221444473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1221444473
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3748845412
Short name T966
Test name
Test status
Simulation time 97754478 ps
CPU time 1.82 seconds
Started Jul 13 06:52:59 PM PDT 24
Finished Jul 13 06:53:01 PM PDT 24
Peak memory 214100 kb
Host smart-dd6e47ef-0589-4198-9c22-d51673a7d339
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748845412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3748845412
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2647968579
Short name T982
Test name
Test status
Simulation time 778249945 ps
CPU time 5.2 seconds
Started Jul 13 06:52:56 PM PDT 24
Finished Jul 13 06:53:02 PM PDT 24
Peak memory 214012 kb
Host smart-d1e877f4-4b03-468e-98a2-ddf8d4815b6c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647968579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2647968579
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4137058247
Short name T1019
Test name
Test status
Simulation time 92713473 ps
CPU time 3.17 seconds
Started Jul 13 06:52:59 PM PDT 24
Finished Jul 13 06:53:03 PM PDT 24
Peak memory 213616 kb
Host smart-525f3709-63f6-4aa1-97ce-8803e5e3b1e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137058247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.4137058247
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2776740136
Short name T939
Test name
Test status
Simulation time 16396432 ps
CPU time 1.22 seconds
Started Jul 13 06:53:13 PM PDT 24
Finished Jul 13 06:53:15 PM PDT 24
Peak memory 205512 kb
Host smart-3a122138-bbb2-46f3-ae82-20beaeb3df58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776740136 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2776740136
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2178177559
Short name T1001
Test name
Test status
Simulation time 31747080 ps
CPU time 0.91 seconds
Started Jul 13 06:52:57 PM PDT 24
Finished Jul 13 06:52:59 PM PDT 24
Peak memory 205444 kb
Host smart-bcb29ec7-0527-41c2-a13b-429c8a0f09f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178177559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2178177559
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2766560334
Short name T926
Test name
Test status
Simulation time 52183918 ps
CPU time 0.78 seconds
Started Jul 13 06:53:01 PM PDT 24
Finished Jul 13 06:53:02 PM PDT 24
Peak memory 205332 kb
Host smart-1d6142b6-3b5e-4b36-87d3-08ec51a8c4a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766560334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2766560334
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1795094714
Short name T983
Test name
Test status
Simulation time 53426846 ps
CPU time 2.68 seconds
Started Jul 13 06:52:59 PM PDT 24
Finished Jul 13 06:53:02 PM PDT 24
Peak memory 205788 kb
Host smart-36ca9ce7-3738-46d2-ac0c-b485c5ced167
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795094714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1795094714
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3587739868
Short name T963
Test name
Test status
Simulation time 207777388 ps
CPU time 3.87 seconds
Started Jul 13 06:53:01 PM PDT 24
Finished Jul 13 06:53:05 PM PDT 24
Peak memory 213960 kb
Host smart-ca0533b8-823a-4232-891b-8a8b559c8228
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587739868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3587739868
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.48157259
Short name T124
Test name
Test status
Simulation time 144458986 ps
CPU time 4.38 seconds
Started Jul 13 06:52:59 PM PDT 24
Finished Jul 13 06:53:04 PM PDT 24
Peak memory 213940 kb
Host smart-f8e61268-1424-4c37-a4a3-0240ae3cb2b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48157259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.k
eymgr_shadow_reg_errors_with_csr_rw.48157259
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3377192114
Short name T943
Test name
Test status
Simulation time 122921822 ps
CPU time 2.41 seconds
Started Jul 13 06:52:57 PM PDT 24
Finished Jul 13 06:53:00 PM PDT 24
Peak memory 215820 kb
Host smart-e66fac0b-3f12-447d-9c35-73c73afea147
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377192114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3377192114
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1908998050
Short name T160
Test name
Test status
Simulation time 230425637 ps
CPU time 5.72 seconds
Started Jul 13 06:52:56 PM PDT 24
Finished Jul 13 06:53:02 PM PDT 24
Peak memory 213640 kb
Host smart-b8f4c366-24ae-4812-b089-1313bde8b13e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908998050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1908998050
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2831190249
Short name T1027
Test name
Test status
Simulation time 28156043 ps
CPU time 1.85 seconds
Started Jul 13 06:53:11 PM PDT 24
Finished Jul 13 06:53:13 PM PDT 24
Peak memory 213848 kb
Host smart-4227eded-a02e-45c8-be39-61241f897cd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831190249 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2831190249
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3353903317
Short name T990
Test name
Test status
Simulation time 22152587 ps
CPU time 1.21 seconds
Started Jul 13 06:53:13 PM PDT 24
Finished Jul 13 06:53:14 PM PDT 24
Peak memory 205536 kb
Host smart-8bd28290-d9cb-469d-9b19-084e5d3c8ecf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353903317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3353903317
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3114585569
Short name T1053
Test name
Test status
Simulation time 17770984 ps
CPU time 0.71 seconds
Started Jul 13 06:53:14 PM PDT 24
Finished Jul 13 06:53:15 PM PDT 24
Peak memory 205284 kb
Host smart-313db544-16cb-40d5-854d-f0f1e9299f59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114585569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3114585569
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.868957391
Short name T145
Test name
Test status
Simulation time 22787836 ps
CPU time 1.4 seconds
Started Jul 13 06:53:08 PM PDT 24
Finished Jul 13 06:53:10 PM PDT 24
Peak memory 205496 kb
Host smart-aa6c6cfd-fd75-49cc-88e2-507f5b656c89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868957391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.868957391
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.379964480
Short name T1070
Test name
Test status
Simulation time 615726741 ps
CPU time 4.63 seconds
Started Jul 13 06:53:15 PM PDT 24
Finished Jul 13 06:53:21 PM PDT 24
Peak memory 214080 kb
Host smart-13edf0f7-5df4-445f-b0e3-0df3a43f523e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379964480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.379964480
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3499403687
Short name T1011
Test name
Test status
Simulation time 585025126 ps
CPU time 6.51 seconds
Started Jul 13 06:53:11 PM PDT 24
Finished Jul 13 06:53:18 PM PDT 24
Peak memory 214128 kb
Host smart-f779ebd4-89b7-45d8-992b-a266c61e2f20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499403687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3499403687
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1253560086
Short name T919
Test name
Test status
Simulation time 148459799 ps
CPU time 2.37 seconds
Started Jul 13 06:53:11 PM PDT 24
Finished Jul 13 06:53:14 PM PDT 24
Peak memory 214500 kb
Host smart-3ffba8ed-8290-4180-b524-d910f6223077
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253560086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1253560086
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3956782614
Short name T165
Test name
Test status
Simulation time 226293580 ps
CPU time 4.52 seconds
Started Jul 13 06:53:06 PM PDT 24
Finished Jul 13 06:53:11 PM PDT 24
Peak memory 214708 kb
Host smart-99289b7d-c553-4ce5-a9d7-cdb88ab7bc23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956782614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3956782614
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2516924892
Short name T989
Test name
Test status
Simulation time 51057350 ps
CPU time 2.21 seconds
Started Jul 13 06:53:13 PM PDT 24
Finished Jul 13 06:53:16 PM PDT 24
Peak memory 213788 kb
Host smart-535ecd72-e8df-49b0-8845-74e5188537f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516924892 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2516924892
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.781222319
Short name T1037
Test name
Test status
Simulation time 42418818 ps
CPU time 1.15 seconds
Started Jul 13 06:53:14 PM PDT 24
Finished Jul 13 06:53:15 PM PDT 24
Peak memory 205524 kb
Host smart-9fd0fdb9-f70a-45d5-940d-91a666f70b7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781222319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.781222319
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1057066317
Short name T916
Test name
Test status
Simulation time 35177848 ps
CPU time 0.78 seconds
Started Jul 13 06:53:16 PM PDT 24
Finished Jul 13 06:53:18 PM PDT 24
Peak memory 205328 kb
Host smart-428799f6-06aa-4440-a100-0919da50b84e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057066317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1057066317
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2709678132
Short name T146
Test name
Test status
Simulation time 196026305 ps
CPU time 2.2 seconds
Started Jul 13 06:53:13 PM PDT 24
Finished Jul 13 06:53:15 PM PDT 24
Peak memory 205536 kb
Host smart-03e16b4a-7e3d-464b-90dd-37ee47c8dde6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709678132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2709678132
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3907743503
Short name T1067
Test name
Test status
Simulation time 494252335 ps
CPU time 2.52 seconds
Started Jul 13 06:53:08 PM PDT 24
Finished Jul 13 06:53:11 PM PDT 24
Peak memory 214064 kb
Host smart-36942df2-40e5-4625-a090-332c5ae9e857
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907743503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3907743503
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2232905071
Short name T123
Test name
Test status
Simulation time 101924160 ps
CPU time 5.24 seconds
Started Jul 13 06:53:15 PM PDT 24
Finished Jul 13 06:53:20 PM PDT 24
Peak memory 213980 kb
Host smart-8d3746de-aed9-4837-9ac1-eb5187d5e186
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232905071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2232905071
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1043832233
Short name T1002
Test name
Test status
Simulation time 209311164 ps
CPU time 1.71 seconds
Started Jul 13 06:53:09 PM PDT 24
Finished Jul 13 06:53:11 PM PDT 24
Peak memory 214744 kb
Host smart-8fd9f925-e34d-46bd-bf04-120b32b193a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043832233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1043832233
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.4046007009
Short name T167
Test name
Test status
Simulation time 221782397 ps
CPU time 3.43 seconds
Started Jul 13 06:53:10 PM PDT 24
Finished Jul 13 06:53:14 PM PDT 24
Peak memory 213952 kb
Host smart-9adce310-2847-4221-99b8-5a088fb3504a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046007009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.4046007009
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2847221558
Short name T1006
Test name
Test status
Simulation time 924061965 ps
CPU time 8.76 seconds
Started Jul 13 06:51:57 PM PDT 24
Finished Jul 13 06:52:06 PM PDT 24
Peak memory 205456 kb
Host smart-7e0d587c-dc30-452f-a92e-83b61433f815
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847221558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
847221558
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.725297079
Short name T922
Test name
Test status
Simulation time 367393958 ps
CPU time 6.29 seconds
Started Jul 13 06:51:58 PM PDT 24
Finished Jul 13 06:52:05 PM PDT 24
Peak memory 205540 kb
Host smart-5d4e7fd9-dc79-49f8-b6b7-255d5d609f42
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725297079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.725297079
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3229203360
Short name T948
Test name
Test status
Simulation time 19687823 ps
CPU time 0.87 seconds
Started Jul 13 06:51:57 PM PDT 24
Finished Jul 13 06:51:58 PM PDT 24
Peak memory 205392 kb
Host smart-aa16ad40-3dec-424d-ac4e-26c9a1c18fdd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229203360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
229203360
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1931323953
Short name T1013
Test name
Test status
Simulation time 35848801 ps
CPU time 1.56 seconds
Started Jul 13 06:51:57 PM PDT 24
Finished Jul 13 06:51:59 PM PDT 24
Peak memory 213788 kb
Host smart-cb29d2fd-196a-44b1-a419-d1993d263e78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931323953 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1931323953
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1625292637
Short name T141
Test name
Test status
Simulation time 28991788 ps
CPU time 1.13 seconds
Started Jul 13 06:51:55 PM PDT 24
Finished Jul 13 06:51:57 PM PDT 24
Peak memory 205592 kb
Host smart-2d56b54e-a657-4000-b2eb-d2ffe5cf75ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625292637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1625292637
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.471701438
Short name T1043
Test name
Test status
Simulation time 25156823 ps
CPU time 0.74 seconds
Started Jul 13 06:52:00 PM PDT 24
Finished Jul 13 06:52:01 PM PDT 24
Peak memory 205260 kb
Host smart-ee07fb9a-3cf1-4844-b4ba-f2db53ad69e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471701438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.471701438
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2834307381
Short name T996
Test name
Test status
Simulation time 191355998 ps
CPU time 2.11 seconds
Started Jul 13 06:51:57 PM PDT 24
Finished Jul 13 06:52:00 PM PDT 24
Peak memory 205568 kb
Host smart-b2ac7e86-e0e7-4e7a-98f8-8bea77fce5e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834307381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2834307381
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2752154550
Short name T114
Test name
Test status
Simulation time 338801050 ps
CPU time 3.53 seconds
Started Jul 13 06:51:48 PM PDT 24
Finished Jul 13 06:51:53 PM PDT 24
Peak memory 214028 kb
Host smart-bf5e5ca4-735f-4d9b-9fb5-c3c3f32a96b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752154550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2752154550
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1979693291
Short name T1055
Test name
Test status
Simulation time 235737352 ps
CPU time 7.92 seconds
Started Jul 13 06:51:51 PM PDT 24
Finished Jul 13 06:51:59 PM PDT 24
Peak memory 214036 kb
Host smart-440a1a47-8d80-4056-88e8-94696bb9d908
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979693291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1979693291
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1090517048
Short name T942
Test name
Test status
Simulation time 260829831 ps
CPU time 3.16 seconds
Started Jul 13 06:51:56 PM PDT 24
Finished Jul 13 06:51:59 PM PDT 24
Peak memory 216744 kb
Host smart-5d827e42-3da0-48bb-b3d7-58d1e240ffd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090517048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1090517048
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.214862014
Short name T979
Test name
Test status
Simulation time 13074491 ps
CPU time 0.74 seconds
Started Jul 13 06:53:09 PM PDT 24
Finished Jul 13 06:53:10 PM PDT 24
Peak memory 205352 kb
Host smart-fa3c6342-bbe7-47d5-babd-3dd9be7d02ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214862014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.214862014
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1986787816
Short name T915
Test name
Test status
Simulation time 40792925 ps
CPU time 0.88 seconds
Started Jul 13 06:53:09 PM PDT 24
Finished Jul 13 06:53:10 PM PDT 24
Peak memory 205236 kb
Host smart-30af4b66-2fdd-469d-b7e7-247c88ce10b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986787816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1986787816
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2205169860
Short name T1009
Test name
Test status
Simulation time 37863220 ps
CPU time 0.68 seconds
Started Jul 13 06:53:13 PM PDT 24
Finished Jul 13 06:53:14 PM PDT 24
Peak memory 205256 kb
Host smart-0960a327-829e-47f4-929a-0f42eb39d09d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205169860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2205169860
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2271210447
Short name T1026
Test name
Test status
Simulation time 34353637 ps
CPU time 0.74 seconds
Started Jul 13 06:53:09 PM PDT 24
Finished Jul 13 06:53:10 PM PDT 24
Peak memory 205256 kb
Host smart-6c863912-71f6-4e42-802b-3ca28d59fa0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271210447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2271210447
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.514313835
Short name T974
Test name
Test status
Simulation time 19139169 ps
CPU time 0.94 seconds
Started Jul 13 06:53:08 PM PDT 24
Finished Jul 13 06:53:10 PM PDT 24
Peak memory 205444 kb
Host smart-64a5d2b7-b054-49e7-b17d-a949a9360fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514313835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.514313835
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1119396454
Short name T920
Test name
Test status
Simulation time 12035088 ps
CPU time 0.73 seconds
Started Jul 13 06:53:15 PM PDT 24
Finished Jul 13 06:53:17 PM PDT 24
Peak memory 205328 kb
Host smart-b746d3ec-dbbb-4821-8324-160a1b3d2aa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119396454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1119396454
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3166200626
Short name T1008
Test name
Test status
Simulation time 140900000 ps
CPU time 0.81 seconds
Started Jul 13 06:53:13 PM PDT 24
Finished Jul 13 06:53:14 PM PDT 24
Peak memory 205328 kb
Host smart-16b37868-495d-4be8-b750-b84aa71cf9a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166200626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3166200626
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1321369012
Short name T1020
Test name
Test status
Simulation time 70321980 ps
CPU time 0.74 seconds
Started Jul 13 06:53:12 PM PDT 24
Finished Jul 13 06:53:13 PM PDT 24
Peak memory 205252 kb
Host smart-9f6735d1-2f9a-44cc-9882-08dc3be6d521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321369012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1321369012
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1322886050
Short name T993
Test name
Test status
Simulation time 17062346 ps
CPU time 0.82 seconds
Started Jul 13 06:53:09 PM PDT 24
Finished Jul 13 06:53:10 PM PDT 24
Peak memory 205344 kb
Host smart-665f1c5d-c1cb-4bc6-af3e-799f5b324eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322886050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1322886050
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.810458945
Short name T913
Test name
Test status
Simulation time 18867287 ps
CPU time 0.79 seconds
Started Jul 13 06:53:16 PM PDT 24
Finished Jul 13 06:53:18 PM PDT 24
Peak memory 205324 kb
Host smart-a9ada83a-7445-4550-b64d-f655d7cb8cd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810458945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.810458945
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.803081462
Short name T1007
Test name
Test status
Simulation time 317555369 ps
CPU time 4.81 seconds
Started Jul 13 06:52:06 PM PDT 24
Finished Jul 13 06:52:11 PM PDT 24
Peak memory 205500 kb
Host smart-02e46cbd-eec0-4fdd-a17a-bc7cc3498e1b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803081462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.803081462
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2189391803
Short name T927
Test name
Test status
Simulation time 12726806422 ps
CPU time 35.55 seconds
Started Jul 13 06:52:07 PM PDT 24
Finished Jul 13 06:52:43 PM PDT 24
Peak memory 205600 kb
Host smart-751e88b3-5eaf-4dfb-bd0b-42b2f0a585f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189391803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
189391803
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3176823051
Short name T1075
Test name
Test status
Simulation time 64838284 ps
CPU time 1.19 seconds
Started Jul 13 06:52:07 PM PDT 24
Finished Jul 13 06:52:08 PM PDT 24
Peak memory 205428 kb
Host smart-17b1de37-c022-4ab9-b63d-1ea478389eaa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176823051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
176823051
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.38019234
Short name T977
Test name
Test status
Simulation time 387865042 ps
CPU time 1.68 seconds
Started Jul 13 06:52:06 PM PDT 24
Finished Jul 13 06:52:08 PM PDT 24
Peak memory 213700 kb
Host smart-9de974d1-1043-4598-bb85-14630f67202f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38019234 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.38019234
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.4045980734
Short name T999
Test name
Test status
Simulation time 119396637 ps
CPU time 1.15 seconds
Started Jul 13 06:52:08 PM PDT 24
Finished Jul 13 06:52:10 PM PDT 24
Peak memory 205532 kb
Host smart-1bc75d7d-dab6-408e-be83-95020dc18cce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045980734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.4045980734
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1072581541
Short name T925
Test name
Test status
Simulation time 10108456 ps
CPU time 0.81 seconds
Started Jul 13 06:52:07 PM PDT 24
Finished Jul 13 06:52:08 PM PDT 24
Peak memory 205436 kb
Host smart-52e4274f-d8e3-45d8-88c6-8832a8b41c0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072581541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1072581541
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3416588819
Short name T961
Test name
Test status
Simulation time 57549545 ps
CPU time 2.42 seconds
Started Jul 13 06:52:06 PM PDT 24
Finished Jul 13 06:52:08 PM PDT 24
Peak memory 205476 kb
Host smart-0898b1eb-d4e5-42bf-b316-1264763c31e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416588819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3416588819
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3408550047
Short name T1048
Test name
Test status
Simulation time 739528186 ps
CPU time 3.92 seconds
Started Jul 13 06:51:59 PM PDT 24
Finished Jul 13 06:52:04 PM PDT 24
Peak memory 214092 kb
Host smart-66187c29-fb7f-4951-a881-4cdde1ab748a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408550047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3408550047
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1233023529
Short name T1071
Test name
Test status
Simulation time 380588040 ps
CPU time 13.27 seconds
Started Jul 13 06:51:57 PM PDT 24
Finished Jul 13 06:52:11 PM PDT 24
Peak memory 213964 kb
Host smart-3107e9f1-1d6e-42d3-bb01-ec79352ea1a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233023529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1233023529
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.4116031899
Short name T1052
Test name
Test status
Simulation time 78630069 ps
CPU time 2.58 seconds
Started Jul 13 06:51:57 PM PDT 24
Finished Jul 13 06:52:00 PM PDT 24
Peak memory 213720 kb
Host smart-68c9bc1a-7539-4d4c-a21f-13ea1d6230f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116031899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.4116031899
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.387709142
Short name T917
Test name
Test status
Simulation time 35492211 ps
CPU time 0.81 seconds
Started Jul 13 06:53:09 PM PDT 24
Finished Jul 13 06:53:10 PM PDT 24
Peak memory 205264 kb
Host smart-ad75a1aa-e4d4-4fc2-afed-ee8268d9dcfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387709142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.387709142
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.12098514
Short name T1018
Test name
Test status
Simulation time 46402047 ps
CPU time 0.7 seconds
Started Jul 13 06:53:16 PM PDT 24
Finished Jul 13 06:53:18 PM PDT 24
Peak memory 205340 kb
Host smart-a69be0c2-bd41-4847-90a9-50ad779ba89d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12098514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.12098514
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2341145795
Short name T1015
Test name
Test status
Simulation time 12866706 ps
CPU time 0.87 seconds
Started Jul 13 06:53:15 PM PDT 24
Finished Jul 13 06:53:16 PM PDT 24
Peak memory 205332 kb
Host smart-e536f2aa-a5a7-4a5d-9d5c-2caa29b5746f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341145795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2341145795
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1504017292
Short name T1022
Test name
Test status
Simulation time 14235857 ps
CPU time 0.71 seconds
Started Jul 13 06:53:07 PM PDT 24
Finished Jul 13 06:53:08 PM PDT 24
Peak memory 205112 kb
Host smart-98650d70-8c29-4f22-989c-16ed92f6cff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504017292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1504017292
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3305407758
Short name T947
Test name
Test status
Simulation time 20382263 ps
CPU time 0.7 seconds
Started Jul 13 06:53:16 PM PDT 24
Finished Jul 13 06:53:18 PM PDT 24
Peak memory 205312 kb
Host smart-20aefa00-e13d-4150-b7db-52ccd87458e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305407758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3305407758
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.898886709
Short name T924
Test name
Test status
Simulation time 9036034 ps
CPU time 0.81 seconds
Started Jul 13 06:53:10 PM PDT 24
Finished Jul 13 06:53:11 PM PDT 24
Peak memory 205328 kb
Host smart-cfd189c4-e829-464a-8ecf-3adc9ae62535
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898886709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.898886709
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3102939961
Short name T1042
Test name
Test status
Simulation time 8996515 ps
CPU time 0.82 seconds
Started Jul 13 06:53:15 PM PDT 24
Finished Jul 13 06:53:17 PM PDT 24
Peak memory 205340 kb
Host smart-850291da-b415-4af3-8c7a-6b641237ecaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102939961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3102939961
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1744892363
Short name T1033
Test name
Test status
Simulation time 8876366 ps
CPU time 0.79 seconds
Started Jul 13 06:53:16 PM PDT 24
Finished Jul 13 06:53:18 PM PDT 24
Peak memory 205340 kb
Host smart-b2f11475-5897-46f1-8687-fff57fe5eab0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744892363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1744892363
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.542828419
Short name T934
Test name
Test status
Simulation time 9585135 ps
CPU time 0.82 seconds
Started Jul 13 06:53:10 PM PDT 24
Finished Jul 13 06:53:11 PM PDT 24
Peak memory 205328 kb
Host smart-e21a21d0-3206-45ac-bfb1-3e77d5f24c8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542828419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.542828419
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.301687465
Short name T1051
Test name
Test status
Simulation time 9069824 ps
CPU time 0.77 seconds
Started Jul 13 06:53:16 PM PDT 24
Finished Jul 13 06:53:18 PM PDT 24
Peak memory 205360 kb
Host smart-40e63a97-41b6-476c-a5b7-f3b58e9bd05e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301687465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.301687465
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.331109921
Short name T1025
Test name
Test status
Simulation time 372153926 ps
CPU time 7.66 seconds
Started Jul 13 06:52:17 PM PDT 24
Finished Jul 13 06:52:25 PM PDT 24
Peak memory 205552 kb
Host smart-10a2ff09-24ec-4b7e-a344-7d05d4ce4e73
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331109921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.331109921
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3282806109
Short name T987
Test name
Test status
Simulation time 512505614 ps
CPU time 7.8 seconds
Started Jul 13 06:52:13 PM PDT 24
Finished Jul 13 06:52:21 PM PDT 24
Peak memory 205524 kb
Host smart-85e73a23-6bba-45e1-ac81-352ea32c8cd5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282806109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
282806109
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1403099924
Short name T164
Test name
Test status
Simulation time 19271279 ps
CPU time 1.12 seconds
Started Jul 13 06:52:16 PM PDT 24
Finished Jul 13 06:52:18 PM PDT 24
Peak memory 205540 kb
Host smart-c8c10c50-59c8-487c-94c4-63c31ce49fd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403099924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
403099924
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3702369518
Short name T958
Test name
Test status
Simulation time 321784801 ps
CPU time 1.56 seconds
Started Jul 13 06:52:13 PM PDT 24
Finished Jul 13 06:52:14 PM PDT 24
Peak memory 213700 kb
Host smart-47d45095-78ab-4bfb-8f2f-27c24dc6dea5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702369518 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3702369518
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.269244287
Short name T980
Test name
Test status
Simulation time 24903230 ps
CPU time 0.89 seconds
Started Jul 13 06:52:14 PM PDT 24
Finished Jul 13 06:52:16 PM PDT 24
Peak memory 205388 kb
Host smart-e3aa7996-7313-496a-a390-5941ddd610fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269244287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.269244287
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1780979404
Short name T1073
Test name
Test status
Simulation time 12934144 ps
CPU time 0.72 seconds
Started Jul 13 06:52:14 PM PDT 24
Finished Jul 13 06:52:15 PM PDT 24
Peak memory 205328 kb
Host smart-732ed080-bec8-44ed-9c35-8d6b8164496d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780979404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1780979404
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2457326323
Short name T1036
Test name
Test status
Simulation time 188373604 ps
CPU time 1.81 seconds
Started Jul 13 06:52:14 PM PDT 24
Finished Jul 13 06:52:17 PM PDT 24
Peak memory 205384 kb
Host smart-e07985a5-309b-4e05-bc5b-fe6168500d38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457326323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2457326323
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1804067289
Short name T986
Test name
Test status
Simulation time 759297877 ps
CPU time 2.96 seconds
Started Jul 13 06:52:10 PM PDT 24
Finished Jul 13 06:52:13 PM PDT 24
Peak memory 214064 kb
Host smart-07ab0a4b-7102-469d-a4c2-0960d9e2938b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804067289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1804067289
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.772802955
Short name T967
Test name
Test status
Simulation time 1233072492 ps
CPU time 12.91 seconds
Started Jul 13 06:52:10 PM PDT 24
Finished Jul 13 06:52:23 PM PDT 24
Peak memory 214040 kb
Host smart-45b2cfbe-bb4e-4057-bbbc-ad72027c3d9b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772802955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.772802955
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.757303873
Short name T912
Test name
Test status
Simulation time 119828156 ps
CPU time 2.9 seconds
Started Jul 13 06:52:07 PM PDT 24
Finished Jul 13 06:52:10 PM PDT 24
Peak memory 213764 kb
Host smart-8da6ccc5-f1f4-45ba-86d9-a2a023849e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757303873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.757303873
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3897140971
Short name T918
Test name
Test status
Simulation time 13451205 ps
CPU time 0.74 seconds
Started Jul 13 06:53:15 PM PDT 24
Finished Jul 13 06:53:17 PM PDT 24
Peak memory 205332 kb
Host smart-5fdf37a4-8230-4427-8271-787f1c40c0b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897140971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3897140971
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1714381010
Short name T929
Test name
Test status
Simulation time 22377108 ps
CPU time 0.74 seconds
Started Jul 13 06:53:15 PM PDT 24
Finished Jul 13 06:53:16 PM PDT 24
Peak memory 205288 kb
Host smart-6c0461d1-c63d-46d1-9956-9f304a988cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714381010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1714381010
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2094785624
Short name T914
Test name
Test status
Simulation time 9396693 ps
CPU time 0.81 seconds
Started Jul 13 06:53:16 PM PDT 24
Finished Jul 13 06:53:18 PM PDT 24
Peak memory 205356 kb
Host smart-c51d9a1f-3d0d-4266-8fda-c3a609510f28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094785624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2094785624
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1722202024
Short name T930
Test name
Test status
Simulation time 86632670 ps
CPU time 0.72 seconds
Started Jul 13 06:53:10 PM PDT 24
Finished Jul 13 06:53:12 PM PDT 24
Peak memory 205264 kb
Host smart-6765fad3-c39d-4398-b7ea-0e2e055baac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722202024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1722202024
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1106459644
Short name T1012
Test name
Test status
Simulation time 19672047 ps
CPU time 0.88 seconds
Started Jul 13 06:53:16 PM PDT 24
Finished Jul 13 06:53:18 PM PDT 24
Peak memory 205484 kb
Host smart-567c124e-bb24-4ca2-8e8e-16a01f758153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106459644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1106459644
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2607977231
Short name T1040
Test name
Test status
Simulation time 16923769 ps
CPU time 0.75 seconds
Started Jul 13 06:53:15 PM PDT 24
Finished Jul 13 06:53:17 PM PDT 24
Peak memory 205240 kb
Host smart-46a37207-7896-4338-a302-40868a00412b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607977231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2607977231
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3945825548
Short name T1056
Test name
Test status
Simulation time 34591644 ps
CPU time 0.77 seconds
Started Jul 13 06:53:14 PM PDT 24
Finished Jul 13 06:53:15 PM PDT 24
Peak memory 205284 kb
Host smart-5d9f33e5-9059-42c9-be77-49a2916037cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945825548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3945825548
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3345402984
Short name T1017
Test name
Test status
Simulation time 82978516 ps
CPU time 0.87 seconds
Started Jul 13 06:53:16 PM PDT 24
Finished Jul 13 06:53:18 PM PDT 24
Peak memory 205332 kb
Host smart-315b5f53-a0f7-4e3e-a10e-fc730f97cc81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345402984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3345402984
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2680892559
Short name T1028
Test name
Test status
Simulation time 11079871 ps
CPU time 0.73 seconds
Started Jul 13 06:53:17 PM PDT 24
Finished Jul 13 06:53:19 PM PDT 24
Peak memory 205344 kb
Host smart-0c641445-bbae-4e1b-bbaa-d46dbf045e55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680892559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2680892559
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.446301583
Short name T991
Test name
Test status
Simulation time 30447660 ps
CPU time 0.7 seconds
Started Jul 13 06:53:19 PM PDT 24
Finished Jul 13 06:53:20 PM PDT 24
Peak memory 205312 kb
Host smart-0ce78983-bdc9-41f3-b16f-ae83c10d8ad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446301583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.446301583
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3031826104
Short name T1077
Test name
Test status
Simulation time 172488197 ps
CPU time 2.19 seconds
Started Jul 13 06:52:24 PM PDT 24
Finished Jul 13 06:52:26 PM PDT 24
Peak memory 213668 kb
Host smart-51834f90-527c-4052-96e0-4b0a4dc1eecc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031826104 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3031826104
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.748622069
Short name T995
Test name
Test status
Simulation time 17855682 ps
CPU time 1.17 seconds
Started Jul 13 06:52:25 PM PDT 24
Finished Jul 13 06:52:27 PM PDT 24
Peak memory 205452 kb
Host smart-c5478dd8-5805-40f4-8e14-0bfd6dbbc52b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748622069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.748622069
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1368509999
Short name T1074
Test name
Test status
Simulation time 23334775 ps
CPU time 0.73 seconds
Started Jul 13 06:52:14 PM PDT 24
Finished Jul 13 06:52:15 PM PDT 24
Peak memory 205328 kb
Host smart-995a84c9-bce2-48f7-b31d-fa22469ff415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368509999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1368509999
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4064926600
Short name T1004
Test name
Test status
Simulation time 110267590 ps
CPU time 2.8 seconds
Started Jul 13 06:52:24 PM PDT 24
Finished Jul 13 06:52:28 PM PDT 24
Peak memory 205524 kb
Host smart-262cdc64-f946-4c71-86b3-339b1ee50c72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064926600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.4064926600
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.249415296
Short name T1005
Test name
Test status
Simulation time 109971351 ps
CPU time 1.81 seconds
Started Jul 13 06:52:20 PM PDT 24
Finished Jul 13 06:52:22 PM PDT 24
Peak memory 214032 kb
Host smart-260138e1-797d-4757-9378-162195a9be33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249415296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.249415296
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3409207044
Short name T1065
Test name
Test status
Simulation time 215194276 ps
CPU time 8.05 seconds
Started Jul 13 06:52:16 PM PDT 24
Finished Jul 13 06:52:25 PM PDT 24
Peak memory 214036 kb
Host smart-78307a6c-28ba-46b2-a270-f674900204ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409207044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3409207044
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3877797303
Short name T945
Test name
Test status
Simulation time 116673469 ps
CPU time 3.03 seconds
Started Jul 13 06:52:16 PM PDT 24
Finished Jul 13 06:52:19 PM PDT 24
Peak memory 213776 kb
Host smart-9f090793-3132-4730-b934-bdb9bdeb3620
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877797303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3877797303
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3602168554
Short name T163
Test name
Test status
Simulation time 87695552 ps
CPU time 1.15 seconds
Started Jul 13 06:52:25 PM PDT 24
Finished Jul 13 06:52:27 PM PDT 24
Peak memory 213688 kb
Host smart-d865cedc-3fed-40fc-9b76-a8a3cf15b4a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602168554 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3602168554
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3597327298
Short name T1064
Test name
Test status
Simulation time 35962035 ps
CPU time 0.96 seconds
Started Jul 13 06:52:23 PM PDT 24
Finished Jul 13 06:52:24 PM PDT 24
Peak memory 205456 kb
Host smart-dcc9052f-9703-463b-9f0e-8cc6f8c2afbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597327298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3597327298
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3015488538
Short name T969
Test name
Test status
Simulation time 47459859 ps
CPU time 0.83 seconds
Started Jul 13 06:52:29 PM PDT 24
Finished Jul 13 06:52:30 PM PDT 24
Peak memory 205296 kb
Host smart-23d86544-255e-423a-8c4a-40c0434cdb6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015488538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3015488538
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.703950469
Short name T940
Test name
Test status
Simulation time 108353870 ps
CPU time 1.69 seconds
Started Jul 13 06:52:29 PM PDT 24
Finished Jul 13 06:52:31 PM PDT 24
Peak memory 205588 kb
Host smart-107c5cde-0a34-4b94-866b-0c8724bf3d0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703950469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.703950469
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2864910467
Short name T118
Test name
Test status
Simulation time 89454227 ps
CPU time 2.93 seconds
Started Jul 13 06:52:23 PM PDT 24
Finished Jul 13 06:52:26 PM PDT 24
Peak memory 214052 kb
Host smart-94b52cd7-b043-4eb0-89b3-aa7a3225340a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864910467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2864910467
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2758088620
Short name T944
Test name
Test status
Simulation time 218689330 ps
CPU time 3.16 seconds
Started Jul 13 06:52:25 PM PDT 24
Finished Jul 13 06:52:28 PM PDT 24
Peak memory 213788 kb
Host smart-ef225bac-ae54-459c-b334-3124285cd6b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758088620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2758088620
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3577335331
Short name T1030
Test name
Test status
Simulation time 186888527 ps
CPU time 1.7 seconds
Started Jul 13 06:52:27 PM PDT 24
Finished Jul 13 06:52:29 PM PDT 24
Peak memory 213660 kb
Host smart-e7c667a8-bb95-4713-ba39-013fbc6a1cbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577335331 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3577335331
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.15899450
Short name T1054
Test name
Test status
Simulation time 44867684 ps
CPU time 1.05 seconds
Started Jul 13 06:52:23 PM PDT 24
Finished Jul 13 06:52:25 PM PDT 24
Peak memory 205364 kb
Host smart-b2282ceb-5e15-4b3b-9d59-a08775084869
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15899450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.15899450
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3535564883
Short name T976
Test name
Test status
Simulation time 14125221 ps
CPU time 0.72 seconds
Started Jul 13 06:52:23 PM PDT 24
Finished Jul 13 06:52:25 PM PDT 24
Peak memory 205268 kb
Host smart-ab69d1a5-9171-470b-98d4-51a83dff1508
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535564883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3535564883
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.4233756962
Short name T1046
Test name
Test status
Simulation time 59213614 ps
CPU time 2.52 seconds
Started Jul 13 06:52:27 PM PDT 24
Finished Jul 13 06:52:30 PM PDT 24
Peak memory 205568 kb
Host smart-eb951b2a-f61e-4434-bdba-4cdb2a28e242
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233756962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.4233756962
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1754608819
Short name T117
Test name
Test status
Simulation time 81876525 ps
CPU time 2.74 seconds
Started Jul 13 06:52:22 PM PDT 24
Finished Jul 13 06:52:25 PM PDT 24
Peak memory 213968 kb
Host smart-ebca4ca9-1f03-4639-b37c-940a498c2d18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754608819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1754608819
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3628255141
Short name T981
Test name
Test status
Simulation time 486764862 ps
CPU time 9.55 seconds
Started Jul 13 06:52:30 PM PDT 24
Finished Jul 13 06:52:40 PM PDT 24
Peak memory 214012 kb
Host smart-fb3a0c88-a0e9-4a63-a883-4e3efc4b7297
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628255141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3628255141
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4144155317
Short name T960
Test name
Test status
Simulation time 45040674 ps
CPU time 2.93 seconds
Started Jul 13 06:52:26 PM PDT 24
Finished Jul 13 06:52:30 PM PDT 24
Peak memory 221992 kb
Host smart-ec0e399d-b016-4b1f-9b3b-762cebc4cb25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144155317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.4144155317
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.671270555
Short name T950
Test name
Test status
Simulation time 19301688 ps
CPU time 1.38 seconds
Started Jul 13 06:52:33 PM PDT 24
Finished Jul 13 06:52:35 PM PDT 24
Peak memory 213788 kb
Host smart-f64a054b-f102-43fc-b471-be8b0fb82f5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671270555 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.671270555
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.199960136
Short name T935
Test name
Test status
Simulation time 11684313 ps
CPU time 1.02 seconds
Started Jul 13 06:52:34 PM PDT 24
Finished Jul 13 06:52:36 PM PDT 24
Peak memory 205428 kb
Host smart-d4b3f719-1f2e-4135-a389-8f891d825fc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199960136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.199960136
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.241153687
Short name T973
Test name
Test status
Simulation time 15294524 ps
CPU time 0.89 seconds
Started Jul 13 06:52:34 PM PDT 24
Finished Jul 13 06:52:36 PM PDT 24
Peak memory 205444 kb
Host smart-33bac379-95d9-45a6-832d-219cf58dded9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241153687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.241153687
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3245592467
Short name T937
Test name
Test status
Simulation time 108137326 ps
CPU time 2.61 seconds
Started Jul 13 06:52:35 PM PDT 24
Finished Jul 13 06:52:38 PM PDT 24
Peak memory 205456 kb
Host smart-25af2d35-fbd5-4d72-aafe-057596958a0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245592467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3245592467
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.456765332
Short name T1023
Test name
Test status
Simulation time 716472883 ps
CPU time 8.97 seconds
Started Jul 13 06:52:23 PM PDT 24
Finished Jul 13 06:52:32 PM PDT 24
Peak memory 214028 kb
Host smart-ab627022-47e7-4cd5-9377-e70710eca794
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456765332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.456765332
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1268679367
Short name T1034
Test name
Test status
Simulation time 33581061 ps
CPU time 2.27 seconds
Started Jul 13 06:52:36 PM PDT 24
Finished Jul 13 06:52:39 PM PDT 24
Peak memory 213996 kb
Host smart-4fd9a9d9-19a3-44ad-ab17-1554cc1a1436
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268679367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1268679367
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4047066333
Short name T171
Test name
Test status
Simulation time 704629485 ps
CPU time 5.58 seconds
Started Jul 13 06:52:33 PM PDT 24
Finished Jul 13 06:52:40 PM PDT 24
Peak memory 215160 kb
Host smart-1bbb0ba7-acef-4e31-9d89-1fe87671d5c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047066333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.4047066333
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.878861365
Short name T978
Test name
Test status
Simulation time 316203410 ps
CPU time 2.17 seconds
Started Jul 13 06:52:34 PM PDT 24
Finished Jul 13 06:52:37 PM PDT 24
Peak memory 213824 kb
Host smart-971404ca-b610-4bc6-83d2-d5ed67a016c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878861365 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.878861365
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3335492316
Short name T144
Test name
Test status
Simulation time 14998278 ps
CPU time 0.89 seconds
Started Jul 13 06:52:35 PM PDT 24
Finished Jul 13 06:52:36 PM PDT 24
Peak memory 205396 kb
Host smart-e1047dd7-f6d4-4d6b-b341-3076416f23f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335492316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3335492316
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1755347276
Short name T972
Test name
Test status
Simulation time 15781893 ps
CPU time 0.87 seconds
Started Jul 13 06:52:33 PM PDT 24
Finished Jul 13 06:52:34 PM PDT 24
Peak memory 205388 kb
Host smart-4fc64212-73b6-4ab5-80e3-4130972d544c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755347276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1755347276
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1321415090
Short name T147
Test name
Test status
Simulation time 22529369 ps
CPU time 1.32 seconds
Started Jul 13 06:52:37 PM PDT 24
Finished Jul 13 06:52:39 PM PDT 24
Peak memory 205712 kb
Host smart-9c36c9cd-f898-44b6-aaa4-36120e16e28f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321415090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1321415090
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1682324103
Short name T1066
Test name
Test status
Simulation time 288765814 ps
CPU time 3.32 seconds
Started Jul 13 06:52:33 PM PDT 24
Finished Jul 13 06:52:36 PM PDT 24
Peak memory 214064 kb
Host smart-b45ac64f-d6fe-43a2-a4ee-f84a99e0a313
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682324103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1682324103
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.506681789
Short name T116
Test name
Test status
Simulation time 918499467 ps
CPU time 7.35 seconds
Started Jul 13 06:52:36 PM PDT 24
Finished Jul 13 06:52:44 PM PDT 24
Peak memory 214092 kb
Host smart-deb52fac-ad30-41de-9166-959b64576506
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506681789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.506681789
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1966730370
Short name T985
Test name
Test status
Simulation time 47779932 ps
CPU time 2.94 seconds
Started Jul 13 06:52:33 PM PDT 24
Finished Jul 13 06:52:37 PM PDT 24
Peak memory 213792 kb
Host smart-ff452168-5c8c-48f8-b1a3-f94ae9b5d0f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966730370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1966730370
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2080498672
Short name T182
Test name
Test status
Simulation time 785568258 ps
CPU time 6.27 seconds
Started Jul 13 06:52:34 PM PDT 24
Finished Jul 13 06:52:41 PM PDT 24
Peak memory 213636 kb
Host smart-b4ec0ae6-e1ba-4fd8-93c3-67d9ac63537c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080498672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2080498672
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3672146737
Short name T660
Test name
Test status
Simulation time 12593228 ps
CPU time 0.85 seconds
Started Jul 13 06:55:40 PM PDT 24
Finished Jul 13 06:55:42 PM PDT 24
Peak memory 205948 kb
Host smart-7c494cdc-37f9-4f20-8172-dddbb77d7d32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672146737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3672146737
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.4282491473
Short name T384
Test name
Test status
Simulation time 115242090 ps
CPU time 2.9 seconds
Started Jul 13 06:55:31 PM PDT 24
Finished Jul 13 06:55:36 PM PDT 24
Peak memory 214244 kb
Host smart-e5a9bf85-24ec-4f92-a66b-53a39b6f7c47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282491473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.4282491473
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2903542373
Short name T877
Test name
Test status
Simulation time 97241772 ps
CPU time 4.06 seconds
Started Jul 13 06:55:40 PM PDT 24
Finished Jul 13 06:55:45 PM PDT 24
Peak memory 209996 kb
Host smart-4dc3e093-28b2-4385-8659-1e7b3f52afb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903542373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2903542373
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3555939389
Short name T763
Test name
Test status
Simulation time 183922284 ps
CPU time 1.61 seconds
Started Jul 13 06:55:31 PM PDT 24
Finished Jul 13 06:55:34 PM PDT 24
Peak memory 206940 kb
Host smart-09127332-dd8b-4f29-aa01-9a7312123154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555939389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3555939389
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2744155119
Short name T63
Test name
Test status
Simulation time 168678301 ps
CPU time 7.09 seconds
Started Jul 13 06:55:30 PM PDT 24
Finished Jul 13 06:55:39 PM PDT 24
Peak memory 222416 kb
Host smart-0199c697-8e92-4a3b-a997-d56fe32efcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744155119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2744155119
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2590247304
Short name T585
Test name
Test status
Simulation time 622454901 ps
CPU time 4.8 seconds
Started Jul 13 06:55:30 PM PDT 24
Finished Jul 13 06:55:36 PM PDT 24
Peak memory 214356 kb
Host smart-8cb5ff5e-58ea-4ec7-a8fc-d381b68ab07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590247304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2590247304
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.476530351
Short name T41
Test name
Test status
Simulation time 1090465746 ps
CPU time 9.06 seconds
Started Jul 13 06:55:41 PM PDT 24
Finished Jul 13 06:55:51 PM PDT 24
Peak memory 229464 kb
Host smart-e47bd6e5-8e72-4ab5-a013-2fcffcd82314
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476530351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.476530351
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3520622078
Short name T476
Test name
Test status
Simulation time 5091939187 ps
CPU time 42.57 seconds
Started Jul 13 06:55:31 PM PDT 24
Finished Jul 13 06:56:15 PM PDT 24
Peak memory 208220 kb
Host smart-839e6276-c99c-4adb-8482-c37786e905a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520622078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3520622078
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.4273262555
Short name T639
Test name
Test status
Simulation time 75441548 ps
CPU time 1.85 seconds
Started Jul 13 06:55:40 PM PDT 24
Finished Jul 13 06:55:43 PM PDT 24
Peak memory 207020 kb
Host smart-df15e401-e062-427f-9679-fa29437d5eb3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273262555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.4273262555
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1395847573
Short name T752
Test name
Test status
Simulation time 76996763 ps
CPU time 3.83 seconds
Started Jul 13 06:55:30 PM PDT 24
Finished Jul 13 06:55:35 PM PDT 24
Peak memory 208556 kb
Host smart-40361563-5c92-45c1-a4d6-e664cd762390
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395847573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1395847573
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3159204799
Short name T507
Test name
Test status
Simulation time 669968726 ps
CPU time 18.4 seconds
Started Jul 13 06:55:41 PM PDT 24
Finished Jul 13 06:56:00 PM PDT 24
Peak memory 208308 kb
Host smart-1e6c84cd-09b9-4e1b-8c42-8c4af1a3a5c3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159204799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3159204799
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2989174059
Short name T779
Test name
Test status
Simulation time 65788949 ps
CPU time 2.78 seconds
Started Jul 13 06:55:28 PM PDT 24
Finished Jul 13 06:55:31 PM PDT 24
Peak memory 208464 kb
Host smart-8522bde8-184f-4c11-a865-8956c1570591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989174059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2989174059
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.536941123
Short name T129
Test name
Test status
Simulation time 1692178330 ps
CPU time 5.6 seconds
Started Jul 13 06:55:33 PM PDT 24
Finished Jul 13 06:55:40 PM PDT 24
Peak memory 208052 kb
Host smart-15f760b7-b31a-447c-93f8-3133d525ab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536941123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.536941123
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3154288725
Short name T108
Test name
Test status
Simulation time 761364915 ps
CPU time 21.05 seconds
Started Jul 13 06:55:32 PM PDT 24
Finished Jul 13 06:55:54 PM PDT 24
Peak memory 214420 kb
Host smart-d6335b7d-3ca6-4550-bd86-38ffa5b480fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154288725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3154288725
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3243494331
Short name T113
Test name
Test status
Simulation time 88074640 ps
CPU time 1.69 seconds
Started Jul 13 06:55:31 PM PDT 24
Finished Jul 13 06:55:34 PM PDT 24
Peak memory 209784 kb
Host smart-936f9a0c-d6b7-48d4-b5dc-b24635fcd66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243494331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3243494331
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.4082059307
Short name T483
Test name
Test status
Simulation time 52729020 ps
CPU time 0.73 seconds
Started Jul 13 06:55:36 PM PDT 24
Finished Jul 13 06:55:37 PM PDT 24
Peak memory 205928 kb
Host smart-ba3de5ea-aafa-400a-b6bc-0b05677f2b1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082059307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.4082059307
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3094560154
Short name T680
Test name
Test status
Simulation time 77547981 ps
CPU time 2.18 seconds
Started Jul 13 06:55:37 PM PDT 24
Finished Jul 13 06:55:40 PM PDT 24
Peak memory 219812 kb
Host smart-72904574-80b6-4f8f-b29a-661f66ad5acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094560154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3094560154
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2917280242
Short name T517
Test name
Test status
Simulation time 42583270 ps
CPU time 2.33 seconds
Started Jul 13 06:55:36 PM PDT 24
Finished Jul 13 06:55:40 PM PDT 24
Peak memory 214432 kb
Host smart-82e88077-2437-442f-9635-e945f0888b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917280242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2917280242
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.579758837
Short name T829
Test name
Test status
Simulation time 80006984 ps
CPU time 2.81 seconds
Started Jul 13 06:55:37 PM PDT 24
Finished Jul 13 06:55:42 PM PDT 24
Peak memory 222380 kb
Host smart-11d1267b-ec64-4225-add5-d65c14c2d95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579758837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.579758837
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2285851357
Short name T888
Test name
Test status
Simulation time 145428425 ps
CPU time 5.53 seconds
Started Jul 13 06:55:37 PM PDT 24
Finished Jul 13 06:55:44 PM PDT 24
Peak memory 206692 kb
Host smart-57f29eda-6eab-42a8-ab46-6cb8900f5aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285851357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2285851357
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3368552612
Short name T284
Test name
Test status
Simulation time 270933493 ps
CPU time 5.36 seconds
Started Jul 13 06:55:43 PM PDT 24
Finished Jul 13 06:55:49 PM PDT 24
Peak memory 209984 kb
Host smart-cf4328cb-1724-4b41-a5ae-c01cb19920dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368552612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3368552612
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2567601192
Short name T13
Test name
Test status
Simulation time 579692547 ps
CPU time 9.44 seconds
Started Jul 13 06:55:42 PM PDT 24
Finished Jul 13 06:55:52 PM PDT 24
Peak memory 237596 kb
Host smart-0fbcb544-2ee0-4ce6-9941-860273533707
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567601192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2567601192
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.58731780
Short name T647
Test name
Test status
Simulation time 1351767051 ps
CPU time 5.2 seconds
Started Jul 13 06:55:30 PM PDT 24
Finished Jul 13 06:55:37 PM PDT 24
Peak memory 207968 kb
Host smart-91cff233-6e94-482e-86db-107982d541ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58731780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.58731780
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2363677175
Short name T615
Test name
Test status
Simulation time 119884575 ps
CPU time 1.97 seconds
Started Jul 13 06:55:37 PM PDT 24
Finished Jul 13 06:55:40 PM PDT 24
Peak memory 207304 kb
Host smart-ffaf5e1c-7b7f-4354-bf28-de183f850375
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363677175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2363677175
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.423447137
Short name T83
Test name
Test status
Simulation time 1237495586 ps
CPU time 28.88 seconds
Started Jul 13 06:55:41 PM PDT 24
Finished Jul 13 06:56:11 PM PDT 24
Peak memory 208640 kb
Host smart-006a163c-9103-4847-9ddc-995967a6e38e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423447137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.423447137
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3524313057
Short name T570
Test name
Test status
Simulation time 38262252 ps
CPU time 2.9 seconds
Started Jul 13 06:55:43 PM PDT 24
Finished Jul 13 06:55:46 PM PDT 24
Peak memory 208572 kb
Host smart-c737708e-bc01-411f-a1e0-9512b3f70e05
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524313057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3524313057
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3451441398
Short name T547
Test name
Test status
Simulation time 252862484 ps
CPU time 5.49 seconds
Started Jul 13 06:55:39 PM PDT 24
Finished Jul 13 06:55:45 PM PDT 24
Peak memory 210092 kb
Host smart-0a358e6f-412a-40a6-afac-439c0743e388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451441398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3451441398
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.4025203214
Short name T437
Test name
Test status
Simulation time 123625020 ps
CPU time 2.24 seconds
Started Jul 13 06:55:29 PM PDT 24
Finished Jul 13 06:55:32 PM PDT 24
Peak memory 206816 kb
Host smart-a0ba6829-f895-488f-aea0-9612d001af6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025203214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.4025203214
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2426950134
Short name T594
Test name
Test status
Simulation time 307681277 ps
CPU time 8.11 seconds
Started Jul 13 06:55:40 PM PDT 24
Finished Jul 13 06:55:49 PM PDT 24
Peak memory 208600 kb
Host smart-c56802f1-5ec7-427e-a599-a49c4efbee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426950134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2426950134
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3882718048
Short name T474
Test name
Test status
Simulation time 88050944 ps
CPU time 3.13 seconds
Started Jul 13 06:55:40 PM PDT 24
Finished Jul 13 06:55:44 PM PDT 24
Peak memory 209824 kb
Host smart-465c140a-4956-41ec-8648-1c2d8ebe51b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882718048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3882718048
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3525586593
Short name T428
Test name
Test status
Simulation time 31879404 ps
CPU time 2.75 seconds
Started Jul 13 06:56:22 PM PDT 24
Finished Jul 13 06:56:26 PM PDT 24
Peak memory 214336 kb
Host smart-f3dd26d3-70e8-4e99-abe7-e8f15ad976a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525586593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3525586593
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.290780762
Short name T9
Test name
Test status
Simulation time 573717427 ps
CPU time 4.55 seconds
Started Jul 13 06:56:18 PM PDT 24
Finished Jul 13 06:56:23 PM PDT 24
Peak memory 218428 kb
Host smart-a2479f2c-edd6-4f12-b9f8-3276ebbefb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290780762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.290780762
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3389124694
Short name T770
Test name
Test status
Simulation time 1548084005 ps
CPU time 9.53 seconds
Started Jul 13 06:56:22 PM PDT 24
Finished Jul 13 06:56:32 PM PDT 24
Peak memory 210088 kb
Host smart-c4a0d4b4-170f-4549-9a4b-af0b9fcd1e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389124694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3389124694
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3211496525
Short name T635
Test name
Test status
Simulation time 87147799 ps
CPU time 2.9 seconds
Started Jul 13 06:56:20 PM PDT 24
Finished Jul 13 06:56:24 PM PDT 24
Peak memory 214328 kb
Host smart-0ec4d632-e7d5-4eb7-a395-95a84bfa99ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211496525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3211496525
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_random.4276422582
Short name T596
Test name
Test status
Simulation time 204291648 ps
CPU time 3.71 seconds
Started Jul 13 06:56:22 PM PDT 24
Finished Jul 13 06:56:27 PM PDT 24
Peak memory 218488 kb
Host smart-31a1afc1-65df-45a0-872a-332b5bc5ed2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276422582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.4276422582
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1871799519
Short name T487
Test name
Test status
Simulation time 2597356521 ps
CPU time 15.99 seconds
Started Jul 13 06:56:21 PM PDT 24
Finished Jul 13 06:56:38 PM PDT 24
Peak memory 208020 kb
Host smart-c55d2440-fc12-4726-a866-f036dd309a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871799519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1871799519
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3353115855
Short name T835
Test name
Test status
Simulation time 57500315 ps
CPU time 2.81 seconds
Started Jul 13 06:56:19 PM PDT 24
Finished Jul 13 06:56:22 PM PDT 24
Peak memory 208552 kb
Host smart-4054aac3-33e8-48cd-b1c7-07621e7d1b8f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353115855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3353115855
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2803246690
Short name T764
Test name
Test status
Simulation time 164676189 ps
CPU time 5 seconds
Started Jul 13 06:56:19 PM PDT 24
Finished Jul 13 06:56:25 PM PDT 24
Peak memory 208868 kb
Host smart-58affdca-1d53-4d41-b5f4-4a6e302530e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803246690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2803246690
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3096738214
Short name T847
Test name
Test status
Simulation time 46416897 ps
CPU time 2.07 seconds
Started Jul 13 06:56:22 PM PDT 24
Finished Jul 13 06:56:25 PM PDT 24
Peak memory 208924 kb
Host smart-d9afc4a3-fd6b-47ca-bbb4-cb937c62eb78
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096738214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3096738214
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.502742221
Short name T516
Test name
Test status
Simulation time 346138008 ps
CPU time 2.58 seconds
Started Jul 13 06:56:19 PM PDT 24
Finished Jul 13 06:56:22 PM PDT 24
Peak memory 218448 kb
Host smart-d785ef76-2c01-4ec2-8553-fd9e03306b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502742221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.502742221
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3305601493
Short name T881
Test name
Test status
Simulation time 42105279 ps
CPU time 2.4 seconds
Started Jul 13 06:56:18 PM PDT 24
Finished Jul 13 06:56:21 PM PDT 24
Peak memory 208412 kb
Host smart-bb722471-8229-4f44-bf85-31c7a4bc3b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305601493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3305601493
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.420657292
Short name T194
Test name
Test status
Simulation time 1248147301 ps
CPU time 49.03 seconds
Started Jul 13 06:56:21 PM PDT 24
Finished Jul 13 06:57:11 PM PDT 24
Peak memory 215548 kb
Host smart-1af453e9-064c-4617-a223-a7fc8149c156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420657292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.420657292
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1060385092
Short name T186
Test name
Test status
Simulation time 1604545451 ps
CPU time 7.2 seconds
Started Jul 13 06:56:20 PM PDT 24
Finished Jul 13 06:56:28 PM PDT 24
Peak memory 222612 kb
Host smart-2486e154-50f0-4e30-9048-a1e2db6e6943
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060385092 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1060385092
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.618764201
Short name T708
Test name
Test status
Simulation time 213904568 ps
CPU time 7.75 seconds
Started Jul 13 06:56:22 PM PDT 24
Finished Jul 13 06:56:31 PM PDT 24
Peak memory 209016 kb
Host smart-881aa0c1-10e0-4181-9448-20711fea53a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618764201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.618764201
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.108701391
Short name T569
Test name
Test status
Simulation time 75504669 ps
CPU time 1.97 seconds
Started Jul 13 06:56:22 PM PDT 24
Finished Jul 13 06:56:25 PM PDT 24
Peak memory 209756 kb
Host smart-1b36e047-2e62-43a0-81c0-ac371e6dc089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108701391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.108701391
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.558268426
Short name T611
Test name
Test status
Simulation time 32550604 ps
CPU time 0.71 seconds
Started Jul 13 06:56:36 PM PDT 24
Finished Jul 13 06:56:38 PM PDT 24
Peak memory 205988 kb
Host smart-b2307647-ed2e-4637-bb73-7cf296c175bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558268426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.558268426
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3218470990
Short name T386
Test name
Test status
Simulation time 74911230 ps
CPU time 1.76 seconds
Started Jul 13 06:56:20 PM PDT 24
Finished Jul 13 06:56:23 PM PDT 24
Peak memory 208224 kb
Host smart-ee89396f-6032-4ea6-8db2-5e70e15eee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218470990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3218470990
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.4159943700
Short name T388
Test name
Test status
Simulation time 528014276 ps
CPU time 3.35 seconds
Started Jul 13 06:56:20 PM PDT 24
Finished Jul 13 06:56:24 PM PDT 24
Peak memory 214436 kb
Host smart-8b3f4027-5315-4196-a3a0-1e5fdf202195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159943700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.4159943700
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.786011681
Short name T501
Test name
Test status
Simulation time 56311019 ps
CPU time 2 seconds
Started Jul 13 06:56:19 PM PDT 24
Finished Jul 13 06:56:22 PM PDT 24
Peak memory 214264 kb
Host smart-fcd48167-5777-46a2-9ec4-0de5bb6edb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786011681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.786011681
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.772314217
Short name T774
Test name
Test status
Simulation time 107442753 ps
CPU time 2.33 seconds
Started Jul 13 06:56:21 PM PDT 24
Finished Jul 13 06:56:24 PM PDT 24
Peak memory 207780 kb
Host smart-7cd3ded2-2cf9-482a-a3cf-79585d825c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772314217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.772314217
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1331672166
Short name T291
Test name
Test status
Simulation time 1064631545 ps
CPU time 10.08 seconds
Started Jul 13 06:56:19 PM PDT 24
Finished Jul 13 06:56:29 PM PDT 24
Peak memory 208592 kb
Host smart-3beb2203-67ae-46c2-8464-b85612501869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331672166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1331672166
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.4225494640
Short name T798
Test name
Test status
Simulation time 148364207 ps
CPU time 2.32 seconds
Started Jul 13 06:56:21 PM PDT 24
Finished Jul 13 06:56:25 PM PDT 24
Peak memory 207320 kb
Host smart-d17b58f8-cf0b-4b84-9636-2a60f794afbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225494640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.4225494640
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3728451349
Short name T861
Test name
Test status
Simulation time 2386779457 ps
CPU time 30.21 seconds
Started Jul 13 06:56:24 PM PDT 24
Finished Jul 13 06:56:54 PM PDT 24
Peak memory 208576 kb
Host smart-2387db35-1181-4bc4-89db-ea7061b509a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728451349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3728451349
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.4137688518
Short name T844
Test name
Test status
Simulation time 1028391245 ps
CPU time 28.34 seconds
Started Jul 13 06:56:23 PM PDT 24
Finished Jul 13 06:56:52 PM PDT 24
Peak memory 208264 kb
Host smart-0da55fe9-2ab0-4668-8df5-6a8bad86d221
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137688518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.4137688518
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.904725561
Short name T818
Test name
Test status
Simulation time 13551791828 ps
CPU time 68.63 seconds
Started Jul 13 06:56:19 PM PDT 24
Finished Jul 13 06:57:29 PM PDT 24
Peak memory 208060 kb
Host smart-d3da4632-8636-43bf-9b91-6c359b2a7b83
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904725561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.904725561
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2461948186
Short name T634
Test name
Test status
Simulation time 118946072 ps
CPU time 2.95 seconds
Started Jul 13 06:56:32 PM PDT 24
Finished Jul 13 06:56:36 PM PDT 24
Peak memory 214348 kb
Host smart-9fca6813-d60e-453f-ba94-36980b05393b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461948186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2461948186
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.657633570
Short name T735
Test name
Test status
Simulation time 100394183 ps
CPU time 3.25 seconds
Started Jul 13 06:56:20 PM PDT 24
Finished Jul 13 06:56:24 PM PDT 24
Peak memory 207052 kb
Host smart-2027a168-835f-407b-954d-240dfe0079b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657633570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.657633570
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2332654657
Short name T479
Test name
Test status
Simulation time 644623305 ps
CPU time 9.06 seconds
Started Jul 13 06:56:22 PM PDT 24
Finished Jul 13 06:56:32 PM PDT 24
Peak memory 208508 kb
Host smart-6a587772-9467-41cd-be53-73dd0cb98edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332654657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2332654657
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.987406167
Short name T782
Test name
Test status
Simulation time 41231955 ps
CPU time 0.85 seconds
Started Jul 13 06:56:28 PM PDT 24
Finished Jul 13 06:56:29 PM PDT 24
Peak memory 206012 kb
Host smart-1c8df0dd-a3c4-4a3b-9d59-a0ea73767dd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987406167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.987406167
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1038701274
Short name T292
Test name
Test status
Simulation time 637763937 ps
CPU time 33.93 seconds
Started Jul 13 06:56:27 PM PDT 24
Finished Jul 13 06:57:01 PM PDT 24
Peak memory 214372 kb
Host smart-1a6c877c-b15a-47e9-b25b-32cdb8240707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1038701274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1038701274
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3238072621
Short name T24
Test name
Test status
Simulation time 282302876 ps
CPU time 2.84 seconds
Started Jul 13 06:56:33 PM PDT 24
Finished Jul 13 06:56:36 PM PDT 24
Peak memory 210780 kb
Host smart-ab2d83c3-c255-4485-bd29-bdfb06c88551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238072621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3238072621
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3603843416
Short name T406
Test name
Test status
Simulation time 18368317 ps
CPU time 1.53 seconds
Started Jul 13 06:56:34 PM PDT 24
Finished Jul 13 06:56:36 PM PDT 24
Peak memory 207392 kb
Host smart-57531926-bbdf-475d-ae18-c7877eb20f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603843416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3603843416
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3646040479
Short name T597
Test name
Test status
Simulation time 550012686 ps
CPU time 5.2 seconds
Started Jul 13 06:56:32 PM PDT 24
Finished Jul 13 06:56:38 PM PDT 24
Peak memory 214408 kb
Host smart-80f651f8-fcd0-44b2-a647-4814a10ba143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646040479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3646040479
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1203647588
Short name T139
Test name
Test status
Simulation time 343611325 ps
CPU time 4.04 seconds
Started Jul 13 06:56:32 PM PDT 24
Finished Jul 13 06:56:37 PM PDT 24
Peak memory 215648 kb
Host smart-881f4af2-dace-42e6-9b94-f0fd3eb95ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203647588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1203647588
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.672806694
Short name T431
Test name
Test status
Simulation time 1328220170 ps
CPU time 5.79 seconds
Started Jul 13 06:56:30 PM PDT 24
Finished Jul 13 06:56:37 PM PDT 24
Peak memory 207168 kb
Host smart-576c0176-307e-48bc-99af-32dc8d85bd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672806694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.672806694
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3452573002
Short name T347
Test name
Test status
Simulation time 142414186 ps
CPU time 3.71 seconds
Started Jul 13 06:56:28 PM PDT 24
Finished Jul 13 06:56:32 PM PDT 24
Peak memory 208856 kb
Host smart-cbc4a9e5-cee8-48f9-848c-62bbfe0d211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452573002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3452573002
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.707236997
Short name T344
Test name
Test status
Simulation time 226003773 ps
CPU time 5.69 seconds
Started Jul 13 06:56:25 PM PDT 24
Finished Jul 13 06:56:31 PM PDT 24
Peak memory 208532 kb
Host smart-f743f324-33a0-4e11-a3de-5f6364ab4d3b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707236997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.707236997
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3542797699
Short name T897
Test name
Test status
Simulation time 125174688 ps
CPU time 2.55 seconds
Started Jul 13 06:56:29 PM PDT 24
Finished Jul 13 06:56:32 PM PDT 24
Peak memory 206980 kb
Host smart-125935dd-3d3b-4e11-a226-123fc7fcf21d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542797699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3542797699
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.977093794
Short name T349
Test name
Test status
Simulation time 33603475 ps
CPU time 2.39 seconds
Started Jul 13 06:56:28 PM PDT 24
Finished Jul 13 06:56:32 PM PDT 24
Peak memory 207028 kb
Host smart-7e0cf33e-730b-4525-9a46-d5e6e0b8312c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977093794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.977093794
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1837358410
Short name T445
Test name
Test status
Simulation time 222093460 ps
CPU time 6.29 seconds
Started Jul 13 06:56:27 PM PDT 24
Finished Jul 13 06:56:34 PM PDT 24
Peak memory 215412 kb
Host smart-8f687e9d-b0e4-4c5e-b892-3a9e135432ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837358410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1837358410
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.732358595
Short name T629
Test name
Test status
Simulation time 8391429998 ps
CPU time 35.07 seconds
Started Jul 13 06:56:28 PM PDT 24
Finished Jul 13 06:57:04 PM PDT 24
Peak memory 209092 kb
Host smart-881fda26-5ed9-4212-af23-5220cbf85812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732358595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.732358595
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3108032473
Short name T841
Test name
Test status
Simulation time 41419751755 ps
CPU time 74.62 seconds
Started Jul 13 06:56:34 PM PDT 24
Finished Jul 13 06:57:49 PM PDT 24
Peak memory 215236 kb
Host smart-c90c627f-ebf5-4648-bee5-56947493db36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108032473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3108032473
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.1892017295
Short name T56
Test name
Test status
Simulation time 227113692 ps
CPU time 9.33 seconds
Started Jul 13 06:56:31 PM PDT 24
Finished Jul 13 06:56:41 PM PDT 24
Peak memory 219796 kb
Host smart-891e835f-0aec-49d5-8c96-6550ddfa5eff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892017295 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.1892017295
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2211581403
Short name T702
Test name
Test status
Simulation time 1137061884 ps
CPU time 33.44 seconds
Started Jul 13 06:56:28 PM PDT 24
Finished Jul 13 06:57:02 PM PDT 24
Peak memory 214340 kb
Host smart-05d22b13-7ddd-4a33-a687-ae0cd9091c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211581403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2211581403
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3322454862
Short name T722
Test name
Test status
Simulation time 90091433 ps
CPU time 2.61 seconds
Started Jul 13 06:56:34 PM PDT 24
Finished Jul 13 06:56:37 PM PDT 24
Peak memory 210344 kb
Host smart-19a350f5-7db3-4998-a2aa-0f02bbb16ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322454862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3322454862
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2086788830
Short name T552
Test name
Test status
Simulation time 29511220 ps
CPU time 0.9 seconds
Started Jul 13 06:56:32 PM PDT 24
Finished Jul 13 06:56:34 PM PDT 24
Peak memory 206004 kb
Host smart-4469fd62-23dc-425b-bb90-3a1c94102a59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086788830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2086788830
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1646179450
Short name T399
Test name
Test status
Simulation time 46592746 ps
CPU time 3.38 seconds
Started Jul 13 06:56:30 PM PDT 24
Finished Jul 13 06:56:34 PM PDT 24
Peak memory 214340 kb
Host smart-65f71f17-7361-41b8-a735-bf8028d930b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646179450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1646179450
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1830516418
Short name T240
Test name
Test status
Simulation time 1937518934 ps
CPU time 7.04 seconds
Started Jul 13 06:56:31 PM PDT 24
Finished Jul 13 06:56:38 PM PDT 24
Peak memory 222872 kb
Host smart-ad6919d1-eeec-4f99-a659-deea08ef13bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830516418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1830516418
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2695655566
Short name T280
Test name
Test status
Simulation time 89748566 ps
CPU time 2.75 seconds
Started Jul 13 06:56:30 PM PDT 24
Finished Jul 13 06:56:34 PM PDT 24
Peak memory 214364 kb
Host smart-6d2217e0-f39a-43ec-8529-061be28c9536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695655566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2695655566
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3904962078
Short name T79
Test name
Test status
Simulation time 40736182 ps
CPU time 1.67 seconds
Started Jul 13 06:56:35 PM PDT 24
Finished Jul 13 06:56:38 PM PDT 24
Peak memory 214264 kb
Host smart-d2cfd81c-46fb-4e24-83f3-a615216bf1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904962078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3904962078
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3614213767
Short name T582
Test name
Test status
Simulation time 330213544 ps
CPU time 3.79 seconds
Started Jul 13 06:56:32 PM PDT 24
Finished Jul 13 06:56:36 PM PDT 24
Peak memory 209964 kb
Host smart-7341d924-ac41-45f3-b753-6935bcf62790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614213767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3614213767
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2406846235
Short name T624
Test name
Test status
Simulation time 64641397 ps
CPU time 4.29 seconds
Started Jul 13 06:56:27 PM PDT 24
Finished Jul 13 06:56:32 PM PDT 24
Peak memory 209688 kb
Host smart-9e3f1f28-9acd-4980-bdb3-08144f139cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406846235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2406846235
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1046477387
Short name T136
Test name
Test status
Simulation time 118082308 ps
CPU time 3.63 seconds
Started Jul 13 06:56:35 PM PDT 24
Finished Jul 13 06:56:39 PM PDT 24
Peak memory 208436 kb
Host smart-c07ed847-c7e0-47d2-8e86-3e252159b071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046477387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1046477387
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.261344450
Short name T832
Test name
Test status
Simulation time 288855003 ps
CPU time 2.96 seconds
Started Jul 13 06:56:30 PM PDT 24
Finished Jul 13 06:56:34 PM PDT 24
Peak memory 207468 kb
Host smart-cfd31586-b4b4-491a-9728-b4a08ef5c568
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261344450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.261344450
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3828520753
Short name T819
Test name
Test status
Simulation time 574324801 ps
CPU time 5.12 seconds
Started Jul 13 06:56:28 PM PDT 24
Finished Jul 13 06:56:34 PM PDT 24
Peak memory 208856 kb
Host smart-78da082d-669a-4eea-bf7d-68044e3c5919
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828520753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3828520753
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3461065744
Short name T632
Test name
Test status
Simulation time 70459179 ps
CPU time 2.44 seconds
Started Jul 13 06:56:28 PM PDT 24
Finished Jul 13 06:56:31 PM PDT 24
Peak memory 206940 kb
Host smart-5721a66f-395a-4b3c-b1c2-6b8db8b83953
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461065744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3461065744
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2602420750
Short name T856
Test name
Test status
Simulation time 61285501 ps
CPU time 2.8 seconds
Started Jul 13 06:56:28 PM PDT 24
Finished Jul 13 06:56:32 PM PDT 24
Peak memory 209992 kb
Host smart-da2184e0-6db6-44d0-95a2-a752622ac0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602420750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2602420750
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.233566139
Short name T401
Test name
Test status
Simulation time 620581667 ps
CPU time 3.63 seconds
Started Jul 13 06:56:25 PM PDT 24
Finished Jul 13 06:56:29 PM PDT 24
Peak memory 208584 kb
Host smart-78f0a7c4-783a-4834-a1b2-f9863c4f25de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233566139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.233566139
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3339878267
Short name T262
Test name
Test status
Simulation time 3558445698 ps
CPU time 26.48 seconds
Started Jul 13 06:56:27 PM PDT 24
Finished Jul 13 06:56:54 PM PDT 24
Peak memory 222456 kb
Host smart-29836fed-0b2a-4ee9-a439-d5b6c18396d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339878267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3339878267
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.599953205
Short name T170
Test name
Test status
Simulation time 132107994 ps
CPU time 9.14 seconds
Started Jul 13 06:56:36 PM PDT 24
Finished Jul 13 06:56:45 PM PDT 24
Peak memory 222540 kb
Host smart-f99c5315-e49b-4c6e-9b57-4b6f30d0612d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599953205 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.599953205
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2044472573
Short name T820
Test name
Test status
Simulation time 473315887 ps
CPU time 6.85 seconds
Started Jul 13 06:56:29 PM PDT 24
Finished Jul 13 06:56:37 PM PDT 24
Peak memory 214324 kb
Host smart-ea6622b7-bdc9-42df-814b-c092f11bd83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044472573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2044472573
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.122863081
Short name T759
Test name
Test status
Simulation time 1235842067 ps
CPU time 6.63 seconds
Started Jul 13 06:56:30 PM PDT 24
Finished Jul 13 06:56:37 PM PDT 24
Peak memory 211068 kb
Host smart-49c9f1bf-1d41-4583-98f9-ca7ef5bb7745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122863081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.122863081
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1274365252
Short name T503
Test name
Test status
Simulation time 59809218 ps
CPU time 0.79 seconds
Started Jul 13 06:56:38 PM PDT 24
Finished Jul 13 06:56:40 PM PDT 24
Peak memory 206004 kb
Host smart-4d62019b-c25c-4f6f-af1a-714d90a5761e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274365252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1274365252
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2022785323
Short name T119
Test name
Test status
Simulation time 39162554 ps
CPU time 3.11 seconds
Started Jul 13 06:56:34 PM PDT 24
Finished Jul 13 06:56:38 PM PDT 24
Peak memory 214252 kb
Host smart-2749d80f-3dce-431a-8ea4-8ecc9b5f81dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2022785323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2022785323
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.325659020
Short name T38
Test name
Test status
Simulation time 176506745 ps
CPU time 1.62 seconds
Started Jul 13 06:56:37 PM PDT 24
Finished Jul 13 06:56:41 PM PDT 24
Peak memory 208252 kb
Host smart-ae981266-4db6-4328-9cc7-fb6a5d0f85cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325659020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.325659020
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.967708648
Short name T67
Test name
Test status
Simulation time 49736168 ps
CPU time 2.77 seconds
Started Jul 13 06:56:29 PM PDT 24
Finished Jul 13 06:56:33 PM PDT 24
Peak memory 209144 kb
Host smart-01e22783-8daa-4df9-b507-3f8eeea26965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967708648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.967708648
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2505349082
Short name T803
Test name
Test status
Simulation time 43081786 ps
CPU time 1.92 seconds
Started Jul 13 06:56:36 PM PDT 24
Finished Jul 13 06:56:40 PM PDT 24
Peak memory 220044 kb
Host smart-85bfac45-6790-4fc5-b243-df14c78b58d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505349082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2505349082
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.863319880
Short name T732
Test name
Test status
Simulation time 70918821 ps
CPU time 3.48 seconds
Started Jul 13 06:56:28 PM PDT 24
Finished Jul 13 06:56:32 PM PDT 24
Peak memory 214908 kb
Host smart-43d9961c-4824-4d0a-ae81-10b214f0834e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863319880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.863319880
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3378118593
Short name T626
Test name
Test status
Simulation time 664793418 ps
CPU time 3.83 seconds
Started Jul 13 06:56:27 PM PDT 24
Finished Jul 13 06:56:31 PM PDT 24
Peak memory 209000 kb
Host smart-a0e69374-4241-4b0e-ac67-e4f457c462c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378118593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3378118593
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1789381281
Short name T661
Test name
Test status
Simulation time 102852800 ps
CPU time 2.38 seconds
Started Jul 13 06:56:30 PM PDT 24
Finished Jul 13 06:56:33 PM PDT 24
Peak memory 206852 kb
Host smart-a9f5e8d8-3bf6-4748-a289-d893c0e65696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789381281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1789381281
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2104509216
Short name T198
Test name
Test status
Simulation time 3390254625 ps
CPU time 38.65 seconds
Started Jul 13 06:56:29 PM PDT 24
Finished Jul 13 06:57:09 PM PDT 24
Peak memory 208600 kb
Host smart-b8bb8afd-8292-4178-9f5c-acbd9d3db0e2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104509216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2104509216
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.936194567
Short name T496
Test name
Test status
Simulation time 22996019 ps
CPU time 1.76 seconds
Started Jul 13 06:56:29 PM PDT 24
Finished Jul 13 06:56:31 PM PDT 24
Peak memory 206964 kb
Host smart-c5606a4d-d968-4330-9172-c51e1727d613
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936194567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.936194567
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3104357625
Short name T878
Test name
Test status
Simulation time 94812270 ps
CPU time 2.1 seconds
Started Jul 13 06:56:29 PM PDT 24
Finished Jul 13 06:56:32 PM PDT 24
Peak memory 208676 kb
Host smart-59cc6b2f-d3eb-4188-86da-fd4539f01920
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104357625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3104357625
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.866952506
Short name T565
Test name
Test status
Simulation time 75750323 ps
CPU time 3.18 seconds
Started Jul 13 06:56:37 PM PDT 24
Finished Jul 13 06:56:42 PM PDT 24
Peak memory 218212 kb
Host smart-426c65e5-9d5f-4350-81c1-afaf218b0eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866952506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.866952506
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1147338123
Short name T688
Test name
Test status
Simulation time 184982852 ps
CPU time 2.82 seconds
Started Jul 13 06:56:27 PM PDT 24
Finished Jul 13 06:56:31 PM PDT 24
Peak memory 208596 kb
Host smart-1dc20995-92d5-4318-88f2-c26f74f1dedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147338123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1147338123
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1178900146
Short name T71
Test name
Test status
Simulation time 481605531 ps
CPU time 9.52 seconds
Started Jul 13 06:56:34 PM PDT 24
Finished Jul 13 06:56:44 PM PDT 24
Peak memory 215160 kb
Host smart-110ece53-6375-46c4-8c26-10f5ccd0170b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178900146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1178900146
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.184175478
Short name T845
Test name
Test status
Simulation time 905774863 ps
CPU time 5.79 seconds
Started Jul 13 06:56:35 PM PDT 24
Finished Jul 13 06:56:42 PM PDT 24
Peak memory 210228 kb
Host smart-9b579457-7361-4c93-b33d-262ecdadfc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184175478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.184175478
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3135216970
Short name T887
Test name
Test status
Simulation time 51731401 ps
CPU time 1.69 seconds
Started Jul 13 06:56:39 PM PDT 24
Finished Jul 13 06:56:42 PM PDT 24
Peak memory 210024 kb
Host smart-180b83a2-f8f9-4eea-8321-ce3697680ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135216970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3135216970
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2352008160
Short name T488
Test name
Test status
Simulation time 11764883 ps
CPU time 0.87 seconds
Started Jul 13 06:56:39 PM PDT 24
Finished Jul 13 06:56:41 PM PDT 24
Peak memory 206000 kb
Host smart-5f89eae5-9eb8-4321-b601-3250d379a14d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352008160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2352008160
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2257670743
Short name T336
Test name
Test status
Simulation time 972922249 ps
CPU time 4.49 seconds
Started Jul 13 06:56:37 PM PDT 24
Finished Jul 13 06:56:44 PM PDT 24
Peak memory 215692 kb
Host smart-90fb9ec2-42c6-4f5a-8e42-a4c108b3d8aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2257670743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2257670743
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.831696074
Short name T11
Test name
Test status
Simulation time 100927063 ps
CPU time 3.15 seconds
Started Jul 13 06:56:38 PM PDT 24
Finished Jul 13 06:56:43 PM PDT 24
Peak memory 208748 kb
Host smart-46b26006-501f-4d58-89f1-4ffb3558f0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831696074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.831696074
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3198815164
Short name T524
Test name
Test status
Simulation time 39141908 ps
CPU time 1.39 seconds
Started Jul 13 06:56:37 PM PDT 24
Finished Jul 13 06:56:40 PM PDT 24
Peak memory 207216 kb
Host smart-a0336528-9be0-4138-9f96-d31f09e60ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198815164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3198815164
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.764514567
Short name T676
Test name
Test status
Simulation time 54126355 ps
CPU time 3.65 seconds
Started Jul 13 06:56:34 PM PDT 24
Finished Jul 13 06:56:39 PM PDT 24
Peak memory 214416 kb
Host smart-d2ff8f63-46e3-4d15-877f-ae0b88f1c7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764514567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.764514567
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1186185226
Short name T714
Test name
Test status
Simulation time 163524145 ps
CPU time 6.39 seconds
Started Jul 13 06:56:43 PM PDT 24
Finished Jul 13 06:56:50 PM PDT 24
Peak memory 210276 kb
Host smart-f8753eae-1378-409a-ae86-cc969c1989cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186185226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1186185226
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1991859693
Short name T593
Test name
Test status
Simulation time 170918591 ps
CPU time 2.49 seconds
Started Jul 13 06:56:37 PM PDT 24
Finished Jul 13 06:56:41 PM PDT 24
Peak memory 208632 kb
Host smart-f303ec81-ed7b-45d5-b092-0423eeb601f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991859693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1991859693
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.401338481
Short name T797
Test name
Test status
Simulation time 93528675 ps
CPU time 3.31 seconds
Started Jul 13 06:56:34 PM PDT 24
Finished Jul 13 06:56:38 PM PDT 24
Peak memory 208772 kb
Host smart-564cfc7c-cacb-462e-8b51-b521c427f48a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401338481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.401338481
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.534379331
Short name T528
Test name
Test status
Simulation time 194878683 ps
CPU time 2.78 seconds
Started Jul 13 06:56:40 PM PDT 24
Finished Jul 13 06:56:43 PM PDT 24
Peak memory 206716 kb
Host smart-2e03b631-e637-4efd-aa91-f6490f46c23f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534379331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.534379331
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3235610647
Short name T743
Test name
Test status
Simulation time 398274660 ps
CPU time 7.78 seconds
Started Jul 13 06:56:36 PM PDT 24
Finished Jul 13 06:56:45 PM PDT 24
Peak memory 208596 kb
Host smart-1f1a4996-5c36-4aed-ae42-4435cc46ebf2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235610647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3235610647
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.4119775230
Short name T742
Test name
Test status
Simulation time 113004986 ps
CPU time 1.65 seconds
Started Jul 13 06:56:37 PM PDT 24
Finished Jul 13 06:56:40 PM PDT 24
Peak memory 209796 kb
Host smart-828a49eb-e607-4553-b3f6-3c40ec8fc989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119775230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.4119775230
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2543599016
Short name T578
Test name
Test status
Simulation time 132743409 ps
CPU time 2.08 seconds
Started Jul 13 06:56:37 PM PDT 24
Finished Jul 13 06:56:41 PM PDT 24
Peak memory 206840 kb
Host smart-11832a3d-a1db-4d54-ace6-db0e7ceff69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543599016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2543599016
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2766325861
Short name T675
Test name
Test status
Simulation time 139578070 ps
CPU time 6.21 seconds
Started Jul 13 06:56:37 PM PDT 24
Finished Jul 13 06:56:46 PM PDT 24
Peak memory 209044 kb
Host smart-82faec68-57ff-434d-96e9-41a78ec65146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766325861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2766325861
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1459574300
Short name T653
Test name
Test status
Simulation time 646298955 ps
CPU time 18.62 seconds
Started Jul 13 06:56:43 PM PDT 24
Finished Jul 13 06:57:02 PM PDT 24
Peak memory 208988 kb
Host smart-8c22a433-5344-42f4-844f-a6aa2c64eccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459574300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1459574300
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.429534201
Short name T883
Test name
Test status
Simulation time 105443767 ps
CPU time 3.1 seconds
Started Jul 13 06:56:35 PM PDT 24
Finished Jul 13 06:56:39 PM PDT 24
Peak memory 210288 kb
Host smart-ba1113b9-0f8a-4c88-99ea-acd08226d6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429534201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.429534201
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3957393417
Short name T438
Test name
Test status
Simulation time 185637544 ps
CPU time 0.99 seconds
Started Jul 13 06:56:45 PM PDT 24
Finished Jul 13 06:56:47 PM PDT 24
Peak memory 206120 kb
Host smart-72d504a6-8672-43fc-9c15-02dc1fa45caa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957393417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3957393417
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2053545120
Short name T738
Test name
Test status
Simulation time 293830743 ps
CPU time 3.59 seconds
Started Jul 13 06:56:39 PM PDT 24
Finished Jul 13 06:56:44 PM PDT 24
Peak memory 214724 kb
Host smart-4ea7d8b7-fd20-453f-abb4-6cff78a2e76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053545120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2053545120
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3257114694
Short name T134
Test name
Test status
Simulation time 22669004 ps
CPU time 1.44 seconds
Started Jul 13 06:56:36 PM PDT 24
Finished Jul 13 06:56:38 PM PDT 24
Peak memory 207340 kb
Host smart-f1c82599-28ff-4195-bf71-1736b10f2ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257114694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3257114694
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1580684646
Short name T693
Test name
Test status
Simulation time 107094275 ps
CPU time 3.5 seconds
Started Jul 13 06:56:37 PM PDT 24
Finished Jul 13 06:56:43 PM PDT 24
Peak memory 221944 kb
Host smart-d4bca9d0-50cc-4064-8dbc-491dd6c9b6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580684646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1580684646
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.4244380766
Short name T783
Test name
Test status
Simulation time 456279097 ps
CPU time 4.08 seconds
Started Jul 13 06:56:36 PM PDT 24
Finished Jul 13 06:56:41 PM PDT 24
Peak memory 210140 kb
Host smart-a31c7568-33ed-453d-ba38-70f420ea6140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244380766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.4244380766
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2487859880
Short name T87
Test name
Test status
Simulation time 203711678 ps
CPU time 2.53 seconds
Started Jul 13 06:56:35 PM PDT 24
Finished Jul 13 06:56:38 PM PDT 24
Peak memory 209092 kb
Host smart-be59cce0-e040-42fd-8bf7-9cbd072b2ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487859880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2487859880
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3103169895
Short name T289
Test name
Test status
Simulation time 1498819381 ps
CPU time 25.55 seconds
Started Jul 13 06:56:43 PM PDT 24
Finished Jul 13 06:57:10 PM PDT 24
Peak memory 208756 kb
Host smart-e807f3e1-f206-4a00-b669-2a7a9a57adc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103169895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3103169895
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2046843132
Short name T513
Test name
Test status
Simulation time 19049222 ps
CPU time 1.78 seconds
Started Jul 13 06:56:40 PM PDT 24
Finished Jul 13 06:56:42 PM PDT 24
Peak memory 206972 kb
Host smart-44d906bf-fbc4-4800-a918-d2fb4fcf2f41
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046843132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2046843132
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1627839420
Short name T530
Test name
Test status
Simulation time 63610608 ps
CPU time 3.26 seconds
Started Jul 13 06:56:37 PM PDT 24
Finished Jul 13 06:56:42 PM PDT 24
Peak memory 208084 kb
Host smart-64ec293d-f4a7-4d2c-be8f-31c67066e5a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627839420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1627839420
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.873700147
Short name T730
Test name
Test status
Simulation time 644206150 ps
CPU time 3.04 seconds
Started Jul 13 06:56:37 PM PDT 24
Finished Jul 13 06:56:42 PM PDT 24
Peak memory 206996 kb
Host smart-d72b74d6-71f3-4312-b49c-0d08dc45bcb8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873700147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.873700147
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2441536142
Short name T106
Test name
Test status
Simulation time 126365467 ps
CPU time 3 seconds
Started Jul 13 06:56:43 PM PDT 24
Finished Jul 13 06:56:47 PM PDT 24
Peak memory 206824 kb
Host smart-e60f54d5-8d0c-40ea-894d-100571eaa54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441536142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2441536142
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.215774526
Short name T222
Test name
Test status
Simulation time 6228168759 ps
CPU time 41.24 seconds
Started Jul 13 06:56:47 PM PDT 24
Finished Jul 13 06:57:28 PM PDT 24
Peak memory 216112 kb
Host smart-85a4e31a-bec9-46fd-b51a-f252955faee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215774526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.215774526
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.4139094935
Short name T335
Test name
Test status
Simulation time 5016903746 ps
CPU time 37.56 seconds
Started Jul 13 06:56:39 PM PDT 24
Finished Jul 13 06:57:18 PM PDT 24
Peak memory 218252 kb
Host smart-f7dfced7-51f7-4c4d-8f31-c2518ef2edbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139094935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.4139094935
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1151240816
Short name T669
Test name
Test status
Simulation time 71300051 ps
CPU time 2.13 seconds
Started Jul 13 06:56:45 PM PDT 24
Finished Jul 13 06:56:48 PM PDT 24
Peak memory 210312 kb
Host smart-81179c9b-ac73-4b6d-b16b-e595ca5e9698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151240816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1151240816
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.784078542
Short name T601
Test name
Test status
Simulation time 12072106 ps
CPU time 0.73 seconds
Started Jul 13 06:56:44 PM PDT 24
Finished Jul 13 06:56:46 PM PDT 24
Peak memory 205996 kb
Host smart-054364a2-c923-4c54-b72e-74eb96c18e91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784078542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.784078542
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3595284830
Short name T657
Test name
Test status
Simulation time 535375144 ps
CPU time 3.85 seconds
Started Jul 13 06:56:46 PM PDT 24
Finished Jul 13 06:56:50 PM PDT 24
Peak memory 210240 kb
Host smart-039a7796-0b99-4346-abd2-3dc835993ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595284830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3595284830
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3293898008
Short name T338
Test name
Test status
Simulation time 108216717 ps
CPU time 3.01 seconds
Started Jul 13 06:56:45 PM PDT 24
Finished Jul 13 06:56:49 PM PDT 24
Peak memory 214420 kb
Host smart-af4154ba-cf8e-4e14-9a73-87e93d901a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293898008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3293898008
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.436458020
Short name T417
Test name
Test status
Simulation time 52351473 ps
CPU time 1.89 seconds
Started Jul 13 06:56:43 PM PDT 24
Finished Jul 13 06:56:46 PM PDT 24
Peak memory 214508 kb
Host smart-af0d20d4-36f3-4f6a-8a7c-6c325f393edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436458020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.436458020
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2518013029
Short name T663
Test name
Test status
Simulation time 98487598 ps
CPU time 2.77 seconds
Started Jul 13 06:56:45 PM PDT 24
Finished Jul 13 06:56:48 PM PDT 24
Peak memory 220976 kb
Host smart-c80f08d7-9b8e-4926-b077-8911c206d0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518013029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2518013029
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2114750872
Short name T235
Test name
Test status
Simulation time 706551309 ps
CPU time 21.47 seconds
Started Jul 13 06:56:48 PM PDT 24
Finished Jul 13 06:57:10 PM PDT 24
Peak memory 219960 kb
Host smart-9a91f7b3-39d0-4edd-bbc3-f378e522b0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114750872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2114750872
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1616402460
Short name T716
Test name
Test status
Simulation time 61050795 ps
CPU time 3.56 seconds
Started Jul 13 06:56:48 PM PDT 24
Finished Jul 13 06:56:52 PM PDT 24
Peak memory 207556 kb
Host smart-598569fe-afd4-4776-8252-4bb3b24a5a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616402460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1616402460
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3610451162
Short name T894
Test name
Test status
Simulation time 112175461 ps
CPU time 2.94 seconds
Started Jul 13 06:56:49 PM PDT 24
Finished Jul 13 06:56:52 PM PDT 24
Peak memory 206844 kb
Host smart-aa96ec00-cb14-4a99-bc4a-3247f0745f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610451162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3610451162
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1071756566
Short name T646
Test name
Test status
Simulation time 127880677 ps
CPU time 4.27 seconds
Started Jul 13 06:56:44 PM PDT 24
Finished Jul 13 06:56:49 PM PDT 24
Peak memory 208484 kb
Host smart-da9b6775-b89e-4e6b-98d9-8239cde589b7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071756566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1071756566
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1509765777
Short name T521
Test name
Test status
Simulation time 70068126 ps
CPU time 2.45 seconds
Started Jul 13 06:56:44 PM PDT 24
Finished Jul 13 06:56:47 PM PDT 24
Peak memory 207624 kb
Host smart-d0f3941a-036f-4a83-a097-1488c7790470
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509765777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1509765777
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.697056022
Short name T576
Test name
Test status
Simulation time 648973827 ps
CPU time 7.29 seconds
Started Jul 13 06:56:48 PM PDT 24
Finished Jul 13 06:56:56 PM PDT 24
Peak memory 208160 kb
Host smart-afde7e78-0c3c-47e5-84b6-63a0788f67c9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697056022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.697056022
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.702665163
Short name T447
Test name
Test status
Simulation time 733694626 ps
CPU time 4.17 seconds
Started Jul 13 06:56:45 PM PDT 24
Finished Jul 13 06:56:50 PM PDT 24
Peak memory 208820 kb
Host smart-4270e86f-a248-438e-ad14-a7f1c12c4378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702665163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.702665163
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3288458211
Short name T694
Test name
Test status
Simulation time 255658658 ps
CPU time 3.33 seconds
Started Jul 13 06:56:44 PM PDT 24
Finished Jul 13 06:56:48 PM PDT 24
Peak memory 206916 kb
Host smart-24622e27-c4f9-44e2-8bc4-230139ecbcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288458211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3288458211
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1577621079
Short name T638
Test name
Test status
Simulation time 811515563 ps
CPU time 9.45 seconds
Started Jul 13 06:56:47 PM PDT 24
Finished Jul 13 06:56:57 PM PDT 24
Peak memory 222500 kb
Host smart-53ac867c-e229-4b33-9069-7412c0bc6621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577621079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1577621079
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3139100620
Short name T840
Test name
Test status
Simulation time 450460267 ps
CPU time 4.53 seconds
Started Jul 13 06:56:44 PM PDT 24
Finished Jul 13 06:56:49 PM PDT 24
Peak memory 209864 kb
Host smart-6312b0e7-7aab-4990-a34e-292d43823214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139100620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3139100620
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1252844767
Short name T102
Test name
Test status
Simulation time 13961783 ps
CPU time 0.78 seconds
Started Jul 13 06:56:55 PM PDT 24
Finished Jul 13 06:56:58 PM PDT 24
Peak memory 205992 kb
Host smart-5fa400c5-d1fd-4694-9dfd-d355777706b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252844767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1252844767
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.759709710
Short name T365
Test name
Test status
Simulation time 46850046 ps
CPU time 2 seconds
Started Jul 13 06:56:45 PM PDT 24
Finished Jul 13 06:56:47 PM PDT 24
Peak memory 214348 kb
Host smart-443c68e2-5c9f-46fc-8a23-0d0e3edef700
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759709710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.759709710
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1851050701
Short name T34
Test name
Test status
Simulation time 75979204 ps
CPU time 2.92 seconds
Started Jul 13 06:56:53 PM PDT 24
Finished Jul 13 06:56:56 PM PDT 24
Peak memory 222848 kb
Host smart-ad775882-32a5-4b38-a874-097f7606a8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851050701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1851050701
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3283266747
Short name T683
Test name
Test status
Simulation time 716934257 ps
CPU time 20.18 seconds
Started Jul 13 06:56:43 PM PDT 24
Finished Jul 13 06:57:04 PM PDT 24
Peak memory 208980 kb
Host smart-030ee6b4-bae4-4886-8b0e-4c0f1866adc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283266747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3283266747
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.760745017
Short name T600
Test name
Test status
Simulation time 381835989 ps
CPU time 3.21 seconds
Started Jul 13 06:56:55 PM PDT 24
Finished Jul 13 06:56:59 PM PDT 24
Peak memory 214224 kb
Host smart-1f1b76f0-e456-45fa-b2a5-237308c37214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760745017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.760745017
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2447384435
Short name T61
Test name
Test status
Simulation time 140260030 ps
CPU time 7.69 seconds
Started Jul 13 06:56:53 PM PDT 24
Finished Jul 13 06:57:01 PM PDT 24
Peak memory 214336 kb
Host smart-b2fa44c4-d3c9-4241-99c7-d9b0fe92077c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447384435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2447384435
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2741516995
Short name T621
Test name
Test status
Simulation time 86632261 ps
CPU time 4.39 seconds
Started Jul 13 06:56:45 PM PDT 24
Finished Jul 13 06:56:50 PM PDT 24
Peak memory 207476 kb
Host smart-5be236a1-76b0-4ca7-9222-d24ffaf3f2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741516995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2741516995
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3397659420
Short name T452
Test name
Test status
Simulation time 199781124 ps
CPU time 2.7 seconds
Started Jul 13 06:56:48 PM PDT 24
Finished Jul 13 06:56:51 PM PDT 24
Peak memory 206932 kb
Host smart-8d70aa14-5a87-4208-b738-c8ba608d9b25
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397659420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3397659420
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2263870950
Short name T784
Test name
Test status
Simulation time 503952507 ps
CPU time 4.39 seconds
Started Jul 13 06:56:48 PM PDT 24
Finished Jul 13 06:56:53 PM PDT 24
Peak memory 209012 kb
Host smart-f2410f8d-e1c7-4f6d-9e34-c8e2e18f5d0b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263870950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2263870950
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.4202798896
Short name T886
Test name
Test status
Simulation time 718921397 ps
CPU time 5.33 seconds
Started Jul 13 06:56:54 PM PDT 24
Finished Jul 13 06:57:00 PM PDT 24
Peak memory 214252 kb
Host smart-0a6494f9-9b01-4346-b341-0afacadade91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202798896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4202798896
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3768896688
Short name T436
Test name
Test status
Simulation time 9216758572 ps
CPU time 28.55 seconds
Started Jul 13 06:56:43 PM PDT 24
Finished Jul 13 06:57:12 PM PDT 24
Peak memory 208416 kb
Host smart-a2009546-b51c-4ee0-8653-6c786fc8f0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768896688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3768896688
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3073571506
Short name T670
Test name
Test status
Simulation time 579869401 ps
CPU time 14.55 seconds
Started Jul 13 06:56:56 PM PDT 24
Finished Jul 13 06:57:12 PM PDT 24
Peak memory 215792 kb
Host smart-0275a352-15ec-4231-a09a-c47c3690ee39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073571506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3073571506
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1239744921
Short name T310
Test name
Test status
Simulation time 40340495 ps
CPU time 3.14 seconds
Started Jul 13 06:56:56 PM PDT 24
Finished Jul 13 06:57:00 PM PDT 24
Peak memory 218336 kb
Host smart-afee28a3-3a51-4c21-b53d-9eea4fc32004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239744921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1239744921
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1181369302
Short name T162
Test name
Test status
Simulation time 150311302 ps
CPU time 2.72 seconds
Started Jul 13 06:56:55 PM PDT 24
Finished Jul 13 06:56:59 PM PDT 24
Peak memory 210156 kb
Host smart-fec259cb-4dcc-4fa4-9b63-712ff84b9a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181369302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1181369302
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.606420033
Short name T475
Test name
Test status
Simulation time 41307222 ps
CPU time 0.85 seconds
Started Jul 13 06:56:54 PM PDT 24
Finished Jul 13 06:56:56 PM PDT 24
Peak memory 206028 kb
Host smart-883d7672-1be3-46de-aa03-6a6b19004233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606420033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.606420033
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2238528795
Short name T236
Test name
Test status
Simulation time 517825424 ps
CPU time 6.27 seconds
Started Jul 13 06:56:55 PM PDT 24
Finished Jul 13 06:57:02 PM PDT 24
Peak memory 219140 kb
Host smart-9a1ef12f-e312-47b3-a99d-77617e0e0ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238528795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2238528795
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3506141956
Short name T460
Test name
Test status
Simulation time 123517320 ps
CPU time 2.92 seconds
Started Jul 13 06:56:53 PM PDT 24
Finished Jul 13 06:56:57 PM PDT 24
Peak memory 219740 kb
Host smart-5ee5b83d-0600-4c2e-9fdd-938918b953b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506141956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3506141956
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3623554473
Short name T678
Test name
Test status
Simulation time 58497100 ps
CPU time 2.4 seconds
Started Jul 13 06:56:55 PM PDT 24
Finished Jul 13 06:56:59 PM PDT 24
Peak memory 222508 kb
Host smart-225fcf93-515d-4007-8b22-b96c41ac9608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623554473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3623554473
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1938757612
Short name T352
Test name
Test status
Simulation time 107010006 ps
CPU time 4.47 seconds
Started Jul 13 06:56:56 PM PDT 24
Finished Jul 13 06:57:02 PM PDT 24
Peak memory 214292 kb
Host smart-43061a39-4bf7-46e5-816c-dc35b4aa0111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938757612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1938757612
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1706339454
Short name T408
Test name
Test status
Simulation time 77739965 ps
CPU time 3.95 seconds
Started Jul 13 06:56:57 PM PDT 24
Finished Jul 13 06:57:02 PM PDT 24
Peak memory 214324 kb
Host smart-6a675c93-4ba0-49aa-aff0-8ae15b4cb14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706339454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1706339454
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_sideload.118137696
Short name T651
Test name
Test status
Simulation time 90094771 ps
CPU time 3.62 seconds
Started Jul 13 06:56:56 PM PDT 24
Finished Jul 13 06:57:01 PM PDT 24
Peak memory 208136 kb
Host smart-a939625b-0472-4151-a059-06792eeba495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118137696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.118137696
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1698306834
Short name T859
Test name
Test status
Simulation time 672831261 ps
CPU time 3.15 seconds
Started Jul 13 06:56:56 PM PDT 24
Finished Jul 13 06:57:01 PM PDT 24
Peak memory 208620 kb
Host smart-3e49f4a7-973c-4ae9-acf5-553d51ec6ece
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698306834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1698306834
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.823991732
Short name T604
Test name
Test status
Simulation time 123755993 ps
CPU time 2.4 seconds
Started Jul 13 06:56:54 PM PDT 24
Finished Jul 13 06:56:58 PM PDT 24
Peak memory 207720 kb
Host smart-bdbcde09-e8a8-423d-a005-276a0c1e0238
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823991732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.823991732
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1001208142
Short name T380
Test name
Test status
Simulation time 35992252 ps
CPU time 2.56 seconds
Started Jul 13 06:56:56 PM PDT 24
Finished Jul 13 06:57:00 PM PDT 24
Peak memory 208996 kb
Host smart-b27ade01-0abf-4b34-8e5c-072807c23b55
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001208142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1001208142
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1470248080
Short name T623
Test name
Test status
Simulation time 483436480 ps
CPU time 2.34 seconds
Started Jul 13 06:56:54 PM PDT 24
Finished Jul 13 06:56:57 PM PDT 24
Peak memory 208036 kb
Host smart-04ee47a3-cd5d-4880-a1c9-6cc5ac7cefa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470248080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1470248080
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2298187270
Short name T808
Test name
Test status
Simulation time 165088933 ps
CPU time 3.68 seconds
Started Jul 13 06:56:56 PM PDT 24
Finished Jul 13 06:57:01 PM PDT 24
Peak memory 207980 kb
Host smart-eb41eb01-b4a4-43a8-b8ae-7c83eff4019b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298187270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2298187270
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3955180195
Short name T430
Test name
Test status
Simulation time 141327053 ps
CPU time 5.47 seconds
Started Jul 13 06:56:56 PM PDT 24
Finished Jul 13 06:57:03 PM PDT 24
Peak memory 208060 kb
Host smart-fdd6f9aa-4749-471e-9a2d-aea2984d45f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955180195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3955180195
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2235070835
Short name T133
Test name
Test status
Simulation time 87694492 ps
CPU time 2.99 seconds
Started Jul 13 06:56:54 PM PDT 24
Finished Jul 13 06:56:58 PM PDT 24
Peak memory 209904 kb
Host smart-e3cb8cff-c12b-48d4-b410-b8574c24f04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235070835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2235070835
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3897356800
Short name T727
Test name
Test status
Simulation time 44096396 ps
CPU time 0.86 seconds
Started Jul 13 06:55:37 PM PDT 24
Finished Jul 13 06:55:40 PM PDT 24
Peak memory 206004 kb
Host smart-51cf9daf-d08a-44e3-9f2a-f5f82407f58b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897356800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3897356800
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3053358662
Short name T371
Test name
Test status
Simulation time 1090372003 ps
CPU time 14.56 seconds
Started Jul 13 06:55:36 PM PDT 24
Finished Jul 13 06:55:52 PM PDT 24
Peak memory 214868 kb
Host smart-b96265fa-6f6e-4ad7-b2fd-8ba9437a27b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3053358662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3053358662
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1149503045
Short name T29
Test name
Test status
Simulation time 404619721 ps
CPU time 2.99 seconds
Started Jul 13 06:55:37 PM PDT 24
Finished Jul 13 06:55:42 PM PDT 24
Peak memory 214696 kb
Host smart-2e27a2c8-4fc3-4dde-94fb-9728bbf31430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149503045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1149503045
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3256138697
Short name T78
Test name
Test status
Simulation time 114922505 ps
CPU time 3.34 seconds
Started Jul 13 06:55:38 PM PDT 24
Finished Jul 13 06:55:42 PM PDT 24
Peak memory 214348 kb
Host smart-a8275e7b-390f-41b3-a587-a55e60a49cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256138697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3256138697
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.4146720536
Short name T92
Test name
Test status
Simulation time 170012840 ps
CPU time 3.18 seconds
Started Jul 13 06:55:38 PM PDT 24
Finished Jul 13 06:55:42 PM PDT 24
Peak memory 214328 kb
Host smart-17c65740-98da-463d-a124-cd61b07ed378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146720536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4146720536
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.952234272
Short name T297
Test name
Test status
Simulation time 50893475 ps
CPU time 2.22 seconds
Started Jul 13 06:55:39 PM PDT 24
Finished Jul 13 06:55:42 PM PDT 24
Peak memory 214284 kb
Host smart-2168df0c-d8f0-415d-bd99-7ca1ff2fcd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952234272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.952234272
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3818266671
Short name T1
Test name
Test status
Simulation time 315235616 ps
CPU time 3.2 seconds
Started Jul 13 06:55:40 PM PDT 24
Finished Jul 13 06:55:44 PM PDT 24
Peak memory 214352 kb
Host smart-c4127b74-c748-45e5-8cca-bf96ad117180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818266671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3818266671
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.486491908
Short name T456
Test name
Test status
Simulation time 248817077 ps
CPU time 6.7 seconds
Started Jul 13 06:55:38 PM PDT 24
Finished Jul 13 06:55:46 PM PDT 24
Peak memory 209092 kb
Host smart-9eb06330-b1f3-44d2-af4c-bb00c2f596c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486491908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.486491908
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.4140416293
Short name T105
Test name
Test status
Simulation time 1405397273 ps
CPU time 22.92 seconds
Started Jul 13 06:55:38 PM PDT 24
Finished Jul 13 06:56:02 PM PDT 24
Peak memory 231012 kb
Host smart-734cf92f-e9c5-421e-90b8-8ad34f95f284
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140416293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.4140416293
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3472002300
Short name T863
Test name
Test status
Simulation time 223606253 ps
CPU time 2.64 seconds
Started Jul 13 06:55:40 PM PDT 24
Finished Jul 13 06:55:44 PM PDT 24
Peak memory 206772 kb
Host smart-6ebd8a36-2ddf-42bd-993e-8b61f8f4f347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472002300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3472002300
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2508552406
Short name T196
Test name
Test status
Simulation time 140204958 ps
CPU time 4.48 seconds
Started Jul 13 06:55:38 PM PDT 24
Finished Jul 13 06:55:43 PM PDT 24
Peak memory 208032 kb
Host smart-b8c5af1c-f91b-42f5-bf6c-711d3b5aeb05
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508552406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2508552406
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3286467143
Short name T718
Test name
Test status
Simulation time 915578246 ps
CPU time 6.87 seconds
Started Jul 13 06:55:36 PM PDT 24
Finished Jul 13 06:55:44 PM PDT 24
Peak memory 208680 kb
Host smart-b1ea15a9-ce80-4530-be36-145f3b15695f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286467143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3286467143
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2508640245
Short name T212
Test name
Test status
Simulation time 48587919 ps
CPU time 2.66 seconds
Started Jul 13 06:55:42 PM PDT 24
Finished Jul 13 06:55:45 PM PDT 24
Peak memory 208548 kb
Host smart-3b80e3dc-380f-4391-b887-d45aea7bd13c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508640245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2508640245
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3344327614
Short name T608
Test name
Test status
Simulation time 163052441 ps
CPU time 3.19 seconds
Started Jul 13 06:55:37 PM PDT 24
Finished Jul 13 06:55:42 PM PDT 24
Peak memory 214264 kb
Host smart-3774db23-9cb9-4cc7-91fb-96473a012b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344327614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3344327614
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.222667648
Short name T875
Test name
Test status
Simulation time 183135672 ps
CPU time 4.86 seconds
Started Jul 13 06:55:36 PM PDT 24
Finished Jul 13 06:55:42 PM PDT 24
Peak memory 208368 kb
Host smart-bb57e03a-3f90-49bd-b971-d9f49471a55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222667648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.222667648
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.318248891
Short name T74
Test name
Test status
Simulation time 5651597678 ps
CPU time 68.28 seconds
Started Jul 13 06:55:36 PM PDT 24
Finished Jul 13 06:56:46 PM PDT 24
Peak memory 215960 kb
Host smart-fc4205f1-4409-42b1-b614-7503a4d0ed55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318248891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.318248891
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3540402457
Short name T780
Test name
Test status
Simulation time 414522534 ps
CPU time 5.86 seconds
Started Jul 13 06:55:36 PM PDT 24
Finished Jul 13 06:55:42 PM PDT 24
Peak memory 214336 kb
Host smart-837c0b56-c86e-4b91-8c3c-0b80ac6dbd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540402457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3540402457
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2849560721
Short name T805
Test name
Test status
Simulation time 6939948513 ps
CPU time 15.04 seconds
Started Jul 13 06:55:36 PM PDT 24
Finished Jul 13 06:55:52 PM PDT 24
Peak memory 211700 kb
Host smart-7d38ba26-3657-4fbb-89d6-8a9c2fae3ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849560721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2849560721
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.4271552506
Short name T664
Test name
Test status
Simulation time 60411503 ps
CPU time 0.78 seconds
Started Jul 13 06:57:07 PM PDT 24
Finished Jul 13 06:57:09 PM PDT 24
Peak memory 205984 kb
Host smart-d1f5573c-77a6-4f11-ba49-d9438caebda0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271552506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.4271552506
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.675667622
Short name T398
Test name
Test status
Simulation time 35324296 ps
CPU time 2.72 seconds
Started Jul 13 06:56:56 PM PDT 24
Finished Jul 13 06:57:01 PM PDT 24
Peak memory 222596 kb
Host smart-145e872d-fde2-44b3-a017-fcc2a51f814c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=675667622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.675667622
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.176584036
Short name T405
Test name
Test status
Simulation time 362331897 ps
CPU time 2.19 seconds
Started Jul 13 06:56:57 PM PDT 24
Finished Jul 13 06:57:01 PM PDT 24
Peak memory 207784 kb
Host smart-df28e67a-026e-48f0-bdbc-c906b0559d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176584036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.176584036
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.37119992
Short name T100
Test name
Test status
Simulation time 351047487 ps
CPU time 3.91 seconds
Started Jul 13 06:56:57 PM PDT 24
Finished Jul 13 06:57:02 PM PDT 24
Peak memory 220864 kb
Host smart-483fa572-bbcf-4532-b5fb-573330adbbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37119992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.37119992
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.1340215085
Short name T606
Test name
Test status
Simulation time 86673846 ps
CPU time 3.62 seconds
Started Jul 13 06:56:56 PM PDT 24
Finished Jul 13 06:57:01 PM PDT 24
Peak memory 214288 kb
Host smart-1845282f-2367-4081-a4ed-a91224c99e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340215085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1340215085
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_random.1626228417
Short name T532
Test name
Test status
Simulation time 1003555562 ps
CPU time 4.68 seconds
Started Jul 13 06:56:56 PM PDT 24
Finished Jul 13 06:57:03 PM PDT 24
Peak memory 207672 kb
Host smart-055c5e29-2d63-4942-ba26-a3d99c27b5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626228417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1626228417
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2895994960
Short name T821
Test name
Test status
Simulation time 337422011 ps
CPU time 3.03 seconds
Started Jul 13 06:56:54 PM PDT 24
Finished Jul 13 06:56:58 PM PDT 24
Peak memory 206752 kb
Host smart-9ec8d39c-ee08-4cde-83a8-1f8191d260cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895994960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2895994960
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.166341256
Short name T111
Test name
Test status
Simulation time 53213580 ps
CPU time 1.75 seconds
Started Jul 13 06:56:55 PM PDT 24
Finished Jul 13 06:56:58 PM PDT 24
Peak memory 206920 kb
Host smart-d7520492-d52f-423d-bfef-a112869d4e14
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166341256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.166341256
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2739566689
Short name T799
Test name
Test status
Simulation time 63588281 ps
CPU time 2.33 seconds
Started Jul 13 06:56:55 PM PDT 24
Finished Jul 13 06:56:59 PM PDT 24
Peak memory 206996 kb
Host smart-156d0078-1637-40bf-901e-53a4b5626fc6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739566689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2739566689
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3842163025
Short name T459
Test name
Test status
Simulation time 304773753 ps
CPU time 9.12 seconds
Started Jul 13 06:56:57 PM PDT 24
Finished Jul 13 06:57:07 PM PDT 24
Peak memory 218680 kb
Host smart-ee5c874b-0efd-4118-8459-20ceb5c2197f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842163025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3842163025
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.112573226
Short name T499
Test name
Test status
Simulation time 185618388 ps
CPU time 5.34 seconds
Started Jul 13 06:56:58 PM PDT 24
Finished Jul 13 06:57:04 PM PDT 24
Peak memory 206876 kb
Host smart-297bd0e8-c98e-488e-9d41-9a45f54bba9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112573226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.112573226
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.16886273
Short name T51
Test name
Test status
Simulation time 298002205 ps
CPU time 2.87 seconds
Started Jul 13 06:56:55 PM PDT 24
Finished Jul 13 06:56:59 PM PDT 24
Peak memory 215976 kb
Host smart-81363394-c5ba-451e-8c0f-299b9bcf68f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16886273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.16886273
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.829435410
Short name T346
Test name
Test status
Simulation time 677278194 ps
CPU time 9.56 seconds
Started Jul 13 06:56:56 PM PDT 24
Finished Jul 13 06:57:07 PM PDT 24
Peak memory 208400 kb
Host smart-71f998ff-6577-4334-a4e5-79fb1d84fd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829435410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.829435410
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2271874977
Short name T185
Test name
Test status
Simulation time 29426414 ps
CPU time 1.91 seconds
Started Jul 13 06:56:54 PM PDT 24
Finished Jul 13 06:56:57 PM PDT 24
Peak memory 210092 kb
Host smart-3c2efbd0-1e76-4ddc-8ff2-d7810cd55aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271874977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2271874977
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2021816809
Short name T103
Test name
Test status
Simulation time 47927478 ps
CPU time 0.77 seconds
Started Jul 13 06:57:08 PM PDT 24
Finished Jul 13 06:57:10 PM PDT 24
Peak memory 206028 kb
Host smart-c7a7ed9f-5ddd-40ab-836d-be93d6b32420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021816809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2021816809
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3118499434
Short name T275
Test name
Test status
Simulation time 160025964 ps
CPU time 2.47 seconds
Started Jul 13 06:57:07 PM PDT 24
Finished Jul 13 06:57:11 PM PDT 24
Peak memory 214376 kb
Host smart-e8ce792d-8111-40aa-9206-c559e6e1b316
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3118499434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3118499434
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3940901231
Short name T690
Test name
Test status
Simulation time 135140539 ps
CPU time 5.08 seconds
Started Jul 13 06:57:09 PM PDT 24
Finished Jul 13 06:57:16 PM PDT 24
Peak memory 222332 kb
Host smart-150ef2bc-e3e3-4837-8eb6-f2ce4b18c5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940901231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3940901231
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2353148676
Short name T429
Test name
Test status
Simulation time 38536925 ps
CPU time 2.42 seconds
Started Jul 13 06:57:06 PM PDT 24
Finished Jul 13 06:57:09 PM PDT 24
Peak memory 206064 kb
Host smart-ce83ac39-c54a-44cb-8f0a-129b681852d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353148676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2353148676
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1657091305
Short name T231
Test name
Test status
Simulation time 81983638 ps
CPU time 2.66 seconds
Started Jul 13 06:57:06 PM PDT 24
Finished Jul 13 06:57:09 PM PDT 24
Peak memory 214328 kb
Host smart-1f5b6716-4ed6-45ee-975d-a7f7d1215ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657091305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1657091305
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.984368058
Short name T342
Test name
Test status
Simulation time 110426222 ps
CPU time 4.19 seconds
Started Jul 13 06:57:07 PM PDT 24
Finished Jul 13 06:57:13 PM PDT 24
Peak memory 209200 kb
Host smart-842259a1-4f29-4de0-9784-4bdf95b86067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984368058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.984368058
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2765272927
Short name T812
Test name
Test status
Simulation time 866755809 ps
CPU time 4.83 seconds
Started Jul 13 06:57:09 PM PDT 24
Finished Jul 13 06:57:16 PM PDT 24
Peak memory 207040 kb
Host smart-1c5ad534-7cc2-4605-923a-1b6300084fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765272927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2765272927
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1042663230
Short name T892
Test name
Test status
Simulation time 64265620 ps
CPU time 2.95 seconds
Started Jul 13 06:57:09 PM PDT 24
Finished Jul 13 06:57:14 PM PDT 24
Peak memory 206964 kb
Host smart-55793ae4-3d74-40a6-91b2-bfcd81646b2c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042663230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1042663230
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2805906665
Short name T211
Test name
Test status
Simulation time 117069879 ps
CPU time 3.11 seconds
Started Jul 13 06:57:06 PM PDT 24
Finished Jul 13 06:57:09 PM PDT 24
Peak memory 208820 kb
Host smart-a83e3830-e699-4ed7-bd45-99d5878b1232
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805906665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2805906665
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.884021001
Short name T869
Test name
Test status
Simulation time 631239306 ps
CPU time 3.23 seconds
Started Jul 13 06:57:08 PM PDT 24
Finished Jul 13 06:57:13 PM PDT 24
Peak memory 208804 kb
Host smart-931abb1e-0c0f-4a02-9336-15b6c561196b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884021001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.884021001
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.56616577
Short name T201
Test name
Test status
Simulation time 472815593 ps
CPU time 5.33 seconds
Started Jul 13 06:57:10 PM PDT 24
Finished Jul 13 06:57:17 PM PDT 24
Peak memory 220828 kb
Host smart-d794d885-a571-4327-be53-c206afdd7ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56616577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.56616577
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1068964810
Short name T435
Test name
Test status
Simulation time 124141143 ps
CPU time 2.23 seconds
Started Jul 13 06:57:07 PM PDT 24
Finished Jul 13 06:57:10 PM PDT 24
Peak memory 206168 kb
Host smart-1476ef90-3625-4332-b43d-20190ca6e582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068964810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1068964810
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3159394801
Short name T554
Test name
Test status
Simulation time 35466261 ps
CPU time 0.82 seconds
Started Jul 13 06:57:07 PM PDT 24
Finished Jul 13 06:57:09 PM PDT 24
Peak memory 206016 kb
Host smart-42b81443-6207-48c1-8128-4682660a3a00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159394801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3159394801
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.315282742
Short name T277
Test name
Test status
Simulation time 44192616 ps
CPU time 3.12 seconds
Started Jul 13 06:57:07 PM PDT 24
Finished Jul 13 06:57:12 PM PDT 24
Peak memory 209868 kb
Host smart-b01a40cd-47a8-4983-92fa-28089643d9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315282742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.315282742
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1119832870
Short name T555
Test name
Test status
Simulation time 50537243 ps
CPU time 2.27 seconds
Started Jul 13 06:57:08 PM PDT 24
Finished Jul 13 06:57:12 PM PDT 24
Peak memory 210064 kb
Host smart-8d37c5c4-f320-419e-95f2-17894a8b9f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119832870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1119832870
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1828449596
Short name T776
Test name
Test status
Simulation time 9896166 ps
CPU time 0.8 seconds
Started Jul 13 06:57:07 PM PDT 24
Finished Jul 13 06:57:09 PM PDT 24
Peak memory 206012 kb
Host smart-a694dae8-74c4-4984-8752-7616d8cc50a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828449596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1828449596
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.4143483637
Short name T906
Test name
Test status
Simulation time 106669857 ps
CPU time 2.51 seconds
Started Jul 13 06:57:11 PM PDT 24
Finished Jul 13 06:57:14 PM PDT 24
Peak memory 214244 kb
Host smart-9573c0c2-ec4f-412f-a35d-7edc3dc8d4e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4143483637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.4143483637
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2385080549
Short name T839
Test name
Test status
Simulation time 244489187 ps
CPU time 4.22 seconds
Started Jul 13 06:57:12 PM PDT 24
Finished Jul 13 06:57:16 PM PDT 24
Peak memory 214324 kb
Host smart-03f7951b-177a-48c3-b983-fff882f2b6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385080549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2385080549
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1555995070
Short name T66
Test name
Test status
Simulation time 70967980 ps
CPU time 2.16 seconds
Started Jul 13 06:57:08 PM PDT 24
Finished Jul 13 06:57:13 PM PDT 24
Peak memory 207432 kb
Host smart-02e74bb1-38ec-41f2-9bd7-2374d5fa6a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555995070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1555995070
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3338576274
Short name T91
Test name
Test status
Simulation time 85669824 ps
CPU time 1.81 seconds
Started Jul 13 06:57:07 PM PDT 24
Finished Jul 13 06:57:10 PM PDT 24
Peak memory 222356 kb
Host smart-484e9c5c-2e7d-47ad-adca-c39485e1456c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338576274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3338576274
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.621264126
Short name T796
Test name
Test status
Simulation time 262310023 ps
CPU time 3.68 seconds
Started Jul 13 06:57:10 PM PDT 24
Finished Jul 13 06:57:15 PM PDT 24
Peak memory 214336 kb
Host smart-0ff29439-9e86-4d58-bcd5-5207c162ad2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621264126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.621264126
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.125577973
Short name T778
Test name
Test status
Simulation time 50254608 ps
CPU time 2.75 seconds
Started Jul 13 06:57:05 PM PDT 24
Finished Jul 13 06:57:08 PM PDT 24
Peak memory 216060 kb
Host smart-70f2c2ac-6b8e-45ae-9a75-0583f639c562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125577973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.125577973
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.307689048
Short name T283
Test name
Test status
Simulation time 5050190748 ps
CPU time 91.35 seconds
Started Jul 13 06:57:09 PM PDT 24
Finished Jul 13 06:58:43 PM PDT 24
Peak memory 222572 kb
Host smart-cb618a5e-4620-42ca-9b28-dd6ffce07829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307689048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.307689048
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3512201986
Short name T383
Test name
Test status
Simulation time 1068521412 ps
CPU time 12.82 seconds
Started Jul 13 06:57:11 PM PDT 24
Finished Jul 13 06:57:25 PM PDT 24
Peak memory 207756 kb
Host smart-d93fcfcf-ccc5-4fc4-ae6a-71d7e1a90d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512201986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3512201986
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3027847942
Short name T539
Test name
Test status
Simulation time 69583780 ps
CPU time 3.66 seconds
Started Jul 13 06:57:09 PM PDT 24
Finished Jul 13 06:57:15 PM PDT 24
Peak memory 208604 kb
Host smart-1812920e-eceb-42d4-9dbd-adf00c835904
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027847942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3027847942
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.833563045
Short name T910
Test name
Test status
Simulation time 60716831 ps
CPU time 1.89 seconds
Started Jul 13 06:57:06 PM PDT 24
Finished Jul 13 06:57:08 PM PDT 24
Peak memory 206892 kb
Host smart-3a5679e1-2ac1-4070-9311-436613e87ba8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833563045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.833563045
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3634233230
Short name T448
Test name
Test status
Simulation time 57558597 ps
CPU time 3 seconds
Started Jul 13 06:57:09 PM PDT 24
Finished Jul 13 06:57:14 PM PDT 24
Peak memory 206904 kb
Host smart-8d00560f-8681-43fe-b302-5fbf60216de7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634233230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3634233230
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1493361175
Short name T510
Test name
Test status
Simulation time 148856792 ps
CPU time 2.54 seconds
Started Jul 13 06:57:08 PM PDT 24
Finished Jul 13 06:57:13 PM PDT 24
Peak memory 207412 kb
Host smart-29723673-9710-45fb-87cb-8030cfbd7583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493361175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1493361175
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.4117371090
Short name T490
Test name
Test status
Simulation time 3100529159 ps
CPU time 20.6 seconds
Started Jul 13 06:57:10 PM PDT 24
Finished Jul 13 06:57:32 PM PDT 24
Peak memory 208152 kb
Host smart-515fea70-05bb-45f2-b15b-07245f4e7aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117371090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.4117371090
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.4179437561
Short name T272
Test name
Test status
Simulation time 132296405 ps
CPU time 4.71 seconds
Started Jul 13 06:57:09 PM PDT 24
Finished Jul 13 06:57:16 PM PDT 24
Peak memory 214324 kb
Host smart-3e524137-7215-4fbd-b537-638601ba045d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179437561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.4179437561
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1249398604
Short name T125
Test name
Test status
Simulation time 95497479 ps
CPU time 2.41 seconds
Started Jul 13 06:57:09 PM PDT 24
Finished Jul 13 06:57:14 PM PDT 24
Peak memory 209896 kb
Host smart-d79cd79d-4715-4383-8d5c-fec677bdf546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249398604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1249398604
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1650083095
Short name T833
Test name
Test status
Simulation time 20361029 ps
CPU time 0.88 seconds
Started Jul 13 06:57:17 PM PDT 24
Finished Jul 13 06:57:18 PM PDT 24
Peak memory 205956 kb
Host smart-7bc7acc0-7942-4db4-b8e4-6b9af2fe3f25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650083095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1650083095
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2496983868
Short name T367
Test name
Test status
Simulation time 37575975 ps
CPU time 2.9 seconds
Started Jul 13 06:57:08 PM PDT 24
Finished Jul 13 06:57:13 PM PDT 24
Peak memory 215340 kb
Host smart-6eed084c-233d-4a45-b4f8-e93d54e5a887
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2496983868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2496983868
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2629202145
Short name T32
Test name
Test status
Simulation time 191061418 ps
CPU time 2.68 seconds
Started Jul 13 06:57:19 PM PDT 24
Finished Jul 13 06:57:23 PM PDT 24
Peak memory 219544 kb
Host smart-1f5fd5fd-a832-44ef-af23-6c84318d390c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629202145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2629202145
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2290550958
Short name T76
Test name
Test status
Simulation time 44945541 ps
CPU time 2.43 seconds
Started Jul 13 06:57:09 PM PDT 24
Finished Jul 13 06:57:13 PM PDT 24
Peak memory 209496 kb
Host smart-8ab332d9-75d1-4199-a5cf-6e4e4115f277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290550958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2290550958
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2111256961
Short name T740
Test name
Test status
Simulation time 228051194 ps
CPU time 3.49 seconds
Started Jul 13 06:57:09 PM PDT 24
Finished Jul 13 06:57:14 PM PDT 24
Peak memory 214292 kb
Host smart-24966c14-a85b-4f70-8c90-d2f3554cd402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111256961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2111256961
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1179294464
Short name T279
Test name
Test status
Simulation time 63300035 ps
CPU time 3.17 seconds
Started Jul 13 06:57:07 PM PDT 24
Finished Jul 13 06:57:11 PM PDT 24
Peak memory 221852 kb
Host smart-cd73b619-23b1-480f-830d-62ef453acd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179294464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1179294464
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1780936195
Short name T49
Test name
Test status
Simulation time 93055506 ps
CPU time 3.51 seconds
Started Jul 13 06:57:09 PM PDT 24
Finished Jul 13 06:57:15 PM PDT 24
Peak memory 214324 kb
Host smart-6b25ca1e-f95f-4121-a577-0adb04de39a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780936195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1780936195
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.970111751
Short name T658
Test name
Test status
Simulation time 297641195 ps
CPU time 9.37 seconds
Started Jul 13 06:57:06 PM PDT 24
Finished Jul 13 06:57:16 PM PDT 24
Peak memory 218500 kb
Host smart-ee8d43ad-be01-4317-997b-daba01e8bf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970111751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.970111751
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.448211392
Short name T368
Test name
Test status
Simulation time 525777449 ps
CPU time 4.63 seconds
Started Jul 13 06:57:06 PM PDT 24
Finished Jul 13 06:57:11 PM PDT 24
Peak memory 208392 kb
Host smart-18c533ad-54e6-4064-92b0-88058fef04bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448211392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.448211392
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2345828634
Short name T741
Test name
Test status
Simulation time 191290051 ps
CPU time 2.65 seconds
Started Jul 13 06:57:07 PM PDT 24
Finished Jul 13 06:57:12 PM PDT 24
Peak memory 206976 kb
Host smart-b06b209a-4733-4926-b652-599e1b9c95ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345828634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2345828634
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3982547671
Short name T545
Test name
Test status
Simulation time 27743041 ps
CPU time 2.24 seconds
Started Jul 13 06:57:09 PM PDT 24
Finished Jul 13 06:57:13 PM PDT 24
Peak memory 208688 kb
Host smart-dbe1bc0b-5881-40d9-803b-1a3373e95170
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982547671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3982547671
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3705051835
Short name T686
Test name
Test status
Simulation time 68983792 ps
CPU time 2.48 seconds
Started Jul 13 06:57:08 PM PDT 24
Finished Jul 13 06:57:13 PM PDT 24
Peak memory 206968 kb
Host smart-40f6399d-0ee3-480d-a813-540d6fdef554
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705051835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3705051835
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.553952234
Short name T588
Test name
Test status
Simulation time 307103854 ps
CPU time 2.85 seconds
Started Jul 13 06:57:18 PM PDT 24
Finished Jul 13 06:57:23 PM PDT 24
Peak memory 218256 kb
Host smart-99c86421-9866-4211-8824-737062cb3b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553952234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.553952234
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3694335051
Short name T753
Test name
Test status
Simulation time 1616130809 ps
CPU time 25.82 seconds
Started Jul 13 06:57:09 PM PDT 24
Finished Jul 13 06:57:37 PM PDT 24
Peak memory 208748 kb
Host smart-067a86cd-00b0-4dbb-ad29-318108f41525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694335051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3694335051
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1774303065
Short name T442
Test name
Test status
Simulation time 139881130 ps
CPU time 5.05 seconds
Started Jul 13 06:57:12 PM PDT 24
Finished Jul 13 06:57:17 PM PDT 24
Peak memory 214320 kb
Host smart-6002e35e-97c2-4e6f-aff6-dd62feb2c47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774303065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1774303065
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.4033956470
Short name T393
Test name
Test status
Simulation time 36559080 ps
CPU time 1.31 seconds
Started Jul 13 06:57:16 PM PDT 24
Finished Jul 13 06:57:18 PM PDT 24
Peak memory 209736 kb
Host smart-fe57f036-15c0-453c-bddb-b7fc1f4826ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033956470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.4033956470
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.4213942293
Short name T905
Test name
Test status
Simulation time 18972735 ps
CPU time 0.77 seconds
Started Jul 13 06:57:17 PM PDT 24
Finished Jul 13 06:57:18 PM PDT 24
Peak memory 205988 kb
Host smart-b581c2ec-8a0b-4a89-9d09-a6e924e3666b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213942293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.4213942293
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.4049955838
Short name T426
Test name
Test status
Simulation time 60308563 ps
CPU time 3.67 seconds
Started Jul 13 06:57:18 PM PDT 24
Finished Jul 13 06:57:23 PM PDT 24
Peak memory 215408 kb
Host smart-2723a8f1-cd47-4d46-ac5e-9ce370e7bd26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4049955838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.4049955838
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.831574208
Short name T69
Test name
Test status
Simulation time 961327675 ps
CPU time 23.1 seconds
Started Jul 13 06:57:20 PM PDT 24
Finished Jul 13 06:57:46 PM PDT 24
Peak memory 218344 kb
Host smart-6d082278-80cb-4023-ba72-dcff6da1fd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831574208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.831574208
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3723338929
Short name T353
Test name
Test status
Simulation time 43699039 ps
CPU time 1.69 seconds
Started Jul 13 06:57:19 PM PDT 24
Finished Jul 13 06:57:23 PM PDT 24
Peak memory 214452 kb
Host smart-dac09760-7e3f-461b-b829-65eb06da94b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723338929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3723338929
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3921140792
Short name T865
Test name
Test status
Simulation time 460077961 ps
CPU time 3.81 seconds
Started Jul 13 06:57:19 PM PDT 24
Finished Jul 13 06:57:24 PM PDT 24
Peak memory 222440 kb
Host smart-9dda9334-0b3c-46aa-9107-ce136ba40d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921140792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3921140792
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3314703762
Short name T314
Test name
Test status
Simulation time 364626260 ps
CPU time 6.13 seconds
Started Jul 13 06:57:20 PM PDT 24
Finished Jul 13 06:57:28 PM PDT 24
Peak memory 220184 kb
Host smart-0fd8bbd0-fdea-4d2e-8628-cee4864e081b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314703762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3314703762
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1132831088
Short name T706
Test name
Test status
Simulation time 716540937 ps
CPU time 5.66 seconds
Started Jul 13 06:57:18 PM PDT 24
Finished Jul 13 06:57:26 PM PDT 24
Peak memory 209572 kb
Host smart-64ba6bcf-196a-4f58-924b-a6a00e9fcbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132831088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1132831088
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3381194416
Short name T872
Test name
Test status
Simulation time 204105965 ps
CPU time 4.47 seconds
Started Jul 13 06:57:16 PM PDT 24
Finished Jul 13 06:57:21 PM PDT 24
Peak memory 206872 kb
Host smart-c4271bae-6825-4501-8aaa-3ea59ee6860e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381194416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3381194416
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.400632256
Short name T700
Test name
Test status
Simulation time 121801772 ps
CPU time 2.29 seconds
Started Jul 13 06:57:19 PM PDT 24
Finished Jul 13 06:57:23 PM PDT 24
Peak memory 206824 kb
Host smart-153c01b6-252b-441e-bec3-efc82c9eafe7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400632256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.400632256
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2993092796
Short name T470
Test name
Test status
Simulation time 438689332 ps
CPU time 5.59 seconds
Started Jul 13 06:57:15 PM PDT 24
Finished Jul 13 06:57:21 PM PDT 24
Peak memory 208588 kb
Host smart-423034aa-011b-4516-a484-db12a6e2246b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993092796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2993092796
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.4050552712
Short name T671
Test name
Test status
Simulation time 709137487 ps
CPU time 5.72 seconds
Started Jul 13 06:57:22 PM PDT 24
Finished Jul 13 06:57:30 PM PDT 24
Peak memory 208660 kb
Host smart-8c7787d9-d754-46e1-b8fb-82dc5ed583aa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050552712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.4050552712
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3183261193
Short name T682
Test name
Test status
Simulation time 100392257 ps
CPU time 1.4 seconds
Started Jul 13 06:57:15 PM PDT 24
Finished Jul 13 06:57:16 PM PDT 24
Peak memory 207684 kb
Host smart-0495bfbe-5843-4d93-8b82-5f56e9637efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183261193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3183261193
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3606694250
Short name T536
Test name
Test status
Simulation time 78830820 ps
CPU time 2.53 seconds
Started Jul 13 06:57:18 PM PDT 24
Finished Jul 13 06:57:22 PM PDT 24
Peak memory 206860 kb
Host smart-8a7e72be-9ff0-41d2-9272-249527e7a282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606694250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3606694250
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1966539961
Short name T50
Test name
Test status
Simulation time 527262395 ps
CPU time 20.38 seconds
Started Jul 13 06:57:19 PM PDT 24
Finished Jul 13 06:57:42 PM PDT 24
Peak memory 223212 kb
Host smart-976e1135-6ea9-4264-b90e-8b77b2db3d91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966539961 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1966539961
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.122802594
Short name T276
Test name
Test status
Simulation time 4017765778 ps
CPU time 24.36 seconds
Started Jul 13 06:57:14 PM PDT 24
Finished Jul 13 06:57:39 PM PDT 24
Peak memory 209056 kb
Host smart-4e2a790f-e1cf-425f-b4e2-ea45179bb1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122802594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.122802594
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1587050671
Short name T802
Test name
Test status
Simulation time 275900157 ps
CPU time 3.33 seconds
Started Jul 13 06:57:17 PM PDT 24
Finished Jul 13 06:57:21 PM PDT 24
Peak memory 210144 kb
Host smart-8338c455-aac4-458a-9b6d-6426bc8ec888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587050671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1587050671
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3319100223
Short name T668
Test name
Test status
Simulation time 13512521 ps
CPU time 0.8 seconds
Started Jul 13 06:57:19 PM PDT 24
Finished Jul 13 06:57:22 PM PDT 24
Peak memory 205960 kb
Host smart-41b9ffbf-22ff-4676-a284-e88d76cabb6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319100223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3319100223
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.665045569
Short name T306
Test name
Test status
Simulation time 508664232 ps
CPU time 13.66 seconds
Started Jul 13 06:57:20 PM PDT 24
Finished Jul 13 06:57:36 PM PDT 24
Peak memory 214396 kb
Host smart-7566e8fc-a334-4f2e-9784-b83ec337e4e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=665045569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.665045569
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1313819478
Short name T620
Test name
Test status
Simulation time 1965343192 ps
CPU time 20.7 seconds
Started Jul 13 06:57:20 PM PDT 24
Finished Jul 13 06:57:44 PM PDT 24
Peak memory 208128 kb
Host smart-d60b5874-419d-4694-83f7-15e421da5428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313819478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1313819478
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3876415886
Short name T867
Test name
Test status
Simulation time 74279489 ps
CPU time 3.5 seconds
Started Jul 13 06:57:20 PM PDT 24
Finished Jul 13 06:57:26 PM PDT 24
Peak memory 214352 kb
Host smart-f4821eaf-dc03-46df-85e4-9178a4dbd90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876415886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3876415886
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1662696773
Short name T355
Test name
Test status
Simulation time 89839303 ps
CPU time 2.19 seconds
Started Jul 13 06:57:21 PM PDT 24
Finished Jul 13 06:57:26 PM PDT 24
Peak memory 214176 kb
Host smart-9f02f477-6b46-40c6-aa73-d3d1a41d038f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662696773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1662696773
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_random.1532781807
Short name T348
Test name
Test status
Simulation time 124837101 ps
CPU time 4.99 seconds
Started Jul 13 06:57:17 PM PDT 24
Finished Jul 13 06:57:24 PM PDT 24
Peak memory 207564 kb
Host smart-e06e0ea7-6bab-4cee-9da0-3669fa9c8d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532781807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1532781807
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3520257111
Short name T86
Test name
Test status
Simulation time 117642821 ps
CPU time 3.04 seconds
Started Jul 13 06:57:16 PM PDT 24
Finished Jul 13 06:57:20 PM PDT 24
Peak memory 206816 kb
Host smart-f1d13530-aed5-4f62-9b1f-78740a4d81cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520257111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3520257111
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3953027422
Short name T538
Test name
Test status
Simulation time 358431287 ps
CPU time 2.96 seconds
Started Jul 13 06:57:21 PM PDT 24
Finished Jul 13 06:57:27 PM PDT 24
Peak memory 208648 kb
Host smart-fb41f6a7-a93d-4297-9e6e-de77e367a125
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953027422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3953027422
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.464815402
Short name T558
Test name
Test status
Simulation time 328414068 ps
CPU time 8.69 seconds
Started Jul 13 06:57:19 PM PDT 24
Finished Jul 13 06:57:30 PM PDT 24
Peak memory 209112 kb
Host smart-e8908fb1-01fd-4094-b973-99977f3b23e1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464815402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.464815402
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1900877368
Short name T282
Test name
Test status
Simulation time 2281984746 ps
CPU time 21.87 seconds
Started Jul 13 06:57:24 PM PDT 24
Finished Jul 13 06:57:48 PM PDT 24
Peak memory 209244 kb
Host smart-8a083335-a3b7-44c6-b127-8d5bd8fcd37f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900877368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1900877368
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.112083808
Short name T322
Test name
Test status
Simulation time 264280452 ps
CPU time 3.21 seconds
Started Jul 13 06:57:21 PM PDT 24
Finished Jul 13 06:57:27 PM PDT 24
Peak memory 209980 kb
Host smart-0c587315-5bb2-4d52-8a77-06814bab0bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112083808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.112083808
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.332467224
Short name T785
Test name
Test status
Simulation time 53610980 ps
CPU time 2.47 seconds
Started Jul 13 06:57:16 PM PDT 24
Finished Jul 13 06:57:19 PM PDT 24
Peak memory 207108 kb
Host smart-80e50a4d-7c4d-4db0-b1ff-48e113f08447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332467224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.332467224
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.4028951968
Short name T28
Test name
Test status
Simulation time 284321595 ps
CPU time 4.27 seconds
Started Jul 13 06:57:17 PM PDT 24
Finished Jul 13 06:57:23 PM PDT 24
Peak memory 208312 kb
Host smart-4260320e-c982-464f-86e2-3825fe697c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028951968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.4028951968
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3508653784
Short name T183
Test name
Test status
Simulation time 39411475 ps
CPU time 1.92 seconds
Started Jul 13 06:57:20 PM PDT 24
Finished Jul 13 06:57:25 PM PDT 24
Peak memory 210664 kb
Host smart-292bd40e-ae9b-44e6-9879-240e20ca5ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508653784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3508653784
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.507737485
Short name T491
Test name
Test status
Simulation time 13099573 ps
CPU time 0.75 seconds
Started Jul 13 06:57:20 PM PDT 24
Finished Jul 13 06:57:24 PM PDT 24
Peak memory 206000 kb
Host smart-2c236cfb-95f3-4af2-8e7e-cf478ee21334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507737485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.507737485
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2983356380
Short name T540
Test name
Test status
Simulation time 24284037 ps
CPU time 1.82 seconds
Started Jul 13 06:57:21 PM PDT 24
Finished Jul 13 06:57:25 PM PDT 24
Peak memory 214204 kb
Host smart-26a7aa1b-71f2-439e-891f-772348fe971b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983356380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2983356380
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1317662366
Short name T89
Test name
Test status
Simulation time 152227254 ps
CPU time 1.91 seconds
Started Jul 13 06:57:21 PM PDT 24
Finished Jul 13 06:57:25 PM PDT 24
Peak memory 214316 kb
Host smart-3d59a2e4-164c-4a9b-8d5b-fd9881c8a412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317662366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1317662366
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3951232690
Short name T358
Test name
Test status
Simulation time 311537320 ps
CPU time 4.19 seconds
Started Jul 13 06:57:24 PM PDT 24
Finished Jul 13 06:57:31 PM PDT 24
Peak memory 214100 kb
Host smart-0b785aac-c919-4ee3-93da-757758410517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951232690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3951232690
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3118316545
Short name T7
Test name
Test status
Simulation time 107710837 ps
CPU time 2.86 seconds
Started Jul 13 06:57:24 PM PDT 24
Finished Jul 13 06:57:29 PM PDT 24
Peak memory 219820 kb
Host smart-eff7398d-c1fe-42e6-8ea3-cfedd432b390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118316545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3118316545
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3800161884
Short name T251
Test name
Test status
Simulation time 976708402 ps
CPU time 3.93 seconds
Started Jul 13 06:57:17 PM PDT 24
Finished Jul 13 06:57:22 PM PDT 24
Peak memory 214412 kb
Host smart-32f6fce9-09ce-4132-850a-0133964b93a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800161884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3800161884
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.191968959
Short name T254
Test name
Test status
Simulation time 26124947 ps
CPU time 1.99 seconds
Started Jul 13 06:57:24 PM PDT 24
Finished Jul 13 06:57:28 PM PDT 24
Peak memory 208668 kb
Host smart-3ca7772d-c1dd-40da-acc6-dc4ce21039b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191968959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.191968959
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1797121866
Short name T560
Test name
Test status
Simulation time 366927592 ps
CPU time 4.33 seconds
Started Jul 13 06:57:20 PM PDT 24
Finished Jul 13 06:57:27 PM PDT 24
Peak memory 208608 kb
Host smart-3759ff8b-bac8-41f4-af1d-ea26dde5ea61
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797121866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1797121866
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2040036769
Short name T751
Test name
Test status
Simulation time 543385224 ps
CPU time 3.43 seconds
Started Jul 13 06:57:19 PM PDT 24
Finished Jul 13 06:57:24 PM PDT 24
Peak memory 208412 kb
Host smart-7d6fc171-49cd-44d4-8c69-637bf06a3778
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040036769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2040036769
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2139095120
Short name T265
Test name
Test status
Simulation time 141478117 ps
CPU time 3.4 seconds
Started Jul 13 06:57:16 PM PDT 24
Finished Jul 13 06:57:20 PM PDT 24
Peak memory 208636 kb
Host smart-a239a7e3-b097-4010-818b-77a195b731ac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139095120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2139095120
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.95053946
Short name T439
Test name
Test status
Simulation time 447252111 ps
CPU time 3.9 seconds
Started Jul 13 06:57:19 PM PDT 24
Finished Jul 13 06:57:25 PM PDT 24
Peak memory 209012 kb
Host smart-1939afd1-7727-4787-b4d8-77e7c0d7012a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95053946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.95053946
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3542546317
Short name T644
Test name
Test status
Simulation time 19269854 ps
CPU time 1.67 seconds
Started Jul 13 06:57:16 PM PDT 24
Finished Jul 13 06:57:18 PM PDT 24
Peak memory 206756 kb
Host smart-97d90b33-a67a-4fe5-8959-e9f027d0aaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542546317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3542546317
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1608758267
Short name T296
Test name
Test status
Simulation time 1273715451 ps
CPU time 31.43 seconds
Started Jul 13 06:57:21 PM PDT 24
Finished Jul 13 06:57:55 PM PDT 24
Peak memory 222612 kb
Host smart-200b47c8-d205-49d4-b7d1-f536f8a57d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608758267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1608758267
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.2509372698
Short name T184
Test name
Test status
Simulation time 314737609 ps
CPU time 12.91 seconds
Started Jul 13 06:57:16 PM PDT 24
Finished Jul 13 06:57:30 PM PDT 24
Peak memory 222548 kb
Host smart-4960c3a7-936e-4dce-80c3-2b7d87096324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509372698 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.2509372698
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2941035394
Short name T361
Test name
Test status
Simulation time 166103541 ps
CPU time 4.95 seconds
Started Jul 13 06:57:16 PM PDT 24
Finished Jul 13 06:57:21 PM PDT 24
Peak memory 209312 kb
Host smart-2b366546-28cf-49a3-86e0-f30a0558e65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941035394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2941035394
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2894457830
Short name T392
Test name
Test status
Simulation time 124845886 ps
CPU time 2.57 seconds
Started Jul 13 06:57:21 PM PDT 24
Finished Jul 13 06:57:26 PM PDT 24
Peak memory 210068 kb
Host smart-8ede551d-6062-4877-b74c-0f0955eea730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894457830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2894457830
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.462417601
Short name T827
Test name
Test status
Simulation time 44345703 ps
CPU time 0.76 seconds
Started Jul 13 06:57:24 PM PDT 24
Finished Jul 13 06:57:27 PM PDT 24
Peak memory 205912 kb
Host smart-8c4f9497-1bcd-43e5-8fa0-f8b1ed78dd05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462417601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.462417601
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2625033345
Short name T37
Test name
Test status
Simulation time 1064145757 ps
CPU time 3.99 seconds
Started Jul 13 06:57:18 PM PDT 24
Finished Jul 13 06:57:24 PM PDT 24
Peak memory 210132 kb
Host smart-e8672013-aa91-4920-8522-27500e60ecbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625033345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2625033345
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3888005289
Short name T736
Test name
Test status
Simulation time 405979987 ps
CPU time 10.44 seconds
Started Jul 13 06:57:18 PM PDT 24
Finished Jul 13 06:57:29 PM PDT 24
Peak memory 208596 kb
Host smart-8963c08e-aaf4-4642-b4a5-0b0a348a3984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888005289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3888005289
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.50610277
Short name T486
Test name
Test status
Simulation time 23166834 ps
CPU time 1.91 seconds
Started Jul 13 06:57:19 PM PDT 24
Finished Jul 13 06:57:23 PM PDT 24
Peak memory 214328 kb
Host smart-ccfb5bfb-a7e8-4555-b410-b098a6cbe6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50610277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.50610277
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3517950302
Short name T85
Test name
Test status
Simulation time 213497684 ps
CPU time 4.49 seconds
Started Jul 13 06:57:18 PM PDT 24
Finished Jul 13 06:57:24 PM PDT 24
Peak memory 222396 kb
Host smart-46e36b9a-1023-456c-8cff-63909bb5069e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517950302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3517950302
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3482071868
Short name T630
Test name
Test status
Simulation time 85707242 ps
CPU time 2.28 seconds
Started Jul 13 06:57:18 PM PDT 24
Finished Jul 13 06:57:21 PM PDT 24
Peak memory 209512 kb
Host smart-65d03f51-c910-4e15-bc16-5a3c45e2f569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482071868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3482071868
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1249142414
Short name T216
Test name
Test status
Simulation time 1439704160 ps
CPU time 34.76 seconds
Started Jul 13 06:57:21 PM PDT 24
Finished Jul 13 06:57:59 PM PDT 24
Peak memory 209372 kb
Host smart-5855ceba-59da-4305-93c4-7b2a926772ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249142414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1249142414
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3745116752
Short name T873
Test name
Test status
Simulation time 40214218 ps
CPU time 1.76 seconds
Started Jul 13 06:57:21 PM PDT 24
Finished Jul 13 06:57:25 PM PDT 24
Peak memory 206992 kb
Host smart-18d8bad8-c62b-42ff-872f-9359790f392e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745116752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3745116752
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2423537939
Short name T815
Test name
Test status
Simulation time 38393418 ps
CPU time 2.78 seconds
Started Jul 13 06:57:21 PM PDT 24
Finished Jul 13 06:57:26 PM PDT 24
Peak memory 209084 kb
Host smart-d99a5cf1-d008-4d77-9815-f370c4087bd0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423537939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2423537939
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.123621586
Short name T609
Test name
Test status
Simulation time 6472236110 ps
CPU time 43.98 seconds
Started Jul 13 06:57:21 PM PDT 24
Finished Jul 13 06:58:08 PM PDT 24
Peak memory 207948 kb
Host smart-10e4a323-7689-4c52-aa49-e7ef4514e2ad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123621586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.123621586
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.4027549917
Short name T339
Test name
Test status
Simulation time 844352545 ps
CPU time 6.31 seconds
Started Jul 13 06:57:21 PM PDT 24
Finished Jul 13 06:57:30 PM PDT 24
Peak memory 208380 kb
Host smart-4717d9fa-a478-40e0-a327-5b73a063674b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027549917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4027549917
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2583444273
Short name T300
Test name
Test status
Simulation time 259879267 ps
CPU time 2.62 seconds
Started Jul 13 06:57:20 PM PDT 24
Finished Jul 13 06:57:25 PM PDT 24
Peak memory 214332 kb
Host smart-9e2ebcb0-c27c-45ed-8aa3-d13c92c3ecf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583444273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2583444273
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.53703342
Short name T455
Test name
Test status
Simulation time 191121846 ps
CPU time 5.17 seconds
Started Jul 13 06:57:21 PM PDT 24
Finished Jul 13 06:57:29 PM PDT 24
Peak memory 208108 kb
Host smart-e1bf7a13-fa47-4130-9068-2130e17687f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53703342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.53703342
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3671434318
Short name T252
Test name
Test status
Simulation time 111821860 ps
CPU time 5.31 seconds
Started Jul 13 06:57:24 PM PDT 24
Finished Jul 13 06:57:32 PM PDT 24
Peak memory 217980 kb
Host smart-8ab7eac1-c83a-4acf-a2d4-8a551b66b853
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671434318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3671434318
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.124870464
Short name T132
Test name
Test status
Simulation time 1167057625 ps
CPU time 23.55 seconds
Started Jul 13 06:57:19 PM PDT 24
Finished Jul 13 06:57:45 PM PDT 24
Peak memory 222616 kb
Host smart-c7357902-cf8f-4249-ad9a-4d0276745a39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124870464 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.124870464
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1647101974
Short name T135
Test name
Test status
Simulation time 1405162819 ps
CPU time 15.31 seconds
Started Jul 13 06:57:21 PM PDT 24
Finished Jul 13 06:57:39 PM PDT 24
Peak memory 214320 kb
Host smart-85a87703-eb08-4073-b368-5e5721ba6231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647101974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1647101974
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2319626586
Short name T489
Test name
Test status
Simulation time 76757212 ps
CPU time 1.9 seconds
Started Jul 13 06:57:19 PM PDT 24
Finished Jul 13 06:57:23 PM PDT 24
Peak memory 210012 kb
Host smart-a781694a-fbd9-4198-8626-6eeae951d3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319626586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2319626586
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3665901147
Short name T453
Test name
Test status
Simulation time 53382016 ps
CPU time 0.79 seconds
Started Jul 13 06:57:28 PM PDT 24
Finished Jul 13 06:57:30 PM PDT 24
Peak memory 205980 kb
Host smart-f86d34e1-04d2-4528-a758-78544deb8767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665901147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3665901147
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.467821039
Short name T765
Test name
Test status
Simulation time 301090522 ps
CPU time 2.84 seconds
Started Jul 13 06:57:23 PM PDT 24
Finished Jul 13 06:57:29 PM PDT 24
Peak memory 214360 kb
Host smart-f3194397-dccf-40ca-816d-59952521b94f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=467821039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.467821039
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.105823120
Short name T31
Test name
Test status
Simulation time 122565104 ps
CPU time 4.02 seconds
Started Jul 13 06:57:28 PM PDT 24
Finished Jul 13 06:57:34 PM PDT 24
Peak memory 214328 kb
Host smart-ff3ee86d-46d1-4e58-9a14-72303dce124e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105823120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.105823120
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2637896352
Short name T410
Test name
Test status
Simulation time 69773336 ps
CPU time 1.62 seconds
Started Jul 13 06:57:25 PM PDT 24
Finished Jul 13 06:57:28 PM PDT 24
Peak memory 207424 kb
Host smart-8207d9b8-2025-4708-9686-9d7cdbb2ded4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637896352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2637896352
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.812162112
Short name T874
Test name
Test status
Simulation time 32017438 ps
CPU time 2.29 seconds
Started Jul 13 06:57:28 PM PDT 24
Finished Jul 13 06:57:32 PM PDT 24
Peak memory 214444 kb
Host smart-c71b8e08-7961-46a3-b6d6-d9950586035d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812162112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.812162112
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3117209719
Short name T356
Test name
Test status
Simulation time 394390105 ps
CPU time 3.4 seconds
Started Jul 13 06:57:26 PM PDT 24
Finished Jul 13 06:57:32 PM PDT 24
Peak memory 214272 kb
Host smart-2e88cf61-8f80-430d-af24-7f430ace7c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117209719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3117209719
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1524009171
Short name T469
Test name
Test status
Simulation time 81071638 ps
CPU time 3.44 seconds
Started Jul 13 06:57:29 PM PDT 24
Finished Jul 13 06:57:34 PM PDT 24
Peak memory 214432 kb
Host smart-4d5d712f-d85c-4e68-886f-a2fd56665d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524009171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1524009171
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3174259044
Short name T264
Test name
Test status
Simulation time 38320464 ps
CPU time 2.9 seconds
Started Jul 13 06:57:26 PM PDT 24
Finished Jul 13 06:57:31 PM PDT 24
Peak memory 209368 kb
Host smart-9636a7ae-2019-4fa2-8c7a-c190f917c52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174259044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3174259044
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3220170636
Short name T583
Test name
Test status
Simulation time 272745839 ps
CPU time 6.03 seconds
Started Jul 13 06:57:18 PM PDT 24
Finished Jul 13 06:57:26 PM PDT 24
Peak memory 208828 kb
Host smart-071294d5-9749-4b4e-9d21-8d31e9cbc9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220170636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3220170636
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3715177197
Short name T717
Test name
Test status
Simulation time 96012459 ps
CPU time 4.15 seconds
Started Jul 13 06:57:29 PM PDT 24
Finished Jul 13 06:57:35 PM PDT 24
Peak memory 208648 kb
Host smart-2af8e893-bf38-4376-a908-8eb2377d2030
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715177197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3715177197
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1131861250
Short name T402
Test name
Test status
Simulation time 1885542152 ps
CPU time 46.24 seconds
Started Jul 13 06:57:19 PM PDT 24
Finished Jul 13 06:58:08 PM PDT 24
Peak memory 209024 kb
Host smart-08245184-f41c-4e3e-a391-d9b980dfd621
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131861250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1131861250
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3575181353
Short name T754
Test name
Test status
Simulation time 145801814 ps
CPU time 5.64 seconds
Started Jul 13 06:57:28 PM PDT 24
Finished Jul 13 06:57:36 PM PDT 24
Peak memory 208552 kb
Host smart-e32d92d5-faf1-4850-82df-f72f4487b85e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575181353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3575181353
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.709662826
Short name T418
Test name
Test status
Simulation time 40336230 ps
CPU time 2.05 seconds
Started Jul 13 06:57:28 PM PDT 24
Finished Jul 13 06:57:32 PM PDT 24
Peak memory 209568 kb
Host smart-687c0859-de1e-4498-a9d4-b02a457fb882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709662826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.709662826
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.4132574723
Short name T673
Test name
Test status
Simulation time 220994840 ps
CPU time 2.89 seconds
Started Jul 13 06:57:24 PM PDT 24
Finished Jul 13 06:57:29 PM PDT 24
Peak memory 208324 kb
Host smart-09c8e4f8-57e3-42b5-b7b7-8d44365f721b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132574723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.4132574723
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3611165862
Short name T188
Test name
Test status
Simulation time 506330270 ps
CPU time 18.6 seconds
Started Jul 13 06:57:26 PM PDT 24
Finished Jul 13 06:57:46 PM PDT 24
Peak memory 221240 kb
Host smart-bb471395-eda2-4c7d-be47-c335d6b52040
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611165862 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3611165862
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3785386048
Short name T895
Test name
Test status
Simulation time 1078501727 ps
CPU time 21.66 seconds
Started Jul 13 06:57:28 PM PDT 24
Finished Jul 13 06:57:52 PM PDT 24
Peak memory 207484 kb
Host smart-d0a0b89f-0b4a-4b2f-96f8-3c71a58ad8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785386048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3785386048
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.323426790
Short name T57
Test name
Test status
Simulation time 93006371 ps
CPU time 2.46 seconds
Started Jul 13 06:57:28 PM PDT 24
Finished Jul 13 06:57:33 PM PDT 24
Peak memory 210368 kb
Host smart-8f418957-928d-41d5-b169-d12a21f35fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323426790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.323426790
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.671482046
Short name T645
Test name
Test status
Simulation time 114296865 ps
CPU time 0.78 seconds
Started Jul 13 06:57:27 PM PDT 24
Finished Jul 13 06:57:30 PM PDT 24
Peak memory 206012 kb
Host smart-12eaaa89-a835-413c-9987-095ecd07f7d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671482046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.671482046
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3649221884
Short name T534
Test name
Test status
Simulation time 209366422 ps
CPU time 2.75 seconds
Started Jul 13 06:57:25 PM PDT 24
Finished Jul 13 06:57:30 PM PDT 24
Peak memory 210404 kb
Host smart-45ed3aec-3d39-443b-8d2b-90290705eb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649221884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3649221884
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.323113354
Short name T553
Test name
Test status
Simulation time 46153901 ps
CPU time 2.17 seconds
Started Jul 13 06:57:25 PM PDT 24
Finished Jul 13 06:57:29 PM PDT 24
Peak memory 208768 kb
Host smart-ee1afd49-c16b-40b2-9e03-07abc51baea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323113354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.323113354
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3124861772
Short name T95
Test name
Test status
Simulation time 651163230 ps
CPU time 6.55 seconds
Started Jul 13 06:57:25 PM PDT 24
Finished Jul 13 06:57:34 PM PDT 24
Peak memory 221328 kb
Host smart-31098362-7a05-434e-8c65-5412b4610d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124861772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3124861772
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3163776383
Short name T789
Test name
Test status
Simulation time 269107569 ps
CPU time 3.53 seconds
Started Jul 13 06:57:30 PM PDT 24
Finished Jul 13 06:57:35 PM PDT 24
Peak memory 222436 kb
Host smart-21ef8fac-57bb-4030-bbf4-2a889cba6794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163776383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3163776383
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3719993093
Short name T494
Test name
Test status
Simulation time 45242414 ps
CPU time 2.24 seconds
Started Jul 13 06:57:30 PM PDT 24
Finished Jul 13 06:57:34 PM PDT 24
Peak memory 214912 kb
Host smart-57dccb6c-d878-415d-94df-5072825653f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719993093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3719993093
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.900314571
Short name T612
Test name
Test status
Simulation time 1561070071 ps
CPU time 38.25 seconds
Started Jul 13 06:57:27 PM PDT 24
Finished Jul 13 06:58:07 PM PDT 24
Peak memory 214336 kb
Host smart-d7d8c6de-e3ce-47d3-a540-36aa196642ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900314571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.900314571
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.275044843
Short name T482
Test name
Test status
Simulation time 75935387 ps
CPU time 1.7 seconds
Started Jul 13 06:57:23 PM PDT 24
Finished Jul 13 06:57:28 PM PDT 24
Peak memory 206136 kb
Host smart-d803059b-733b-4c96-9fb6-3518b7221fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275044843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.275044843
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2367527879
Short name T537
Test name
Test status
Simulation time 63483853 ps
CPU time 2.95 seconds
Started Jul 13 06:57:25 PM PDT 24
Finished Jul 13 06:57:30 PM PDT 24
Peak memory 207108 kb
Host smart-12c29b27-06a0-420c-8645-2c6c0fa360de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367527879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2367527879
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3641620480
Short name T112
Test name
Test status
Simulation time 35400478 ps
CPU time 2.53 seconds
Started Jul 13 06:57:26 PM PDT 24
Finished Jul 13 06:57:30 PM PDT 24
Peak memory 208452 kb
Host smart-0c6d8a43-9a71-4153-9882-d97ce2afd49d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641620480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3641620480
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.415311254
Short name T544
Test name
Test status
Simulation time 72991649 ps
CPU time 3.3 seconds
Started Jul 13 06:57:27 PM PDT 24
Finished Jul 13 06:57:33 PM PDT 24
Peak memory 208116 kb
Host smart-8b09baf1-c805-4134-a757-5fff5542c23d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415311254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.415311254
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1221548356
Short name T303
Test name
Test status
Simulation time 861608617 ps
CPU time 4.62 seconds
Started Jul 13 06:57:27 PM PDT 24
Finished Jul 13 06:57:33 PM PDT 24
Peak memory 208824 kb
Host smart-ca50eeb1-1ce9-43b2-ad94-11b6d2808022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221548356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1221548356
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1313393569
Short name T610
Test name
Test status
Simulation time 81874085 ps
CPU time 3.12 seconds
Started Jul 13 06:57:30 PM PDT 24
Finished Jul 13 06:57:34 PM PDT 24
Peak memory 208500 kb
Host smart-eb5a1071-8d92-40f6-b123-733fd5053d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313393569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1313393569
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.347841410
Short name T713
Test name
Test status
Simulation time 104910007 ps
CPU time 5.1 seconds
Started Jul 13 06:57:30 PM PDT 24
Finished Jul 13 06:57:37 PM PDT 24
Peak memory 214440 kb
Host smart-fbecdaa8-4394-4c1d-be52-abc86863b6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347841410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.347841410
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2084715464
Short name T885
Test name
Test status
Simulation time 65923998 ps
CPU time 1.99 seconds
Started Jul 13 06:57:25 PM PDT 24
Finished Jul 13 06:57:29 PM PDT 24
Peak memory 210176 kb
Host smart-ec92cb8e-5ac0-46e9-befd-3e73e9f835a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084715464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2084715464
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.4136038230
Short name T526
Test name
Test status
Simulation time 36863855 ps
CPU time 0.74 seconds
Started Jul 13 06:55:46 PM PDT 24
Finished Jul 13 06:55:48 PM PDT 24
Peak memory 206004 kb
Host smart-e5193ed2-824c-423d-80e5-225aab3becbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136038230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.4136038230
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1884667447
Short name T903
Test name
Test status
Simulation time 158878980 ps
CPU time 5.97 seconds
Started Jul 13 06:55:47 PM PDT 24
Finished Jul 13 06:55:53 PM PDT 24
Peak memory 218412 kb
Host smart-4a3ab34a-1a35-4b86-9773-0a7175b43fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884667447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1884667447
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.317567809
Short name T411
Test name
Test status
Simulation time 1306516993 ps
CPU time 13.35 seconds
Started Jul 13 06:55:47 PM PDT 24
Finished Jul 13 06:56:01 PM PDT 24
Peak memory 208852 kb
Host smart-844116dc-2c3d-4b9f-a759-552ac09e1748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317567809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.317567809
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2783622246
Short name T313
Test name
Test status
Simulation time 141826182 ps
CPU time 4.27 seconds
Started Jul 13 06:55:45 PM PDT 24
Finished Jul 13 06:55:50 PM PDT 24
Peak memory 214276 kb
Host smart-0e8f6e63-292b-4cce-9d33-8f83fecde727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783622246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2783622246
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2440512793
Short name T568
Test name
Test status
Simulation time 416944552 ps
CPU time 5.35 seconds
Started Jul 13 06:55:46 PM PDT 24
Finished Jul 13 06:55:52 PM PDT 24
Peak memory 215520 kb
Host smart-7c39d693-d75e-45e6-bd4d-421c334e408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440512793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2440512793
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2940772645
Short name T762
Test name
Test status
Simulation time 180767795 ps
CPU time 4.24 seconds
Started Jul 13 06:55:45 PM PDT 24
Finished Jul 13 06:55:49 PM PDT 24
Peak memory 207492 kb
Host smart-7a7339de-18a0-4dee-a10a-b6a580f0f986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940772645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2940772645
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3257062437
Short name T14
Test name
Test status
Simulation time 440095281 ps
CPU time 9.96 seconds
Started Jul 13 06:55:47 PM PDT 24
Finished Jul 13 06:55:57 PM PDT 24
Peak memory 237868 kb
Host smart-f2634847-a200-46bc-b335-868b7827d86c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257062437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3257062437
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2744760520
Short name T628
Test name
Test status
Simulation time 80372479 ps
CPU time 1.89 seconds
Started Jul 13 06:55:49 PM PDT 24
Finished Jul 13 06:55:51 PM PDT 24
Peak memory 207008 kb
Host smart-ee068355-1d11-449b-b635-4925bde72e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744760520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2744760520
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.887760896
Short name T696
Test name
Test status
Simulation time 2633955628 ps
CPU time 9.47 seconds
Started Jul 13 06:55:48 PM PDT 24
Finished Jul 13 06:55:58 PM PDT 24
Peak memory 208540 kb
Host smart-5b9566d0-cf42-426a-a7c4-dbd5b5d1d9c8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887760896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.887760896
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.268111863
Short name T707
Test name
Test status
Simulation time 713254992 ps
CPU time 5.47 seconds
Started Jul 13 06:55:48 PM PDT 24
Finished Jul 13 06:55:54 PM PDT 24
Peak memory 208908 kb
Host smart-9034ab03-1065-4b6b-bfd1-ad86549abc94
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268111863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.268111863
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1026345354
Short name T327
Test name
Test status
Simulation time 184628478 ps
CPU time 4 seconds
Started Jul 13 06:55:48 PM PDT 24
Finished Jul 13 06:55:53 PM PDT 24
Peak memory 208896 kb
Host smart-938cbc30-f125-4a73-9a68-eb59a5ed6e40
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026345354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1026345354
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.4139024711
Short name T200
Test name
Test status
Simulation time 70735952 ps
CPU time 3.12 seconds
Started Jul 13 06:55:46 PM PDT 24
Finished Jul 13 06:55:49 PM PDT 24
Peak memory 210204 kb
Host smart-f524b7ec-00cc-4b87-aec0-a4e24ffaa6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139024711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.4139024711
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.677660134
Short name T843
Test name
Test status
Simulation time 85146917 ps
CPU time 3.25 seconds
Started Jul 13 06:55:47 PM PDT 24
Finished Jul 13 06:55:51 PM PDT 24
Peak memory 208564 kb
Host smart-16e95b38-323f-4874-9354-6ec78be7454b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677660134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.677660134
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1171020271
Short name T317
Test name
Test status
Simulation time 7155719161 ps
CPU time 40.61 seconds
Started Jul 13 06:55:47 PM PDT 24
Finished Jul 13 06:56:29 PM PDT 24
Peak memory 222264 kb
Host smart-0c109d47-47e7-43ac-b99a-42cba7e1b483
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171020271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1171020271
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3017114740
Short name T747
Test name
Test status
Simulation time 2272108381 ps
CPU time 6.3 seconds
Started Jul 13 06:55:45 PM PDT 24
Finished Jul 13 06:55:52 PM PDT 24
Peak memory 207304 kb
Host smart-ff233271-e66a-4441-8597-202f3a96fd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017114740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3017114740
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.882022545
Short name T824
Test name
Test status
Simulation time 336102185 ps
CPU time 3.63 seconds
Started Jul 13 06:55:46 PM PDT 24
Finished Jul 13 06:55:50 PM PDT 24
Peak memory 210692 kb
Host smart-b137ded8-1772-454d-8f1d-85c8fcb59d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882022545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.882022545
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3633838836
Short name T772
Test name
Test status
Simulation time 33591256 ps
CPU time 0.97 seconds
Started Jul 13 06:57:35 PM PDT 24
Finished Jul 13 06:57:38 PM PDT 24
Peak memory 206116 kb
Host smart-5d31cee7-cf44-4564-a557-6ab42c8edb69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633838836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3633838836
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2307891564
Short name T382
Test name
Test status
Simulation time 518081217 ps
CPU time 7.78 seconds
Started Jul 13 06:57:30 PM PDT 24
Finished Jul 13 06:57:39 PM PDT 24
Peak memory 222488 kb
Host smart-e43feacf-7e38-4def-bdf7-0fe4aeb79bb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2307891564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2307891564
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3928094458
Short name T656
Test name
Test status
Simulation time 135514918 ps
CPU time 3.39 seconds
Started Jul 13 06:57:31 PM PDT 24
Finished Jul 13 06:57:35 PM PDT 24
Peak memory 218264 kb
Host smart-a546eafd-bff2-41df-8634-09bf1426ceb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928094458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3928094458
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1791297234
Short name T93
Test name
Test status
Simulation time 83822444 ps
CPU time 3.26 seconds
Started Jul 13 06:57:27 PM PDT 24
Finished Jul 13 06:57:32 PM PDT 24
Peak memory 215276 kb
Host smart-b931ebaa-9c82-4656-9409-42cddead00b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791297234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1791297234
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2156243522
Short name T331
Test name
Test status
Simulation time 133405018 ps
CPU time 4.37 seconds
Started Jul 13 06:57:26 PM PDT 24
Finished Jul 13 06:57:32 PM PDT 24
Peak memory 222436 kb
Host smart-b5dba63a-b65f-4a3f-9af1-3a961c18209a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156243522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2156243522
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.663632627
Short name T220
Test name
Test status
Simulation time 197349564 ps
CPU time 4.67 seconds
Started Jul 13 06:57:27 PM PDT 24
Finished Jul 13 06:57:33 PM PDT 24
Peak memory 209984 kb
Host smart-01ed563f-a29a-4089-8756-7dcca838175f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663632627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.663632627
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.214311814
Short name T643
Test name
Test status
Simulation time 35766855 ps
CPU time 2.63 seconds
Started Jul 13 06:57:27 PM PDT 24
Finished Jul 13 06:57:32 PM PDT 24
Peak memory 214360 kb
Host smart-66bb2cae-5e3d-45f4-9654-eb95d68d4358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214311814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.214311814
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.910070084
Short name T549
Test name
Test status
Simulation time 361152688 ps
CPU time 4.79 seconds
Started Jul 13 06:57:25 PM PDT 24
Finished Jul 13 06:57:32 PM PDT 24
Peak memory 207944 kb
Host smart-7f1da146-315d-4ab4-b9a5-a76d96eaa904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910070084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.910070084
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3313888648
Short name T733
Test name
Test status
Simulation time 772181768 ps
CPU time 8.03 seconds
Started Jul 13 06:57:29 PM PDT 24
Finished Jul 13 06:57:39 PM PDT 24
Peak memory 208720 kb
Host smart-db692dd2-ae73-48f3-8f07-e5d93e645c13
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313888648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3313888648
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.420042842
Short name T190
Test name
Test status
Simulation time 75658777 ps
CPU time 3.61 seconds
Started Jul 13 06:57:31 PM PDT 24
Finished Jul 13 06:57:35 PM PDT 24
Peak memory 208680 kb
Host smart-16e89ecc-3662-4535-a757-c80a88d74385
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420042842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.420042842
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3862663434
Short name T703
Test name
Test status
Simulation time 181300861 ps
CPU time 5 seconds
Started Jul 13 06:57:25 PM PDT 24
Finished Jul 13 06:57:32 PM PDT 24
Peak memory 208708 kb
Host smart-4a2e9010-7914-433d-b706-ca72880239cf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862663434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3862663434
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.423449844
Short name T699
Test name
Test status
Simulation time 1245922598 ps
CPU time 8.48 seconds
Started Jul 13 06:57:27 PM PDT 24
Finished Jul 13 06:57:37 PM PDT 24
Peak memory 209580 kb
Host smart-d9a016fe-b52e-435d-99d1-63d1be34472a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423449844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.423449844
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1758902567
Short name T745
Test name
Test status
Simulation time 45246579 ps
CPU time 2.07 seconds
Started Jul 13 06:57:26 PM PDT 24
Finished Jul 13 06:57:30 PM PDT 24
Peak memory 206904 kb
Host smart-89404e89-6506-486b-94c6-6acda925cfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758902567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1758902567
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.149546218
Short name T581
Test name
Test status
Simulation time 65243559 ps
CPU time 4.26 seconds
Started Jul 13 06:57:27 PM PDT 24
Finished Jul 13 06:57:34 PM PDT 24
Peak memory 218492 kb
Host smart-bb503d5e-e4d0-4c3e-bb1e-61d09c5dbc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149546218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.149546218
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3980116740
Short name T590
Test name
Test status
Simulation time 57126379 ps
CPU time 2.88 seconds
Started Jul 13 06:57:26 PM PDT 24
Finished Jul 13 06:57:31 PM PDT 24
Peak memory 210180 kb
Host smart-c3e17a89-c39b-4bab-8312-a4dd618710fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980116740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3980116740
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.947646552
Short name T618
Test name
Test status
Simulation time 49312368 ps
CPU time 0.78 seconds
Started Jul 13 06:57:35 PM PDT 24
Finished Jul 13 06:57:38 PM PDT 24
Peak memory 205540 kb
Host smart-b4c58e3e-fca4-4e21-b90d-01a99912ff8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947646552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.947646552
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2229931472
Short name T302
Test name
Test status
Simulation time 164499403 ps
CPU time 5.55 seconds
Started Jul 13 06:57:37 PM PDT 24
Finished Jul 13 06:57:44 PM PDT 24
Peak memory 215476 kb
Host smart-69f62601-0b7e-4d33-9e31-20313748af82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2229931472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2229931472
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2121309782
Short name T566
Test name
Test status
Simulation time 172587313 ps
CPU time 3.2 seconds
Started Jul 13 06:57:34 PM PDT 24
Finished Jul 13 06:57:38 PM PDT 24
Peak memory 216984 kb
Host smart-defb8d7b-e69d-4923-93b8-54bdca7976cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121309782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2121309782
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2969846783
Short name T788
Test name
Test status
Simulation time 57713141 ps
CPU time 2.74 seconds
Started Jul 13 06:57:34 PM PDT 24
Finished Jul 13 06:57:38 PM PDT 24
Peak memory 207624 kb
Host smart-f12fbac6-a26e-4ab4-8456-79d2ce5387d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969846783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2969846783
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2757052211
Short name T853
Test name
Test status
Simulation time 133763153 ps
CPU time 2.35 seconds
Started Jul 13 06:57:35 PM PDT 24
Finished Jul 13 06:57:39 PM PDT 24
Peak memory 220896 kb
Host smart-96739cfd-407c-45a4-bccd-b68856944062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757052211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2757052211
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2566900245
Short name T909
Test name
Test status
Simulation time 202539530 ps
CPU time 4.78 seconds
Started Jul 13 06:57:33 PM PDT 24
Finished Jul 13 06:57:38 PM PDT 24
Peak memory 222604 kb
Host smart-cb0314c6-ce26-4bf2-a97e-62ec27837fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566900245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2566900245
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.383896212
Short name T579
Test name
Test status
Simulation time 153529760 ps
CPU time 4.92 seconds
Started Jul 13 06:57:35 PM PDT 24
Finished Jul 13 06:57:42 PM PDT 24
Peak memory 210300 kb
Host smart-272ed513-9ec9-46e2-ba05-2d3f5d351ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383896212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.383896212
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.583976389
Short name T685
Test name
Test status
Simulation time 60402509 ps
CPU time 3.09 seconds
Started Jul 13 06:57:34 PM PDT 24
Finished Jul 13 06:57:38 PM PDT 24
Peak memory 208708 kb
Host smart-01d004a8-4250-4ec3-acc4-3c97e794e0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583976389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.583976389
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.4040064609
Short name T294
Test name
Test status
Simulation time 19265902 ps
CPU time 1.78 seconds
Started Jul 13 06:57:38 PM PDT 24
Finished Jul 13 06:57:41 PM PDT 24
Peak memory 206940 kb
Host smart-87b82a88-0121-4946-80a9-c07e57a779d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040064609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.4040064609
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.57058659
Short name T441
Test name
Test status
Simulation time 249154672 ps
CPU time 6.13 seconds
Started Jul 13 06:57:34 PM PDT 24
Finished Jul 13 06:57:42 PM PDT 24
Peak memory 207064 kb
Host smart-f70e0af3-7c56-4b2a-8e29-ee089086a53c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57058659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.57058659
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3354048735
Short name T826
Test name
Test status
Simulation time 988143157 ps
CPU time 7.97 seconds
Started Jul 13 06:57:42 PM PDT 24
Finished Jul 13 06:57:51 PM PDT 24
Peak memory 208000 kb
Host smart-e821ae00-a9ad-413e-9585-8aaf336b9453
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354048735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3354048735
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1525974254
Short name T822
Test name
Test status
Simulation time 125609236 ps
CPU time 4.57 seconds
Started Jul 13 06:57:34 PM PDT 24
Finished Jul 13 06:57:39 PM PDT 24
Peak memory 214356 kb
Host smart-58a877c7-c278-4716-bdde-07d65c74c9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525974254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1525974254
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.72828699
Short name T586
Test name
Test status
Simulation time 259541532 ps
CPU time 3.3 seconds
Started Jul 13 06:57:35 PM PDT 24
Finished Jul 13 06:57:40 PM PDT 24
Peak memory 208232 kb
Host smart-98c06eb2-31ab-4b90-866e-d95b522c94ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72828699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.72828699
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2290581502
Short name T622
Test name
Test status
Simulation time 55641321 ps
CPU time 2.43 seconds
Started Jul 13 06:57:37 PM PDT 24
Finished Jul 13 06:57:41 PM PDT 24
Peak memory 214416 kb
Host smart-b801e337-15be-4dee-9ebb-479c104b635a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290581502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2290581502
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1538780645
Short name T328
Test name
Test status
Simulation time 1493364931 ps
CPU time 15.08 seconds
Started Jul 13 06:57:33 PM PDT 24
Finished Jul 13 06:57:49 PM PDT 24
Peak memory 220028 kb
Host smart-71ef2194-abfd-44a3-a11a-4cf073a89aa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538780645 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1538780645
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2060757022
Short name T295
Test name
Test status
Simulation time 467865401 ps
CPU time 5.94 seconds
Started Jul 13 06:57:42 PM PDT 24
Finished Jul 13 06:57:50 PM PDT 24
Peak memory 210220 kb
Host smart-754bc5e1-f73c-4fda-acee-7c7c87a9f1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060757022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2060757022
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.4028096999
Short name T563
Test name
Test status
Simulation time 79269925 ps
CPU time 2.73 seconds
Started Jul 13 06:57:35 PM PDT 24
Finished Jul 13 06:57:39 PM PDT 24
Peak memory 209984 kb
Host smart-f9cd2b32-df88-446c-9ba5-7aa291c0412d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028096999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.4028096999
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2618165213
Short name T443
Test name
Test status
Simulation time 31048716 ps
CPU time 0.92 seconds
Started Jul 13 06:57:40 PM PDT 24
Finished Jul 13 06:57:42 PM PDT 24
Peak memory 206112 kb
Host smart-c3dbd413-9363-4e7b-9574-bee31b4e6414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618165213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2618165213
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2316934938
Short name T400
Test name
Test status
Simulation time 255617258 ps
CPU time 4.12 seconds
Started Jul 13 06:57:35 PM PDT 24
Finished Jul 13 06:57:40 PM PDT 24
Peak memory 214328 kb
Host smart-3f194de1-7ec3-4197-8a7b-a9fd2a52f59f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2316934938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2316934938
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2918141427
Short name T22
Test name
Test status
Simulation time 366739322 ps
CPU time 3.95 seconds
Started Jul 13 06:57:42 PM PDT 24
Finished Jul 13 06:57:48 PM PDT 24
Peak memory 221180 kb
Host smart-69e4beca-ec07-4eed-8571-4a1d83974313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918141427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2918141427
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2899956664
Short name T52
Test name
Test status
Simulation time 37734251 ps
CPU time 1.87 seconds
Started Jul 13 06:57:35 PM PDT 24
Finished Jul 13 06:57:38 PM PDT 24
Peak memory 209032 kb
Host smart-009298df-15af-4fad-91b1-a8cf11167974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899956664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2899956664
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1288203146
Short name T477
Test name
Test status
Simulation time 142387257 ps
CPU time 4.15 seconds
Started Jul 13 06:57:36 PM PDT 24
Finished Jul 13 06:57:42 PM PDT 24
Peak memory 211520 kb
Host smart-bcf6329d-d1d4-42dc-9fe8-67fc261226af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288203146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1288203146
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3930877530
Short name T899
Test name
Test status
Simulation time 110287697 ps
CPU time 5.6 seconds
Started Jul 13 06:57:33 PM PDT 24
Finished Jul 13 06:57:40 PM PDT 24
Peak memory 219312 kb
Host smart-60c7cb2e-47be-41a4-a4ae-01f550cefbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930877530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3930877530
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3478458683
Short name T250
Test name
Test status
Simulation time 68972280 ps
CPU time 3.66 seconds
Started Jul 13 06:57:33 PM PDT 24
Finished Jul 13 06:57:38 PM PDT 24
Peak memory 208712 kb
Host smart-694ed27c-096f-49b4-88fc-dfc03fa104b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478458683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3478458683
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.931579102
Short name T574
Test name
Test status
Simulation time 591401201 ps
CPU time 3.45 seconds
Started Jul 13 06:57:36 PM PDT 24
Finished Jul 13 06:57:41 PM PDT 24
Peak memory 208468 kb
Host smart-6b888a34-0c6a-47ea-a969-95b4cce5c435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931579102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.931579102
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.7060014
Short name T80
Test name
Test status
Simulation time 504117714 ps
CPU time 4.36 seconds
Started Jul 13 06:57:36 PM PDT 24
Finished Jul 13 06:57:42 PM PDT 24
Peak memory 206804 kb
Host smart-47d2d0b2-d0b5-4ec6-8ae9-13915d3e0837
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7060014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.7060014
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2497457373
Short name T468
Test name
Test status
Simulation time 121427892 ps
CPU time 3.06 seconds
Started Jul 13 06:57:36 PM PDT 24
Finished Jul 13 06:57:40 PM PDT 24
Peak memory 206960 kb
Host smart-f56537a3-c4d4-4564-bb33-ce8fa09e34b8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497457373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2497457373
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3047519028
Short name T613
Test name
Test status
Simulation time 319153914 ps
CPU time 2.46 seconds
Started Jul 13 06:57:35 PM PDT 24
Finished Jul 13 06:57:39 PM PDT 24
Peak memory 208404 kb
Host smart-f3b0eb24-ef72-41f5-8797-2246de4fe692
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047519028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3047519028
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2490669147
Short name T614
Test name
Test status
Simulation time 82697323 ps
CPU time 1.88 seconds
Started Jul 13 06:57:35 PM PDT 24
Finished Jul 13 06:57:39 PM PDT 24
Peak memory 207692 kb
Host smart-a69a4e44-4f52-4233-a301-170d714b4bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490669147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2490669147
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.745373216
Short name T454
Test name
Test status
Simulation time 402562224 ps
CPU time 2.07 seconds
Started Jul 13 06:57:33 PM PDT 24
Finished Jul 13 06:57:35 PM PDT 24
Peak memory 208800 kb
Host smart-51d0e97e-0ac2-4566-8a24-5bf06e81cd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745373216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.745373216
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1907714470
Short name T465
Test name
Test status
Simulation time 367207694 ps
CPU time 3.39 seconds
Started Jul 13 06:57:42 PM PDT 24
Finished Jul 13 06:57:47 PM PDT 24
Peak memory 207884 kb
Host smart-43783be1-fc4e-45ee-bc3f-dc1184fa9f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907714470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1907714470
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3183646145
Short name T704
Test name
Test status
Simulation time 132494907 ps
CPU time 2.06 seconds
Started Jul 13 06:57:35 PM PDT 24
Finished Jul 13 06:57:39 PM PDT 24
Peak memory 210296 kb
Host smart-cb7eb27a-6390-4ade-b550-027b941e3c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183646145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3183646145
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2988593211
Short name T577
Test name
Test status
Simulation time 12935313 ps
CPU time 0.87 seconds
Started Jul 13 06:57:45 PM PDT 24
Finished Jul 13 06:57:47 PM PDT 24
Peak memory 206000 kb
Host smart-026a30aa-3f07-487c-b9a0-42a61b49f20f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988593211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2988593211
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2837726740
Short name T904
Test name
Test status
Simulation time 63171849 ps
CPU time 4.24 seconds
Started Jul 13 06:57:42 PM PDT 24
Finished Jul 13 06:57:47 PM PDT 24
Peak memory 222500 kb
Host smart-f8f94cc0-09b1-44de-8d1d-4c3a1e21e1df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2837726740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2837726740
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.90335743
Short name T4
Test name
Test status
Simulation time 214994538 ps
CPU time 4.61 seconds
Started Jul 13 06:57:41 PM PDT 24
Finished Jul 13 06:57:47 PM PDT 24
Peak memory 218532 kb
Host smart-7c594810-85f6-4c69-a436-464662486410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90335743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.90335743
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3353805370
Short name T359
Test name
Test status
Simulation time 25728410 ps
CPU time 1.75 seconds
Started Jul 13 06:57:42 PM PDT 24
Finished Jul 13 06:57:46 PM PDT 24
Peak memory 214328 kb
Host smart-20c7025a-0079-4888-b3ce-ab11cf96fbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353805370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3353805370
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1144005509
Short name T860
Test name
Test status
Simulation time 266026375 ps
CPU time 9.45 seconds
Started Jul 13 06:57:40 PM PDT 24
Finished Jul 13 06:57:50 PM PDT 24
Peak memory 222356 kb
Host smart-eecd77c6-cb5f-4b49-9ebb-3181598f529c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144005509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1144005509
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1633382995
Short name T562
Test name
Test status
Simulation time 58361321 ps
CPU time 2.12 seconds
Started Jul 13 06:57:41 PM PDT 24
Finished Jul 13 06:57:45 PM PDT 24
Peak memory 207940 kb
Host smart-39e04b52-ce03-4eec-800a-b50608d36ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633382995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1633382995
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3269046780
Short name T884
Test name
Test status
Simulation time 2011264479 ps
CPU time 5.65 seconds
Started Jul 13 06:57:53 PM PDT 24
Finished Jul 13 06:58:00 PM PDT 24
Peak memory 208120 kb
Host smart-1d5e7c61-94c2-4103-bf80-8d501498789a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269046780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3269046780
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2586484668
Short name T687
Test name
Test status
Simulation time 34400110 ps
CPU time 1.67 seconds
Started Jul 13 06:57:52 PM PDT 24
Finished Jul 13 06:57:54 PM PDT 24
Peak memory 206872 kb
Host smart-f3dd5ef1-a941-4077-8f59-17cd177a87bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586484668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2586484668
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.299363689
Short name T695
Test name
Test status
Simulation time 651921825 ps
CPU time 8.04 seconds
Started Jul 13 06:57:42 PM PDT 24
Finished Jul 13 06:57:51 PM PDT 24
Peak memory 208292 kb
Host smart-ff08f785-26fb-4a6a-b929-a4f4cd8d08fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299363689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.299363689
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3007819166
Short name T756
Test name
Test status
Simulation time 128335936 ps
CPU time 3.84 seconds
Started Jul 13 06:57:42 PM PDT 24
Finished Jul 13 06:57:47 PM PDT 24
Peak memory 206876 kb
Host smart-de294092-86e1-4986-8e29-7fe6f67724c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007819166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3007819166
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.4287316729
Short name T522
Test name
Test status
Simulation time 124423680 ps
CPU time 2.48 seconds
Started Jul 13 06:57:52 PM PDT 24
Finished Jul 13 06:57:55 PM PDT 24
Peak memory 207376 kb
Host smart-c5d66351-94ae-4fb4-a077-71a17cd79423
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287316729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.4287316729
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.4024445704
Short name T561
Test name
Test status
Simulation time 1001451132 ps
CPU time 6.02 seconds
Started Jul 13 06:57:44 PM PDT 24
Finished Jul 13 06:57:51 PM PDT 24
Peak memory 208068 kb
Host smart-9a1e01d7-ed9f-4792-8da6-39435683c954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024445704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.4024445704
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1215490000
Short name T773
Test name
Test status
Simulation time 153408305 ps
CPU time 4.23 seconds
Started Jul 13 06:57:43 PM PDT 24
Finished Jul 13 06:57:49 PM PDT 24
Peak memory 206828 kb
Host smart-e31df093-237f-4605-bcae-ab596569f21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215490000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1215490000
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2992537729
Short name T908
Test name
Test status
Simulation time 955348566 ps
CPU time 17.45 seconds
Started Jul 13 06:57:42 PM PDT 24
Finished Jul 13 06:58:01 PM PDT 24
Peak memory 214408 kb
Host smart-6b7971c1-177e-47d3-9363-1cd9ac2bdce5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992537729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2992537729
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2929511570
Short name T127
Test name
Test status
Simulation time 671938843 ps
CPU time 9.28 seconds
Started Jul 13 06:57:54 PM PDT 24
Finished Jul 13 06:58:05 PM PDT 24
Peak memory 222580 kb
Host smart-3a8ca63d-c0f8-49e6-b1c3-c8a9690d688d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929511570 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2929511570
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3152716414
Short name T715
Test name
Test status
Simulation time 688999733 ps
CPU time 7.08 seconds
Started Jul 13 06:57:54 PM PDT 24
Finished Jul 13 06:58:02 PM PDT 24
Peak memory 214380 kb
Host smart-196b56aa-7661-4c09-abd7-dba865c3fec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152716414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3152716414
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.952071998
Short name T535
Test name
Test status
Simulation time 946895589 ps
CPU time 6.95 seconds
Started Jul 13 06:57:41 PM PDT 24
Finished Jul 13 06:57:50 PM PDT 24
Peak memory 210776 kb
Host smart-d4671092-6d13-4d8c-82bb-7aadfa750999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952071998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.952071998
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.749697090
Short name T463
Test name
Test status
Simulation time 15657968 ps
CPU time 0.94 seconds
Started Jul 13 06:57:43 PM PDT 24
Finished Jul 13 06:57:45 PM PDT 24
Peak memory 206136 kb
Host smart-1ce9a656-2554-488c-aac8-2ae530e6ceaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749697090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.749697090
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3672572785
Short name T343
Test name
Test status
Simulation time 76604330 ps
CPU time 3.14 seconds
Started Jul 13 06:57:39 PM PDT 24
Finished Jul 13 06:57:43 PM PDT 24
Peak memory 215164 kb
Host smart-8e7fc315-be57-45b2-87bf-d271ebe42a0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672572785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3672572785
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2926059550
Short name T786
Test name
Test status
Simulation time 2229200925 ps
CPU time 11.27 seconds
Started Jul 13 06:57:54 PM PDT 24
Finished Jul 13 06:58:07 PM PDT 24
Peak memory 218456 kb
Host smart-143dc5ed-9ae6-48ef-9963-fc05dda88b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926059550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2926059550
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.589957333
Short name T64
Test name
Test status
Simulation time 399881338 ps
CPU time 4.97 seconds
Started Jul 13 06:57:54 PM PDT 24
Finished Jul 13 06:58:01 PM PDT 24
Peak memory 210356 kb
Host smart-878dab97-c46b-45dc-b162-8cc70cd9c2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589957333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.589957333
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2295675208
Short name T810
Test name
Test status
Simulation time 64381676 ps
CPU time 3.65 seconds
Started Jul 13 06:57:41 PM PDT 24
Finished Jul 13 06:57:46 PM PDT 24
Peak memory 214324 kb
Host smart-46238e06-c136-4f25-a19a-9a4fa22414a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295675208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2295675208
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2832742867
Short name T333
Test name
Test status
Simulation time 196318941 ps
CPU time 2.35 seconds
Started Jul 13 06:57:52 PM PDT 24
Finished Jul 13 06:57:55 PM PDT 24
Peak memory 214288 kb
Host smart-664bc5fd-988d-4fe3-82be-0c01efb132a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832742867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2832742867
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2375786875
Short name T744
Test name
Test status
Simulation time 54569262 ps
CPU time 2.04 seconds
Started Jul 13 06:57:43 PM PDT 24
Finished Jul 13 06:57:46 PM PDT 24
Peak memory 215140 kb
Host smart-4e633ebc-d3ea-45f5-a542-a482f9c42c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375786875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2375786875
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.14987941
Short name T505
Test name
Test status
Simulation time 746634108 ps
CPU time 5.56 seconds
Started Jul 13 06:57:41 PM PDT 24
Finished Jul 13 06:57:48 PM PDT 24
Peak memory 209040 kb
Host smart-302bc43b-4734-4844-a3b9-c2fd405cbbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14987941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.14987941
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2138028549
Short name T589
Test name
Test status
Simulation time 35312095 ps
CPU time 2.28 seconds
Started Jul 13 06:57:40 PM PDT 24
Finished Jul 13 06:57:42 PM PDT 24
Peak memory 206892 kb
Host smart-ff4f0b60-4f11-414a-a506-a2c4863bcc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138028549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2138028549
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.497251700
Short name T637
Test name
Test status
Simulation time 535577537 ps
CPU time 4.3 seconds
Started Jul 13 06:57:43 PM PDT 24
Finished Jul 13 06:57:49 PM PDT 24
Peak memory 208816 kb
Host smart-87a33370-8a87-47c7-8892-3b126c04691d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497251700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.497251700
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.4144313696
Short name T800
Test name
Test status
Simulation time 2254671880 ps
CPU time 14.16 seconds
Started Jul 13 06:57:52 PM PDT 24
Finished Jul 13 06:58:07 PM PDT 24
Peak memory 208960 kb
Host smart-17208767-1767-416b-b296-ef77f57a038a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144313696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4144313696
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3619594111
Short name T440
Test name
Test status
Simulation time 162420938 ps
CPU time 3.35 seconds
Started Jul 13 06:57:42 PM PDT 24
Finished Jul 13 06:57:47 PM PDT 24
Peak memory 207068 kb
Host smart-7a11ec68-db37-4835-bf2d-a3eafb4607f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619594111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3619594111
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1976461724
Short name T214
Test name
Test status
Simulation time 162985675 ps
CPU time 4.08 seconds
Started Jul 13 06:57:52 PM PDT 24
Finished Jul 13 06:57:57 PM PDT 24
Peak memory 209600 kb
Host smart-96a13598-4009-42e0-9d19-7687ef2228b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976461724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1976461724
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.408169309
Short name T648
Test name
Test status
Simulation time 455500436 ps
CPU time 3.71 seconds
Started Jul 13 06:57:46 PM PDT 24
Finished Jul 13 06:57:51 PM PDT 24
Peak memory 208640 kb
Host smart-03bae150-cf2f-4e36-b632-f4d2f447222c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408169309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.408169309
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2505267611
Short name T290
Test name
Test status
Simulation time 285524283 ps
CPU time 4.45 seconds
Started Jul 13 06:57:42 PM PDT 24
Finished Jul 13 06:57:48 PM PDT 24
Peak memory 208892 kb
Host smart-883b2ae9-0f47-4fbc-9cbc-90c03e1ddec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505267611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2505267611
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2677191474
Short name T813
Test name
Test status
Simulation time 156046206 ps
CPU time 5.34 seconds
Started Jul 13 06:57:54 PM PDT 24
Finished Jul 13 06:58:00 PM PDT 24
Peak memory 214352 kb
Host smart-07c98887-0ffd-4bd9-a00b-0a0800ad8a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677191474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2677191474
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1850861158
Short name T35
Test name
Test status
Simulation time 54590868 ps
CPU time 2.16 seconds
Started Jul 13 06:57:41 PM PDT 24
Finished Jul 13 06:57:44 PM PDT 24
Peak memory 209968 kb
Host smart-47be3ea4-2d89-47c1-93de-c048bae2e606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850861158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1850861158
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3309897675
Short name T104
Test name
Test status
Simulation time 42178189 ps
CPU time 0.83 seconds
Started Jul 13 06:57:50 PM PDT 24
Finished Jul 13 06:57:51 PM PDT 24
Peak memory 205948 kb
Host smart-2e7fb310-de2b-48c3-ba59-729e74f3c1b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309897675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3309897675
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2477381546
Short name T420
Test name
Test status
Simulation time 90322610 ps
CPU time 4.99 seconds
Started Jul 13 06:57:42 PM PDT 24
Finished Jul 13 06:57:49 PM PDT 24
Peak memory 214328 kb
Host smart-0c008c1b-c367-4141-b2c3-72dd931d57a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2477381546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2477381546
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2571231556
Short name T62
Test name
Test status
Simulation time 253651364 ps
CPU time 5.82 seconds
Started Jul 13 06:57:53 PM PDT 24
Finished Jul 13 06:58:00 PM PDT 24
Peak memory 208824 kb
Host smart-97cf13b0-ba91-4bc5-9860-7d3415684035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571231556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2571231556
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2943663107
Short name T636
Test name
Test status
Simulation time 579039068 ps
CPU time 18.74 seconds
Started Jul 13 06:57:43 PM PDT 24
Finished Jul 13 06:58:03 PM PDT 24
Peak memory 209656 kb
Host smart-44046e44-7ede-4e41-b843-98b858f83303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943663107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2943663107
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.556667218
Short name T866
Test name
Test status
Simulation time 579278995 ps
CPU time 4.79 seconds
Started Jul 13 06:57:53 PM PDT 24
Finished Jul 13 06:57:59 PM PDT 24
Peak memory 214340 kb
Host smart-c63b47ae-948f-484e-b57c-18d7edd686fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556667218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.556667218
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.4072776027
Short name T259
Test name
Test status
Simulation time 128104099 ps
CPU time 3.25 seconds
Started Jul 13 06:57:52 PM PDT 24
Finished Jul 13 06:57:57 PM PDT 24
Peak memory 220512 kb
Host smart-ce685430-0f97-4e87-b264-2a1022b753a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072776027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.4072776027
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1289267549
Short name T520
Test name
Test status
Simulation time 129878181 ps
CPU time 3.08 seconds
Started Jul 13 06:57:41 PM PDT 24
Finished Jul 13 06:57:46 PM PDT 24
Peak memory 210416 kb
Host smart-a467a20c-798c-4093-bd13-d0911c6cc7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289267549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1289267549
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.4064177821
Short name T662
Test name
Test status
Simulation time 212815774 ps
CPU time 4.9 seconds
Started Jul 13 06:57:43 PM PDT 24
Finished Jul 13 06:57:49 PM PDT 24
Peak memory 209076 kb
Host smart-18a43a8f-458b-48fe-92f1-7fbdd2072c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064177821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.4064177821
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3940436040
Short name T599
Test name
Test status
Simulation time 25831101 ps
CPU time 1.99 seconds
Started Jul 13 06:57:44 PM PDT 24
Finished Jul 13 06:57:47 PM PDT 24
Peak memory 207264 kb
Host smart-0f6ff248-02ab-4365-851e-f58bbdbd3572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940436040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3940436040
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2760050437
Short name T728
Test name
Test status
Simulation time 396968175 ps
CPU time 5.62 seconds
Started Jul 13 06:57:54 PM PDT 24
Finished Jul 13 06:58:01 PM PDT 24
Peak memory 208180 kb
Host smart-926b99cf-5486-4564-9faf-d5dc11128e5e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760050437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2760050437
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.959850981
Short name T617
Test name
Test status
Simulation time 62498695 ps
CPU time 3.12 seconds
Started Jul 13 06:57:42 PM PDT 24
Finished Jul 13 06:57:47 PM PDT 24
Peak memory 208588 kb
Host smart-c2ecdb31-64bf-4aea-8f06-aed610e1c208
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959850981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.959850981
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3405126965
Short name T434
Test name
Test status
Simulation time 37603108 ps
CPU time 2.34 seconds
Started Jul 13 06:57:41 PM PDT 24
Finished Jul 13 06:57:44 PM PDT 24
Peak memory 208284 kb
Host smart-9f8aa73d-04dc-4807-93c7-a57225a3b5f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405126965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3405126965
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.4051929588
Short name T550
Test name
Test status
Simulation time 555529714 ps
CPU time 2.7 seconds
Started Jul 13 06:57:52 PM PDT 24
Finished Jul 13 06:57:56 PM PDT 24
Peak memory 215852 kb
Host smart-3270fac4-3d08-4d55-bbc6-b769aecac09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051929588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.4051929588
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.710839091
Short name T701
Test name
Test status
Simulation time 188142701 ps
CPU time 2.52 seconds
Started Jul 13 06:57:43 PM PDT 24
Finished Jul 13 06:57:47 PM PDT 24
Peak memory 206832 kb
Host smart-08d3d378-34cd-4d60-a029-fc76c4ad7651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710839091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.710839091
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3330985772
Short name T247
Test name
Test status
Simulation time 1508370329 ps
CPU time 15.3 seconds
Started Jul 13 06:57:52 PM PDT 24
Finished Jul 13 06:58:08 PM PDT 24
Peak memory 215452 kb
Host smart-940b154f-ebae-4093-8c12-b261fa7d3673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330985772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3330985772
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2260482064
Short name T213
Test name
Test status
Simulation time 73792310 ps
CPU time 3.54 seconds
Started Jul 13 06:57:41 PM PDT 24
Finished Jul 13 06:57:47 PM PDT 24
Peak memory 209420 kb
Host smart-f86e9caa-1ce0-4b90-a6ea-3c0bebc0fe0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260482064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2260482064
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1003812182
Short name T591
Test name
Test status
Simulation time 41008581 ps
CPU time 1.68 seconds
Started Jul 13 06:57:50 PM PDT 24
Finished Jul 13 06:57:53 PM PDT 24
Peak memory 214312 kb
Host smart-13220e6f-276e-4e7f-b928-b8b737bf4219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003812182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1003812182
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3702186015
Short name T739
Test name
Test status
Simulation time 51526795 ps
CPU time 0.75 seconds
Started Jul 13 06:57:51 PM PDT 24
Finished Jul 13 06:57:52 PM PDT 24
Peak memory 206000 kb
Host smart-4cfe1444-3a45-4c3f-8cf2-bb006a835d58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702186015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3702186015
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2403341377
Short name T423
Test name
Test status
Simulation time 562750194 ps
CPU time 7.26 seconds
Started Jul 13 06:57:50 PM PDT 24
Finished Jul 13 06:57:58 PM PDT 24
Peak memory 215068 kb
Host smart-a729d1b2-1084-490b-9163-2f480e7a359f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2403341377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2403341377
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1372838879
Short name T564
Test name
Test status
Simulation time 1414057506 ps
CPU time 5.42 seconds
Started Jul 13 06:57:50 PM PDT 24
Finished Jul 13 06:57:56 PM PDT 24
Peak memory 217756 kb
Host smart-1c438235-7fb4-4433-bf1c-0b5a5cf10043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372838879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1372838879
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.141335710
Short name T667
Test name
Test status
Simulation time 622807110 ps
CPU time 7.13 seconds
Started Jul 13 06:57:53 PM PDT 24
Finished Jul 13 06:58:01 PM PDT 24
Peak memory 214416 kb
Host smart-3e869459-9ac6-4dae-ac36-ca75332707b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141335710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.141335710
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3771581203
Short name T790
Test name
Test status
Simulation time 244823779 ps
CPU time 4.89 seconds
Started Jul 13 06:57:54 PM PDT 24
Finished Jul 13 06:58:00 PM PDT 24
Peak memory 214340 kb
Host smart-1d0fce87-0621-4c98-9d31-ec788b77f8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771581203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3771581203
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3229287660
Short name T681
Test name
Test status
Simulation time 93001984 ps
CPU time 2.16 seconds
Started Jul 13 06:57:53 PM PDT 24
Finished Jul 13 06:57:56 PM PDT 24
Peak memory 214264 kb
Host smart-90b2718c-470f-4ceb-99a5-ecb1557c56a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229287660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3229287660
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1602521994
Short name T230
Test name
Test status
Simulation time 594357358 ps
CPU time 4.67 seconds
Started Jul 13 06:57:58 PM PDT 24
Finished Jul 13 06:58:04 PM PDT 24
Peak memory 210048 kb
Host smart-6f69d2f1-8f8e-4992-b334-ba15f8fdde51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602521994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1602521994
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3235906526
Short name T316
Test name
Test status
Simulation time 84811551 ps
CPU time 3.56 seconds
Started Jul 13 06:57:53 PM PDT 24
Finished Jul 13 06:57:58 PM PDT 24
Peak memory 207616 kb
Host smart-43b9d376-995f-4f27-a867-2f8065199b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235906526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3235906526
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.4142679958
Short name T837
Test name
Test status
Simulation time 41370976 ps
CPU time 2.65 seconds
Started Jul 13 06:57:52 PM PDT 24
Finished Jul 13 06:57:56 PM PDT 24
Peak memory 208832 kb
Host smart-978cdb6b-afe2-4aec-b1cb-bc1c9c762fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142679958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.4142679958
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3766515690
Short name T792
Test name
Test status
Simulation time 119448409 ps
CPU time 3.62 seconds
Started Jul 13 06:57:49 PM PDT 24
Finished Jul 13 06:57:53 PM PDT 24
Peak memory 208776 kb
Host smart-7cccb6f7-c1f7-4996-a040-5cc07dd0ddfc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766515690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3766515690
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3799969504
Short name T595
Test name
Test status
Simulation time 105928476 ps
CPU time 3.06 seconds
Started Jul 13 06:57:49 PM PDT 24
Finished Jul 13 06:57:53 PM PDT 24
Peak memory 206824 kb
Host smart-0f3977b1-0613-45c1-ad9f-49540512769a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799969504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3799969504
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2209441843
Short name T451
Test name
Test status
Simulation time 711619065 ps
CPU time 4.12 seconds
Started Jul 13 06:57:49 PM PDT 24
Finished Jul 13 06:57:54 PM PDT 24
Peak memory 206780 kb
Host smart-ef5b9a32-6e7d-4825-ae6d-0aacd286d778
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209441843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2209441843
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3375778043
Short name T602
Test name
Test status
Simulation time 228466907 ps
CPU time 2.68 seconds
Started Jul 13 06:57:53 PM PDT 24
Finished Jul 13 06:57:58 PM PDT 24
Peak memory 215168 kb
Host smart-9594dfa6-fea3-4c56-8ee3-c7a94d610e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375778043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3375778043
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3758832566
Short name T202
Test name
Test status
Simulation time 1800146773 ps
CPU time 29.88 seconds
Started Jul 13 06:57:49 PM PDT 24
Finished Jul 13 06:58:20 PM PDT 24
Peak memory 208300 kb
Host smart-d15abe91-d050-48d1-8767-ed7a75427f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758832566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3758832566
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.424317077
Short name T325
Test name
Test status
Simulation time 291346859 ps
CPU time 6.27 seconds
Started Jul 13 06:57:51 PM PDT 24
Finished Jul 13 06:57:58 PM PDT 24
Peak memory 209540 kb
Host smart-1e396045-0bd8-40fe-a1b5-112d0d8c8963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424317077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.424317077
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1171864417
Short name T631
Test name
Test status
Simulation time 1656301354 ps
CPU time 13.35 seconds
Started Jul 13 06:57:51 PM PDT 24
Finished Jul 13 06:58:05 PM PDT 24
Peak memory 210500 kb
Host smart-9f589a02-99c9-4419-a574-54322be965e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171864417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1171864417
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2143247708
Short name T642
Test name
Test status
Simulation time 10563007 ps
CPU time 0.73 seconds
Started Jul 13 06:57:53 PM PDT 24
Finished Jul 13 06:57:55 PM PDT 24
Peak memory 205356 kb
Host smart-2b591f0e-7119-45b6-92ac-2816eccf40e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143247708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2143247708
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3994401550
Short name T825
Test name
Test status
Simulation time 589808771 ps
CPU time 8.07 seconds
Started Jul 13 06:57:58 PM PDT 24
Finished Jul 13 06:58:07 PM PDT 24
Peak memory 214324 kb
Host smart-c390165b-e20f-4f3c-9fda-5afcf9347f5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3994401550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3994401550
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2945122667
Short name T224
Test name
Test status
Simulation time 127347687 ps
CPU time 5.8 seconds
Started Jul 13 06:57:51 PM PDT 24
Finished Jul 13 06:57:57 PM PDT 24
Peak memory 210848 kb
Host smart-0cb33cd0-d87a-4eda-a63a-a916e7c5b754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945122667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2945122667
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1747992506
Short name T777
Test name
Test status
Simulation time 32982118 ps
CPU time 1.94 seconds
Started Jul 13 06:57:53 PM PDT 24
Finished Jul 13 06:57:56 PM PDT 24
Peak memory 206864 kb
Host smart-5b35444f-c543-44ec-a14a-4c4ceba1cb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747992506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1747992506
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.915465497
Short name T509
Test name
Test status
Simulation time 547728474 ps
CPU time 4.08 seconds
Started Jul 13 06:57:52 PM PDT 24
Finished Jul 13 06:57:58 PM PDT 24
Peak memory 214768 kb
Host smart-42964f89-fc44-47c2-850e-1d7e2a03a9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915465497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.915465497
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1842415248
Short name T373
Test name
Test status
Simulation time 58936683 ps
CPU time 3.19 seconds
Started Jul 13 06:57:50 PM PDT 24
Finished Jul 13 06:57:54 PM PDT 24
Peak memory 222452 kb
Host smart-48583952-e209-44d0-902a-2e6a8bb5a134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842415248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1842415248
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3381323963
Short name T592
Test name
Test status
Simulation time 239822117 ps
CPU time 2.54 seconds
Started Jul 13 06:57:52 PM PDT 24
Finished Jul 13 06:57:56 PM PDT 24
Peak memory 220328 kb
Host smart-98c55a20-d14b-40bd-9225-f7e67f99e0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381323963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3381323963
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3805746593
Short name T484
Test name
Test status
Simulation time 835055050 ps
CPU time 5.34 seconds
Started Jul 13 06:57:51 PM PDT 24
Finished Jul 13 06:57:57 PM PDT 24
Peak memory 218312 kb
Host smart-d0cbcb8c-d59e-4b15-9bb2-21a827ca937c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805746593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3805746593
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1258035573
Short name T326
Test name
Test status
Simulation time 247105782 ps
CPU time 2.58 seconds
Started Jul 13 06:57:49 PM PDT 24
Finished Jul 13 06:57:52 PM PDT 24
Peak memory 208532 kb
Host smart-71179b93-dd79-4bc0-81f4-f66716e17766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258035573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1258035573
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.4087872511
Short name T627
Test name
Test status
Simulation time 890556685 ps
CPU time 29.15 seconds
Started Jul 13 06:57:54 PM PDT 24
Finished Jul 13 06:58:24 PM PDT 24
Peak memory 208556 kb
Host smart-5c2178f3-ce9d-4464-9b7a-653d2c8273d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087872511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.4087872511
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3793929543
Short name T270
Test name
Test status
Simulation time 6179474325 ps
CPU time 43.15 seconds
Started Jul 13 06:57:51 PM PDT 24
Finished Jul 13 06:58:35 PM PDT 24
Peak memory 209284 kb
Host smart-d1a25613-c019-4797-beef-688e0da93b6d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793929543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3793929543
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1822744421
Short name T529
Test name
Test status
Simulation time 380198786 ps
CPU time 3.51 seconds
Started Jul 13 06:57:54 PM PDT 24
Finished Jul 13 06:57:59 PM PDT 24
Peak memory 206892 kb
Host smart-c9969369-1458-4b1f-a24a-8d6c6a74509a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822744421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1822744421
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1218177135
Short name T746
Test name
Test status
Simulation time 210430863 ps
CPU time 3.17 seconds
Started Jul 13 06:58:04 PM PDT 24
Finished Jul 13 06:58:08 PM PDT 24
Peak memory 215668 kb
Host smart-e3cb8201-34d4-498a-8948-3c120b3eeabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218177135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1218177135
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1871665570
Short name T433
Test name
Test status
Simulation time 53076685 ps
CPU time 2.56 seconds
Started Jul 13 06:57:51 PM PDT 24
Finished Jul 13 06:57:55 PM PDT 24
Peak memory 208192 kb
Host smart-e8c77618-9669-4f25-9963-beef1600a90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871665570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1871665570
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1568219778
Short name T748
Test name
Test status
Simulation time 854192305 ps
CPU time 15.82 seconds
Started Jul 13 06:57:59 PM PDT 24
Finished Jul 13 06:58:15 PM PDT 24
Peak memory 221452 kb
Host smart-e8b23243-fff3-4765-a7fe-9db85528cbba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568219778 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1568219778
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.639038952
Short name T293
Test name
Test status
Simulation time 438044011 ps
CPU time 6.33 seconds
Started Jul 13 06:57:48 PM PDT 24
Finished Jul 13 06:57:55 PM PDT 24
Peak memory 209312 kb
Host smart-094f6907-18c3-487a-a6d6-91c71dea6eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639038952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.639038952
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.858422174
Short name T771
Test name
Test status
Simulation time 19270886 ps
CPU time 0.89 seconds
Started Jul 13 06:58:08 PM PDT 24
Finished Jul 13 06:58:12 PM PDT 24
Peak memory 205996 kb
Host smart-775085e8-0c02-47f5-beeb-96a0f81f2ef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858422174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.858422174
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1641175286
Short name T876
Test name
Test status
Simulation time 390324917 ps
CPU time 4.19 seconds
Started Jul 13 06:58:08 PM PDT 24
Finished Jul 13 06:58:15 PM PDT 24
Peak memory 215600 kb
Host smart-fbd7fe4c-0c05-4405-be5f-1772f3b2dade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641175286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1641175286
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1761080213
Short name T543
Test name
Test status
Simulation time 311461556 ps
CPU time 4.17 seconds
Started Jul 13 06:58:06 PM PDT 24
Finished Jul 13 06:58:10 PM PDT 24
Peak memory 208024 kb
Host smart-3209275b-1b6b-44ae-a3de-b93e266b5f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761080213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1761080213
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.907116680
Short name T527
Test name
Test status
Simulation time 71886800 ps
CPU time 3.69 seconds
Started Jul 13 06:58:08 PM PDT 24
Finished Jul 13 06:58:15 PM PDT 24
Peak memory 214328 kb
Host smart-895640c5-d729-4d4d-b110-f0097a2678e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907116680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.907116680
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.128117623
Short name T47
Test name
Test status
Simulation time 189245640 ps
CPU time 2.08 seconds
Started Jul 13 06:58:08 PM PDT 24
Finished Jul 13 06:58:12 PM PDT 24
Peak memory 214396 kb
Host smart-9f885e33-f7b7-42c6-a0a2-2c8c4bc91002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128117623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.128117623
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.389619339
Short name T720
Test name
Test status
Simulation time 95226910 ps
CPU time 4.63 seconds
Started Jul 13 06:58:07 PM PDT 24
Finished Jul 13 06:58:12 PM PDT 24
Peak memory 220332 kb
Host smart-ea21ec1a-95db-411b-bb2d-27aa0dfb9749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389619339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.389619339
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1696384
Short name T882
Test name
Test status
Simulation time 3457961652 ps
CPU time 26.61 seconds
Started Jul 13 06:58:07 PM PDT 24
Finished Jul 13 06:58:35 PM PDT 24
Peak memory 214096 kb
Host smart-6e54ba15-57fc-489e-a611-2a836a147cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1696384
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3092940445
Short name T253
Test name
Test status
Simulation time 293779375 ps
CPU time 4.69 seconds
Started Jul 13 06:57:59 PM PDT 24
Finished Jul 13 06:58:04 PM PDT 24
Peak memory 208016 kb
Host smart-c8381068-6e33-414e-91e1-137186f29aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092940445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3092940445
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.4077699548
Short name T674
Test name
Test status
Simulation time 2629108729 ps
CPU time 20.05 seconds
Started Jul 13 06:58:07 PM PDT 24
Finished Jul 13 06:58:29 PM PDT 24
Peak memory 208772 kb
Host smart-8e488173-dbc0-45e4-86b8-5a09012fa87a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077699548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.4077699548
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2759229316
Short name T3
Test name
Test status
Simulation time 168864074 ps
CPU time 4.06 seconds
Started Jul 13 06:57:54 PM PDT 24
Finished Jul 13 06:58:00 PM PDT 24
Peak memory 209176 kb
Host smart-6b7b295b-1058-40e8-aa2c-ef80e80a6b3a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759229316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2759229316
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.172103069
Short name T768
Test name
Test status
Simulation time 310662858 ps
CPU time 4.44 seconds
Started Jul 13 06:58:10 PM PDT 24
Finished Jul 13 06:58:19 PM PDT 24
Peak memory 209004 kb
Host smart-864bde62-8140-4d9c-ba97-aea17b627724
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172103069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.172103069
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1592279800
Short name T879
Test name
Test status
Simulation time 126576160 ps
CPU time 3.66 seconds
Started Jul 13 06:58:08 PM PDT 24
Finished Jul 13 06:58:15 PM PDT 24
Peak memory 218248 kb
Host smart-83c0a1cd-7198-4c99-98ca-176a409dc934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592279800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1592279800
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.87175522
Short name T197
Test name
Test status
Simulation time 336504063 ps
CPU time 4.43 seconds
Started Jul 13 06:57:53 PM PDT 24
Finished Jul 13 06:57:58 PM PDT 24
Peak memory 208692 kb
Host smart-8a93c275-393d-4f9c-a61a-14cb91150d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87175522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.87175522
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.2685069274
Short name T70
Test name
Test status
Simulation time 288701518 ps
CPU time 10.34 seconds
Started Jul 13 06:58:08 PM PDT 24
Finished Jul 13 06:58:22 PM PDT 24
Peak memory 222588 kb
Host smart-346cdca0-541c-4907-b9c6-790e51b12be3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685069274 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.2685069274
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1600186667
Short name T421
Test name
Test status
Simulation time 73018620 ps
CPU time 3.04 seconds
Started Jul 13 06:58:06 PM PDT 24
Finished Jul 13 06:58:10 PM PDT 24
Peak memory 209648 kb
Host smart-46bc6e6e-49b4-4b5d-a790-15c31965d9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600186667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1600186667
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1650170193
Short name T807
Test name
Test status
Simulation time 22308919 ps
CPU time 0.87 seconds
Started Jul 13 06:58:05 PM PDT 24
Finished Jul 13 06:58:06 PM PDT 24
Peak memory 205992 kb
Host smart-64c19559-c5f1-4075-8603-d0a7119e9a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650170193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1650170193
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2260794440
Short name T397
Test name
Test status
Simulation time 50228917 ps
CPU time 3.53 seconds
Started Jul 13 06:58:06 PM PDT 24
Finished Jul 13 06:58:10 PM PDT 24
Peak memory 214336 kb
Host smart-b16907e1-f7e2-4a5e-b023-1e2929ef2f1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2260794440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2260794440
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1208386591
Short name T757
Test name
Test status
Simulation time 913273510 ps
CPU time 13.39 seconds
Started Jul 13 06:58:07 PM PDT 24
Finished Jul 13 06:58:21 PM PDT 24
Peak memory 214724 kb
Host smart-eec6bddb-363d-4894-a7b3-9d6825718378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208386591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1208386591
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.345950281
Short name T461
Test name
Test status
Simulation time 84357629 ps
CPU time 2.67 seconds
Started Jul 13 06:58:08 PM PDT 24
Finished Jul 13 06:58:12 PM PDT 24
Peak memory 218240 kb
Host smart-3fe37229-6d14-4e10-8b27-b4765287e28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345950281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.345950281
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3218970371
Short name T25
Test name
Test status
Simulation time 90347187 ps
CPU time 4.21 seconds
Started Jul 13 06:58:12 PM PDT 24
Finished Jul 13 06:58:21 PM PDT 24
Peak memory 214468 kb
Host smart-9a57f89b-ec1b-4a0d-b144-178fc2fc2813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218970371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3218970371
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.368086515
Short name T319
Test name
Test status
Simulation time 147416828 ps
CPU time 2.81 seconds
Started Jul 13 06:58:08 PM PDT 24
Finished Jul 13 06:58:13 PM PDT 24
Peak memory 214308 kb
Host smart-2dba5dc3-a0d7-4317-9eab-02f6d8401387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368086515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.368086515
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3653029933
Short name T269
Test name
Test status
Simulation time 184870944 ps
CPU time 4.68 seconds
Started Jul 13 06:58:06 PM PDT 24
Finished Jul 13 06:58:11 PM PDT 24
Peak memory 218188 kb
Host smart-bee46d35-bd77-4903-8c88-7b59b4d65a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653029933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3653029933
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2954181534
Short name T531
Test name
Test status
Simulation time 44827060 ps
CPU time 1.9 seconds
Started Jul 13 06:58:06 PM PDT 24
Finished Jul 13 06:58:08 PM PDT 24
Peak memory 208748 kb
Host smart-bc8b43c9-6dff-4c4a-8072-7d6762337310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954181534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2954181534
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3301325896
Short name T312
Test name
Test status
Simulation time 34229724 ps
CPU time 2.49 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:18 PM PDT 24
Peak memory 208684 kb
Host smart-bb2b49ab-fc2f-4b91-8746-7c3481d13026
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301325896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3301325896
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.73825037
Short name T587
Test name
Test status
Simulation time 2088277464 ps
CPU time 6.85 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:23 PM PDT 24
Peak memory 206908 kb
Host smart-b065a880-12f0-4b84-b018-b7968fcb42b3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73825037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.73825037
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1204186834
Short name T572
Test name
Test status
Simulation time 224165018 ps
CPU time 3.11 seconds
Started Jul 13 06:58:05 PM PDT 24
Finished Jul 13 06:58:08 PM PDT 24
Peak memory 209048 kb
Host smart-ab82155a-6a99-48c5-820a-357d5aad504f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204186834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1204186834
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.668469325
Short name T650
Test name
Test status
Simulation time 148135888 ps
CPU time 2.65 seconds
Started Jul 13 06:58:08 PM PDT 24
Finished Jul 13 06:58:12 PM PDT 24
Peak memory 218260 kb
Host smart-202b1a77-25d4-40c5-8348-45be45512f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668469325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.668469325
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3486200740
Short name T625
Test name
Test status
Simulation time 432553893 ps
CPU time 3.19 seconds
Started Jul 13 06:58:08 PM PDT 24
Finished Jul 13 06:58:14 PM PDT 24
Peak memory 208456 kb
Host smart-8120e4cf-4fe5-463e-8d0a-a220f694d918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486200740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3486200740
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3718714698
Short name T369
Test name
Test status
Simulation time 1033539754 ps
CPU time 4.64 seconds
Started Jul 13 06:58:05 PM PDT 24
Finished Jul 13 06:58:10 PM PDT 24
Peak memory 210032 kb
Host smart-d86ee947-9460-4f58-b778-f251360c54e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718714698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3718714698
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.317741293
Short name T394
Test name
Test status
Simulation time 168618645 ps
CPU time 1.51 seconds
Started Jul 13 06:58:08 PM PDT 24
Finished Jul 13 06:58:11 PM PDT 24
Peak memory 208600 kb
Host smart-ee22e63d-aa5f-40a9-bbd0-72c6ce419dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317741293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.317741293
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1976478943
Short name T508
Test name
Test status
Simulation time 40562975 ps
CPU time 0.81 seconds
Started Jul 13 06:55:55 PM PDT 24
Finished Jul 13 06:55:56 PM PDT 24
Peak memory 205948 kb
Host smart-13f65314-b7bb-4da4-9442-c6ebfccefab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976478943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1976478943
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.4076845805
Short name T227
Test name
Test status
Simulation time 480511168 ps
CPU time 2.04 seconds
Started Jul 13 06:55:54 PM PDT 24
Finished Jul 13 06:55:57 PM PDT 24
Peak memory 209132 kb
Host smart-9400737b-6d3c-4b23-9e75-60b6814865aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076845805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.4076845805
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3177056302
Short name T385
Test name
Test status
Simulation time 38562545 ps
CPU time 2.21 seconds
Started Jul 13 06:55:47 PM PDT 24
Finished Jul 13 06:55:50 PM PDT 24
Peak memory 207508 kb
Host smart-aa7ef55d-21e9-4fd1-ab00-2dada14c0e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177056302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3177056302
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.128371952
Short name T81
Test name
Test status
Simulation time 191256276 ps
CPU time 2.87 seconds
Started Jul 13 06:55:54 PM PDT 24
Finished Jul 13 06:55:58 PM PDT 24
Peak memory 214352 kb
Host smart-ffa1e643-b853-4b87-a72d-f788545cd953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128371952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.128371952
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.764083995
Short name T257
Test name
Test status
Simulation time 110271180 ps
CPU time 4.53 seconds
Started Jul 13 06:55:54 PM PDT 24
Finished Jul 13 06:56:00 PM PDT 24
Peak memory 214312 kb
Host smart-983020b0-42b4-4921-866f-289aafa9c183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764083995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.764083995
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.4192764866
Short name T226
Test name
Test status
Simulation time 93603036 ps
CPU time 2.3 seconds
Started Jul 13 06:55:54 PM PDT 24
Finished Jul 13 06:55:57 PM PDT 24
Peak memory 215128 kb
Host smart-4ffb2f6f-1e01-4232-ac10-d571647a643f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192764866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.4192764866
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3198273227
Short name T206
Test name
Test status
Simulation time 277373814 ps
CPU time 4.43 seconds
Started Jul 13 06:55:48 PM PDT 24
Finished Jul 13 06:55:53 PM PDT 24
Peak memory 208004 kb
Host smart-90d27ea3-835b-4d33-b9f6-6826c4b7342b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198273227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3198273227
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3680054521
Short name T370
Test name
Test status
Simulation time 25548179 ps
CPU time 2.05 seconds
Started Jul 13 06:55:45 PM PDT 24
Finished Jul 13 06:55:47 PM PDT 24
Peak memory 208808 kb
Host smart-0b6001b4-7114-4cb4-9403-946878c43748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680054521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3680054521
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1096212644
Short name T556
Test name
Test status
Simulation time 756468053 ps
CPU time 3.66 seconds
Started Jul 13 06:55:45 PM PDT 24
Finished Jul 13 06:55:49 PM PDT 24
Peak memory 206812 kb
Host smart-cd1944c7-bd0b-4ab3-a4f9-ec524a8a0ef2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096212644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1096212644
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3373747715
Short name T287
Test name
Test status
Simulation time 121680246 ps
CPU time 2.41 seconds
Started Jul 13 06:55:46 PM PDT 24
Finished Jul 13 06:55:49 PM PDT 24
Peak memory 207520 kb
Host smart-c57437ed-d49f-480c-9c5e-8974894922e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373747715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3373747715
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1061849875
Short name T834
Test name
Test status
Simulation time 44187345 ps
CPU time 2.54 seconds
Started Jul 13 06:55:47 PM PDT 24
Finished Jul 13 06:55:51 PM PDT 24
Peak memory 208144 kb
Host smart-82dd7d76-5923-4284-9485-cb337d4db85c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061849875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1061849875
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3280437876
Short name T301
Test name
Test status
Simulation time 22120658 ps
CPU time 1.69 seconds
Started Jul 13 06:55:55 PM PDT 24
Finished Jul 13 06:55:57 PM PDT 24
Peak memory 216236 kb
Host smart-e4b7c4ff-7f96-4066-b6b1-b1db43fd16af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280437876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3280437876
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1951960371
Short name T619
Test name
Test status
Simulation time 623308603 ps
CPU time 2.73 seconds
Started Jul 13 06:55:48 PM PDT 24
Finished Jul 13 06:55:51 PM PDT 24
Peak memory 206760 kb
Host smart-23f713fd-6469-4e55-ab03-4a17edfe2a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951960371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1951960371
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3389847677
Short name T893
Test name
Test status
Simulation time 3492630509 ps
CPU time 38.86 seconds
Started Jul 13 06:55:57 PM PDT 24
Finished Jul 13 06:56:36 PM PDT 24
Peak memory 216464 kb
Host smart-a13e3089-4d33-429f-b927-c5031fe6267e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389847677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3389847677
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.2814298100
Short name T324
Test name
Test status
Simulation time 1020662654 ps
CPU time 12.91 seconds
Started Jul 13 06:55:57 PM PDT 24
Finished Jul 13 06:56:10 PM PDT 24
Peak memory 220580 kb
Host smart-d120715c-7404-4ed9-b63b-c98b75f450ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814298100 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.2814298100
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3171256901
Short name T871
Test name
Test status
Simulation time 754077243 ps
CPU time 7.03 seconds
Started Jul 13 06:55:58 PM PDT 24
Finished Jul 13 06:56:06 PM PDT 24
Peak memory 208360 kb
Host smart-d76cf297-bf31-4c5d-8402-d8b6ee85c5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171256901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3171256901
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1329505639
Short name T710
Test name
Test status
Simulation time 81955313 ps
CPU time 1.43 seconds
Started Jul 13 06:55:56 PM PDT 24
Finished Jul 13 06:55:58 PM PDT 24
Peak memory 209888 kb
Host smart-0759645c-7613-45a1-b5dc-ea88ad5de8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329505639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1329505639
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3510613391
Short name T855
Test name
Test status
Simulation time 18569207 ps
CPU time 0.97 seconds
Started Jul 13 06:58:12 PM PDT 24
Finished Jul 13 06:58:18 PM PDT 24
Peak memory 205916 kb
Host smart-2ae9eef0-e95b-4170-b56e-8689ca596430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510613391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3510613391
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3646014645
Short name T246
Test name
Test status
Simulation time 977164024 ps
CPU time 12.92 seconds
Started Jul 13 06:58:12 PM PDT 24
Finished Jul 13 06:58:31 PM PDT 24
Peak memory 214336 kb
Host smart-bb1b00e7-bb11-48de-9f13-be5f5e25cf9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3646014645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3646014645
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3369477187
Short name T525
Test name
Test status
Simulation time 428969659 ps
CPU time 12.37 seconds
Started Jul 13 06:58:07 PM PDT 24
Finished Jul 13 06:58:21 PM PDT 24
Peak memory 222716 kb
Host smart-2e86385f-d7e6-43af-986e-26638dfe5986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369477187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3369477187
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.435826
Short name T256
Test name
Test status
Simulation time 102817437 ps
CPU time 2.04 seconds
Started Jul 13 06:58:10 PM PDT 24
Finished Jul 13 06:58:16 PM PDT 24
Peak memory 209824 kb
Host smart-76091db2-1c39-4f74-8658-cc0a8fcf8fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.435826
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2812560431
Short name T691
Test name
Test status
Simulation time 175008815 ps
CPU time 4.18 seconds
Started Jul 13 06:58:12 PM PDT 24
Finished Jul 13 06:58:21 PM PDT 24
Peak memory 221168 kb
Host smart-7cd2f8c3-8ebe-4d3c-9f78-1cff4fde47b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812560431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2812560431
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.864994649
Short name T191
Test name
Test status
Simulation time 856419787 ps
CPU time 4.1 seconds
Started Jul 13 06:58:10 PM PDT 24
Finished Jul 13 06:58:18 PM PDT 24
Peak memory 214260 kb
Host smart-557af670-cbc6-4903-a750-2c6684fccfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864994649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.864994649
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2580334144
Short name T711
Test name
Test status
Simulation time 336465572 ps
CPU time 3.24 seconds
Started Jul 13 06:58:07 PM PDT 24
Finished Jul 13 06:58:11 PM PDT 24
Peak memory 217868 kb
Host smart-c3d58f5f-bc49-4799-b081-509a60d02881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580334144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2580334144
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.271360772
Short name T850
Test name
Test status
Simulation time 122101453 ps
CPU time 2.61 seconds
Started Jul 13 06:58:07 PM PDT 24
Finished Jul 13 06:58:11 PM PDT 24
Peak memory 207588 kb
Host smart-0671730d-dc07-4a49-af39-58e78b7f9193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271360772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.271360772
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1407451081
Short name T109
Test name
Test status
Simulation time 5262315376 ps
CPU time 34.28 seconds
Started Jul 13 06:58:07 PM PDT 24
Finished Jul 13 06:58:43 PM PDT 24
Peak memory 208208 kb
Host smart-b3cef14b-7704-475b-8937-98e15d7143ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407451081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1407451081
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3571130849
Short name T616
Test name
Test status
Simulation time 1610107898 ps
CPU time 3.96 seconds
Started Jul 13 06:58:06 PM PDT 24
Finished Jul 13 06:58:11 PM PDT 24
Peak memory 207044 kb
Host smart-c3501f49-7f4a-45e9-b6d5-1b48a3a40439
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571130849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3571130849
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.193002082
Short name T217
Test name
Test status
Simulation time 938543030 ps
CPU time 23.63 seconds
Started Jul 13 06:58:09 PM PDT 24
Finished Jul 13 06:58:35 PM PDT 24
Peak memory 208796 kb
Host smart-f3f56a7b-a530-4abb-b7bb-a86ff33b1542
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193002082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.193002082
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1221989015
Short name T497
Test name
Test status
Simulation time 61393357 ps
CPU time 2.58 seconds
Started Jul 13 06:58:09 PM PDT 24
Finished Jul 13 06:58:16 PM PDT 24
Peak memory 206784 kb
Host smart-91677cff-79dd-4f7c-a5aa-5850ee45a1e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221989015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1221989015
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1360395601
Short name T725
Test name
Test status
Simulation time 151933442 ps
CPU time 3.95 seconds
Started Jul 13 06:58:09 PM PDT 24
Finished Jul 13 06:58:17 PM PDT 24
Peak memory 214400 kb
Host smart-05ceaa9e-622b-40eb-ad38-1bff9e9762cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360395601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1360395601
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.152643725
Short name T828
Test name
Test status
Simulation time 215461769 ps
CPU time 2.6 seconds
Started Jul 13 06:58:07 PM PDT 24
Finished Jul 13 06:58:10 PM PDT 24
Peak memory 208580 kb
Host smart-c6faffe0-ea94-4310-ab0e-3a965cff35ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152643725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.152643725
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2641991245
Short name T891
Test name
Test status
Simulation time 17336118251 ps
CPU time 303.52 seconds
Started Jul 13 06:58:08 PM PDT 24
Finished Jul 13 07:03:13 PM PDT 24
Peak memory 218860 kb
Host smart-484cc872-75fb-456b-80b0-d4f06d6ba612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641991245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2641991245
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.369862970
Short name T852
Test name
Test status
Simulation time 55278041 ps
CPU time 3.19 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:19 PM PDT 24
Peak memory 207712 kb
Host smart-128d40a4-4c98-441e-9b2c-f99a711bdb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369862970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.369862970
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.145679757
Short name T851
Test name
Test status
Simulation time 291534300 ps
CPU time 2.39 seconds
Started Jul 13 06:58:12 PM PDT 24
Finished Jul 13 06:58:20 PM PDT 24
Peak memory 210652 kb
Host smart-534265ce-8b98-48e9-823f-486613b51df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145679757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.145679757
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3992350522
Short name T679
Test name
Test status
Simulation time 30218245 ps
CPU time 0.76 seconds
Started Jul 13 06:58:12 PM PDT 24
Finished Jul 13 06:58:18 PM PDT 24
Peak memory 205784 kb
Host smart-f45a2d9f-71e5-4294-adee-eddcb257bb2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992350522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3992350522
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.553143089
Short name T228
Test name
Test status
Simulation time 131543375 ps
CPU time 2.96 seconds
Started Jul 13 06:58:12 PM PDT 24
Finished Jul 13 06:58:20 PM PDT 24
Peak memory 216432 kb
Host smart-23be9ff1-b9d4-404b-a109-76d0311b9309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553143089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.553143089
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3418450695
Short name T677
Test name
Test status
Simulation time 107501063 ps
CPU time 2.36 seconds
Started Jul 13 06:58:08 PM PDT 24
Finished Jul 13 06:58:13 PM PDT 24
Peak memory 208744 kb
Host smart-5f23df18-948b-4f12-9b4a-41a8e2e5f954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418450695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3418450695
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.814676168
Short name T684
Test name
Test status
Simulation time 598149532 ps
CPU time 4.27 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:20 PM PDT 24
Peak memory 209432 kb
Host smart-0be1886c-f8d1-4d3e-8e4b-434c11ea026e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814676168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.814676168
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1115864387
Short name T379
Test name
Test status
Simulation time 413728466 ps
CPU time 4.25 seconds
Started Jul 13 06:58:09 PM PDT 24
Finished Jul 13 06:58:18 PM PDT 24
Peak memory 214280 kb
Host smart-5c98d77d-21b0-4c67-a77d-7072371c45c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115864387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1115864387
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3846518907
Short name T229
Test name
Test status
Simulation time 43165684 ps
CPU time 2.68 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:18 PM PDT 24
Peak memory 214332 kb
Host smart-0aa7fab0-06cb-42c3-bece-b93a141e0c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846518907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3846518907
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2832498484
Short name T450
Test name
Test status
Simulation time 61646438 ps
CPU time 3.26 seconds
Started Jul 13 06:58:09 PM PDT 24
Finished Jul 13 06:58:15 PM PDT 24
Peak memory 208152 kb
Host smart-b4f6ec57-1fc7-47d4-97a5-eba08881d2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832498484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2832498484
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1575868409
Short name T795
Test name
Test status
Simulation time 192497401 ps
CPU time 7.12 seconds
Started Jul 13 06:58:14 PM PDT 24
Finished Jul 13 06:58:28 PM PDT 24
Peak memory 206820 kb
Host smart-a6a0d59f-815a-4257-b746-27a24ff94953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575868409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1575868409
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3990985782
Short name T755
Test name
Test status
Simulation time 117419801 ps
CPU time 4.47 seconds
Started Jul 13 06:58:07 PM PDT 24
Finished Jul 13 06:58:13 PM PDT 24
Peak memory 208192 kb
Host smart-66da602b-0889-459c-9827-b195ab112964
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990985782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3990985782
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3001632395
Short name T862
Test name
Test status
Simulation time 233496174 ps
CPU time 3.09 seconds
Started Jul 13 06:58:13 PM PDT 24
Finished Jul 13 06:58:22 PM PDT 24
Peak memory 209020 kb
Host smart-cddfb2cb-6d04-4322-8a05-b7f74cc91c31
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001632395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3001632395
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3019396390
Short name T360
Test name
Test status
Simulation time 42664271 ps
CPU time 2.68 seconds
Started Jul 13 06:58:09 PM PDT 24
Finished Jul 13 06:58:16 PM PDT 24
Peak memory 214428 kb
Host smart-3669b165-f55d-4ab2-8097-4f5cad65196e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019396390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3019396390
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.282740809
Short name T203
Test name
Test status
Simulation time 87407554 ps
CPU time 2.32 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:18 PM PDT 24
Peak memory 206992 kb
Host smart-193d4753-4edd-42d6-80ca-01df950fef2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282740809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.282740809
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3553705215
Short name T330
Test name
Test status
Simulation time 225692813 ps
CPU time 3.14 seconds
Started Jul 13 06:58:10 PM PDT 24
Finished Jul 13 06:58:17 PM PDT 24
Peak memory 206912 kb
Host smart-cf387804-fa5e-433b-a5ff-ed35e5e4e6e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553705215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3553705215
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.144896195
Short name T210
Test name
Test status
Simulation time 104811087 ps
CPU time 4.37 seconds
Started Jul 13 06:58:08 PM PDT 24
Finished Jul 13 06:58:15 PM PDT 24
Peak memory 209336 kb
Host smart-0d6985e6-eed5-489b-90b7-43e61a41403d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144896195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.144896195
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.780183155
Short name T655
Test name
Test status
Simulation time 33021660 ps
CPU time 1.93 seconds
Started Jul 13 06:58:09 PM PDT 24
Finished Jul 13 06:58:14 PM PDT 24
Peak memory 210040 kb
Host smart-aa0bfa17-b4e4-413f-a3e1-99a0393bc833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780183155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.780183155
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2940793426
Short name T767
Test name
Test status
Simulation time 21480658 ps
CPU time 0.85 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:17 PM PDT 24
Peak memory 205984 kb
Host smart-406c16e1-6e3b-48df-bd5d-0e3317b00110
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940793426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2940793426
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.4106117519
Short name T299
Test name
Test status
Simulation time 877958589 ps
CPU time 46.48 seconds
Started Jul 13 06:58:10 PM PDT 24
Finished Jul 13 06:59:00 PM PDT 24
Peak memory 214536 kb
Host smart-b3fb953c-86bf-4ca6-8059-e8558b0b1494
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106117519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.4106117519
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1997341395
Short name T607
Test name
Test status
Simulation time 787360449 ps
CPU time 7.09 seconds
Started Jul 13 06:58:18 PM PDT 24
Finished Jul 13 06:58:30 PM PDT 24
Peak memory 214344 kb
Host smart-3503c152-559c-43a1-a986-6772e8388d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997341395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1997341395
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.437915922
Short name T65
Test name
Test status
Simulation time 72597633 ps
CPU time 1.69 seconds
Started Jul 13 06:58:09 PM PDT 24
Finished Jul 13 06:58:14 PM PDT 24
Peak memory 207244 kb
Host smart-67757bc9-3fc7-4e54-add8-556c67ebffc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437915922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.437915922
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.4153391653
Short name T90
Test name
Test status
Simulation time 444351683 ps
CPU time 5.21 seconds
Started Jul 13 06:58:09 PM PDT 24
Finished Jul 13 06:58:17 PM PDT 24
Peak memory 222444 kb
Host smart-1fcd56c3-97f3-4c77-8240-e8dc95da1226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153391653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.4153391653
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1270462692
Short name T567
Test name
Test status
Simulation time 137427856 ps
CPU time 5.46 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:21 PM PDT 24
Peak memory 214240 kb
Host smart-50bec208-a07d-4202-b28a-e4770756353f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270462692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1270462692
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1196992948
Short name T801
Test name
Test status
Simulation time 44219238 ps
CPU time 2.51 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:19 PM PDT 24
Peak memory 210240 kb
Host smart-5a4960b4-1820-44af-a156-04c333970053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196992948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1196992948
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3499393730
Short name T107
Test name
Test status
Simulation time 98274307 ps
CPU time 4.41 seconds
Started Jul 13 06:58:10 PM PDT 24
Finished Jul 13 06:58:19 PM PDT 24
Peak memory 207608 kb
Host smart-c0136500-0ccb-46bd-b066-893bdfe57c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499393730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3499393730
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3772062290
Short name T512
Test name
Test status
Simulation time 815013807 ps
CPU time 22.6 seconds
Started Jul 13 06:58:13 PM PDT 24
Finished Jul 13 06:58:42 PM PDT 24
Peak memory 208140 kb
Host smart-e8d6d44e-fa00-44ae-96ea-f87b1ffb492f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772062290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3772062290
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3143758326
Short name T721
Test name
Test status
Simulation time 175998246 ps
CPU time 2.71 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:19 PM PDT 24
Peak memory 208380 kb
Host smart-518046ef-7acd-4172-9b61-6df3a720b77c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143758326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3143758326
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1123854315
Short name T705
Test name
Test status
Simulation time 873545169 ps
CPU time 11.26 seconds
Started Jul 13 06:58:15 PM PDT 24
Finished Jul 13 06:58:33 PM PDT 24
Peak memory 207964 kb
Host smart-8afb5643-4017-4e8c-991d-a4c04ec140a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123854315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1123854315
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2814984130
Short name T514
Test name
Test status
Simulation time 74351713 ps
CPU time 2.74 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:18 PM PDT 24
Peak memory 207016 kb
Host smart-8fbc1f51-cfcd-4e05-be69-fce1abc00a74
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814984130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2814984130
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.256456924
Short name T498
Test name
Test status
Simulation time 199520531 ps
CPU time 2.09 seconds
Started Jul 13 06:58:10 PM PDT 24
Finished Jul 13 06:58:16 PM PDT 24
Peak memory 208860 kb
Host smart-1da30f92-80ef-467e-b786-15afee35533c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256456924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.256456924
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3723420391
Short name T791
Test name
Test status
Simulation time 428588628 ps
CPU time 2.8 seconds
Started Jul 13 06:58:12 PM PDT 24
Finished Jul 13 06:58:21 PM PDT 24
Peak memory 208468 kb
Host smart-65715498-72af-4cab-9adc-aeba0573963d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723420391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3723420391
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.314494584
Short name T218
Test name
Test status
Simulation time 91611897 ps
CPU time 2.99 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:18 PM PDT 24
Peak memory 218240 kb
Host smart-2eb6b5cc-d351-4ae0-9877-980f391574fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314494584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.314494584
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3321793522
Short name T396
Test name
Test status
Simulation time 503570000 ps
CPU time 2.74 seconds
Started Jul 13 06:58:10 PM PDT 24
Finished Jul 13 06:58:16 PM PDT 24
Peak memory 210424 kb
Host smart-690bdc63-46ca-4e04-adf3-1631cef3491f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321793522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3321793522
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.46287036
Short name T493
Test name
Test status
Simulation time 27259404 ps
CPU time 0.69 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:17 PM PDT 24
Peak memory 205984 kb
Host smart-084b470c-b934-401c-99c5-0a3c6db57dc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46287036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.46287036
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2574854265
Short name T889
Test name
Test status
Simulation time 494956316 ps
CPU time 10.79 seconds
Started Jul 13 06:58:12 PM PDT 24
Finished Jul 13 06:58:27 PM PDT 24
Peak memory 214328 kb
Host smart-f99ffd81-082d-4c64-b1d9-63fe15a79736
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2574854265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2574854265
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2427714886
Short name T30
Test name
Test status
Simulation time 46548301 ps
CPU time 3 seconds
Started Jul 13 06:58:15 PM PDT 24
Finished Jul 13 06:58:24 PM PDT 24
Peak memory 209532 kb
Host smart-80f6ca0e-36f7-4442-8149-d4b3708b91cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427714886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2427714886
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.4261128363
Short name T458
Test name
Test status
Simulation time 397372636 ps
CPU time 11.19 seconds
Started Jul 13 06:58:15 PM PDT 24
Finished Jul 13 06:58:32 PM PDT 24
Peak memory 208048 kb
Host smart-e5e2c243-75d9-48e0-a0fd-2bb358ea5ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261128363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.4261128363
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3599946215
Short name T96
Test name
Test status
Simulation time 980907338 ps
CPU time 16.16 seconds
Started Jul 13 06:58:12 PM PDT 24
Finished Jul 13 06:58:34 PM PDT 24
Peak memory 219728 kb
Host smart-f66d820d-3320-4ad4-8bb7-70b80336226b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599946215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3599946215
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3225056129
Short name T40
Test name
Test status
Simulation time 364117177 ps
CPU time 3.58 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:19 PM PDT 24
Peak memory 214272 kb
Host smart-e98ee098-8a39-4e19-a59d-405e36390d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225056129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3225056129
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3989278817
Short name T846
Test name
Test status
Simulation time 111791287 ps
CPU time 3.07 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:19 PM PDT 24
Peak memory 215244 kb
Host smart-bf254a43-2881-4f2f-9b9c-f547d6171c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989278817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3989278817
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3752358399
Short name T659
Test name
Test status
Simulation time 329785593 ps
CPU time 3.13 seconds
Started Jul 13 06:58:18 PM PDT 24
Finished Jul 13 06:58:26 PM PDT 24
Peak memory 208736 kb
Host smart-f3bb8546-8c55-430b-a24c-a4dcbffbf720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752358399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3752358399
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2965877555
Short name T248
Test name
Test status
Simulation time 476493946 ps
CPU time 2.97 seconds
Started Jul 13 06:58:14 PM PDT 24
Finished Jul 13 06:58:24 PM PDT 24
Peak memory 206424 kb
Host smart-83bc81eb-3a8a-4f24-a364-ff78bf25cbae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965877555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2965877555
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3618085491
Short name T110
Test name
Test status
Simulation time 79894880 ps
CPU time 1.69 seconds
Started Jul 13 06:58:12 PM PDT 24
Finished Jul 13 06:58:18 PM PDT 24
Peak memory 206940 kb
Host smart-0f0293f8-e72b-4468-beeb-da0f3abfe76b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618085491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3618085491
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2037501560
Short name T271
Test name
Test status
Simulation time 534868591 ps
CPU time 17.52 seconds
Started Jul 13 06:58:13 PM PDT 24
Finished Jul 13 06:58:36 PM PDT 24
Peak memory 208584 kb
Host smart-510f77d0-75d2-437e-8756-b02b5a85f3b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037501560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2037501560
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2014545855
Short name T603
Test name
Test status
Simulation time 107786042 ps
CPU time 4.41 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:20 PM PDT 24
Peak memory 207636 kb
Host smart-e94532e5-aa47-4d11-8b52-d7f4b14f1001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014545855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2014545855
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2453355137
Short name T432
Test name
Test status
Simulation time 2677546006 ps
CPU time 35.69 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:52 PM PDT 24
Peak memory 209148 kb
Host smart-76a0a099-af5d-41d6-9b2e-23d8444d73dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453355137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2453355137
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1096588049
Short name T848
Test name
Test status
Simulation time 244815018 ps
CPU time 9.09 seconds
Started Jul 13 06:58:10 PM PDT 24
Finished Jul 13 06:58:24 PM PDT 24
Peak memory 214324 kb
Host smart-9ac7a533-f578-46ae-8a43-ba5fe1cd98db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096588049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1096588049
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3656786098
Short name T692
Test name
Test status
Simulation time 25646365 ps
CPU time 0.94 seconds
Started Jul 13 06:58:16 PM PDT 24
Finished Jul 13 06:58:23 PM PDT 24
Peak memory 205996 kb
Host smart-82a49e75-27ff-4724-ada8-814c13d326ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656786098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3656786098
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1898270228
Short name T817
Test name
Test status
Simulation time 1601392309 ps
CPU time 39.71 seconds
Started Jul 13 06:58:14 PM PDT 24
Finished Jul 13 06:58:59 PM PDT 24
Peak memory 214980 kb
Host smart-a00dd8ba-0ad6-4ea6-8e54-60d14c9f7c7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1898270228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1898270228
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.8310359
Short name T672
Test name
Test status
Simulation time 164092270 ps
CPU time 1.78 seconds
Started Jul 13 06:58:13 PM PDT 24
Finished Jul 13 06:58:21 PM PDT 24
Peak memory 207648 kb
Host smart-538d87ad-401f-43e2-8e9d-fc9f06eb26e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8310359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.8310359
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2928012297
Short name T88
Test name
Test status
Simulation time 778096369 ps
CPU time 6.01 seconds
Started Jul 13 06:58:16 PM PDT 24
Finished Jul 13 06:58:28 PM PDT 24
Peak memory 209764 kb
Host smart-42dc8d46-6bb5-471e-a20a-e1d344cbe42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928012297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2928012297
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3674051321
Short name T580
Test name
Test status
Simulation time 40119232 ps
CPU time 2.13 seconds
Started Jul 13 06:58:10 PM PDT 24
Finished Jul 13 06:58:17 PM PDT 24
Peak memory 208252 kb
Host smart-cf77a093-727c-4f44-a72d-a94d2ca5932a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674051321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3674051321
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.956831697
Short name T321
Test name
Test status
Simulation time 362042516 ps
CPU time 4.96 seconds
Started Jul 13 06:58:16 PM PDT 24
Finished Jul 13 06:58:27 PM PDT 24
Peak memory 208320 kb
Host smart-86acf481-3a68-4543-be77-7a5c80327027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956831697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.956831697
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2050556440
Short name T649
Test name
Test status
Simulation time 54815008 ps
CPU time 2.8 seconds
Started Jul 13 06:58:14 PM PDT 24
Finished Jul 13 06:58:23 PM PDT 24
Peak memory 208064 kb
Host smart-32f7b276-c6ab-4fa0-bf75-57eaf56fbccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050556440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2050556440
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3172662234
Short name T836
Test name
Test status
Simulation time 165350888 ps
CPU time 3.62 seconds
Started Jul 13 06:58:12 PM PDT 24
Finished Jul 13 06:58:21 PM PDT 24
Peak memory 208612 kb
Host smart-9ca92c20-36db-49ad-a553-4a7a9f57fea1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172662234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3172662234
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3867336243
Short name T345
Test name
Test status
Simulation time 215175330 ps
CPU time 2.76 seconds
Started Jul 13 06:58:10 PM PDT 24
Finished Jul 13 06:58:17 PM PDT 24
Peak memory 206912 kb
Host smart-08a66170-178e-4f09-be8c-5b1cd393f1a7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867336243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3867336243
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.785582655
Short name T830
Test name
Test status
Simulation time 898454472 ps
CPU time 23.9 seconds
Started Jul 13 06:58:14 PM PDT 24
Finished Jul 13 06:58:45 PM PDT 24
Peak memory 208616 kb
Host smart-f9c1da8c-49df-48b4-aa45-cc3ca06cde41
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785582655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.785582655
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2377088929
Short name T376
Test name
Test status
Simulation time 56036978 ps
CPU time 2.93 seconds
Started Jul 13 06:58:16 PM PDT 24
Finished Jul 13 06:58:25 PM PDT 24
Peak memory 214392 kb
Host smart-0aa0d0c1-28c4-4744-bab2-178ea26b64b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377088929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2377088929
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2712319086
Short name T719
Test name
Test status
Simulation time 314353689 ps
CPU time 2.62 seconds
Started Jul 13 06:58:18 PM PDT 24
Finished Jul 13 06:58:26 PM PDT 24
Peak memory 206896 kb
Host smart-3713be42-5677-4598-8da2-60b0538cb565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712319086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2712319086
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.999910657
Short name T315
Test name
Test status
Simulation time 316560380 ps
CPU time 16.69 seconds
Started Jul 13 06:58:16 PM PDT 24
Finished Jul 13 06:58:39 PM PDT 24
Peak memory 221140 kb
Host smart-2d5de3cb-b7be-4190-9a22-2179df1b7926
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999910657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.999910657
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.4246454972
Short name T806
Test name
Test status
Simulation time 3806939432 ps
CPU time 32.46 seconds
Started Jul 13 06:58:11 PM PDT 24
Finished Jul 13 06:58:48 PM PDT 24
Peak memory 222700 kb
Host smart-fe0e71eb-f784-40f2-baa1-7406880d0131
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246454972 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.4246454972
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1724372262
Short name T337
Test name
Test status
Simulation time 117381518 ps
CPU time 5.58 seconds
Started Jul 13 06:58:18 PM PDT 24
Finished Jul 13 06:58:29 PM PDT 24
Peak memory 209824 kb
Host smart-80da2c2e-9526-4fb9-9326-c7aafc32d3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724372262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1724372262
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.313007609
Short name T45
Test name
Test status
Simulation time 41938510 ps
CPU time 1.92 seconds
Started Jul 13 06:58:16 PM PDT 24
Finished Jul 13 06:58:24 PM PDT 24
Peak memory 210000 kb
Host smart-54f8309b-74b4-4bab-9064-08d4d427d564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313007609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.313007609
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1750412761
Short name T689
Test name
Test status
Simulation time 19386481 ps
CPU time 1.02 seconds
Started Jul 13 06:58:16 PM PDT 24
Finished Jul 13 06:58:23 PM PDT 24
Peak memory 206104 kb
Host smart-93a0d9b8-ee45-4fc4-ae00-ca68d0a0d2b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750412761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1750412761
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3815275402
Short name T409
Test name
Test status
Simulation time 214826407 ps
CPU time 6.38 seconds
Started Jul 13 06:58:21 PM PDT 24
Finished Jul 13 06:58:31 PM PDT 24
Peak memory 208448 kb
Host smart-cb3ed483-e823-4b44-b94a-0b83e66e1a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815275402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3815275402
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.297927427
Short name T857
Test name
Test status
Simulation time 464167035 ps
CPU time 3.59 seconds
Started Jul 13 06:58:17 PM PDT 24
Finished Jul 13 06:58:26 PM PDT 24
Peak memory 221388 kb
Host smart-d1677a2b-f65e-4a14-9453-6f8478368814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297927427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.297927427
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3441091585
Short name T258
Test name
Test status
Simulation time 86798658 ps
CPU time 3.66 seconds
Started Jul 13 06:58:21 PM PDT 24
Finished Jul 13 06:58:29 PM PDT 24
Peak memory 222460 kb
Host smart-e30d494f-c251-4442-965f-1f08f7a6c318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441091585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3441091585
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1430992834
Short name T304
Test name
Test status
Simulation time 87014080 ps
CPU time 3.67 seconds
Started Jul 13 06:58:32 PM PDT 24
Finished Jul 13 06:58:36 PM PDT 24
Peak memory 222460 kb
Host smart-e086a83c-4e9a-4cbc-b16f-c5fa6cf56a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430992834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1430992834
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3159582694
Short name T896
Test name
Test status
Simulation time 125078014 ps
CPU time 3.56 seconds
Started Jul 13 06:58:20 PM PDT 24
Finished Jul 13 06:58:28 PM PDT 24
Peak memory 206720 kb
Host smart-b2bcd5a6-0ee3-41ec-a672-811d69b0871a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159582694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3159582694
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2465152998
Short name T902
Test name
Test status
Simulation time 169998159 ps
CPU time 4.94 seconds
Started Jul 13 06:58:18 PM PDT 24
Finished Jul 13 06:58:29 PM PDT 24
Peak memory 208412 kb
Host smart-6b7244fc-829d-4dd2-94d4-f2ce1ca84fee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465152998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2465152998
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.4239968011
Short name T311
Test name
Test status
Simulation time 119817532 ps
CPU time 4.02 seconds
Started Jul 13 06:58:19 PM PDT 24
Finished Jul 13 06:58:28 PM PDT 24
Peak memory 208968 kb
Host smart-954515ca-136e-48b5-b70c-49c23666c904
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239968011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.4239968011
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1041051465
Short name T573
Test name
Test status
Simulation time 97712711 ps
CPU time 3.03 seconds
Started Jul 13 06:58:16 PM PDT 24
Finished Jul 13 06:58:25 PM PDT 24
Peak memory 206812 kb
Host smart-897116bb-b7ad-403d-bd3f-4d3a458337d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041051465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1041051465
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.657384528
Short name T641
Test name
Test status
Simulation time 55539173 ps
CPU time 2.18 seconds
Started Jul 13 06:58:18 PM PDT 24
Finished Jul 13 06:58:25 PM PDT 24
Peak memory 209684 kb
Host smart-e72f726a-c4cc-40ec-b88d-d7eae2036e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657384528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.657384528
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2291246760
Short name T511
Test name
Test status
Simulation time 183985434 ps
CPU time 4.86 seconds
Started Jul 13 06:58:14 PM PDT 24
Finished Jul 13 06:58:25 PM PDT 24
Peak memory 207776 kb
Host smart-3698c170-2881-4222-9db8-b2481139f745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291246760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2291246760
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2481319678
Short name T207
Test name
Test status
Simulation time 1459892330 ps
CPU time 30.12 seconds
Started Jul 13 06:58:16 PM PDT 24
Finished Jul 13 06:58:52 PM PDT 24
Peak memory 214304 kb
Host smart-cb44cb02-0e76-4b1d-8049-5a7ed683ea79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481319678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2481319678
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3509823423
Short name T340
Test name
Test status
Simulation time 2223671577 ps
CPU time 23.64 seconds
Started Jul 13 06:58:16 PM PDT 24
Finished Jul 13 06:58:46 PM PDT 24
Peak memory 209624 kb
Host smart-d528e058-0656-480f-b661-40f6ab2c0b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509823423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3509823423
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.960701380
Short name T39
Test name
Test status
Simulation time 73450088 ps
CPU time 2.51 seconds
Started Jul 13 06:58:32 PM PDT 24
Finished Jul 13 06:58:36 PM PDT 24
Peak memory 210048 kb
Host smart-968e6e77-1851-4645-8ea2-2dd625239edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960701380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.960701380
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.916943519
Short name T769
Test name
Test status
Simulation time 19202934 ps
CPU time 0.99 seconds
Started Jul 13 06:58:18 PM PDT 24
Finished Jul 13 06:58:24 PM PDT 24
Peak memory 206132 kb
Host smart-de060694-a9d9-407a-8a17-d592a90120e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916943519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.916943519
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1356370910
Short name T255
Test name
Test status
Simulation time 23867096 ps
CPU time 1.72 seconds
Started Jul 13 06:58:18 PM PDT 24
Finished Jul 13 06:58:25 PM PDT 24
Peak memory 208164 kb
Host smart-99bab0e4-8241-4365-86b1-cdded2a1dd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356370910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1356370910
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1067515136
Short name T99
Test name
Test status
Simulation time 140954165 ps
CPU time 3.23 seconds
Started Jul 13 06:58:20 PM PDT 24
Finished Jul 13 06:58:27 PM PDT 24
Peak memory 208520 kb
Host smart-2c32edb5-bcbb-43d1-bf0f-093a40f4ee4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067515136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1067515136
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1443367781
Short name T515
Test name
Test status
Simulation time 114617032 ps
CPU time 2.78 seconds
Started Jul 13 06:58:32 PM PDT 24
Finished Jul 13 06:58:36 PM PDT 24
Peak memory 218984 kb
Host smart-0f3741f7-1ab5-4937-b1c3-66dc2cf44777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443367781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1443367781
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1213013000
Short name T189
Test name
Test status
Simulation time 116425048 ps
CPU time 2.39 seconds
Started Jul 13 06:58:17 PM PDT 24
Finished Jul 13 06:58:25 PM PDT 24
Peak memory 208888 kb
Host smart-750ab36f-b9fe-4720-81ef-40565afe6ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213013000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1213013000
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.894749870
Short name T652
Test name
Test status
Simulation time 82860320 ps
CPU time 3.45 seconds
Started Jul 13 06:58:20 PM PDT 24
Finished Jul 13 06:58:27 PM PDT 24
Peak memory 206896 kb
Host smart-d0297b52-218b-4de0-8352-8244a5495e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894749870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.894749870
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2676930615
Short name T559
Test name
Test status
Simulation time 6984246913 ps
CPU time 44.02 seconds
Started Jul 13 06:58:16 PM PDT 24
Finished Jul 13 06:59:06 PM PDT 24
Peak memory 208280 kb
Host smart-ae9494b3-0b3d-43de-b223-12fc66a06220
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676930615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2676930615
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3534031506
Short name T462
Test name
Test status
Simulation time 70263300 ps
CPU time 2.75 seconds
Started Jul 13 06:58:15 PM PDT 24
Finished Jul 13 06:58:24 PM PDT 24
Peak memory 207108 kb
Host smart-9217b184-e428-4306-b897-6d65fcaff8b1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534031506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3534031506
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3517871649
Short name T868
Test name
Test status
Simulation time 693338831 ps
CPU time 5.09 seconds
Started Jul 13 06:58:17 PM PDT 24
Finished Jul 13 06:58:27 PM PDT 24
Peak memory 208844 kb
Host smart-37fd2f23-802e-4855-b234-ef1c068a01aa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517871649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3517871649
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2495746583
Short name T814
Test name
Test status
Simulation time 117937391 ps
CPU time 3.57 seconds
Started Jul 13 06:58:20 PM PDT 24
Finished Jul 13 06:58:28 PM PDT 24
Peak memory 208536 kb
Host smart-779df98d-2470-4c64-80d0-e770a6175468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495746583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2495746583
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1340965662
Short name T466
Test name
Test status
Simulation time 107674695 ps
CPU time 3.49 seconds
Started Jul 13 06:58:21 PM PDT 24
Finished Jul 13 06:58:28 PM PDT 24
Peak memory 206728 kb
Host smart-602473f2-d084-48b5-a907-21daf72aa035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340965662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1340965662
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.925325546
Short name T760
Test name
Test status
Simulation time 5198841246 ps
CPU time 33.84 seconds
Started Jul 13 06:58:21 PM PDT 24
Finished Jul 13 06:58:59 PM PDT 24
Peak memory 214380 kb
Host smart-a233750a-78c0-40b7-ac20-7a3b4b470efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925325546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.925325546
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2743529763
Short name T775
Test name
Test status
Simulation time 53750825 ps
CPU time 2.26 seconds
Started Jul 13 06:58:21 PM PDT 24
Finished Jul 13 06:58:27 PM PDT 24
Peak memory 209972 kb
Host smart-152c048c-2b53-4c43-9b03-b3a5b667af25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743529763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2743529763
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.601875416
Short name T804
Test name
Test status
Simulation time 38354101 ps
CPU time 0.71 seconds
Started Jul 13 06:58:27 PM PDT 24
Finished Jul 13 06:58:30 PM PDT 24
Peak memory 205964 kb
Host smart-b3fa7370-0ce8-42fb-b03f-78867e92c365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601875416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.601875416
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1283961613
Short name T749
Test name
Test status
Simulation time 88084409 ps
CPU time 1.52 seconds
Started Jul 13 06:58:33 PM PDT 24
Finished Jul 13 06:58:35 PM PDT 24
Peak memory 214296 kb
Host smart-150b38f6-789d-412f-a2e5-82df3b1b1a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283961613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1283961613
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1174751482
Short name T305
Test name
Test status
Simulation time 126168871 ps
CPU time 5.44 seconds
Started Jul 13 06:58:33 PM PDT 24
Finished Jul 13 06:58:39 PM PDT 24
Peak memory 214308 kb
Host smart-5a1b5f89-06fa-4723-825d-3480eacc4f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174751482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1174751482
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1233622677
Short name T94
Test name
Test status
Simulation time 121650773 ps
CPU time 2.78 seconds
Started Jul 13 06:58:33 PM PDT 24
Finished Jul 13 06:58:37 PM PDT 24
Peak memory 221528 kb
Host smart-211cc702-d64d-469b-a2f4-4dfbd0be4bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233622677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1233622677
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_random.1363508176
Short name T329
Test name
Test status
Simulation time 46848972 ps
CPU time 2.5 seconds
Started Jul 13 06:58:17 PM PDT 24
Finished Jul 13 06:58:26 PM PDT 24
Peak memory 209304 kb
Host smart-e9179d8e-9bc0-422f-9b75-f1e676676a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363508176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1363508176
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.116960000
Short name T274
Test name
Test status
Simulation time 422411664 ps
CPU time 5.79 seconds
Started Jul 13 06:58:17 PM PDT 24
Finished Jul 13 06:58:28 PM PDT 24
Peak memory 208544 kb
Host smart-97d629c0-7839-4e9d-8fe7-1fa4144fa794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116960000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.116960000
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.4201382861
Short name T734
Test name
Test status
Simulation time 452921202 ps
CPU time 5.51 seconds
Started Jul 13 06:58:21 PM PDT 24
Finished Jul 13 06:58:30 PM PDT 24
Peak memory 208040 kb
Host smart-8850d22d-1d2b-4457-8e75-64c5337a8078
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201382861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.4201382861
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2329357898
Short name T750
Test name
Test status
Simulation time 1097483055 ps
CPU time 16.51 seconds
Started Jul 13 06:58:22 PM PDT 24
Finished Jul 13 06:58:42 PM PDT 24
Peak memory 208580 kb
Host smart-375d9678-04c0-45a6-9c15-db4c795522b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329357898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2329357898
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.828375217
Short name T864
Test name
Test status
Simulation time 401262979 ps
CPU time 5.47 seconds
Started Jul 13 06:58:33 PM PDT 24
Finished Jul 13 06:58:39 PM PDT 24
Peak memory 206936 kb
Host smart-2a7d71af-607a-4f0d-8a23-08dba2ab5e6f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828375217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.828375217
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.246236257
Short name T307
Test name
Test status
Simulation time 1364241175 ps
CPU time 4.55 seconds
Started Jul 13 06:58:19 PM PDT 24
Finished Jul 13 06:58:28 PM PDT 24
Peak memory 218284 kb
Host smart-f090fd34-6e29-483a-83d3-57fc63d5373d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246236257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.246236257
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3630435126
Short name T838
Test name
Test status
Simulation time 94007087 ps
CPU time 2.49 seconds
Started Jul 13 06:58:17 PM PDT 24
Finished Jul 13 06:58:25 PM PDT 24
Peak memory 206884 kb
Host smart-e687d397-cf47-43dc-a8fe-a4a0809426c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630435126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3630435126
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3995042767
Short name T281
Test name
Test status
Simulation time 487794667 ps
CPU time 4.25 seconds
Started Jul 13 06:58:20 PM PDT 24
Finished Jul 13 06:58:28 PM PDT 24
Peak memory 219760 kb
Host smart-d5279621-8f23-44fa-9fa4-c0e7dab50d8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995042767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3995042767
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.150065427
Short name T412
Test name
Test status
Simulation time 926102132 ps
CPU time 6.58 seconds
Started Jul 13 06:58:16 PM PDT 24
Finished Jul 13 06:58:29 PM PDT 24
Peak memory 207972 kb
Host smart-ead64c83-244f-4da5-8d4f-c9b16342b225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150065427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.150065427
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.4077898345
Short name T413
Test name
Test status
Simulation time 514365234 ps
CPU time 6.19 seconds
Started Jul 13 06:58:19 PM PDT 24
Finished Jul 13 06:58:30 PM PDT 24
Peak memory 211016 kb
Host smart-d83677c8-5d9c-4262-bfa6-dbdeefb38a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077898345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.4077898345
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1913224571
Short name T598
Test name
Test status
Simulation time 52115930 ps
CPU time 0.83 seconds
Started Jul 13 06:58:27 PM PDT 24
Finished Jul 13 06:58:30 PM PDT 24
Peak memory 205984 kb
Host smart-f506ef27-7fa0-451b-8f18-a4091d22f94a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913224571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1913224571
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3934940620
Short name T15
Test name
Test status
Simulation time 126843817 ps
CPU time 4.96 seconds
Started Jul 13 06:58:30 PM PDT 24
Finished Jul 13 06:58:41 PM PDT 24
Peak memory 222796 kb
Host smart-ee38b5cc-1f22-4eec-8ea3-f0608a20d5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934940620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3934940620
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3838382407
Short name T351
Test name
Test status
Simulation time 140833244 ps
CPU time 2.21 seconds
Started Jul 13 06:58:28 PM PDT 24
Finished Jul 13 06:58:33 PM PDT 24
Peak memory 207616 kb
Host smart-57331909-66c9-4552-82be-8a41892a853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838382407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3838382407
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.951234040
Short name T761
Test name
Test status
Simulation time 696953296 ps
CPU time 5.2 seconds
Started Jul 13 06:58:28 PM PDT 24
Finished Jul 13 06:58:35 PM PDT 24
Peak memory 214760 kb
Host smart-094e179d-0990-48cf-b322-1be9c2bf1a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951234040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.951234040
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.220344523
Short name T842
Test name
Test status
Simulation time 47019463 ps
CPU time 2.25 seconds
Started Jul 13 06:58:25 PM PDT 24
Finished Jul 13 06:58:28 PM PDT 24
Peak memory 214276 kb
Host smart-71829553-ab1c-42e9-983b-b4ec8987f8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220344523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.220344523
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2616401640
Short name T781
Test name
Test status
Simulation time 207705928 ps
CPU time 2.68 seconds
Started Jul 13 06:58:25 PM PDT 24
Finished Jul 13 06:58:29 PM PDT 24
Peak memory 209692 kb
Host smart-f2e62fc6-c7a1-4b3c-9484-41fa36d9955a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616401640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2616401640
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1192287271
Short name T907
Test name
Test status
Simulation time 328340349 ps
CPU time 4.05 seconds
Started Jul 13 06:58:32 PM PDT 24
Finished Jul 13 06:58:37 PM PDT 24
Peak memory 207564 kb
Host smart-a1f34b6d-72fc-4a54-80d4-6b3ec9d60a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192287271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1192287271
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1504759407
Short name T366
Test name
Test status
Simulation time 366669334 ps
CPU time 3.07 seconds
Started Jul 13 06:58:27 PM PDT 24
Finished Jul 13 06:58:32 PM PDT 24
Peak memory 208456 kb
Host smart-6616fe14-20ea-4fb5-8bde-dfdf9ca299d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504759407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1504759407
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2419006635
Short name T381
Test name
Test status
Simulation time 238061888 ps
CPU time 7.3 seconds
Started Jul 13 06:58:26 PM PDT 24
Finished Jul 13 06:58:35 PM PDT 24
Peak memory 208464 kb
Host smart-53b4cac4-62b2-4375-b4d1-e7f5d41fe1e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419006635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2419006635
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2298109571
Short name T467
Test name
Test status
Simulation time 254741943 ps
CPU time 5.66 seconds
Started Jul 13 06:58:26 PM PDT 24
Finished Jul 13 06:58:32 PM PDT 24
Peak memory 208900 kb
Host smart-e8b6ba62-f764-40d9-83da-1562b7b2b9d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298109571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2298109571
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1417262366
Short name T377
Test name
Test status
Simulation time 1887362590 ps
CPU time 12.27 seconds
Started Jul 13 06:58:28 PM PDT 24
Finished Jul 13 06:58:42 PM PDT 24
Peak memory 208788 kb
Host smart-1ab167e6-f7fd-43f7-a451-3a24f6044285
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417262366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1417262366
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.4156057154
Short name T378
Test name
Test status
Simulation time 138932927 ps
CPU time 3.25 seconds
Started Jul 13 06:58:26 PM PDT 24
Finished Jul 13 06:58:30 PM PDT 24
Peak memory 214332 kb
Host smart-1316ebd5-ef26-4ce2-8368-b506082f1b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156057154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.4156057154
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.158822656
Short name T457
Test name
Test status
Simulation time 159451570 ps
CPU time 3.18 seconds
Started Jul 13 06:58:30 PM PDT 24
Finished Jul 13 06:58:35 PM PDT 24
Peak memory 206732 kb
Host smart-57a581db-02a2-473d-97e7-ca4a4c54fdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158822656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.158822656
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.666295561
Short name T77
Test name
Test status
Simulation time 786850654 ps
CPU time 10.14 seconds
Started Jul 13 06:58:27 PM PDT 24
Finished Jul 13 06:58:39 PM PDT 24
Peak memory 216152 kb
Host smart-b81d3319-9146-452d-bc22-f20484356ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666295561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.666295561
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.763569062
Short name T712
Test name
Test status
Simulation time 225987923 ps
CPU time 6.55 seconds
Started Jul 13 06:58:29 PM PDT 24
Finished Jul 13 06:58:38 PM PDT 24
Peak memory 214340 kb
Host smart-c5122b6e-a105-403c-83f3-4597ab637c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763569062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.763569062
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2235317327
Short name T731
Test name
Test status
Simulation time 114961819 ps
CPU time 3.34 seconds
Started Jul 13 06:58:26 PM PDT 24
Finished Jul 13 06:58:30 PM PDT 24
Peak memory 210660 kb
Host smart-c433ede7-7603-4ff6-95a3-b16df1cb691e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235317327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2235317327
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.108255713
Short name T890
Test name
Test status
Simulation time 26256319 ps
CPU time 0.76 seconds
Started Jul 13 06:58:32 PM PDT 24
Finished Jul 13 06:58:34 PM PDT 24
Peak memory 206012 kb
Host smart-6a7714ee-b755-41d4-b972-424aaac52eae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108255713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.108255713
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.307851191
Short name T425
Test name
Test status
Simulation time 605791994 ps
CPU time 8.81 seconds
Started Jul 13 06:58:28 PM PDT 24
Finished Jul 13 06:58:39 PM PDT 24
Peak memory 215224 kb
Host smart-3f6b84ac-cd01-4255-969a-cf9c00b9f8af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=307851191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.307851191
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.784531586
Short name T758
Test name
Test status
Simulation time 200520210 ps
CPU time 4.62 seconds
Started Jul 13 06:58:28 PM PDT 24
Finished Jul 13 06:58:35 PM PDT 24
Peak memory 209460 kb
Host smart-99935644-30f0-4f44-a2f9-97e783ae8c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784531586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.784531586
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3799479039
Short name T75
Test name
Test status
Simulation time 348296408 ps
CPU time 12.53 seconds
Started Jul 13 06:58:28 PM PDT 24
Finished Jul 13 06:58:43 PM PDT 24
Peak memory 214340 kb
Host smart-4a0b5dac-e364-49ff-a835-38c12cf89223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799479039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3799479039
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2338672848
Short name T880
Test name
Test status
Simulation time 68281982 ps
CPU time 2.55 seconds
Started Jul 13 06:58:27 PM PDT 24
Finished Jul 13 06:58:31 PM PDT 24
Peak memory 214644 kb
Host smart-c6809c67-2d67-492c-aeea-cdc61bb8eb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338672848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2338672848
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1553295497
Short name T332
Test name
Test status
Simulation time 197249684 ps
CPU time 3.17 seconds
Started Jul 13 06:58:27 PM PDT 24
Finished Jul 13 06:58:32 PM PDT 24
Peak memory 214264 kb
Host smart-fa51facc-78bf-4099-93d7-0ae2ea372110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553295497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1553295497
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2153918129
Short name T724
Test name
Test status
Simulation time 544812999 ps
CPU time 3.54 seconds
Started Jul 13 06:58:25 PM PDT 24
Finished Jul 13 06:58:30 PM PDT 24
Peak memory 208384 kb
Host smart-596a1256-eff5-4e2b-bd1f-32b0be89c9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153918129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2153918129
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2278654633
Short name T794
Test name
Test status
Simulation time 146286046 ps
CPU time 3.17 seconds
Started Jul 13 06:58:26 PM PDT 24
Finished Jul 13 06:58:31 PM PDT 24
Peak memory 207624 kb
Host smart-95ef74d2-dac7-48ab-874e-8cb55167719d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278654633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2278654633
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3198843843
Short name T285
Test name
Test status
Simulation time 1177061433 ps
CPU time 27.76 seconds
Started Jul 13 06:58:31 PM PDT 24
Finished Jul 13 06:59:00 PM PDT 24
Peak memory 208352 kb
Host smart-7930a749-02df-4b45-8ce7-bb15fee9a4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198843843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3198843843
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.312414247
Short name T506
Test name
Test status
Simulation time 65904811 ps
CPU time 3.07 seconds
Started Jul 13 06:58:31 PM PDT 24
Finished Jul 13 06:58:35 PM PDT 24
Peak memory 208860 kb
Host smart-7c32f7c1-62ef-42bb-81b4-ba195b5c8e2f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312414247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.312414247
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.521286394
Short name T787
Test name
Test status
Simulation time 1588811666 ps
CPU time 5.91 seconds
Started Jul 13 06:58:29 PM PDT 24
Finished Jul 13 06:58:37 PM PDT 24
Peak memory 209164 kb
Host smart-aebb7b9b-7f7d-4690-a1fa-d5544a65a117
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521286394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.521286394
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2484117222
Short name T849
Test name
Test status
Simulation time 346876834 ps
CPU time 6.74 seconds
Started Jul 13 06:58:26 PM PDT 24
Finished Jul 13 06:58:33 PM PDT 24
Peak memory 208832 kb
Host smart-02ee3eac-746e-43a0-8483-e07d54965115
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484117222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2484117222
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.932583912
Short name T898
Test name
Test status
Simulation time 5420889599 ps
CPU time 35 seconds
Started Jul 13 06:58:27 PM PDT 24
Finished Jul 13 06:59:04 PM PDT 24
Peak memory 209920 kb
Host smart-c4a17d4d-39ae-4429-85b9-6bd7d4b49ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932583912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.932583912
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.17299565
Short name T205
Test name
Test status
Simulation time 171404437 ps
CPU time 2.23 seconds
Started Jul 13 06:58:28 PM PDT 24
Finished Jul 13 06:58:32 PM PDT 24
Peak memory 208840 kb
Host smart-073bb5e7-83f4-45ea-8795-67ebe9f65e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17299565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.17299565
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.2162962730
Short name T128
Test name
Test status
Simulation time 1091420653 ps
CPU time 21.38 seconds
Started Jul 13 06:58:27 PM PDT 24
Finished Jul 13 06:58:51 PM PDT 24
Peak memory 219964 kb
Host smart-69a337d2-cca7-481e-b7d5-fdce7f51c1af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162962730 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.2162962730
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.4148987493
Short name T605
Test name
Test status
Simulation time 96040172 ps
CPU time 3.41 seconds
Started Jul 13 06:58:29 PM PDT 24
Finished Jul 13 06:58:35 PM PDT 24
Peak memory 207384 kb
Host smart-a38f3a03-f2e2-4208-9ae2-46356b338b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148987493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.4148987493
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3456947379
Short name T557
Test name
Test status
Simulation time 221804970 ps
CPU time 2.14 seconds
Started Jul 13 06:58:30 PM PDT 24
Finished Jul 13 06:58:34 PM PDT 24
Peak memory 209848 kb
Host smart-11e59723-5b71-4729-8f0a-1b6ef89e90b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456947379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3456947379
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1698097762
Short name T811
Test name
Test status
Simulation time 9352065 ps
CPU time 0.78 seconds
Started Jul 13 06:56:04 PM PDT 24
Finished Jul 13 06:56:06 PM PDT 24
Peak memory 205936 kb
Host smart-49535184-9fd8-40a5-be28-6296fb568df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698097762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1698097762
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2007046791
Short name T419
Test name
Test status
Simulation time 1743497861 ps
CPU time 45.96 seconds
Started Jul 13 06:55:59 PM PDT 24
Finished Jul 13 06:56:45 PM PDT 24
Peak memory 215424 kb
Host smart-3ab54523-81e0-40c3-96d6-f004bf763504
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2007046791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2007046791
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1308130627
Short name T20
Test name
Test status
Simulation time 55895899 ps
CPU time 2.35 seconds
Started Jul 13 06:55:54 PM PDT 24
Finished Jul 13 06:55:57 PM PDT 24
Peak memory 207244 kb
Host smart-d198db99-0e41-4e08-a23b-c39f946db0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308130627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1308130627
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2365748182
Short name T551
Test name
Test status
Simulation time 97795239 ps
CPU time 2.81 seconds
Started Jul 13 06:55:55 PM PDT 24
Finished Jul 13 06:55:59 PM PDT 24
Peak memory 214288 kb
Host smart-fb8d8abe-fc7b-4aaa-992f-42645531a4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365748182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2365748182
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1434904312
Short name T18
Test name
Test status
Simulation time 89832444 ps
CPU time 4.08 seconds
Started Jul 13 06:55:55 PM PDT 24
Finished Jul 13 06:56:00 PM PDT 24
Peak memory 209784 kb
Host smart-163650ab-ccfe-47b5-81fc-622d848c648e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434904312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1434904312
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1311840465
Short name T362
Test name
Test status
Simulation time 264968483 ps
CPU time 6.36 seconds
Started Jul 13 06:55:57 PM PDT 24
Finished Jul 13 06:56:03 PM PDT 24
Peak memory 218164 kb
Host smart-c5962e8b-7b8c-4315-b6e1-5351737bc6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311840465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1311840465
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3051830220
Short name T809
Test name
Test status
Simulation time 150186471 ps
CPU time 2.28 seconds
Started Jul 13 06:55:54 PM PDT 24
Finished Jul 13 06:55:56 PM PDT 24
Peak memory 206876 kb
Host smart-65838026-a92f-4a74-8416-b53ad9cc889a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051830220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3051830220
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1786803320
Short name T518
Test name
Test status
Simulation time 236542559 ps
CPU time 3.22 seconds
Started Jul 13 06:55:54 PM PDT 24
Finished Jul 13 06:55:59 PM PDT 24
Peak memory 207048 kb
Host smart-ac0077c4-7243-4b60-a5af-d502e5999d67
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786803320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1786803320
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.508588484
Short name T542
Test name
Test status
Simulation time 7540428337 ps
CPU time 51.85 seconds
Started Jul 13 06:55:55 PM PDT 24
Finished Jul 13 06:56:47 PM PDT 24
Peak memory 209264 kb
Host smart-7946dda6-b3b9-4f29-b706-4cba0d69d2da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508588484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.508588484
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.577406570
Short name T478
Test name
Test status
Simulation time 731341665 ps
CPU time 24.17 seconds
Started Jul 13 06:55:58 PM PDT 24
Finished Jul 13 06:56:22 PM PDT 24
Peak memory 206980 kb
Host smart-90c0a7b8-2830-413b-aee7-50aedac2e6b2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577406570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.577406570
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3144922278
Short name T523
Test name
Test status
Simulation time 792179228 ps
CPU time 20.29 seconds
Started Jul 13 06:55:59 PM PDT 24
Finished Jul 13 06:56:20 PM PDT 24
Peak memory 209636 kb
Host smart-ee7104ff-d410-459c-9e15-78e893de57bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144922278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3144922278
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.4223241150
Short name T464
Test name
Test status
Simulation time 198866221 ps
CPU time 4.03 seconds
Started Jul 13 06:55:59 PM PDT 24
Finished Jul 13 06:56:03 PM PDT 24
Peak memory 208032 kb
Host smart-52215bc8-6419-465e-9423-13f20c959c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223241150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.4223241150
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3018739793
Short name T73
Test name
Test status
Simulation time 1587242853 ps
CPU time 24.78 seconds
Started Jul 13 06:56:03 PM PDT 24
Finished Jul 13 06:56:28 PM PDT 24
Peak memory 222584 kb
Host smart-3d0a5a86-8310-4c55-b8ac-03e8d8cb4566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018739793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3018739793
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.633197404
Short name T858
Test name
Test status
Simulation time 23452553330 ps
CPU time 46.51 seconds
Started Jul 13 06:55:56 PM PDT 24
Finished Jul 13 06:56:43 PM PDT 24
Peak memory 222580 kb
Host smart-9d128f93-1b63-462f-8c61-8021f0fb0bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633197404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.633197404
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3977233028
Short name T640
Test name
Test status
Simulation time 45241946 ps
CPU time 2.05 seconds
Started Jul 13 06:56:02 PM PDT 24
Finished Jul 13 06:56:04 PM PDT 24
Peak memory 210188 kb
Host smart-c623cf9e-43b8-4ab1-a3d8-243f6ef6a598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977233028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3977233028
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.560424274
Short name T449
Test name
Test status
Simulation time 52118722 ps
CPU time 0.7 seconds
Started Jul 13 06:56:11 PM PDT 24
Finished Jul 13 06:56:13 PM PDT 24
Peak memory 206016 kb
Host smart-04709d0a-dde3-47f3-a80c-1a7ec46ed4ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560424274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.560424274
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3508357256
Short name T424
Test name
Test status
Simulation time 60700119 ps
CPU time 4.3 seconds
Started Jul 13 06:56:04 PM PDT 24
Finished Jul 13 06:56:09 PM PDT 24
Peak memory 214324 kb
Host smart-9798dcbc-dd1e-4961-9d3f-2c55aad9e641
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3508357256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3508357256
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.4007460563
Short name T793
Test name
Test status
Simulation time 124486265 ps
CPU time 4.77 seconds
Started Jul 13 06:56:04 PM PDT 24
Finished Jul 13 06:56:09 PM PDT 24
Peak memory 214412 kb
Host smart-29989c70-d030-48c2-a791-3e41f5be0967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007460563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.4007460563
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1545718347
Short name T403
Test name
Test status
Simulation time 116909635 ps
CPU time 2.04 seconds
Started Jul 13 06:56:05 PM PDT 24
Finished Jul 13 06:56:07 PM PDT 24
Peak memory 207872 kb
Host smart-781f0b70-14c8-44c3-9b5d-024ddbeb8ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545718347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1545718347
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3327493769
Short name T192
Test name
Test status
Simulation time 312936154 ps
CPU time 3.09 seconds
Started Jul 13 06:56:03 PM PDT 24
Finished Jul 13 06:56:07 PM PDT 24
Peak memory 214292 kb
Host smart-4b668527-d94a-4e0a-a6d4-9ec7fba2ae2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327493769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3327493769
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1396556788
Short name T737
Test name
Test status
Simulation time 41230997 ps
CPU time 2.74 seconds
Started Jul 13 06:56:03 PM PDT 24
Finished Jul 13 06:56:06 PM PDT 24
Peak memory 214368 kb
Host smart-63b184cf-492a-49d9-9d71-255524748f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396556788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1396556788
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.456772703
Short name T697
Test name
Test status
Simulation time 83292233 ps
CPU time 2.53 seconds
Started Jul 13 06:56:04 PM PDT 24
Finished Jul 13 06:56:07 PM PDT 24
Peak memory 209972 kb
Host smart-bdd42640-2b03-47be-8519-70a5a54bb54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456772703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.456772703
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.435207159
Short name T709
Test name
Test status
Simulation time 881767385 ps
CPU time 5.92 seconds
Started Jul 13 06:56:04 PM PDT 24
Finished Jul 13 06:56:11 PM PDT 24
Peak memory 208696 kb
Host smart-f7f2de48-eef6-41b1-9560-92cf81d83f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435207159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.435207159
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3725880864
Short name T485
Test name
Test status
Simulation time 2664002949 ps
CPU time 8.6 seconds
Started Jul 13 06:56:04 PM PDT 24
Finished Jul 13 06:56:13 PM PDT 24
Peak memory 206916 kb
Host smart-fd8958b2-cd23-40be-b7c1-4b5dd1ee8d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725880864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3725880864
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2225232590
Short name T546
Test name
Test status
Simulation time 139711600 ps
CPU time 2.89 seconds
Started Jul 13 06:56:01 PM PDT 24
Finished Jul 13 06:56:04 PM PDT 24
Peak memory 206816 kb
Host smart-20443100-3479-4ca9-b118-e4715c481217
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225232590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2225232590
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.49974719
Short name T446
Test name
Test status
Simulation time 226651600 ps
CPU time 2.77 seconds
Started Jul 13 06:56:01 PM PDT 24
Finished Jul 13 06:56:04 PM PDT 24
Peak memory 206828 kb
Host smart-8c38974c-3f9f-484c-93bf-409b61e6e7a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49974719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.49974719
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1129405408
Short name T364
Test name
Test status
Simulation time 43229810 ps
CPU time 2.44 seconds
Started Jul 13 06:56:00 PM PDT 24
Finished Jul 13 06:56:03 PM PDT 24
Peak memory 206804 kb
Host smart-43d80695-087f-4e69-9c66-37a392f915a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129405408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1129405408
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3325408778
Short name T541
Test name
Test status
Simulation time 29352034 ps
CPU time 1.81 seconds
Started Jul 13 06:56:05 PM PDT 24
Finished Jul 13 06:56:07 PM PDT 24
Peak memory 208580 kb
Host smart-58b43202-b949-4cb9-a830-c1025e3b2219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325408778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3325408778
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3974245498
Short name T901
Test name
Test status
Simulation time 499423816 ps
CPU time 5.5 seconds
Started Jul 13 06:56:02 PM PDT 24
Finished Jul 13 06:56:08 PM PDT 24
Peak memory 206832 kb
Host smart-6d11fe05-7522-4e0c-8e1e-d3098480d939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974245498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3974245498
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.4234842487
Short name T126
Test name
Test status
Simulation time 1307727877 ps
CPU time 12.98 seconds
Started Jul 13 06:56:04 PM PDT 24
Finished Jul 13 06:56:18 PM PDT 24
Peak memory 219432 kb
Host smart-d9885f50-880a-4123-ab63-6ac5eb5ac69d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234842487 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.4234842487
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3162528856
Short name T390
Test name
Test status
Simulation time 54548312 ps
CPU time 3.07 seconds
Started Jul 13 06:56:04 PM PDT 24
Finished Jul 13 06:56:07 PM PDT 24
Peak memory 208160 kb
Host smart-cf36f7c6-09a4-4ba7-914c-1a21db5b20d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162528856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3162528856
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2611993494
Short name T58
Test name
Test status
Simulation time 45396763 ps
CPU time 2.57 seconds
Started Jul 13 06:56:03 PM PDT 24
Finished Jul 13 06:56:06 PM PDT 24
Peak memory 209968 kb
Host smart-1c0937ba-c08c-4dbe-a03c-b6b4a40df5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611993494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2611993494
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2143879801
Short name T870
Test name
Test status
Simulation time 40803006 ps
CPU time 0.86 seconds
Started Jul 13 06:56:10 PM PDT 24
Finished Jul 13 06:56:12 PM PDT 24
Peak memory 205992 kb
Host smart-20ce7378-82d4-4636-bae6-65163e08602e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143879801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2143879801
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2648794108
Short name T245
Test name
Test status
Simulation time 427799123 ps
CPU time 19.79 seconds
Started Jul 13 06:56:09 PM PDT 24
Finished Jul 13 06:56:29 PM PDT 24
Peak memory 214856 kb
Host smart-bb8219c9-c193-4d9c-bd05-c0b8155041d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648794108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2648794108
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2981431203
Short name T831
Test name
Test status
Simulation time 99956674 ps
CPU time 2.21 seconds
Started Jul 13 06:56:10 PM PDT 24
Finished Jul 13 06:56:12 PM PDT 24
Peak memory 206976 kb
Host smart-cbe1c560-7a13-44b5-8632-5957c89ee010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981431203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2981431203
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3450907308
Short name T698
Test name
Test status
Simulation time 95368993 ps
CPU time 4.47 seconds
Started Jul 13 06:56:10 PM PDT 24
Finished Jul 13 06:56:15 PM PDT 24
Peak memory 214908 kb
Host smart-d2fa115f-7876-4bf7-a953-002ea40b364d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450907308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3450907308
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.258352959
Short name T374
Test name
Test status
Simulation time 157925282 ps
CPU time 2.29 seconds
Started Jul 13 06:56:13 PM PDT 24
Finished Jul 13 06:56:16 PM PDT 24
Peak memory 222332 kb
Host smart-11a25fb6-8700-426f-9f16-8ca81589b950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258352959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.258352959
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1003335518
Short name T68
Test name
Test status
Simulation time 353292008 ps
CPU time 19.45 seconds
Started Jul 13 06:56:13 PM PDT 24
Finished Jul 13 06:56:33 PM PDT 24
Peak memory 209784 kb
Host smart-cb4eb7e2-55a6-4a74-9a32-eb94e901bce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003335518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1003335518
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1518633048
Short name T267
Test name
Test status
Simulation time 30811544 ps
CPU time 2.34 seconds
Started Jul 13 06:56:13 PM PDT 24
Finished Jul 13 06:56:16 PM PDT 24
Peak memory 207028 kb
Host smart-83b26404-0146-46b4-af31-48f94c57e1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518633048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1518633048
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.129301532
Short name T375
Test name
Test status
Simulation time 125952853 ps
CPU time 3.21 seconds
Started Jul 13 06:56:10 PM PDT 24
Finished Jul 13 06:56:14 PM PDT 24
Peak memory 208804 kb
Host smart-66b6ea74-9055-46f2-890a-4cb910304c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129301532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.129301532
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2205843931
Short name T209
Test name
Test status
Simulation time 207585686 ps
CPU time 2.95 seconds
Started Jul 13 06:56:12 PM PDT 24
Finished Jul 13 06:56:15 PM PDT 24
Peak memory 206772 kb
Host smart-49a377fd-94a9-4e72-b0fd-3c2364768280
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205843931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2205843931
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3189610884
Short name T654
Test name
Test status
Simulation time 226251659 ps
CPU time 3.15 seconds
Started Jul 13 06:56:10 PM PDT 24
Finished Jul 13 06:56:13 PM PDT 24
Peak memory 208576 kb
Host smart-af735fe6-fb44-4cdb-925b-715d83772395
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189610884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3189610884
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1727588699
Short name T519
Test name
Test status
Simulation time 235346601 ps
CPU time 2.56 seconds
Started Jul 13 06:56:12 PM PDT 24
Finished Jul 13 06:56:16 PM PDT 24
Peak memory 206844 kb
Host smart-f7c32a3f-8f1d-4de7-a13d-d4ab2209a95b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727588699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1727588699
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.742623673
Short name T471
Test name
Test status
Simulation time 563640050 ps
CPU time 9.05 seconds
Started Jul 13 06:56:11 PM PDT 24
Finished Jul 13 06:56:21 PM PDT 24
Peak memory 209560 kb
Host smart-d21fbede-6f79-42bf-a608-f209c243604f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742623673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.742623673
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3410100842
Short name T665
Test name
Test status
Simulation time 108827423 ps
CPU time 2.74 seconds
Started Jul 13 06:56:12 PM PDT 24
Finished Jul 13 06:56:16 PM PDT 24
Peak memory 207024 kb
Host smart-e5c3cced-1bf6-4118-b397-cd48f64b5406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410100842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3410100842
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.672812517
Short name T195
Test name
Test status
Simulation time 566300392 ps
CPU time 20.59 seconds
Started Jul 13 06:56:11 PM PDT 24
Finished Jul 13 06:56:32 PM PDT 24
Peak memory 222212 kb
Host smart-a25359b1-9883-404d-9553-78b8f3ccd264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672812517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.672812517
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.141272317
Short name T244
Test name
Test status
Simulation time 287842077 ps
CPU time 13.85 seconds
Started Jul 13 06:56:14 PM PDT 24
Finished Jul 13 06:56:28 PM PDT 24
Peak memory 222624 kb
Host smart-db287240-aeef-4140-a6ef-c99acfe2ee9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141272317 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.141272317
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2712883099
Short name T533
Test name
Test status
Simulation time 571189360 ps
CPU time 9.08 seconds
Started Jul 13 06:56:12 PM PDT 24
Finished Jul 13 06:56:22 PM PDT 24
Peak memory 218364 kb
Host smart-ce780bae-c309-4c69-b995-aebab9ad2f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712883099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2712883099
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3040995185
Short name T395
Test name
Test status
Simulation time 119268538 ps
CPU time 2.73 seconds
Started Jul 13 06:56:10 PM PDT 24
Finished Jul 13 06:56:14 PM PDT 24
Peak memory 210248 kb
Host smart-172ee608-cf47-4873-a5ed-b16bdfd0416e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040995185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3040995185
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1077606742
Short name T480
Test name
Test status
Simulation time 10653748 ps
CPU time 0.78 seconds
Started Jul 13 06:56:21 PM PDT 24
Finished Jul 13 06:56:22 PM PDT 24
Peak memory 205984 kb
Host smart-c883bf09-d2db-472f-a323-dc8be364aa3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077606742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1077606742
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1480161623
Short name T137
Test name
Test status
Simulation time 149574302 ps
CPU time 4.43 seconds
Started Jul 13 06:56:12 PM PDT 24
Finished Jul 13 06:56:17 PM PDT 24
Peak memory 215412 kb
Host smart-397f6291-4225-4dbe-902a-b40c13594837
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1480161623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1480161623
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.282351853
Short name T633
Test name
Test status
Simulation time 145476316 ps
CPU time 3.12 seconds
Started Jul 13 06:56:11 PM PDT 24
Finished Jul 13 06:56:15 PM PDT 24
Peak memory 214336 kb
Host smart-6cdcd2df-c614-41e9-80af-21e2af2b1071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282351853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.282351853
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.612104306
Short name T495
Test name
Test status
Simulation time 83470078 ps
CPU time 2.85 seconds
Started Jul 13 06:56:11 PM PDT 24
Finished Jul 13 06:56:14 PM PDT 24
Peak memory 209180 kb
Host smart-ba95b9ce-84e8-4f46-ad70-34e322100f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612104306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.612104306
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3963077838
Short name T334
Test name
Test status
Simulation time 45933788 ps
CPU time 2.84 seconds
Started Jul 13 06:56:11 PM PDT 24
Finished Jul 13 06:56:15 PM PDT 24
Peak memory 222320 kb
Host smart-0ecbb372-fab1-4d13-a7be-3f6ba54c4b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963077838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3963077838
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.265007778
Short name T53
Test name
Test status
Simulation time 121802193 ps
CPU time 1.98 seconds
Started Jul 13 06:56:15 PM PDT 24
Finished Jul 13 06:56:18 PM PDT 24
Peak memory 206132 kb
Host smart-e9e94a3f-608b-4f45-a144-a2db0599552c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265007778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.265007778
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3278328338
Short name T500
Test name
Test status
Simulation time 186046419 ps
CPU time 5.4 seconds
Started Jul 13 06:56:12 PM PDT 24
Finished Jul 13 06:56:18 PM PDT 24
Peak memory 207448 kb
Host smart-a7654dfe-ca00-4308-ad84-b2a84e89b3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278328338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3278328338
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2260364813
Short name T407
Test name
Test status
Simulation time 672456656 ps
CPU time 2.76 seconds
Started Jul 13 06:56:12 PM PDT 24
Finished Jul 13 06:56:16 PM PDT 24
Peak memory 206896 kb
Host smart-2e7f20af-13bb-4295-9332-db49177d265f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260364813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2260364813
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1136469388
Short name T584
Test name
Test status
Simulation time 194941555 ps
CPU time 2.63 seconds
Started Jul 13 06:56:11 PM PDT 24
Finished Jul 13 06:56:14 PM PDT 24
Peak memory 206800 kb
Host smart-febc5592-e9f6-4b39-a0b1-df784c7fc84c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136469388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1136469388
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2678957580
Short name T729
Test name
Test status
Simulation time 146399155 ps
CPU time 3.94 seconds
Started Jul 13 06:56:12 PM PDT 24
Finished Jul 13 06:56:17 PM PDT 24
Peak memory 208824 kb
Host smart-3bdd0665-45e7-40b8-a88d-0b8a6e187e88
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678957580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2678957580
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.894325395
Short name T548
Test name
Test status
Simulation time 44663920 ps
CPU time 2.44 seconds
Started Jul 13 06:56:10 PM PDT 24
Finished Jul 13 06:56:13 PM PDT 24
Peak memory 208460 kb
Host smart-aba55838-3ed2-4744-afb4-e05e4055f8ff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894325395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.894325395
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1753211213
Short name T263
Test name
Test status
Simulation time 47105535 ps
CPU time 2.76 seconds
Started Jul 13 06:56:10 PM PDT 24
Finished Jul 13 06:56:13 PM PDT 24
Peak memory 214364 kb
Host smart-90671fb6-585f-4015-847d-8867724d6a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753211213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1753211213
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1040654074
Short name T481
Test name
Test status
Simulation time 865505688 ps
CPU time 7.76 seconds
Started Jul 13 06:56:12 PM PDT 24
Finished Jul 13 06:56:20 PM PDT 24
Peak memory 208252 kb
Host smart-bffc6871-a079-4508-aa0c-5afd7a227fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040654074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1040654074
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1152719306
Short name T187
Test name
Test status
Simulation time 283609266 ps
CPU time 10.75 seconds
Started Jul 13 06:56:23 PM PDT 24
Finished Jul 13 06:56:35 PM PDT 24
Peak memory 219236 kb
Host smart-6487b340-d345-437d-b2f1-a12e86edc770
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152719306 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1152719306
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.428908198
Short name T204
Test name
Test status
Simulation time 305329704 ps
CPU time 7.63 seconds
Started Jul 13 06:56:09 PM PDT 24
Finished Jul 13 06:56:18 PM PDT 24
Peak memory 218576 kb
Host smart-06c314cf-ee49-48e3-bdd4-0cc9bea948ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428908198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.428908198
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3596305646
Short name T391
Test name
Test status
Simulation time 66762822 ps
CPU time 1.23 seconds
Started Jul 13 06:56:14 PM PDT 24
Finished Jul 13 06:56:16 PM PDT 24
Peak memory 208588 kb
Host smart-07929f99-1342-44cf-88a7-b7903234a182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596305646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3596305646
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.4223148817
Short name T504
Test name
Test status
Simulation time 9198163 ps
CPU time 0.82 seconds
Started Jul 13 06:56:19 PM PDT 24
Finished Jul 13 06:56:21 PM PDT 24
Peak memory 206004 kb
Host smart-7e504d1b-677b-4d51-a0ab-2653006798d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223148817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.4223148817
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.50273783
Short name T148
Test name
Test status
Simulation time 159913680 ps
CPU time 3.29 seconds
Started Jul 13 06:56:18 PM PDT 24
Finished Jul 13 06:56:22 PM PDT 24
Peak memory 214600 kb
Host smart-bc90413c-34a3-4f4e-8a4d-78f63a815e8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50273783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.50273783
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.4047257052
Short name T571
Test name
Test status
Simulation time 69784220 ps
CPU time 2.9 seconds
Started Jul 13 06:56:22 PM PDT 24
Finished Jul 13 06:56:26 PM PDT 24
Peak memory 218300 kb
Host smart-00c26c27-60b3-4297-9712-33c249785c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047257052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.4047257052
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3896938754
Short name T101
Test name
Test status
Simulation time 613245041 ps
CPU time 7.67 seconds
Started Jul 13 06:56:21 PM PDT 24
Finished Jul 13 06:56:30 PM PDT 24
Peak memory 209780 kb
Host smart-30bf2f54-59b2-4292-ace1-cc0dd025addd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896938754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3896938754
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2221011807
Short name T5
Test name
Test status
Simulation time 72140281 ps
CPU time 2.87 seconds
Started Jul 13 06:56:22 PM PDT 24
Finished Jul 13 06:56:26 PM PDT 24
Peak memory 222444 kb
Host smart-f4be7dba-1026-46d6-ab03-db1389a1c2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221011807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2221011807
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2673047297
Short name T238
Test name
Test status
Simulation time 261946353 ps
CPU time 3.09 seconds
Started Jul 13 06:56:19 PM PDT 24
Finished Jul 13 06:56:23 PM PDT 24
Peak memory 219220 kb
Host smart-fe92ad4b-48f3-4391-afc4-9da23c494aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673047297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2673047297
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2112305545
Short name T575
Test name
Test status
Simulation time 44602898 ps
CPU time 2.65 seconds
Started Jul 13 06:56:20 PM PDT 24
Finished Jul 13 06:56:24 PM PDT 24
Peak memory 209168 kb
Host smart-50185135-e9b2-4d60-a791-46c12446d271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112305545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2112305545
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.792702102
Short name T766
Test name
Test status
Simulation time 146385442 ps
CPU time 3.47 seconds
Started Jul 13 06:56:18 PM PDT 24
Finished Jul 13 06:56:21 PM PDT 24
Peak memory 208532 kb
Host smart-3b23736e-872b-4526-a26b-24e6de3d6360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792702102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.792702102
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.131541079
Short name T823
Test name
Test status
Simulation time 477962543 ps
CPU time 7.25 seconds
Started Jul 13 06:56:22 PM PDT 24
Finished Jul 13 06:56:30 PM PDT 24
Peak memory 208768 kb
Host smart-4e3eedb8-cd1d-4d60-8e4a-6ef2171ddbde
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131541079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.131541079
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2350209464
Short name T502
Test name
Test status
Simulation time 24513359 ps
CPU time 1.92 seconds
Started Jul 13 06:56:22 PM PDT 24
Finished Jul 13 06:56:25 PM PDT 24
Peak memory 207256 kb
Host smart-78c8ea87-ea93-4612-a9ec-b0409274e1d8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350209464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2350209464
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.526449830
Short name T666
Test name
Test status
Simulation time 40342313 ps
CPU time 2.28 seconds
Started Jul 13 06:56:19 PM PDT 24
Finished Jul 13 06:56:22 PM PDT 24
Peak memory 208876 kb
Host smart-7709da2c-fa3e-4bdb-9e80-55c724635aeb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526449830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.526449830
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.500004648
Short name T723
Test name
Test status
Simulation time 152989752 ps
CPU time 3.7 seconds
Started Jul 13 06:56:19 PM PDT 24
Finished Jul 13 06:56:24 PM PDT 24
Peak memory 214320 kb
Host smart-bf1d2dd4-22db-411e-9311-d0382ab087af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500004648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.500004648
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1198376828
Short name T404
Test name
Test status
Simulation time 267011142 ps
CPU time 3.32 seconds
Started Jul 13 06:56:21 PM PDT 24
Finished Jul 13 06:56:25 PM PDT 24
Peak memory 207044 kb
Host smart-566a5d51-84f4-47a0-a287-481cfeff9489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198376828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1198376828
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.54341071
Short name T473
Test name
Test status
Simulation time 411874002 ps
CPU time 4.84 seconds
Started Jul 13 06:56:20 PM PDT 24
Finished Jul 13 06:56:25 PM PDT 24
Peak memory 206960 kb
Host smart-ff9ed245-1a7e-48e2-b43c-6ba762a043b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54341071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.54341071
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1090659810
Short name T130
Test name
Test status
Simulation time 138056794 ps
CPU time 2.6 seconds
Started Jul 13 06:56:19 PM PDT 24
Finished Jul 13 06:56:22 PM PDT 24
Peak memory 214440 kb
Host smart-ffa7a949-2026-4c46-8d81-d64aa7a4aa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090659810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1090659810
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2183398024
Short name T168
Test name
Test status
Simulation time 43627481 ps
CPU time 2.58 seconds
Started Jul 13 06:56:20 PM PDT 24
Finished Jul 13 06:56:23 PM PDT 24
Peak memory 210200 kb
Host smart-b1cd0c8c-d456-4126-b084-986ce3d16051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183398024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2183398024
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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