Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
77.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	13	36	73.47

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	12	23	65.71	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	42	1			T6	2		T45	1		T46	1
auto[OpGenId]	10	1			T219	1		T220	1		T127	1
auto[OpGenSwOut]	20	1			T59	1		T64	1		T221	1
auto[OpGenHwOut]	25	1			T6	2		T39	1		T7	2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1510	1			T6	2		T222	1		T46	1
auto[StInit]	73	1			T6	1		T45	1		T54	1
auto[StCreatorRootKey]	57	1			T3	1		T56	1		T110	1
auto[StOwnerIntKey]	42	1			T6	2		T58	1		T20	1
auto[StOwnerKey]	46	1			T5	1		T38	1		T42	1
auto[StDisabled]	479	1			T6	14		T110	3		T54	12
auto[StInvalid]	50	1			T2	1		T16	1		T99	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3244

1

T1

1

T2

2

T3

2

auto[1]

97

1

T6

4

T45

1

T46

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1501	1			T6	2		T222	1		T110	1
auto[StReset]	auto[1]	9	1			T46	1		T39	1		T157	1
auto[StInit]	auto[0]	34	1			T54	1		T59	1		T111	1
auto[StInit]	auto[1]	39	1			T6	1		T45	1		T59	1
auto[StCreatorRootKey]	auto[0]	45	1			T3	1		T56	1		T110	1
auto[StCreatorRootKey]	auto[1]	12	1			T30	1		T7	1		T123	2
auto[StOwnerIntKey]	auto[0]	27	1			T20	1		T59	1		T31	1
auto[StOwnerIntKey]	auto[1]	15	1			T6	2		T58	1		T196	1
auto[StOwnerKey]	auto[0]	36	1			T5	1		T38	1		T42	1
auto[StOwnerKey]	auto[1]	10	1			T196	1		T127	1		T73	1
auto[StDisabled]	auto[0]	467	1			T6	13		T110	3		T54	12
auto[StDisabled]	auto[1]	12	1			T6	1		T64	1		T223	1
auto[StInvalid]	auto[0]	50	1			T2	1		T16	1		T99	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	12	23	65.71	12

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId]]	0	1	1
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	5

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	6	1			T46	1		T48	1		T49	1
auto[StReset]	auto[OpGenSwOut]	2	1			T157	1		T224	1		-	-
auto[StReset]	auto[OpGenHwOut]	1	1			T39	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	13	1			T6	1		T45	1		T22	1
auto[StInit]	auto[OpGenId]	5	1			T220	1		T73	1		T225	1
auto[StInit]	auto[OpGenSwOut]	9	1			T59	1		T221	1		T226	1
auto[StInit]	auto[OpGenHwOut]	12	1			T7	1		T9	1		T23	1
auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T30	1		T123	1		T219	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T227	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	1	1			T123	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenHwOut]	1	1			T7	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T6	1		T58	1		T196	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T219	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T33	1		T228	1		T229	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	4	1			T6	1		T230	1		T231	1
auto[StOwnerKey]	auto[OpAdvance]	2	1			T196	1		T232	1		-	-
auto[StOwnerKey]	auto[OpGenId]	2	1			T127	1		T233	1		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T73	1		T234	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	4	1			T235	1		T236	1		T237	1
auto[StDisabled]	auto[OpAdvance]	6	1			T223	1		T219	1		T238	1
auto[StDisabled]	auto[OpGenId]	1	1			T239	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	2	1			T64	1		T240	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	3	1			T6	1		T198	1		T241	1