Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4860

1

T1

8

T2

10

T4

5

auto[1]

535

1

T15

3

T44

2

T28

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4860

1

T1

8

T2

10

T4

5

auto[1]

535

1

T15

3

T44

2

T28

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4834

1

T1

8

T2

10

T4

4

auto[1]

561

1

T4

1

T5

2

T19

4

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4834

1

T1

8

T2

10

T4

4

auto[1]

561

1

T4

1

T5

2

T19

4

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	432	1			T4	1		T47	1		T85	1
auto[OpGenId]	1132	1			T2	2		T4	1		T5	2
auto[OpGenSwOut]	1171	1			T2	2		T5	3		T16	1
auto[OpGenHwOut]	2577	1			T1	8		T2	6		T4	3
auto[OpDisable]	83	1			T37	1		T55	1		T6	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	432	1			T4	1		T47	1		T85	1
auto[OpGenId]	1132	1			T2	2		T4	1		T5	2
auto[OpGenSwOut]	1171	1			T2	2		T5	3		T16	1
auto[OpGenHwOut]	2577	1			T1	8		T2	6		T4	3
auto[OpDisable]	83	1			T37	1		T55	1		T6	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4870

1

T1

3

T2

10

T4

5

auto[1]

525

1

T1

5

T5

1

T37

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4870

1

T1

3

T2

10

T4

5

auto[1]

525

1

T1

5

T5

1

T37

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5156

1

T1

8

T2

10

T4

5

auto[1]

239

1

T78

6

T118

8

T119

2

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1848	1			T1	2		T2	4		T4	2
auto[1]	711	1			T1	4		T2	2		T15	1
auto[2]	687	1			T2	1		T16	1		T47	2
auto[3]	736	1			T4	2		T15	5		T16	1
auto[4]	334	1			T2	1		T15	4		T19	2
auto[5]	388	1			T1	1		T2	1		T4	1
auto[6]	344	1			T2	1		T15	1		T17	1
auto[7]	347	1			T1	1		T15	1		T5	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1413	1			T1	2		T2	3		T4	1
clear_one[1]	711	1			T1	4		T2	2		T15	1
clear_one[2]	687	1			T2	1		T16	1		T47	2
clear_one[3]	736	1			T4	2		T15	5		T16	1
clear_none	1848	1			T1	2		T2	4		T4	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1032	1			T2	4		T4	2		T15	5
auto[StInit]	651	1			T1	1		T15	1		T17	1
auto[StCreatorRootKey]	577	1			T1	1		T15	1		T5	1
auto[StOwnerIntKey]	517	1			T1	1		T4	1		T15	1
auto[StOwnerKey]	457	1			T1	1		T15	1		T5	1
auto[StDisabled]	1869	1			T1	4		T4	2		T15	4
auto[StInvalid]	292	1			T2	6		T16	4		T18	3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1032	1			T2	4		T4	2		T15	5
auto[StInit]	651	1			T1	1		T15	1		T17	1
auto[StCreatorRootKey]	577	1			T1	1		T15	1		T5	1
auto[StOwnerIntKey]	517	1			T1	1		T4	1		T15	1
auto[StOwnerKey]	457	1			T1	1		T15	1		T5	1
auto[StDisabled]	1869	1			T1	4		T4	2		T15	4
auto[StInvalid]	292	1			T2	6		T16	4		T18	3

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2] - auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[2] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit]]	[auto[OpGenSwOut]]	0	1	1
[auto[4]]	[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[6]]	[auto[StOwnerKey]]	[auto[OpGenId]]	0	1	1
[auto[6]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	7	1			T213	1		T199	1		T242	1
auto[0]	auto[StReset]	auto[OpGenId]	180	1			T5	2		T29	1		T76	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	165	1			T2	2		T17	1		T29	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	251	1			T4	2		T15	1		T19	2
auto[0]	auto[StInit]	auto[OpAdvance]	40	1			T54	1		T26	1		T243	1
auto[0]	auto[StInit]	auto[OpGenId]	89	1			T6	2		T156	1		T63	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	91	1			T110	1		T54	3		T210	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	184	1			T1	1		T44	1		T55	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	25	1			T6	1		T211	1		T54	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	48	1			T37	1		T218	1		T62	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	43	1			T5	1		T28	1		T98	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	71	1			T6	1		T54	1		T62	2
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T244	1		T245	1		-	-
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	32	1			T207	1		T110	2		T246	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	31	1			T144	1		T208	1		T145	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	50	1			T6	2		T62	1		T58	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T63	1		T62	1		T223	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	24	1			T54	1		T247	1		T196	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T139	1		T248	1		T249	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	51	1			T140	1		T250	1		T251	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	37	1			T78	2		T6	1		T217	1
auto[0]	auto[StDisabled]	auto[OpGenId]	52	1			T37	1		T6	1		T62	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	77	1			T6	1		T128	1		T54	2
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	162	1			T1	1		T50	1		T29	1
auto[0]	auto[StDisabled]	auto[OpDisable]	27	1			T6	1		T131	1		T62	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	13	1			T202	1		T252	1		T83	1
auto[0]	auto[StInvalid]	auto[OpGenId]	22	1			T2	2		T85	1		T77	2
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	32	1			T18	2		T77	1		T99	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	17	1			T16	1		T47	1		T100	1
auto[1]	auto[StReset]	auto[OpGenId]	17	1			T157	1		T253	1		T254	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	16	1			T190	1		T7	1		T68	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	48	1			T19	1		T78	1		T143	1
auto[1]	auto[StInit]	auto[OpAdvance]	6	1			T6	1		T64	1		T106	1
auto[1]	auto[StInit]	auto[OpGenId]	12	1			T76	1		T207	1		T119	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	6	1			T255	1		T256	1		T73	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	19	1			T142	1		T257	1		T112	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T59	1		T258	1		T259	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T62	1		T260	1		T240	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	20	1			T118	2		T21	1		T223	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T1	1		T78	2		T25	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T6	1		T258	1		T261	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T116	1		T196	2		T70	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	21	1			T142	1		T110	1		T215	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	45	1			T1	1		T37	1		T143	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T62	2		T58	1		T67	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	22	1			T64	1		T262	1		T263	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T5	1		T6	1		T128	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T264	1		T265	1		T54	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	24	1			T6	2		T144	2		T199	1
auto[1]	auto[StDisabled]	auto[OpGenId]	47	1			T139	1		T6	1		T110	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T6	2		T110	1		T7	2
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	160	1			T1	2		T15	1		T19	1
auto[1]	auto[StDisabled]	auto[OpDisable]	8	1			T54	1		T266	1		T194	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	3	1			T252	1		T267	1		T268	1
auto[1]	auto[StInvalid]	auto[OpGenId]	12	1			T85	1		T269	1		T200	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T16	1		T200	1		T270	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T2	2		T63	1		T271	1
auto[2]	auto[StReset]	auto[OpAdvance]	1	1			T272	1		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	23	1			T29	1		T255	1		T111	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	17	1			T59	1		T196	1		T223	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	43	1			T2	1		T143	1		T110	1
auto[2]	auto[StInit]	auto[OpAdvance]	8	1			T54	1		T213	1		T7	1
auto[2]	auto[StInit]	auto[OpGenId]	4	1			T273	1		T69	1		T73	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	12	1			T78	1		T274	1		T273	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	18	1			T140	1		T62	1		T275	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T212	1		T119	1		T7	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T67	1		T70	1		T65	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T58	1		T116	1		T69	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	37	1			T134	1		T265	1		T250	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T276	1		T70	1		T277	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T62	1		T112	1		T249	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T28	1		T213	3		T62	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	36	1			T278	1		T201	1		T279	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T78	1		T273	1		T223	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	17	1			T25	1		T208	1		T62	2
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T7	1		T61	1		T196	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	35	1			T138	1		T143	1		T129	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	25	1			T62	1		T146	3		T276	1
auto[2]	auto[StDisabled]	auto[OpGenId]	46	1			T6	1		T156	1		T128	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	69	1			T28	1		T6	2		T246	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	156	1			T44	1		T138	2		T139	1
auto[2]	auto[StDisabled]	auto[OpDisable]	10	1			T62	1		T249	1		T124	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	6	1			T47	1		T280	1		T281	1
auto[2]	auto[StInvalid]	auto[OpGenId]	14	1			T51	1		T267	1		T102	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	15	1			T47	1		T77	1		T271	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T16	1		T77	1		T271	1
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T282	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	20	1			T119	1		T213	1		T62	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	22	1			T6	1		T110	1		T59	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	52	1			T15	2		T110	1		T216	1
auto[3]	auto[StInit]	auto[OpAdvance]	10	1			T248	1		T283	1		T127	1
auto[3]	auto[StInit]	auto[OpGenId]	12	1			T21	1		T59	1		T244	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	6	1			T284	1		T285	1		T286	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	24	1			T6	1		T7	1		T147	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T215	1		T287	1		T223	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T58	1		T112	1		T288	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	19	1			T6	1		T156	1		T54	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	45	1			T278	1		T58	1		T67	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T61	1		T289	1		T231	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T6	1		T290	1		T69	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	22	1			T119	1		T156	1		T190	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T4	1		T15	1		T19	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T144	1		T273	1		T127	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	15	1			T199	1		T61	1		T196	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	23	1			T110	1		T290	1		T276	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T19	1		T141	1		T62	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	31	1			T76	1		T118	3		T54	1
auto[3]	auto[StDisabled]	auto[OpGenId]	52	1			T4	1		T78	1		T6	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	46	1			T141	1		T118	2		T110	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	155	1			T15	2		T19	1		T44	1
auto[3]	auto[StDisabled]	auto[OpDisable]	10	1			T37	1		T54	1		T62	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	14	1			T99	1		T98	1		T270	1
auto[3]	auto[StInvalid]	auto[OpGenId]	11	1			T47	1		T291	1		T292	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T200	1		T51	1		T293	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T16	1		T18	1		T51	1
auto[4]	auto[StReset]	auto[OpAdvance]	1	1			T248	1		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	8	1			T6	1		T200	1		T58	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	11	1			T118	1		T207	1		T269	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	23	1			T2	1		T15	1		T29	1
auto[4]	auto[StInit]	auto[OpAdvance]	5	1			T104	1		T261	1		T294	1
auto[4]	auto[StInit]	auto[OpGenId]	9	1			T248	1		T295	1		T80	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	18	1			T15	1		T19	1		T203	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T78	1		T296	1		T104	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T290	1		T262	1		T240	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T214	1		T124	1		T70	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	24	1			T15	1		T19	1		T55	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T59	1		T286	1		T294	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T297	1		T298	1		T299	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T78	2		T212	1		T300	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T78	1		T138	1		T134	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T116	1		T196	1		T242	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	4	1			T70	1		T297	1		T301	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T59	1		T88	1		T302	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	12	1			T44	1		T58	1		T303	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	6	1			T196	1		T70	1		T73	1
auto[4]	auto[StDisabled]	auto[OpGenId]	28	1			T110	1		T128	1		T62	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T141	1		T6	1		T213	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	73	1			T15	1		T76	1		T203	1
auto[4]	auto[StDisabled]	auto[OpDisable]	2	1			T304	1		T305	1		-	-
auto[4]	auto[StInvalid]	auto[OpAdvance]	5	1			T252	1		T270	1		T268	1
auto[4]	auto[StInvalid]	auto[OpGenId]	2	1			T306	1		T307	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T269	1		T268	1		T308	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T309	1		T310	1		T311	1
auto[5]	auto[StReset]	auto[OpGenId]	6	1			T62	1		T67	1		T124	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	9	1			T7	1		T312	1		T219	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	27	1			T143	1		T6	1		T218	1
auto[5]	auto[StInit]	auto[OpAdvance]	3	1			T283	1		T313	1		T314	1
auto[5]	auto[StInit]	auto[OpGenId]	8	1			T62	1		T26	1		T315	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T316	1		T70	1		T260	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	20	1			T17	1		T143	1		T201	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T58	1		T317	2		T318	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T17	1		T247	1		T319	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T6	1		T266	1		T31	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T54	1		T59	1		T320	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T58	1		T283	1		T321	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T61	1		T127	1		T322	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T6	1		T276	1		T223	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T6	1		T323	1		T324	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T69	1		T325	1		T326	2
auto[5]	auto[StOwnerKey]	auto[OpGenId]	9	1			T6	1		T69	1		T283	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T62	1		T61	1		T316	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T67	1		T276	2		T327	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	15	1			T4	1		T6	2		T62	1
auto[5]	auto[StDisabled]	auto[OpGenId]	29	1			T7	1		T116	1		T68	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T6	3		T119	1		T62	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	92	1			T1	1		T143	1		T6	2
auto[5]	auto[StDisabled]	auto[OpDisable]	8	1			T66	1		T54	1		T62	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T202	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	6	1			T202	1		T52	1		T53	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T328	1		T329	1		T330	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T2	1		T269	1		T293	1
auto[6]	auto[StReset]	auto[OpGenId]	14	1			T110	1		T276	1		T124	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	14	1			T17	1		T255	1		T59	2
auto[6]	auto[StReset]	auto[OpGenHwOut]	18	1			T15	1		T6	1		T59	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T6	1		T249	1		T331	1
auto[6]	auto[StInit]	auto[OpGenId]	3	1			T94	1		T332	1		T333	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	4	1			T110	1		T58	1		T261	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	2	1			T186	1		T334	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T196	1		T127	1		T335	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T125	1		T336	1		T73	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T337	1		T219	2		T90	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T44	1		T112	1		T7	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T21	1		T59	1		T64	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T58	1		T7	1		T79	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T6	1		T54	1		T7	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	12	1			T140	1		T250	1		T338	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T73	1		T232	1		T339	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T156	2		T145	1		T58	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T203	1		T279	1		T340	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	11	1			T119	1		T25	1		T62	1
auto[6]	auto[StDisabled]	auto[OpGenId]	34	1			T6	1		T110	1		T208	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	21	1			T215	1		T67	4		T61	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	87	1			T19	1		T44	1		T264	1
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T276	1		T341	1		T342	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T52	1		T343	1		T344	1
auto[6]	auto[StInvalid]	auto[OpGenId]	5	1			T85	1		T63	1		T94	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T269	1		T52	1		T292	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T2	1		T86	1		T267	1
auto[7]	auto[StReset]	auto[OpGenId]	13	1			T214	1		T200	1		T64	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	6	1			T6	1		T126	1		T336	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	19	1			T19	1		T143	1		T215	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T26	1		T345	1		T346	1
auto[7]	auto[StInit]	auto[OpGenId]	7	1			T118	1		T276	1		T197	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T214	1		T249	1		T124	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	13	1			T192	1		T22	1		T327	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T104	2		T322	1		T347	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T348	1		T219	1		T347	2
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T349	1		T261	1		T49	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T140	1		T143	1		T216	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T6	1		T199	1		T347	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T67	1		T59	1		T350	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T5	1		T351	1		T352	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T44	1		T275	1		T327	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T207	1		T353	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	7	1			T246	1		T196	1		T93	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T294	1		T298	1		T354	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	14	1			T1	1		T15	1		T355	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	8	1			T64	1		T356	1		T357	1
auto[7]	auto[StDisabled]	auto[OpGenId]	24	1			T110	1		T214	1		T54	2
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T6	1		T290	1		T358	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	72	1			T19	1		T264	1		T118	2
auto[7]	auto[StDisabled]	auto[OpDisable]	13	1			T55	1		T255	1		T54	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	2	1			T85	1		T82	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	4	1			T267	1		T291	1		T281	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T63	1		T83	1		T280	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T99	1		T98	1		T83	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1413

1

T1

2

T2

3

T4

1

clear_one[1]

auto[0]

auto[0]

auto[0]

420

1

T2

2

T15

1

T16

1

clear_one[1]

auto[0]

auto[0]

auto[1]

116

1

T1

4

T37

1

T78

1

clear_one[1]

auto[0]

auto[1]

auto[0]

139

1

T19

1

T138

1

T143

1

clear_one[1]

auto[0]

auto[1]

auto[1]

36

1

T5

1

T144

2

T217

1

clear_one[2]

auto[0]

auto[0]

auto[0]

420

1

T2

1

T16

1

T47

2

clear_one[2]

auto[0]

auto[0]

auto[1]

107

1

T6

1

T156

1

T128

1

clear_one[2]

auto[1]

auto[0]

auto[0]

108

1

T44

1

T28

1

T25

1

clear_one[2]

auto[1]

auto[0]

auto[1]

52

1

T54

1

T62

1

T58

1

clear_one[3]

auto[0]

auto[0]

auto[0]

435

1

T4

1

T15

2

T16

1

clear_one[3]

auto[0]

auto[1]

auto[0]

141

1

T4

1

T19

3

T78

1

clear_one[3]

auto[1]

auto[0]

auto[0]

139

1

T15

3

T44

1

T76

1

clear_one[3]

auto[1]

auto[1]

auto[0]

21

1

T208

1

T54

1

T61

1

clear_none

auto[0]

auto[0]

auto[0]

1338

1

T1

1

T2

4

T4

2

clear_none

auto[0]

auto[0]

auto[1]

116

1

T1

1

T6

1

T128

1

clear_none

auto[0]

auto[1]

auto[0]

145

1

T5

1

T37

1

T78

3

clear_none

auto[0]

auto[1]

auto[1]

34

1

T29

1

T6

2

T217

1

clear_none

auto[1]

auto[0]

auto[0]

122

1

T50

1

T140

2

T6

2

clear_none

auto[1]

auto[0]

auto[1]

48

1

T62

1

T58

2

T112

1

clear_none

auto[1]

auto[1]

auto[0]

29

1

T54

1

T58

2

T112

1

clear_none

auto[1]

auto[1]

auto[1]

16

1

T67

1

T359

1

T360

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1357	1			T1	2		T2	3		T4	1
clear_all	auto[1]	56	1			T78	3		T118	2		T119	2
clear_one[1]	auto[0]	682	1			T1	4		T2	2		T15	1
clear_one[1]	auto[1]	29	1			T78	1		T118	3		T144	2
clear_one[2]	auto[0]	637	1			T2	1		T16	1		T47	2
clear_one[2]	auto[1]	50	1			T156	2		T213	5		T146	3
clear_one[3]	auto[0]	700	1			T4	2		T15	5		T16	1
clear_one[3]	auto[1]	36	1			T118	3		T156	2		T144	1
clear_none	auto[0]	1780	1			T1	2		T2	4		T4	2
clear_none	auto[1]	68	1			T78	2		T213	1		T199	1