Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11136

1

T1

5

T2

18

T3

15

auto[Attestation]

7869

1

T1

3

T3

3

T4

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2733	1			T2	2		T3	3		T4	4
auto[Aes]	3389	1			T2	3		T3	1		T4	3
auto[Kmac]	3331	1			T2	4		T3	5		T4	3
auto[Otbn]	3460	1			T1	8		T2	4		T3	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7745	1			T1	8		T2	1		T3	2
auto[OpGenId]	6092	1			T2	5		T3	5		T4	5
auto[OpGenSwOut]	5984	1			T2	9		T3	6		T4	2
auto[OpGenHwOut]	6929	1			T1	8		T2	4		T3	7
auto[OpDisable]	157	1			T17	1		T36	1		T37	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10847

1

T1

8

T2

1

T3

6

auto[OpDoneFail]

16060

1

T1

8

T2

18

T3

14

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6602	1			T1	1		T2	19		T3	14
auto[StInit]	3735	1			T1	2		T3	2		T4	3
auto[StCreatorRootKey]	3179	1			T1	2		T3	4		T4	1
auto[StOwnerIntKey]	2888	1			T1	2		T4	3		T15	2
auto[StOwnerKey]	2527	1			T1	2		T4	3		T15	2
auto[StDisabled]	7976	1			T1	7		T4	11		T15	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	309	1			T2	1		T3	2		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	109	1			T4	1		T29	2		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	79	1			T76	1		T42	1		T54	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	77	1			T28	1		T6	2		T145	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	63	1			T38	1		T139	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	210	1			T50	1		T29	2		T141	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	321	1			T2	2		T17	3		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	94	1			T36	1		T28	1		T78	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	76	1			T5	1		T118	1		T54	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	77	1			T78	1		T144	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	78	1			T75	1		T119	1		T133	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	213	1			T4	1		T29	2		T6	5
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	315	1			T2	4		T5	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	96	1			T3	1		T141	1		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	89	1			T29	1		T139	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	60	1			T29	1		T119	1		T110	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	67	1			T5	1		T76	3		T141	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	193	1			T141	2		T6	3		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	325	1			T2	2		T3	2		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	102	1			T6	2		T110	1		T66	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	95	1			T17	1		T6	1		T118	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	80	1			T38	1		T119	1		T130	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	75	1			T5	1		T130	1		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	198	1			T28	1		T29	1		T6	6
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	90	1			T6	1		T54	1		T62	6
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	90	1			T141	1		T142	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	83	1			T29	1		T76	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	83	1			T76	1		T78	1		T142	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	63	1			T6	1		T209	1		T210	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	223	1			T76	1		T141	1		T6	6
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	82	1			T6	1		T54	1		T62	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	88	1			T5	1		T6	1		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	83	1			T6	1		T132	1		T54	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	70	1			T5	1		T6	1		T54	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	64	1			T17	1		T29	1		T144	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	259	1			T6	5		T118	1		T119	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	87	1			T6	2		T110	1		T62	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	93	1			T5	1		T6	2		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	87	1			T3	1		T28	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T6	2		T156	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	74	1			T76	1		T6	2		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	235	1			T17	1		T75	1		T28	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	107	1			T6	4		T110	2		T54	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	97	1			T139	1		T211	1		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T28	2		T38	1		T141	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	79	1			T6	1		T212	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	54	1			T17	1		T6	1		T213	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	217	1			T17	1		T55	1		T141	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	283	1			T2	1		T3	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	87	1			T50	1		T6	3		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	56	1			T76	1		T54	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	87	1			T139	1		T6	2		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	58	1			T76	1		T214	1		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	166	1			T4	2		T76	1		T139	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	465	1			T2	1		T3	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	104	1			T4	1		T15	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	112	1			T55	1		T140	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	96	1			T15	1		T140	1		T142	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	72	1			T15	1		T140	1		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	300	1			T15	2		T44	1		T28	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	414	1			T3	1		T17	1		T19	9
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	120	1			T36	1		T138	1		T141	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T141	1		T6	1		T216	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	82	1			T78	1		T138	1		T143	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	92	1			T4	1		T141	1		T143	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	291	1			T19	2		T37	1		T76	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	492	1			T2	2		T3	2		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	112	1			T1	1		T55	1		T6	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	123	1			T1	1		T78	2		T141	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	95	1			T6	1		T212	1		T156	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	85	1			T1	1		T4	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	281	1			T1	2		T29	1		T6	5
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	79	1			T6	3		T62	2		T67	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	99	1			T17	1		T142	2		T6	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	71	1			T29	1		T6	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	55	1			T6	1		T156	1		T217	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	41	1			T141	1		T6	1		T218	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	172	1			T37	1		T29	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	67	1			T6	2		T110	1		T62	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	121	1			T36	1		T44	1		T140	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	108	1			T15	1		T16	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	100	1			T44	1		T207	1		T218	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	91	1			T44	1		T38	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	248	1			T15	2		T36	1		T44	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	69	1			T6	3		T110	2		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	106	1			T19	1		T37	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	105	1			T3	2		T5	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	103	1			T4	1		T5	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	81	1			T5	1		T19	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	282	1			T4	1		T19	2		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	66	1			T67	1		T59	1		T112	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	125	1			T55	1		T6	2		T144	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	95	1			T78	1		T6	2		T110	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T1	1		T37	1		T28	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	94	1			T17	1		T54	1		T210	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	282	1			T1	2		T36	2		T6	4

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	203	1			T28	1		T76	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	644	1			T2	1		T3	2		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	220	1			T5	1		T75	1		T78	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	639	1			T2	2		T4	1		T17	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	208	1			T5	1		T29	1		T76	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	612	1			T2	4		T3	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	238	1			T5	1		T17	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	637	1			T2	2		T3	2		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	206	1			T76	2		T78	1		T142	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	426	1			T29	1		T76	1		T141	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	198	1			T5	1		T17	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	448	1			T5	1		T29	1		T6	7
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	231	1			T3	1		T55	1		T76	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	432	1			T5	1		T17	1		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	205	1			T17	1		T28	2		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	437	1			T17	1		T55	1		T139	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	185	1			T76	2		T139	1		T6	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	552	1			T2	1		T3	1		T4	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	265	1			T15	2		T55	1		T140	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	884	1			T2	1		T3	1		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	259	1			T4	1		T78	1		T138	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	843	1			T3	1		T17	1		T19	11
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	291	1			T1	2		T4	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	897	1			T1	3		T2	2		T3	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	158	1			T29	1		T141	1		T6	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	359	1			T17	1		T37	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	284	1			T15	1		T17	1		T44	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	451	1			T15	2		T16	1		T36	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	267	1			T3	2		T5	3		T19	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	479	1			T4	2		T19	3		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	263	1			T1	1		T17	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	492	1			T1	2		T36	2		T28	1